xref: /linux/drivers/usb/dwc3/dwc3-qcom.c (revision c88fb897c1fb5a590dc6353ac4b01c8f46a347b3)
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018, The Linux Foundation. All rights reserved.
3  *
4  * Inspired by dwc3-of-simple.c
5  */
6 
7 #include <linux/acpi.h>
8 #include <linux/io.h>
9 #include <linux/of.h>
10 #include <linux/clk.h>
11 #include <linux/irq.h>
12 #include <linux/of_clk.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/extcon.h>
16 #include <linux/interconnect.h>
17 #include <linux/of_platform.h>
18 #include <linux/platform_device.h>
19 #include <linux/phy/phy.h>
20 #include <linux/usb/of.h>
21 #include <linux/reset.h>
22 #include <linux/iopoll.h>
23 
24 #include "core.h"
25 
26 /* USB QSCRATCH Hardware registers */
27 #define QSCRATCH_HS_PHY_CTRL			0x10
28 #define UTMI_OTG_VBUS_VALID			BIT(20)
29 #define SW_SESSVLD_SEL				BIT(28)
30 
31 #define QSCRATCH_SS_PHY_CTRL			0x30
32 #define LANE0_PWR_PRESENT			BIT(24)
33 
34 #define QSCRATCH_GENERAL_CFG			0x08
35 #define PIPE_UTMI_CLK_SEL			BIT(0)
36 #define PIPE3_PHYSTATUS_SW			BIT(3)
37 #define PIPE_UTMI_CLK_DIS			BIT(8)
38 
39 #define PWR_EVNT_IRQ_STAT_REG			0x58
40 #define PWR_EVNT_LPM_IN_L2_MASK			BIT(4)
41 #define PWR_EVNT_LPM_OUT_L2_MASK		BIT(5)
42 
43 #define SDM845_QSCRATCH_BASE_OFFSET		0xf8800
44 #define SDM845_QSCRATCH_SIZE			0x400
45 #define SDM845_DWC3_CORE_SIZE			0xcd00
46 
47 /* Interconnect path bandwidths in MBps */
48 #define USB_MEMORY_AVG_HS_BW MBps_to_icc(240)
49 #define USB_MEMORY_PEAK_HS_BW MBps_to_icc(700)
50 #define USB_MEMORY_AVG_SS_BW  MBps_to_icc(1000)
51 #define USB_MEMORY_PEAK_SS_BW MBps_to_icc(2500)
52 #define APPS_USB_AVG_BW 0
53 #define APPS_USB_PEAK_BW MBps_to_icc(40)
54 
55 struct dwc3_acpi_pdata {
56 	u32			qscratch_base_offset;
57 	u32			qscratch_base_size;
58 	u32			dwc3_core_base_size;
59 	int			hs_phy_irq_index;
60 	int			dp_hs_phy_irq_index;
61 	int			dm_hs_phy_irq_index;
62 	int			ss_phy_irq_index;
63 	bool			is_urs;
64 };
65 
66 struct dwc3_qcom {
67 	struct device		*dev;
68 	void __iomem		*qscratch_base;
69 	struct platform_device	*dwc3;
70 	struct platform_device	*urs_usb;
71 	struct clk		**clks;
72 	int			num_clocks;
73 	struct reset_control	*resets;
74 
75 	int			hs_phy_irq;
76 	int			dp_hs_phy_irq;
77 	int			dm_hs_phy_irq;
78 	int			ss_phy_irq;
79 
80 	struct extcon_dev	*edev;
81 	struct extcon_dev	*host_edev;
82 	struct notifier_block	vbus_nb;
83 	struct notifier_block	host_nb;
84 
85 	const struct dwc3_acpi_pdata *acpi_pdata;
86 
87 	enum usb_dr_mode	mode;
88 	bool			is_suspended;
89 	bool			pm_suspended;
90 	struct icc_path		*icc_path_ddr;
91 	struct icc_path		*icc_path_apps;
92 };
93 
94 static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val)
95 {
96 	u32 reg;
97 
98 	reg = readl(base + offset);
99 	reg |= val;
100 	writel(reg, base + offset);
101 
102 	/* ensure that above write is through */
103 	readl(base + offset);
104 }
105 
106 static inline void dwc3_qcom_clrbits(void __iomem *base, u32 offset, u32 val)
107 {
108 	u32 reg;
109 
110 	reg = readl(base + offset);
111 	reg &= ~val;
112 	writel(reg, base + offset);
113 
114 	/* ensure that above write is through */
115 	readl(base + offset);
116 }
117 
118 static void dwc3_qcom_vbus_overrride_enable(struct dwc3_qcom *qcom, bool enable)
119 {
120 	if (enable) {
121 		dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL,
122 				  LANE0_PWR_PRESENT);
123 		dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL,
124 				  UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
125 	} else {
126 		dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL,
127 				  LANE0_PWR_PRESENT);
128 		dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL,
129 				  UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
130 	}
131 }
132 
133 static int dwc3_qcom_vbus_notifier(struct notifier_block *nb,
134 				   unsigned long event, void *ptr)
135 {
136 	struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, vbus_nb);
137 
138 	/* enable vbus override for device mode */
139 	dwc3_qcom_vbus_overrride_enable(qcom, event);
140 	qcom->mode = event ? USB_DR_MODE_PERIPHERAL : USB_DR_MODE_HOST;
141 
142 	return NOTIFY_DONE;
143 }
144 
145 static int dwc3_qcom_host_notifier(struct notifier_block *nb,
146 				   unsigned long event, void *ptr)
147 {
148 	struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, host_nb);
149 
150 	/* disable vbus override in host mode */
151 	dwc3_qcom_vbus_overrride_enable(qcom, !event);
152 	qcom->mode = event ? USB_DR_MODE_HOST : USB_DR_MODE_PERIPHERAL;
153 
154 	return NOTIFY_DONE;
155 }
156 
157 static int dwc3_qcom_register_extcon(struct dwc3_qcom *qcom)
158 {
159 	struct device		*dev = qcom->dev;
160 	struct extcon_dev	*host_edev;
161 	int			ret;
162 
163 	if (!of_property_read_bool(dev->of_node, "extcon"))
164 		return 0;
165 
166 	qcom->edev = extcon_get_edev_by_phandle(dev, 0);
167 	if (IS_ERR(qcom->edev))
168 		return PTR_ERR(qcom->edev);
169 
170 	qcom->vbus_nb.notifier_call = dwc3_qcom_vbus_notifier;
171 
172 	qcom->host_edev = extcon_get_edev_by_phandle(dev, 1);
173 	if (IS_ERR(qcom->host_edev))
174 		qcom->host_edev = NULL;
175 
176 	ret = devm_extcon_register_notifier(dev, qcom->edev, EXTCON_USB,
177 					    &qcom->vbus_nb);
178 	if (ret < 0) {
179 		dev_err(dev, "VBUS notifier register failed\n");
180 		return ret;
181 	}
182 
183 	if (qcom->host_edev)
184 		host_edev = qcom->host_edev;
185 	else
186 		host_edev = qcom->edev;
187 
188 	qcom->host_nb.notifier_call = dwc3_qcom_host_notifier;
189 	ret = devm_extcon_register_notifier(dev, host_edev, EXTCON_USB_HOST,
190 					    &qcom->host_nb);
191 	if (ret < 0) {
192 		dev_err(dev, "Host notifier register failed\n");
193 		return ret;
194 	}
195 
196 	/* Update initial VBUS override based on extcon state */
197 	if (extcon_get_state(qcom->edev, EXTCON_USB) ||
198 	    !extcon_get_state(host_edev, EXTCON_USB_HOST))
199 		dwc3_qcom_vbus_notifier(&qcom->vbus_nb, true, qcom->edev);
200 	else
201 		dwc3_qcom_vbus_notifier(&qcom->vbus_nb, false, qcom->edev);
202 
203 	return 0;
204 }
205 
206 static int dwc3_qcom_interconnect_enable(struct dwc3_qcom *qcom)
207 {
208 	int ret;
209 
210 	ret = icc_enable(qcom->icc_path_ddr);
211 	if (ret)
212 		return ret;
213 
214 	ret = icc_enable(qcom->icc_path_apps);
215 	if (ret)
216 		icc_disable(qcom->icc_path_ddr);
217 
218 	return ret;
219 }
220 
221 static int dwc3_qcom_interconnect_disable(struct dwc3_qcom *qcom)
222 {
223 	int ret;
224 
225 	ret = icc_disable(qcom->icc_path_ddr);
226 	if (ret)
227 		return ret;
228 
229 	ret = icc_disable(qcom->icc_path_apps);
230 	if (ret)
231 		icc_enable(qcom->icc_path_ddr);
232 
233 	return ret;
234 }
235 
236 /**
237  * dwc3_qcom_interconnect_init() - Get interconnect path handles
238  * and set bandwidhth.
239  * @qcom:			Pointer to the concerned usb core.
240  *
241  */
242 static int dwc3_qcom_interconnect_init(struct dwc3_qcom *qcom)
243 {
244 	struct device *dev = qcom->dev;
245 	int ret;
246 
247 	qcom->icc_path_ddr = of_icc_get(dev, "usb-ddr");
248 	if (IS_ERR(qcom->icc_path_ddr)) {
249 		dev_err(dev, "failed to get usb-ddr path: %ld\n",
250 			PTR_ERR(qcom->icc_path_ddr));
251 		return PTR_ERR(qcom->icc_path_ddr);
252 	}
253 
254 	qcom->icc_path_apps = of_icc_get(dev, "apps-usb");
255 	if (IS_ERR(qcom->icc_path_apps)) {
256 		dev_err(dev, "failed to get apps-usb path: %ld\n",
257 				PTR_ERR(qcom->icc_path_apps));
258 		return PTR_ERR(qcom->icc_path_apps);
259 	}
260 
261 	if (usb_get_maximum_speed(&qcom->dwc3->dev) >= USB_SPEED_SUPER ||
262 			usb_get_maximum_speed(&qcom->dwc3->dev) == USB_SPEED_UNKNOWN)
263 		ret = icc_set_bw(qcom->icc_path_ddr,
264 			USB_MEMORY_AVG_SS_BW, USB_MEMORY_PEAK_SS_BW);
265 	else
266 		ret = icc_set_bw(qcom->icc_path_ddr,
267 			USB_MEMORY_AVG_HS_BW, USB_MEMORY_PEAK_HS_BW);
268 
269 	if (ret) {
270 		dev_err(dev, "failed to set bandwidth for usb-ddr path: %d\n", ret);
271 		return ret;
272 	}
273 
274 	ret = icc_set_bw(qcom->icc_path_apps,
275 		APPS_USB_AVG_BW, APPS_USB_PEAK_BW);
276 	if (ret) {
277 		dev_err(dev, "failed to set bandwidth for apps-usb path: %d\n", ret);
278 		return ret;
279 	}
280 
281 	return 0;
282 }
283 
284 /**
285  * dwc3_qcom_interconnect_exit() - Release interconnect path handles
286  * @qcom:			Pointer to the concerned usb core.
287  *
288  * This function is used to release interconnect path handle.
289  */
290 static void dwc3_qcom_interconnect_exit(struct dwc3_qcom *qcom)
291 {
292 	icc_put(qcom->icc_path_ddr);
293 	icc_put(qcom->icc_path_apps);
294 }
295 
296 static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom)
297 {
298 	if (qcom->hs_phy_irq) {
299 		disable_irq_wake(qcom->hs_phy_irq);
300 		disable_irq_nosync(qcom->hs_phy_irq);
301 	}
302 
303 	if (qcom->dp_hs_phy_irq) {
304 		disable_irq_wake(qcom->dp_hs_phy_irq);
305 		disable_irq_nosync(qcom->dp_hs_phy_irq);
306 	}
307 
308 	if (qcom->dm_hs_phy_irq) {
309 		disable_irq_wake(qcom->dm_hs_phy_irq);
310 		disable_irq_nosync(qcom->dm_hs_phy_irq);
311 	}
312 
313 	if (qcom->ss_phy_irq) {
314 		disable_irq_wake(qcom->ss_phy_irq);
315 		disable_irq_nosync(qcom->ss_phy_irq);
316 	}
317 }
318 
319 static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
320 {
321 	if (qcom->hs_phy_irq) {
322 		enable_irq(qcom->hs_phy_irq);
323 		enable_irq_wake(qcom->hs_phy_irq);
324 	}
325 
326 	if (qcom->dp_hs_phy_irq) {
327 		enable_irq(qcom->dp_hs_phy_irq);
328 		enable_irq_wake(qcom->dp_hs_phy_irq);
329 	}
330 
331 	if (qcom->dm_hs_phy_irq) {
332 		enable_irq(qcom->dm_hs_phy_irq);
333 		enable_irq_wake(qcom->dm_hs_phy_irq);
334 	}
335 
336 	if (qcom->ss_phy_irq) {
337 		enable_irq(qcom->ss_phy_irq);
338 		enable_irq_wake(qcom->ss_phy_irq);
339 	}
340 }
341 
342 static int dwc3_qcom_suspend(struct dwc3_qcom *qcom)
343 {
344 	u32 val;
345 	int i, ret;
346 
347 	if (qcom->is_suspended)
348 		return 0;
349 
350 	val = readl(qcom->qscratch_base + PWR_EVNT_IRQ_STAT_REG);
351 	if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
352 		dev_err(qcom->dev, "HS-PHY not in L2\n");
353 
354 	for (i = qcom->num_clocks - 1; i >= 0; i--)
355 		clk_disable_unprepare(qcom->clks[i]);
356 
357 	ret = dwc3_qcom_interconnect_disable(qcom);
358 	if (ret)
359 		dev_warn(qcom->dev, "failed to disable interconnect: %d\n", ret);
360 
361 	qcom->is_suspended = true;
362 	dwc3_qcom_enable_interrupts(qcom);
363 
364 	return 0;
365 }
366 
367 static int dwc3_qcom_resume(struct dwc3_qcom *qcom)
368 {
369 	int ret;
370 	int i;
371 
372 	if (!qcom->is_suspended)
373 		return 0;
374 
375 	dwc3_qcom_disable_interrupts(qcom);
376 
377 	for (i = 0; i < qcom->num_clocks; i++) {
378 		ret = clk_prepare_enable(qcom->clks[i]);
379 		if (ret < 0) {
380 			while (--i >= 0)
381 				clk_disable_unprepare(qcom->clks[i]);
382 			return ret;
383 		}
384 	}
385 
386 	ret = dwc3_qcom_interconnect_enable(qcom);
387 	if (ret)
388 		dev_warn(qcom->dev, "failed to enable interconnect: %d\n", ret);
389 
390 	/* Clear existing events from PHY related to L2 in/out */
391 	dwc3_qcom_setbits(qcom->qscratch_base, PWR_EVNT_IRQ_STAT_REG,
392 			  PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK);
393 
394 	qcom->is_suspended = false;
395 
396 	return 0;
397 }
398 
399 static irqreturn_t qcom_dwc3_resume_irq(int irq, void *data)
400 {
401 	struct dwc3_qcom *qcom = data;
402 	struct dwc3	*dwc = platform_get_drvdata(qcom->dwc3);
403 
404 	/* If pm_suspended then let pm_resume take care of resuming h/w */
405 	if (qcom->pm_suspended)
406 		return IRQ_HANDLED;
407 
408 	if (dwc->xhci)
409 		pm_runtime_resume(&dwc->xhci->dev);
410 
411 	return IRQ_HANDLED;
412 }
413 
414 static void dwc3_qcom_select_utmi_clk(struct dwc3_qcom *qcom)
415 {
416 	/* Configure dwc3 to use UTMI clock as PIPE clock not present */
417 	dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
418 			  PIPE_UTMI_CLK_DIS);
419 
420 	usleep_range(100, 1000);
421 
422 	dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
423 			  PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW);
424 
425 	usleep_range(100, 1000);
426 
427 	dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
428 			  PIPE_UTMI_CLK_DIS);
429 }
430 
431 static int dwc3_qcom_get_irq(struct platform_device *pdev,
432 			     const char *name, int num)
433 {
434 	struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
435 	struct platform_device *pdev_irq = qcom->urs_usb ? qcom->urs_usb : pdev;
436 	struct device_node *np = pdev->dev.of_node;
437 	int ret;
438 
439 	if (np)
440 		ret = platform_get_irq_byname(pdev_irq, name);
441 	else
442 		ret = platform_get_irq(pdev_irq, num);
443 
444 	return ret;
445 }
446 
447 static int dwc3_qcom_setup_irq(struct platform_device *pdev)
448 {
449 	struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
450 	const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata;
451 	int irq;
452 	int ret;
453 
454 	irq = dwc3_qcom_get_irq(pdev, "hs_phy_irq",
455 				pdata ? pdata->hs_phy_irq_index : -1);
456 	if (irq > 0) {
457 		/* Keep wakeup interrupts disabled until suspend */
458 		irq_set_status_flags(irq, IRQ_NOAUTOEN);
459 		ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
460 					qcom_dwc3_resume_irq,
461 					IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
462 					"qcom_dwc3 HS", qcom);
463 		if (ret) {
464 			dev_err(qcom->dev, "hs_phy_irq failed: %d\n", ret);
465 			return ret;
466 		}
467 		qcom->hs_phy_irq = irq;
468 	}
469 
470 	irq = dwc3_qcom_get_irq(pdev, "dp_hs_phy_irq",
471 				pdata ? pdata->dp_hs_phy_irq_index : -1);
472 	if (irq > 0) {
473 		irq_set_status_flags(irq, IRQ_NOAUTOEN);
474 		ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
475 					qcom_dwc3_resume_irq,
476 					IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
477 					"qcom_dwc3 DP_HS", qcom);
478 		if (ret) {
479 			dev_err(qcom->dev, "dp_hs_phy_irq failed: %d\n", ret);
480 			return ret;
481 		}
482 		qcom->dp_hs_phy_irq = irq;
483 	}
484 
485 	irq = dwc3_qcom_get_irq(pdev, "dm_hs_phy_irq",
486 				pdata ? pdata->dm_hs_phy_irq_index : -1);
487 	if (irq > 0) {
488 		irq_set_status_flags(irq, IRQ_NOAUTOEN);
489 		ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
490 					qcom_dwc3_resume_irq,
491 					IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
492 					"qcom_dwc3 DM_HS", qcom);
493 		if (ret) {
494 			dev_err(qcom->dev, "dm_hs_phy_irq failed: %d\n", ret);
495 			return ret;
496 		}
497 		qcom->dm_hs_phy_irq = irq;
498 	}
499 
500 	irq = dwc3_qcom_get_irq(pdev, "ss_phy_irq",
501 				pdata ? pdata->ss_phy_irq_index : -1);
502 	if (irq > 0) {
503 		irq_set_status_flags(irq, IRQ_NOAUTOEN);
504 		ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
505 					qcom_dwc3_resume_irq,
506 					IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
507 					"qcom_dwc3 SS", qcom);
508 		if (ret) {
509 			dev_err(qcom->dev, "ss_phy_irq failed: %d\n", ret);
510 			return ret;
511 		}
512 		qcom->ss_phy_irq = irq;
513 	}
514 
515 	return 0;
516 }
517 
518 static int dwc3_qcom_clk_init(struct dwc3_qcom *qcom, int count)
519 {
520 	struct device		*dev = qcom->dev;
521 	struct device_node	*np = dev->of_node;
522 	int			i;
523 
524 	if (!np || !count)
525 		return 0;
526 
527 	if (count < 0)
528 		return count;
529 
530 	qcom->num_clocks = count;
531 
532 	qcom->clks = devm_kcalloc(dev, qcom->num_clocks,
533 				  sizeof(struct clk *), GFP_KERNEL);
534 	if (!qcom->clks)
535 		return -ENOMEM;
536 
537 	for (i = 0; i < qcom->num_clocks; i++) {
538 		struct clk	*clk;
539 		int		ret;
540 
541 		clk = of_clk_get(np, i);
542 		if (IS_ERR(clk)) {
543 			while (--i >= 0)
544 				clk_put(qcom->clks[i]);
545 			return PTR_ERR(clk);
546 		}
547 
548 		ret = clk_prepare_enable(clk);
549 		if (ret < 0) {
550 			while (--i >= 0) {
551 				clk_disable_unprepare(qcom->clks[i]);
552 				clk_put(qcom->clks[i]);
553 			}
554 			clk_put(clk);
555 
556 			return ret;
557 		}
558 
559 		qcom->clks[i] = clk;
560 	}
561 
562 	return 0;
563 }
564 
565 static const struct property_entry dwc3_qcom_acpi_properties[] = {
566 	PROPERTY_ENTRY_STRING("dr_mode", "host"),
567 	{}
568 };
569 
570 static const struct software_node dwc3_qcom_swnode = {
571 	.properties = dwc3_qcom_acpi_properties,
572 };
573 
574 static int dwc3_qcom_acpi_register_core(struct platform_device *pdev)
575 {
576 	struct dwc3_qcom	*qcom = platform_get_drvdata(pdev);
577 	struct device		*dev = &pdev->dev;
578 	struct resource		*res, *child_res = NULL;
579 	struct platform_device	*pdev_irq = qcom->urs_usb ? qcom->urs_usb :
580 							    pdev;
581 	int			irq;
582 	int			ret;
583 
584 	qcom->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
585 	if (!qcom->dwc3)
586 		return -ENOMEM;
587 
588 	qcom->dwc3->dev.parent = dev;
589 	qcom->dwc3->dev.type = dev->type;
590 	qcom->dwc3->dev.dma_mask = dev->dma_mask;
591 	qcom->dwc3->dev.dma_parms = dev->dma_parms;
592 	qcom->dwc3->dev.coherent_dma_mask = dev->coherent_dma_mask;
593 
594 	child_res = kcalloc(2, sizeof(*child_res), GFP_KERNEL);
595 	if (!child_res)
596 		return -ENOMEM;
597 
598 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
599 	if (!res) {
600 		dev_err(&pdev->dev, "failed to get memory resource\n");
601 		ret = -ENODEV;
602 		goto out;
603 	}
604 
605 	child_res[0].flags = res->flags;
606 	child_res[0].start = res->start;
607 	child_res[0].end = child_res[0].start +
608 		qcom->acpi_pdata->dwc3_core_base_size;
609 
610 	irq = platform_get_irq(pdev_irq, 0);
611 	child_res[1].flags = IORESOURCE_IRQ;
612 	child_res[1].start = child_res[1].end = irq;
613 
614 	ret = platform_device_add_resources(qcom->dwc3, child_res, 2);
615 	if (ret) {
616 		dev_err(&pdev->dev, "failed to add resources\n");
617 		goto out;
618 	}
619 
620 	ret = device_add_software_node(&qcom->dwc3->dev, &dwc3_qcom_swnode);
621 	if (ret < 0) {
622 		dev_err(&pdev->dev, "failed to add properties\n");
623 		goto out;
624 	}
625 
626 	ret = platform_device_add(qcom->dwc3);
627 	if (ret) {
628 		dev_err(&pdev->dev, "failed to add device\n");
629 		device_remove_software_node(&qcom->dwc3->dev);
630 	}
631 
632 out:
633 	kfree(child_res);
634 	return ret;
635 }
636 
637 static int dwc3_qcom_of_register_core(struct platform_device *pdev)
638 {
639 	struct dwc3_qcom	*qcom = platform_get_drvdata(pdev);
640 	struct device_node	*np = pdev->dev.of_node, *dwc3_np;
641 	struct device		*dev = &pdev->dev;
642 	int			ret;
643 
644 	dwc3_np = of_get_child_by_name(np, "dwc3");
645 	if (!dwc3_np) {
646 		dev_err(dev, "failed to find dwc3 core child\n");
647 		return -ENODEV;
648 	}
649 
650 	ret = of_platform_populate(np, NULL, NULL, dev);
651 	if (ret) {
652 		dev_err(dev, "failed to register dwc3 core - %d\n", ret);
653 		return ret;
654 	}
655 
656 	qcom->dwc3 = of_find_device_by_node(dwc3_np);
657 	if (!qcom->dwc3) {
658 		dev_err(dev, "failed to get dwc3 platform device\n");
659 		return -ENODEV;
660 	}
661 
662 	return 0;
663 }
664 
665 static struct platform_device *
666 dwc3_qcom_create_urs_usb_platdev(struct device *dev)
667 {
668 	struct fwnode_handle *fwh;
669 	struct acpi_device *adev;
670 	char name[8];
671 	int ret;
672 	int id;
673 
674 	/* Figure out device id */
675 	ret = sscanf(fwnode_get_name(dev->fwnode), "URS%d", &id);
676 	if (!ret)
677 		return NULL;
678 
679 	/* Find the child using name */
680 	snprintf(name, sizeof(name), "USB%d", id);
681 	fwh = fwnode_get_named_child_node(dev->fwnode, name);
682 	if (!fwh)
683 		return NULL;
684 
685 	adev = to_acpi_device_node(fwh);
686 	if (!adev)
687 		return NULL;
688 
689 	return acpi_create_platform_device(adev, NULL);
690 }
691 
692 static int dwc3_qcom_probe(struct platform_device *pdev)
693 {
694 	struct device_node	*np = pdev->dev.of_node;
695 	struct device		*dev = &pdev->dev;
696 	struct dwc3_qcom	*qcom;
697 	struct resource		*res, *parent_res = NULL;
698 	int			ret, i;
699 	bool			ignore_pipe_clk;
700 
701 	qcom = devm_kzalloc(&pdev->dev, sizeof(*qcom), GFP_KERNEL);
702 	if (!qcom)
703 		return -ENOMEM;
704 
705 	platform_set_drvdata(pdev, qcom);
706 	qcom->dev = &pdev->dev;
707 
708 	if (has_acpi_companion(dev)) {
709 		qcom->acpi_pdata = acpi_device_get_match_data(dev);
710 		if (!qcom->acpi_pdata) {
711 			dev_err(&pdev->dev, "no supporting ACPI device data\n");
712 			return -EINVAL;
713 		}
714 	}
715 
716 	qcom->resets = devm_reset_control_array_get_optional_exclusive(dev);
717 	if (IS_ERR(qcom->resets)) {
718 		ret = PTR_ERR(qcom->resets);
719 		dev_err(&pdev->dev, "failed to get resets, err=%d\n", ret);
720 		return ret;
721 	}
722 
723 	ret = reset_control_assert(qcom->resets);
724 	if (ret) {
725 		dev_err(&pdev->dev, "failed to assert resets, err=%d\n", ret);
726 		return ret;
727 	}
728 
729 	usleep_range(10, 1000);
730 
731 	ret = reset_control_deassert(qcom->resets);
732 	if (ret) {
733 		dev_err(&pdev->dev, "failed to deassert resets, err=%d\n", ret);
734 		goto reset_assert;
735 	}
736 
737 	ret = dwc3_qcom_clk_init(qcom, of_clk_get_parent_count(np));
738 	if (ret) {
739 		dev_err(dev, "failed to get clocks\n");
740 		goto reset_assert;
741 	}
742 
743 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
744 
745 	if (np) {
746 		parent_res = res;
747 	} else {
748 		parent_res = kmemdup(res, sizeof(struct resource), GFP_KERNEL);
749 		if (!parent_res)
750 			return -ENOMEM;
751 
752 		parent_res->start = res->start +
753 			qcom->acpi_pdata->qscratch_base_offset;
754 		parent_res->end = parent_res->start +
755 			qcom->acpi_pdata->qscratch_base_size;
756 
757 		if (qcom->acpi_pdata->is_urs) {
758 			qcom->urs_usb = dwc3_qcom_create_urs_usb_platdev(dev);
759 			if (!qcom->urs_usb) {
760 				dev_err(dev, "failed to create URS USB platdev\n");
761 				return -ENODEV;
762 			}
763 		}
764 	}
765 
766 	qcom->qscratch_base = devm_ioremap_resource(dev, parent_res);
767 	if (IS_ERR(qcom->qscratch_base)) {
768 		dev_err(dev, "failed to map qscratch, err=%d\n", ret);
769 		ret = PTR_ERR(qcom->qscratch_base);
770 		goto clk_disable;
771 	}
772 
773 	ret = dwc3_qcom_setup_irq(pdev);
774 	if (ret) {
775 		dev_err(dev, "failed to setup IRQs, err=%d\n", ret);
776 		goto clk_disable;
777 	}
778 
779 	/*
780 	 * Disable pipe_clk requirement if specified. Used when dwc3
781 	 * operates without SSPHY and only HS/FS/LS modes are supported.
782 	 */
783 	ignore_pipe_clk = device_property_read_bool(dev,
784 				"qcom,select-utmi-as-pipe-clk");
785 	if (ignore_pipe_clk)
786 		dwc3_qcom_select_utmi_clk(qcom);
787 
788 	if (np)
789 		ret = dwc3_qcom_of_register_core(pdev);
790 	else
791 		ret = dwc3_qcom_acpi_register_core(pdev);
792 
793 	if (ret) {
794 		dev_err(dev, "failed to register DWC3 Core, err=%d\n", ret);
795 		goto depopulate;
796 	}
797 
798 	ret = dwc3_qcom_interconnect_init(qcom);
799 	if (ret)
800 		goto depopulate;
801 
802 	qcom->mode = usb_get_dr_mode(&qcom->dwc3->dev);
803 
804 	/* enable vbus override for device mode */
805 	if (qcom->mode == USB_DR_MODE_PERIPHERAL)
806 		dwc3_qcom_vbus_overrride_enable(qcom, true);
807 
808 	/* register extcon to override sw_vbus on Vbus change later */
809 	ret = dwc3_qcom_register_extcon(qcom);
810 	if (ret)
811 		goto interconnect_exit;
812 
813 	device_init_wakeup(&pdev->dev, 1);
814 	qcom->is_suspended = false;
815 	pm_runtime_set_active(dev);
816 	pm_runtime_enable(dev);
817 	pm_runtime_forbid(dev);
818 
819 	return 0;
820 
821 interconnect_exit:
822 	dwc3_qcom_interconnect_exit(qcom);
823 depopulate:
824 	if (np)
825 		of_platform_depopulate(&pdev->dev);
826 	else
827 		platform_device_put(pdev);
828 clk_disable:
829 	for (i = qcom->num_clocks - 1; i >= 0; i--) {
830 		clk_disable_unprepare(qcom->clks[i]);
831 		clk_put(qcom->clks[i]);
832 	}
833 reset_assert:
834 	reset_control_assert(qcom->resets);
835 
836 	return ret;
837 }
838 
839 static int dwc3_qcom_remove(struct platform_device *pdev)
840 {
841 	struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
842 	struct device *dev = &pdev->dev;
843 	int i;
844 
845 	device_remove_software_node(&qcom->dwc3->dev);
846 	of_platform_depopulate(dev);
847 
848 	for (i = qcom->num_clocks - 1; i >= 0; i--) {
849 		clk_disable_unprepare(qcom->clks[i]);
850 		clk_put(qcom->clks[i]);
851 	}
852 	qcom->num_clocks = 0;
853 
854 	dwc3_qcom_interconnect_exit(qcom);
855 	reset_control_assert(qcom->resets);
856 
857 	pm_runtime_allow(dev);
858 	pm_runtime_disable(dev);
859 
860 	return 0;
861 }
862 
863 static int __maybe_unused dwc3_qcom_pm_suspend(struct device *dev)
864 {
865 	struct dwc3_qcom *qcom = dev_get_drvdata(dev);
866 	int ret = 0;
867 
868 	ret = dwc3_qcom_suspend(qcom);
869 	if (!ret)
870 		qcom->pm_suspended = true;
871 
872 	return ret;
873 }
874 
875 static int __maybe_unused dwc3_qcom_pm_resume(struct device *dev)
876 {
877 	struct dwc3_qcom *qcom = dev_get_drvdata(dev);
878 	int ret;
879 
880 	ret = dwc3_qcom_resume(qcom);
881 	if (!ret)
882 		qcom->pm_suspended = false;
883 
884 	return ret;
885 }
886 
887 static int __maybe_unused dwc3_qcom_runtime_suspend(struct device *dev)
888 {
889 	struct dwc3_qcom *qcom = dev_get_drvdata(dev);
890 
891 	return dwc3_qcom_suspend(qcom);
892 }
893 
894 static int __maybe_unused dwc3_qcom_runtime_resume(struct device *dev)
895 {
896 	struct dwc3_qcom *qcom = dev_get_drvdata(dev);
897 
898 	return dwc3_qcom_resume(qcom);
899 }
900 
901 static const struct dev_pm_ops dwc3_qcom_dev_pm_ops = {
902 	SET_SYSTEM_SLEEP_PM_OPS(dwc3_qcom_pm_suspend, dwc3_qcom_pm_resume)
903 	SET_RUNTIME_PM_OPS(dwc3_qcom_runtime_suspend, dwc3_qcom_runtime_resume,
904 			   NULL)
905 };
906 
907 static const struct of_device_id dwc3_qcom_of_match[] = {
908 	{ .compatible = "qcom,dwc3" },
909 	{ .compatible = "qcom,msm8996-dwc3" },
910 	{ .compatible = "qcom,msm8998-dwc3" },
911 	{ .compatible = "qcom,sdm845-dwc3" },
912 	{ }
913 };
914 MODULE_DEVICE_TABLE(of, dwc3_qcom_of_match);
915 
916 #ifdef CONFIG_ACPI
917 static const struct dwc3_acpi_pdata sdm845_acpi_pdata = {
918 	.qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET,
919 	.qscratch_base_size = SDM845_QSCRATCH_SIZE,
920 	.dwc3_core_base_size = SDM845_DWC3_CORE_SIZE,
921 	.hs_phy_irq_index = 1,
922 	.dp_hs_phy_irq_index = 4,
923 	.dm_hs_phy_irq_index = 3,
924 	.ss_phy_irq_index = 2
925 };
926 
927 static const struct dwc3_acpi_pdata sdm845_acpi_urs_pdata = {
928 	.qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET,
929 	.qscratch_base_size = SDM845_QSCRATCH_SIZE,
930 	.dwc3_core_base_size = SDM845_DWC3_CORE_SIZE,
931 	.hs_phy_irq_index = 1,
932 	.dp_hs_phy_irq_index = 4,
933 	.dm_hs_phy_irq_index = 3,
934 	.ss_phy_irq_index = 2,
935 	.is_urs = true,
936 };
937 
938 static const struct acpi_device_id dwc3_qcom_acpi_match[] = {
939 	{ "QCOM2430", (unsigned long)&sdm845_acpi_pdata },
940 	{ "QCOM0304", (unsigned long)&sdm845_acpi_urs_pdata },
941 	{ },
942 };
943 MODULE_DEVICE_TABLE(acpi, dwc3_qcom_acpi_match);
944 #endif
945 
946 static struct platform_driver dwc3_qcom_driver = {
947 	.probe		= dwc3_qcom_probe,
948 	.remove		= dwc3_qcom_remove,
949 	.driver		= {
950 		.name	= "dwc3-qcom",
951 		.pm	= &dwc3_qcom_dev_pm_ops,
952 		.of_match_table	= dwc3_qcom_of_match,
953 		.acpi_match_table = ACPI_PTR(dwc3_qcom_acpi_match),
954 	},
955 };
956 
957 module_platform_driver(dwc3_qcom_driver);
958 
959 MODULE_LICENSE("GPL v2");
960 MODULE_DESCRIPTION("DesignWare DWC3 QCOM Glue Driver");
961