1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018, The Linux Foundation. All rights reserved. 3 * 4 * Inspired by dwc3-of-simple.c 5 */ 6 7 #include <linux/io.h> 8 #include <linux/of.h> 9 #include <linux/clk.h> 10 #include <linux/irq.h> 11 #include <linux/of_clk.h> 12 #include <linux/module.h> 13 #include <linux/kernel.h> 14 #include <linux/extcon.h> 15 #include <linux/interconnect.h> 16 #include <linux/of_platform.h> 17 #include <linux/platform_device.h> 18 #include <linux/phy/phy.h> 19 #include <linux/usb/of.h> 20 #include <linux/reset.h> 21 #include <linux/iopoll.h> 22 #include <linux/usb/hcd.h> 23 #include <linux/usb.h> 24 #include "core.h" 25 26 /* USB QSCRATCH Hardware registers */ 27 #define QSCRATCH_HS_PHY_CTRL 0x10 28 #define UTMI_OTG_VBUS_VALID BIT(20) 29 #define SW_SESSVLD_SEL BIT(28) 30 31 #define QSCRATCH_SS_PHY_CTRL 0x30 32 #define LANE0_PWR_PRESENT BIT(24) 33 34 #define QSCRATCH_GENERAL_CFG 0x08 35 #define PIPE_UTMI_CLK_SEL BIT(0) 36 #define PIPE3_PHYSTATUS_SW BIT(3) 37 #define PIPE_UTMI_CLK_DIS BIT(8) 38 39 #define PWR_EVNT_LPM_IN_L2_MASK BIT(4) 40 #define PWR_EVNT_LPM_OUT_L2_MASK BIT(5) 41 42 #define SDM845_QSCRATCH_BASE_OFFSET 0xf8800 43 #define SDM845_QSCRATCH_SIZE 0x400 44 #define SDM845_DWC3_CORE_SIZE 0xcd00 45 46 /* Interconnect path bandwidths in MBps */ 47 #define USB_MEMORY_AVG_HS_BW MBps_to_icc(240) 48 #define USB_MEMORY_PEAK_HS_BW MBps_to_icc(700) 49 #define USB_MEMORY_AVG_SS_BW MBps_to_icc(1000) 50 #define USB_MEMORY_PEAK_SS_BW MBps_to_icc(2500) 51 #define APPS_USB_AVG_BW 0 52 #define APPS_USB_PEAK_BW MBps_to_icc(40) 53 54 /* Qualcomm SoCs with multiport support has up to 4 ports */ 55 #define DWC3_QCOM_MAX_PORTS 4 56 57 static const u32 pwr_evnt_irq_stat_reg[DWC3_QCOM_MAX_PORTS] = { 58 0x58, 59 0x1dc, 60 0x228, 61 0x238, 62 }; 63 64 struct dwc3_qcom_port { 65 int qusb2_phy_irq; 66 int dp_hs_phy_irq; 67 int dm_hs_phy_irq; 68 int ss_phy_irq; 69 enum usb_device_speed usb2_speed; 70 }; 71 72 struct dwc3_qcom { 73 struct device *dev; 74 void __iomem *qscratch_base; 75 struct platform_device *dwc3; 76 struct clk **clks; 77 int num_clocks; 78 struct reset_control *resets; 79 struct dwc3_qcom_port ports[DWC3_QCOM_MAX_PORTS]; 80 u8 num_ports; 81 82 struct extcon_dev *edev; 83 struct extcon_dev *host_edev; 84 struct notifier_block vbus_nb; 85 struct notifier_block host_nb; 86 87 enum usb_dr_mode mode; 88 bool is_suspended; 89 bool pm_suspended; 90 struct icc_path *icc_path_ddr; 91 struct icc_path *icc_path_apps; 92 }; 93 94 static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val) 95 { 96 u32 reg; 97 98 reg = readl(base + offset); 99 reg |= val; 100 writel(reg, base + offset); 101 102 /* ensure that above write is through */ 103 readl(base + offset); 104 } 105 106 static inline void dwc3_qcom_clrbits(void __iomem *base, u32 offset, u32 val) 107 { 108 u32 reg; 109 110 reg = readl(base + offset); 111 reg &= ~val; 112 writel(reg, base + offset); 113 114 /* ensure that above write is through */ 115 readl(base + offset); 116 } 117 118 static void dwc3_qcom_vbus_override_enable(struct dwc3_qcom *qcom, bool enable) 119 { 120 if (enable) { 121 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL, 122 LANE0_PWR_PRESENT); 123 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL, 124 UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL); 125 } else { 126 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL, 127 LANE0_PWR_PRESENT); 128 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL, 129 UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL); 130 } 131 } 132 133 static int dwc3_qcom_vbus_notifier(struct notifier_block *nb, 134 unsigned long event, void *ptr) 135 { 136 struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, vbus_nb); 137 138 /* enable vbus override for device mode */ 139 dwc3_qcom_vbus_override_enable(qcom, event); 140 qcom->mode = event ? USB_DR_MODE_PERIPHERAL : USB_DR_MODE_HOST; 141 142 return NOTIFY_DONE; 143 } 144 145 static int dwc3_qcom_host_notifier(struct notifier_block *nb, 146 unsigned long event, void *ptr) 147 { 148 struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, host_nb); 149 150 /* disable vbus override in host mode */ 151 dwc3_qcom_vbus_override_enable(qcom, !event); 152 qcom->mode = event ? USB_DR_MODE_HOST : USB_DR_MODE_PERIPHERAL; 153 154 return NOTIFY_DONE; 155 } 156 157 static int dwc3_qcom_register_extcon(struct dwc3_qcom *qcom) 158 { 159 struct device *dev = qcom->dev; 160 struct extcon_dev *host_edev; 161 int ret; 162 163 if (!of_property_read_bool(dev->of_node, "extcon")) 164 return 0; 165 166 qcom->edev = extcon_get_edev_by_phandle(dev, 0); 167 if (IS_ERR(qcom->edev)) 168 return dev_err_probe(dev, PTR_ERR(qcom->edev), 169 "Failed to get extcon\n"); 170 171 qcom->vbus_nb.notifier_call = dwc3_qcom_vbus_notifier; 172 173 qcom->host_edev = extcon_get_edev_by_phandle(dev, 1); 174 if (IS_ERR(qcom->host_edev)) 175 qcom->host_edev = NULL; 176 177 ret = devm_extcon_register_notifier(dev, qcom->edev, EXTCON_USB, 178 &qcom->vbus_nb); 179 if (ret < 0) { 180 dev_err(dev, "VBUS notifier register failed\n"); 181 return ret; 182 } 183 184 if (qcom->host_edev) 185 host_edev = qcom->host_edev; 186 else 187 host_edev = qcom->edev; 188 189 qcom->host_nb.notifier_call = dwc3_qcom_host_notifier; 190 ret = devm_extcon_register_notifier(dev, host_edev, EXTCON_USB_HOST, 191 &qcom->host_nb); 192 if (ret < 0) { 193 dev_err(dev, "Host notifier register failed\n"); 194 return ret; 195 } 196 197 /* Update initial VBUS override based on extcon state */ 198 if (extcon_get_state(qcom->edev, EXTCON_USB) || 199 !extcon_get_state(host_edev, EXTCON_USB_HOST)) 200 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, true, qcom->edev); 201 else 202 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, false, qcom->edev); 203 204 return 0; 205 } 206 207 static int dwc3_qcom_interconnect_enable(struct dwc3_qcom *qcom) 208 { 209 int ret; 210 211 ret = icc_enable(qcom->icc_path_ddr); 212 if (ret) 213 return ret; 214 215 ret = icc_enable(qcom->icc_path_apps); 216 if (ret) 217 icc_disable(qcom->icc_path_ddr); 218 219 return ret; 220 } 221 222 static int dwc3_qcom_interconnect_disable(struct dwc3_qcom *qcom) 223 { 224 int ret; 225 226 ret = icc_disable(qcom->icc_path_ddr); 227 if (ret) 228 return ret; 229 230 ret = icc_disable(qcom->icc_path_apps); 231 if (ret) 232 icc_enable(qcom->icc_path_ddr); 233 234 return ret; 235 } 236 237 /** 238 * dwc3_qcom_interconnect_init() - Get interconnect path handles 239 * and set bandwidth. 240 * @qcom: Pointer to the concerned usb core. 241 * 242 */ 243 static int dwc3_qcom_interconnect_init(struct dwc3_qcom *qcom) 244 { 245 enum usb_device_speed max_speed; 246 struct device *dev = qcom->dev; 247 int ret; 248 249 qcom->icc_path_ddr = of_icc_get(dev, "usb-ddr"); 250 if (IS_ERR(qcom->icc_path_ddr)) { 251 return dev_err_probe(dev, PTR_ERR(qcom->icc_path_ddr), 252 "failed to get usb-ddr path\n"); 253 } 254 255 qcom->icc_path_apps = of_icc_get(dev, "apps-usb"); 256 if (IS_ERR(qcom->icc_path_apps)) { 257 ret = dev_err_probe(dev, PTR_ERR(qcom->icc_path_apps), 258 "failed to get apps-usb path\n"); 259 goto put_path_ddr; 260 } 261 262 max_speed = usb_get_maximum_speed(&qcom->dwc3->dev); 263 if (max_speed >= USB_SPEED_SUPER || max_speed == USB_SPEED_UNKNOWN) { 264 ret = icc_set_bw(qcom->icc_path_ddr, 265 USB_MEMORY_AVG_SS_BW, USB_MEMORY_PEAK_SS_BW); 266 } else { 267 ret = icc_set_bw(qcom->icc_path_ddr, 268 USB_MEMORY_AVG_HS_BW, USB_MEMORY_PEAK_HS_BW); 269 } 270 if (ret) { 271 dev_err(dev, "failed to set bandwidth for usb-ddr path: %d\n", ret); 272 goto put_path_apps; 273 } 274 275 ret = icc_set_bw(qcom->icc_path_apps, APPS_USB_AVG_BW, APPS_USB_PEAK_BW); 276 if (ret) { 277 dev_err(dev, "failed to set bandwidth for apps-usb path: %d\n", ret); 278 goto put_path_apps; 279 } 280 281 return 0; 282 283 put_path_apps: 284 icc_put(qcom->icc_path_apps); 285 put_path_ddr: 286 icc_put(qcom->icc_path_ddr); 287 return ret; 288 } 289 290 /** 291 * dwc3_qcom_interconnect_exit() - Release interconnect path handles 292 * @qcom: Pointer to the concerned usb core. 293 * 294 * This function is used to release interconnect path handle. 295 */ 296 static void dwc3_qcom_interconnect_exit(struct dwc3_qcom *qcom) 297 { 298 icc_put(qcom->icc_path_ddr); 299 icc_put(qcom->icc_path_apps); 300 } 301 302 /* Only usable in contexts where the role can not change. */ 303 static bool dwc3_qcom_is_host(struct dwc3_qcom *qcom) 304 { 305 struct dwc3 *dwc; 306 307 /* 308 * FIXME: Fix this layering violation. 309 */ 310 dwc = platform_get_drvdata(qcom->dwc3); 311 312 /* Core driver may not have probed yet. */ 313 if (!dwc) 314 return false; 315 316 return dwc->xhci; 317 } 318 319 static enum usb_device_speed dwc3_qcom_read_usb2_speed(struct dwc3_qcom *qcom, int port_index) 320 { 321 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3); 322 struct usb_device *udev; 323 struct usb_hcd __maybe_unused *hcd; 324 325 /* 326 * FIXME: Fix this layering violation. 327 */ 328 hcd = platform_get_drvdata(dwc->xhci); 329 330 #ifdef CONFIG_USB 331 udev = usb_hub_find_child(hcd->self.root_hub, port_index + 1); 332 #else 333 udev = NULL; 334 #endif 335 if (!udev) 336 return USB_SPEED_UNKNOWN; 337 338 return udev->speed; 339 } 340 341 static void dwc3_qcom_enable_wakeup_irq(int irq, unsigned int polarity) 342 { 343 if (!irq) 344 return; 345 346 if (polarity) 347 irq_set_irq_type(irq, polarity); 348 349 enable_irq(irq); 350 enable_irq_wake(irq); 351 } 352 353 static void dwc3_qcom_disable_wakeup_irq(int irq) 354 { 355 if (!irq) 356 return; 357 358 disable_irq_wake(irq); 359 disable_irq_nosync(irq); 360 } 361 362 static void dwc3_qcom_disable_port_interrupts(struct dwc3_qcom_port *port) 363 { 364 dwc3_qcom_disable_wakeup_irq(port->qusb2_phy_irq); 365 366 if (port->usb2_speed == USB_SPEED_LOW) { 367 dwc3_qcom_disable_wakeup_irq(port->dm_hs_phy_irq); 368 } else if ((port->usb2_speed == USB_SPEED_HIGH) || 369 (port->usb2_speed == USB_SPEED_FULL)) { 370 dwc3_qcom_disable_wakeup_irq(port->dp_hs_phy_irq); 371 } else { 372 dwc3_qcom_disable_wakeup_irq(port->dp_hs_phy_irq); 373 dwc3_qcom_disable_wakeup_irq(port->dm_hs_phy_irq); 374 } 375 376 dwc3_qcom_disable_wakeup_irq(port->ss_phy_irq); 377 } 378 379 static void dwc3_qcom_enable_port_interrupts(struct dwc3_qcom_port *port) 380 { 381 dwc3_qcom_enable_wakeup_irq(port->qusb2_phy_irq, 0); 382 383 /* 384 * Configure DP/DM line interrupts based on the USB2 device attached to 385 * the root hub port. When HS/FS device is connected, configure the DP line 386 * as falling edge to detect both disconnect and remote wakeup scenarios. When 387 * LS device is connected, configure DM line as falling edge to detect both 388 * disconnect and remote wakeup. When no device is connected, configure both 389 * DP and DM lines as rising edge to detect HS/HS/LS device connect scenario. 390 */ 391 392 if (port->usb2_speed == USB_SPEED_LOW) { 393 dwc3_qcom_enable_wakeup_irq(port->dm_hs_phy_irq, 394 IRQ_TYPE_EDGE_FALLING); 395 } else if ((port->usb2_speed == USB_SPEED_HIGH) || 396 (port->usb2_speed == USB_SPEED_FULL)) { 397 dwc3_qcom_enable_wakeup_irq(port->dp_hs_phy_irq, 398 IRQ_TYPE_EDGE_FALLING); 399 } else { 400 dwc3_qcom_enable_wakeup_irq(port->dp_hs_phy_irq, 401 IRQ_TYPE_EDGE_RISING); 402 dwc3_qcom_enable_wakeup_irq(port->dm_hs_phy_irq, 403 IRQ_TYPE_EDGE_RISING); 404 } 405 406 dwc3_qcom_enable_wakeup_irq(port->ss_phy_irq, 0); 407 } 408 409 static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom) 410 { 411 int i; 412 413 for (i = 0; i < qcom->num_ports; i++) 414 dwc3_qcom_disable_port_interrupts(&qcom->ports[i]); 415 } 416 417 static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom) 418 { 419 int i; 420 421 for (i = 0; i < qcom->num_ports; i++) 422 dwc3_qcom_enable_port_interrupts(&qcom->ports[i]); 423 } 424 425 static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup) 426 { 427 u32 val; 428 int i, ret; 429 430 if (qcom->is_suspended) 431 return 0; 432 433 for (i = 0; i < qcom->num_ports; i++) { 434 val = readl(qcom->qscratch_base + pwr_evnt_irq_stat_reg[i]); 435 if (!(val & PWR_EVNT_LPM_IN_L2_MASK)) 436 dev_err(qcom->dev, "port-%d HS-PHY not in L2\n", i + 1); 437 } 438 439 for (i = qcom->num_clocks - 1; i >= 0; i--) 440 clk_disable_unprepare(qcom->clks[i]); 441 442 ret = dwc3_qcom_interconnect_disable(qcom); 443 if (ret) 444 dev_warn(qcom->dev, "failed to disable interconnect: %d\n", ret); 445 446 /* 447 * The role is stable during suspend as role switching is done from a 448 * freezable workqueue. 449 */ 450 if (dwc3_qcom_is_host(qcom) && wakeup) { 451 for (i = 0; i < qcom->num_ports; i++) 452 qcom->ports[i].usb2_speed = dwc3_qcom_read_usb2_speed(qcom, i); 453 dwc3_qcom_enable_interrupts(qcom); 454 } 455 456 qcom->is_suspended = true; 457 458 return 0; 459 } 460 461 static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup) 462 { 463 int ret; 464 int i; 465 466 if (!qcom->is_suspended) 467 return 0; 468 469 if (dwc3_qcom_is_host(qcom) && wakeup) 470 dwc3_qcom_disable_interrupts(qcom); 471 472 for (i = 0; i < qcom->num_clocks; i++) { 473 ret = clk_prepare_enable(qcom->clks[i]); 474 if (ret < 0) { 475 while (--i >= 0) 476 clk_disable_unprepare(qcom->clks[i]); 477 return ret; 478 } 479 } 480 481 ret = dwc3_qcom_interconnect_enable(qcom); 482 if (ret) 483 dev_warn(qcom->dev, "failed to enable interconnect: %d\n", ret); 484 485 /* Clear existing events from PHY related to L2 in/out */ 486 for (i = 0; i < qcom->num_ports; i++) { 487 dwc3_qcom_setbits(qcom->qscratch_base, 488 pwr_evnt_irq_stat_reg[i], 489 PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK); 490 } 491 492 qcom->is_suspended = false; 493 494 return 0; 495 } 496 497 static irqreturn_t qcom_dwc3_resume_irq(int irq, void *data) 498 { 499 struct dwc3_qcom *qcom = data; 500 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3); 501 502 /* If pm_suspended then let pm_resume take care of resuming h/w */ 503 if (qcom->pm_suspended) 504 return IRQ_HANDLED; 505 506 /* 507 * This is safe as role switching is done from a freezable workqueue 508 * and the wakeup interrupts are disabled as part of resume. 509 */ 510 if (dwc3_qcom_is_host(qcom)) 511 pm_runtime_resume(&dwc->xhci->dev); 512 513 return IRQ_HANDLED; 514 } 515 516 static void dwc3_qcom_select_utmi_clk(struct dwc3_qcom *qcom) 517 { 518 /* Configure dwc3 to use UTMI clock as PIPE clock not present */ 519 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG, 520 PIPE_UTMI_CLK_DIS); 521 522 usleep_range(100, 1000); 523 524 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG, 525 PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW); 526 527 usleep_range(100, 1000); 528 529 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG, 530 PIPE_UTMI_CLK_DIS); 531 } 532 533 static int dwc3_qcom_request_irq(struct dwc3_qcom *qcom, int irq, 534 const char *name) 535 { 536 int ret; 537 538 /* Keep wakeup interrupts disabled until suspend */ 539 ret = devm_request_threaded_irq(qcom->dev, irq, NULL, 540 qcom_dwc3_resume_irq, 541 IRQF_ONESHOT | IRQF_NO_AUTOEN, 542 name, qcom); 543 if (ret) 544 dev_err(qcom->dev, "failed to request irq %s: %d\n", name, ret); 545 546 return ret; 547 } 548 549 static int dwc3_qcom_setup_port_irq(struct platform_device *pdev, int port_index, bool is_multiport) 550 { 551 struct dwc3_qcom *qcom = platform_get_drvdata(pdev); 552 const char *irq_name; 553 int irq; 554 int ret; 555 556 if (is_multiport) 557 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "dp_hs_phy_%d", port_index + 1); 558 else 559 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "dp_hs_phy_irq"); 560 if (!irq_name) 561 return -ENOMEM; 562 563 irq = platform_get_irq_byname_optional(pdev, irq_name); 564 if (irq > 0) { 565 ret = dwc3_qcom_request_irq(qcom, irq, irq_name); 566 if (ret) 567 return ret; 568 qcom->ports[port_index].dp_hs_phy_irq = irq; 569 } 570 571 if (is_multiport) 572 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "dm_hs_phy_%d", port_index + 1); 573 else 574 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "dm_hs_phy_irq"); 575 if (!irq_name) 576 return -ENOMEM; 577 578 irq = platform_get_irq_byname_optional(pdev, irq_name); 579 if (irq > 0) { 580 ret = dwc3_qcom_request_irq(qcom, irq, irq_name); 581 if (ret) 582 return ret; 583 qcom->ports[port_index].dm_hs_phy_irq = irq; 584 } 585 586 if (is_multiport) 587 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "ss_phy_%d", port_index + 1); 588 else 589 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "ss_phy_irq"); 590 if (!irq_name) 591 return -ENOMEM; 592 593 irq = platform_get_irq_byname_optional(pdev, irq_name); 594 if (irq > 0) { 595 ret = dwc3_qcom_request_irq(qcom, irq, irq_name); 596 if (ret) 597 return ret; 598 qcom->ports[port_index].ss_phy_irq = irq; 599 } 600 601 if (is_multiport) 602 return 0; 603 604 irq = platform_get_irq_byname_optional(pdev, "qusb2_phy"); 605 if (irq > 0) { 606 ret = dwc3_qcom_request_irq(qcom, irq, "qusb2_phy"); 607 if (ret) 608 return ret; 609 qcom->ports[port_index].qusb2_phy_irq = irq; 610 } 611 612 return 0; 613 } 614 615 static int dwc3_qcom_find_num_ports(struct platform_device *pdev) 616 { 617 char irq_name[14]; 618 int port_num; 619 int irq; 620 621 irq = platform_get_irq_byname_optional(pdev, "dp_hs_phy_1"); 622 if (irq <= 0) 623 return 1; 624 625 for (port_num = 2; port_num <= DWC3_QCOM_MAX_PORTS; port_num++) { 626 sprintf(irq_name, "dp_hs_phy_%d", port_num); 627 628 irq = platform_get_irq_byname_optional(pdev, irq_name); 629 if (irq <= 0) 630 return port_num - 1; 631 } 632 633 return DWC3_QCOM_MAX_PORTS; 634 } 635 636 static int dwc3_qcom_setup_irq(struct platform_device *pdev) 637 { 638 struct dwc3_qcom *qcom = platform_get_drvdata(pdev); 639 bool is_multiport; 640 int ret; 641 int i; 642 643 qcom->num_ports = dwc3_qcom_find_num_ports(pdev); 644 is_multiport = (qcom->num_ports > 1); 645 646 for (i = 0; i < qcom->num_ports; i++) { 647 ret = dwc3_qcom_setup_port_irq(pdev, i, is_multiport); 648 if (ret) 649 return ret; 650 } 651 652 return 0; 653 } 654 655 static int dwc3_qcom_clk_init(struct dwc3_qcom *qcom, int count) 656 { 657 struct device *dev = qcom->dev; 658 struct device_node *np = dev->of_node; 659 int i; 660 661 if (!np || !count) 662 return 0; 663 664 if (count < 0) 665 return count; 666 667 qcom->num_clocks = count; 668 669 qcom->clks = devm_kcalloc(dev, qcom->num_clocks, 670 sizeof(struct clk *), GFP_KERNEL); 671 if (!qcom->clks) 672 return -ENOMEM; 673 674 for (i = 0; i < qcom->num_clocks; i++) { 675 struct clk *clk; 676 int ret; 677 678 clk = of_clk_get(np, i); 679 if (IS_ERR(clk)) { 680 while (--i >= 0) 681 clk_put(qcom->clks[i]); 682 return PTR_ERR(clk); 683 } 684 685 ret = clk_prepare_enable(clk); 686 if (ret < 0) { 687 while (--i >= 0) { 688 clk_disable_unprepare(qcom->clks[i]); 689 clk_put(qcom->clks[i]); 690 } 691 clk_put(clk); 692 693 return ret; 694 } 695 696 qcom->clks[i] = clk; 697 } 698 699 return 0; 700 } 701 702 static int dwc3_qcom_of_register_core(struct platform_device *pdev) 703 { 704 struct dwc3_qcom *qcom = platform_get_drvdata(pdev); 705 struct device_node *np = pdev->dev.of_node, *dwc3_np; 706 struct device *dev = &pdev->dev; 707 int ret; 708 709 dwc3_np = of_get_compatible_child(np, "snps,dwc3"); 710 if (!dwc3_np) { 711 dev_err(dev, "failed to find dwc3 core child\n"); 712 return -ENODEV; 713 } 714 715 ret = of_platform_populate(np, NULL, NULL, dev); 716 if (ret) { 717 dev_err(dev, "failed to register dwc3 core - %d\n", ret); 718 goto node_put; 719 } 720 721 qcom->dwc3 = of_find_device_by_node(dwc3_np); 722 if (!qcom->dwc3) { 723 ret = -ENODEV; 724 dev_err(dev, "failed to get dwc3 platform device\n"); 725 of_platform_depopulate(dev); 726 } 727 728 node_put: 729 of_node_put(dwc3_np); 730 731 return ret; 732 } 733 734 static int dwc3_qcom_probe(struct platform_device *pdev) 735 { 736 struct device_node *np = pdev->dev.of_node; 737 struct device *dev = &pdev->dev; 738 struct dwc3_qcom *qcom; 739 struct resource *res; 740 int ret, i; 741 bool ignore_pipe_clk; 742 bool wakeup_source; 743 744 qcom = devm_kzalloc(&pdev->dev, sizeof(*qcom), GFP_KERNEL); 745 if (!qcom) 746 return -ENOMEM; 747 748 platform_set_drvdata(pdev, qcom); 749 qcom->dev = &pdev->dev; 750 751 qcom->resets = devm_reset_control_array_get_optional_exclusive(dev); 752 if (IS_ERR(qcom->resets)) { 753 return dev_err_probe(&pdev->dev, PTR_ERR(qcom->resets), 754 "failed to get resets\n"); 755 } 756 757 ret = reset_control_assert(qcom->resets); 758 if (ret) { 759 dev_err(&pdev->dev, "failed to assert resets, err=%d\n", ret); 760 return ret; 761 } 762 763 usleep_range(10, 1000); 764 765 ret = reset_control_deassert(qcom->resets); 766 if (ret) { 767 dev_err(&pdev->dev, "failed to deassert resets, err=%d\n", ret); 768 goto reset_assert; 769 } 770 771 ret = dwc3_qcom_clk_init(qcom, of_clk_get_parent_count(np)); 772 if (ret) { 773 dev_err_probe(dev, ret, "failed to get clocks\n"); 774 goto reset_assert; 775 } 776 777 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 778 779 qcom->qscratch_base = devm_ioremap_resource(dev, res); 780 if (IS_ERR(qcom->qscratch_base)) { 781 ret = PTR_ERR(qcom->qscratch_base); 782 goto clk_disable; 783 } 784 785 ret = dwc3_qcom_setup_irq(pdev); 786 if (ret) { 787 dev_err(dev, "failed to setup IRQs, err=%d\n", ret); 788 goto clk_disable; 789 } 790 791 /* 792 * Disable pipe_clk requirement if specified. Used when dwc3 793 * operates without SSPHY and only HS/FS/LS modes are supported. 794 */ 795 ignore_pipe_clk = device_property_read_bool(dev, 796 "qcom,select-utmi-as-pipe-clk"); 797 if (ignore_pipe_clk) 798 dwc3_qcom_select_utmi_clk(qcom); 799 800 ret = dwc3_qcom_of_register_core(pdev); 801 if (ret) { 802 dev_err(dev, "failed to register DWC3 Core, err=%d\n", ret); 803 goto clk_disable; 804 } 805 806 ret = dwc3_qcom_interconnect_init(qcom); 807 if (ret) 808 goto depopulate; 809 810 qcom->mode = usb_get_dr_mode(&qcom->dwc3->dev); 811 812 /* enable vbus override for device mode */ 813 if (qcom->mode != USB_DR_MODE_HOST) 814 dwc3_qcom_vbus_override_enable(qcom, true); 815 816 /* register extcon to override sw_vbus on Vbus change later */ 817 ret = dwc3_qcom_register_extcon(qcom); 818 if (ret) 819 goto interconnect_exit; 820 821 wakeup_source = of_property_read_bool(dev->of_node, "wakeup-source"); 822 device_init_wakeup(&pdev->dev, wakeup_source); 823 device_init_wakeup(&qcom->dwc3->dev, wakeup_source); 824 825 qcom->is_suspended = false; 826 pm_runtime_set_active(dev); 827 pm_runtime_enable(dev); 828 pm_runtime_forbid(dev); 829 830 return 0; 831 832 interconnect_exit: 833 dwc3_qcom_interconnect_exit(qcom); 834 depopulate: 835 of_platform_depopulate(&pdev->dev); 836 platform_device_put(qcom->dwc3); 837 clk_disable: 838 for (i = qcom->num_clocks - 1; i >= 0; i--) { 839 clk_disable_unprepare(qcom->clks[i]); 840 clk_put(qcom->clks[i]); 841 } 842 reset_assert: 843 reset_control_assert(qcom->resets); 844 845 return ret; 846 } 847 848 static void dwc3_qcom_remove(struct platform_device *pdev) 849 { 850 struct dwc3_qcom *qcom = platform_get_drvdata(pdev); 851 struct device *dev = &pdev->dev; 852 int i; 853 854 of_platform_depopulate(&pdev->dev); 855 platform_device_put(qcom->dwc3); 856 857 for (i = qcom->num_clocks - 1; i >= 0; i--) { 858 clk_disable_unprepare(qcom->clks[i]); 859 clk_put(qcom->clks[i]); 860 } 861 qcom->num_clocks = 0; 862 863 dwc3_qcom_interconnect_exit(qcom); 864 reset_control_assert(qcom->resets); 865 866 pm_runtime_allow(dev); 867 pm_runtime_disable(dev); 868 } 869 870 static int __maybe_unused dwc3_qcom_pm_suspend(struct device *dev) 871 { 872 struct dwc3_qcom *qcom = dev_get_drvdata(dev); 873 bool wakeup = device_may_wakeup(dev); 874 int ret; 875 876 ret = dwc3_qcom_suspend(qcom, wakeup); 877 if (ret) 878 return ret; 879 880 qcom->pm_suspended = true; 881 882 return 0; 883 } 884 885 static int __maybe_unused dwc3_qcom_pm_resume(struct device *dev) 886 { 887 struct dwc3_qcom *qcom = dev_get_drvdata(dev); 888 bool wakeup = device_may_wakeup(dev); 889 int ret; 890 891 ret = dwc3_qcom_resume(qcom, wakeup); 892 if (ret) 893 return ret; 894 895 qcom->pm_suspended = false; 896 897 return 0; 898 } 899 900 static int __maybe_unused dwc3_qcom_runtime_suspend(struct device *dev) 901 { 902 struct dwc3_qcom *qcom = dev_get_drvdata(dev); 903 904 return dwc3_qcom_suspend(qcom, true); 905 } 906 907 static int __maybe_unused dwc3_qcom_runtime_resume(struct device *dev) 908 { 909 struct dwc3_qcom *qcom = dev_get_drvdata(dev); 910 911 return dwc3_qcom_resume(qcom, true); 912 } 913 914 static const struct dev_pm_ops dwc3_qcom_dev_pm_ops = { 915 SET_SYSTEM_SLEEP_PM_OPS(dwc3_qcom_pm_suspend, dwc3_qcom_pm_resume) 916 SET_RUNTIME_PM_OPS(dwc3_qcom_runtime_suspend, dwc3_qcom_runtime_resume, 917 NULL) 918 }; 919 920 static const struct of_device_id dwc3_qcom_of_match[] = { 921 { .compatible = "qcom,dwc3" }, 922 { } 923 }; 924 MODULE_DEVICE_TABLE(of, dwc3_qcom_of_match); 925 926 static struct platform_driver dwc3_qcom_driver = { 927 .probe = dwc3_qcom_probe, 928 .remove_new = dwc3_qcom_remove, 929 .driver = { 930 .name = "dwc3-qcom", 931 .pm = &dwc3_qcom_dev_pm_ops, 932 .of_match_table = dwc3_qcom_of_match, 933 }, 934 }; 935 936 module_platform_driver(dwc3_qcom_driver); 937 938 MODULE_LICENSE("GPL v2"); 939 MODULE_DESCRIPTION("DesignWare DWC3 QCOM Glue Driver"); 940