1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * dwc3-pci.c - PCI Specific glue layer 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/slab.h> 14 #include <linux/pci.h> 15 #include <linux/workqueue.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/platform_device.h> 18 #include <linux/gpio/consumer.h> 19 #include <linux/gpio/machine.h> 20 #include <linux/acpi.h> 21 #include <linux/delay.h> 22 23 #define PCI_DEVICE_ID_INTEL_BYT 0x0f37 24 #define PCI_DEVICE_ID_INTEL_MRFLD 0x119e 25 #define PCI_DEVICE_ID_INTEL_BSW 0x22b7 26 #define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30 27 #define PCI_DEVICE_ID_INTEL_SPTH 0xa130 28 #define PCI_DEVICE_ID_INTEL_BXT 0x0aaa 29 #define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa 30 #define PCI_DEVICE_ID_INTEL_APL 0x5aaa 31 #define PCI_DEVICE_ID_INTEL_KBP 0xa2b0 32 #define PCI_DEVICE_ID_INTEL_CMLLP 0x02ee 33 #define PCI_DEVICE_ID_INTEL_CMLH 0x06ee 34 #define PCI_DEVICE_ID_INTEL_GLK 0x31aa 35 #define PCI_DEVICE_ID_INTEL_CNPLP 0x9dee 36 #define PCI_DEVICE_ID_INTEL_CNPH 0xa36e 37 #define PCI_DEVICE_ID_INTEL_CNPV 0xa3b0 38 #define PCI_DEVICE_ID_INTEL_ICLLP 0x34ee 39 #define PCI_DEVICE_ID_INTEL_EHL 0x4b7e 40 #define PCI_DEVICE_ID_INTEL_TGPLP 0xa0ee 41 #define PCI_DEVICE_ID_INTEL_TGPH 0x43ee 42 #define PCI_DEVICE_ID_INTEL_JSP 0x4dee 43 #define PCI_DEVICE_ID_INTEL_ADL 0x460e 44 #define PCI_DEVICE_ID_INTEL_ADL_PCH 0x51ee 45 #define PCI_DEVICE_ID_INTEL_ADLN 0x465e 46 #define PCI_DEVICE_ID_INTEL_ADLN_PCH 0x54ee 47 #define PCI_DEVICE_ID_INTEL_ADLS 0x7ae1 48 #define PCI_DEVICE_ID_INTEL_RPL 0x460e 49 #define PCI_DEVICE_ID_INTEL_RPLS 0x7a61 50 #define PCI_DEVICE_ID_INTEL_MTLP 0x7ec1 51 #define PCI_DEVICE_ID_INTEL_MTL 0x7e7e 52 #define PCI_DEVICE_ID_INTEL_TGL 0x9a15 53 #define PCI_DEVICE_ID_AMD_MR 0x163a 54 55 #define PCI_INTEL_BXT_DSM_GUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511" 56 #define PCI_INTEL_BXT_FUNC_PMU_PWR 4 57 #define PCI_INTEL_BXT_STATE_D0 0 58 #define PCI_INTEL_BXT_STATE_D3 3 59 60 #define GP_RWBAR 1 61 #define GP_RWREG1 0xa0 62 #define GP_RWREG1_ULPI_REFCLK_DISABLE (1 << 17) 63 64 /** 65 * struct dwc3_pci - Driver private structure 66 * @dwc3: child dwc3 platform_device 67 * @pci: our link to PCI bus 68 * @guid: _DSM GUID 69 * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM 70 * @wakeup_work: work for asynchronous resume 71 */ 72 struct dwc3_pci { 73 struct platform_device *dwc3; 74 struct pci_dev *pci; 75 76 guid_t guid; 77 78 unsigned int has_dsm_for_pm:1; 79 struct work_struct wakeup_work; 80 }; 81 82 static const struct acpi_gpio_params reset_gpios = { 0, 0, false }; 83 static const struct acpi_gpio_params cs_gpios = { 1, 0, false }; 84 85 static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = { 86 { "reset-gpios", &reset_gpios, 1 }, 87 { "cs-gpios", &cs_gpios, 1 }, 88 { }, 89 }; 90 91 static struct gpiod_lookup_table platform_bytcr_gpios = { 92 .dev_id = "0000:00:16.0", 93 .table = { 94 GPIO_LOOKUP("INT33FC:00", 54, "cs", GPIO_ACTIVE_HIGH), 95 GPIO_LOOKUP("INT33FC:02", 14, "reset", GPIO_ACTIVE_HIGH), 96 {} 97 }, 98 }; 99 100 static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci) 101 { 102 void __iomem *reg; 103 u32 value; 104 105 reg = pcim_iomap(pci, GP_RWBAR, 0); 106 if (!reg) 107 return -ENOMEM; 108 109 value = readl(reg + GP_RWREG1); 110 if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE)) 111 goto unmap; /* ULPI refclk already enabled */ 112 113 value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE; 114 writel(value, reg + GP_RWREG1); 115 /* This comes from the Intel Android x86 tree w/o any explanation */ 116 msleep(100); 117 unmap: 118 pcim_iounmap(pci, reg); 119 return 0; 120 } 121 122 static const struct property_entry dwc3_pci_intel_properties[] = { 123 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"), 124 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 125 {} 126 }; 127 128 static const struct property_entry dwc3_pci_intel_phy_charger_detect_properties[] = { 129 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"), 130 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), 131 PROPERTY_ENTRY_BOOL("linux,phy_charger_detect"), 132 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 133 {} 134 }; 135 136 static const struct property_entry dwc3_pci_intel_byt_properties[] = { 137 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"), 138 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), 139 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 140 {} 141 }; 142 143 static const struct property_entry dwc3_pci_mrfld_properties[] = { 144 PROPERTY_ENTRY_STRING("dr_mode", "otg"), 145 PROPERTY_ENTRY_STRING("linux,extcon-name", "mrfld_bcove_pwrsrc"), 146 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"), 147 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), 148 PROPERTY_ENTRY_BOOL("snps,usb2-gadget-lpm-disable"), 149 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 150 {} 151 }; 152 153 static const struct property_entry dwc3_pci_amd_properties[] = { 154 PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"), 155 PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf), 156 PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"), 157 PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"), 158 PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"), 159 PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"), 160 PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"), 161 PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"), 162 PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"), 163 PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"), 164 PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1), 165 /* FIXME these quirks should be removed when AMD NL tapes out */ 166 PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"), 167 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"), 168 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), 169 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 170 {} 171 }; 172 173 static const struct property_entry dwc3_pci_mr_properties[] = { 174 PROPERTY_ENTRY_STRING("dr_mode", "otg"), 175 PROPERTY_ENTRY_BOOL("usb-role-switch"), 176 PROPERTY_ENTRY_STRING("role-switch-default-mode", "host"), 177 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 178 {} 179 }; 180 181 static const struct software_node dwc3_pci_intel_swnode = { 182 .properties = dwc3_pci_intel_properties, 183 }; 184 185 static const struct software_node dwc3_pci_intel_phy_charger_detect_swnode = { 186 .properties = dwc3_pci_intel_phy_charger_detect_properties, 187 }; 188 189 static const struct software_node dwc3_pci_intel_byt_swnode = { 190 .properties = dwc3_pci_intel_byt_properties, 191 }; 192 193 static const struct software_node dwc3_pci_intel_mrfld_swnode = { 194 .properties = dwc3_pci_mrfld_properties, 195 }; 196 197 static const struct software_node dwc3_pci_amd_swnode = { 198 .properties = dwc3_pci_amd_properties, 199 }; 200 201 static const struct software_node dwc3_pci_amd_mr_swnode = { 202 .properties = dwc3_pci_mr_properties, 203 }; 204 205 static int dwc3_pci_quirks(struct dwc3_pci *dwc, 206 const struct software_node *swnode) 207 { 208 struct pci_dev *pdev = dwc->pci; 209 210 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 211 if (pdev->device == PCI_DEVICE_ID_INTEL_BXT || 212 pdev->device == PCI_DEVICE_ID_INTEL_BXT_M || 213 pdev->device == PCI_DEVICE_ID_INTEL_EHL) { 214 guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid); 215 dwc->has_dsm_for_pm = true; 216 } 217 218 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) { 219 struct gpio_desc *gpio; 220 int ret; 221 222 /* On BYT the FW does not always enable the refclock */ 223 ret = dwc3_byt_enable_ulpi_refclock(pdev); 224 if (ret) 225 return ret; 226 227 ret = devm_acpi_dev_add_driver_gpios(&pdev->dev, 228 acpi_dwc3_byt_gpios); 229 if (ret) 230 dev_dbg(&pdev->dev, "failed to add mapping table\n"); 231 232 /* 233 * A lot of BYT devices lack ACPI resource entries for 234 * the GPIOs, add a fallback mapping to the reference 235 * design GPIOs which all boards seem to use. 236 */ 237 gpiod_add_lookup_table(&platform_bytcr_gpios); 238 239 /* 240 * These GPIOs will turn on the USB2 PHY. Note that we have to 241 * put the gpio descriptors again here because the phy driver 242 * might want to grab them, too. 243 */ 244 gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW); 245 if (IS_ERR(gpio)) 246 return PTR_ERR(gpio); 247 248 gpiod_set_value_cansleep(gpio, 1); 249 gpiod_put(gpio); 250 251 gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW); 252 if (IS_ERR(gpio)) 253 return PTR_ERR(gpio); 254 255 if (gpio) { 256 gpiod_set_value_cansleep(gpio, 1); 257 gpiod_put(gpio); 258 usleep_range(10000, 11000); 259 } 260 261 /* 262 * Make the pdev name predictable (only 1 DWC3 on BYT) 263 * and patch the phy dev-name into the lookup table so 264 * that the phy-driver can get the GPIOs. 265 */ 266 dwc->dwc3->id = PLATFORM_DEVID_NONE; 267 platform_bytcr_gpios.dev_id = "dwc3.ulpi"; 268 269 /* 270 * Some Android tablets with a Crystal Cove PMIC 271 * (INT33FD), rely on the TUSB1211 phy for charger 272 * detection. These can be identified by them _not_ 273 * using the standard ACPI battery and ac drivers. 274 */ 275 if (acpi_dev_present("INT33FD", "1", 2) && 276 acpi_quirk_skip_acpi_ac_and_battery()) { 277 dev_info(&pdev->dev, "Using TUSB1211 phy for charger detection\n"); 278 swnode = &dwc3_pci_intel_phy_charger_detect_swnode; 279 } 280 } 281 } 282 283 return device_add_software_node(&dwc->dwc3->dev, swnode); 284 } 285 286 #ifdef CONFIG_PM 287 static void dwc3_pci_resume_work(struct work_struct *work) 288 { 289 struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work); 290 struct platform_device *dwc3 = dwc->dwc3; 291 int ret; 292 293 ret = pm_runtime_get_sync(&dwc3->dev); 294 if (ret < 0) { 295 pm_runtime_put_sync_autosuspend(&dwc3->dev); 296 return; 297 } 298 299 pm_runtime_mark_last_busy(&dwc3->dev); 300 pm_runtime_put_sync_autosuspend(&dwc3->dev); 301 } 302 #endif 303 304 static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id) 305 { 306 struct dwc3_pci *dwc; 307 struct resource res[2]; 308 int ret; 309 struct device *dev = &pci->dev; 310 311 ret = pcim_enable_device(pci); 312 if (ret) { 313 dev_err(dev, "failed to enable pci device\n"); 314 return -ENODEV; 315 } 316 317 pci_set_master(pci); 318 319 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 320 if (!dwc) 321 return -ENOMEM; 322 323 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); 324 if (!dwc->dwc3) 325 return -ENOMEM; 326 327 memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res)); 328 329 res[0].start = pci_resource_start(pci, 0); 330 res[0].end = pci_resource_end(pci, 0); 331 res[0].name = "dwc_usb3"; 332 res[0].flags = IORESOURCE_MEM; 333 334 res[1].start = pci->irq; 335 res[1].name = "dwc_usb3"; 336 res[1].flags = IORESOURCE_IRQ; 337 338 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res)); 339 if (ret) { 340 dev_err(dev, "couldn't add resources to dwc3 device\n"); 341 goto err; 342 } 343 344 dwc->pci = pci; 345 dwc->dwc3->dev.parent = dev; 346 ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev)); 347 348 ret = dwc3_pci_quirks(dwc, (void *)id->driver_data); 349 if (ret) 350 goto err; 351 352 ret = platform_device_add(dwc->dwc3); 353 if (ret) { 354 dev_err(dev, "failed to register dwc3 device\n"); 355 goto err; 356 } 357 358 device_init_wakeup(dev, true); 359 pci_set_drvdata(pci, dwc); 360 pm_runtime_put(dev); 361 #ifdef CONFIG_PM 362 INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work); 363 #endif 364 365 return 0; 366 err: 367 device_remove_software_node(&dwc->dwc3->dev); 368 platform_device_put(dwc->dwc3); 369 return ret; 370 } 371 372 static void dwc3_pci_remove(struct pci_dev *pci) 373 { 374 struct dwc3_pci *dwc = pci_get_drvdata(pci); 375 struct pci_dev *pdev = dwc->pci; 376 377 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) 378 gpiod_remove_lookup_table(&platform_bytcr_gpios); 379 #ifdef CONFIG_PM 380 cancel_work_sync(&dwc->wakeup_work); 381 #endif 382 device_init_wakeup(&pci->dev, false); 383 pm_runtime_get(&pci->dev); 384 device_remove_software_node(&dwc->dwc3->dev); 385 platform_device_unregister(dwc->dwc3); 386 } 387 388 static const struct pci_device_id dwc3_pci_id_table[] = { 389 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BSW), 390 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 391 392 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BYT), 393 (kernel_ulong_t) &dwc3_pci_intel_byt_swnode, }, 394 395 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD), 396 (kernel_ulong_t) &dwc3_pci_intel_mrfld_swnode, }, 397 398 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLLP), 399 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 400 401 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLH), 402 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 403 404 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTLP), 405 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 406 407 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTH), 408 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 409 410 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT), 411 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 412 413 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT_M), 414 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 415 416 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_APL), 417 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 418 419 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_KBP), 420 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 421 422 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_GLK), 423 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 424 425 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPLP), 426 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 427 428 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPH), 429 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 430 431 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPV), 432 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 433 434 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICLLP), 435 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 436 437 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_EHL), 438 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 439 440 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPLP), 441 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 442 443 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPH), 444 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 445 446 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_JSP), 447 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 448 449 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADL), 450 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 451 452 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADL_PCH), 453 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 454 455 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLN), 456 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 457 458 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLN_PCH), 459 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 460 461 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLS), 462 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 463 464 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_RPL), 465 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 466 467 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_RPLS), 468 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 469 470 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTLP), 471 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 472 473 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTL), 474 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 475 476 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL), 477 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 478 479 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_NL_USB), 480 (kernel_ulong_t) &dwc3_pci_amd_swnode, }, 481 482 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_MR), 483 (kernel_ulong_t)&dwc3_pci_amd_mr_swnode, }, 484 485 { } /* Terminating Entry */ 486 }; 487 MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table); 488 489 #if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP) 490 static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param) 491 { 492 union acpi_object *obj; 493 union acpi_object tmp; 494 union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp); 495 496 if (!dwc->has_dsm_for_pm) 497 return 0; 498 499 tmp.type = ACPI_TYPE_INTEGER; 500 tmp.integer.value = param; 501 502 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid, 503 1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4); 504 if (!obj) { 505 dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n"); 506 return -EIO; 507 } 508 509 ACPI_FREE(obj); 510 511 return 0; 512 } 513 #endif /* CONFIG_PM || CONFIG_PM_SLEEP */ 514 515 #ifdef CONFIG_PM 516 static int dwc3_pci_runtime_suspend(struct device *dev) 517 { 518 struct dwc3_pci *dwc = dev_get_drvdata(dev); 519 520 if (device_can_wakeup(dev)) 521 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3); 522 523 return -EBUSY; 524 } 525 526 static int dwc3_pci_runtime_resume(struct device *dev) 527 { 528 struct dwc3_pci *dwc = dev_get_drvdata(dev); 529 int ret; 530 531 ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0); 532 if (ret) 533 return ret; 534 535 queue_work(pm_wq, &dwc->wakeup_work); 536 537 return 0; 538 } 539 #endif /* CONFIG_PM */ 540 541 #ifdef CONFIG_PM_SLEEP 542 static int dwc3_pci_suspend(struct device *dev) 543 { 544 struct dwc3_pci *dwc = dev_get_drvdata(dev); 545 546 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3); 547 } 548 549 static int dwc3_pci_resume(struct device *dev) 550 { 551 struct dwc3_pci *dwc = dev_get_drvdata(dev); 552 553 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0); 554 } 555 #endif /* CONFIG_PM_SLEEP */ 556 557 static const struct dev_pm_ops dwc3_pci_dev_pm_ops = { 558 SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume) 559 SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume, 560 NULL) 561 }; 562 563 static struct pci_driver dwc3_pci_driver = { 564 .name = "dwc3-pci", 565 .id_table = dwc3_pci_id_table, 566 .probe = dwc3_pci_probe, 567 .remove = dwc3_pci_remove, 568 .driver = { 569 .pm = &dwc3_pci_dev_pm_ops, 570 } 571 }; 572 573 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 574 MODULE_LICENSE("GPL v2"); 575 MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer"); 576 577 module_pci_driver(dwc3_pci_driver); 578