1 // SPDX-License-Identifier: GPL-2.0 2 /** 3 * dwc3-pci.c - PCI Specific glue layer 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/slab.h> 14 #include <linux/pci.h> 15 #include <linux/workqueue.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/platform_device.h> 18 #include <linux/gpio/consumer.h> 19 #include <linux/gpio/machine.h> 20 #include <linux/acpi.h> 21 #include <linux/delay.h> 22 23 #define PCI_DEVICE_ID_INTEL_BYT 0x0f37 24 #define PCI_DEVICE_ID_INTEL_MRFLD 0x119e 25 #define PCI_DEVICE_ID_INTEL_BSW 0x22b7 26 #define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30 27 #define PCI_DEVICE_ID_INTEL_SPTH 0xa130 28 #define PCI_DEVICE_ID_INTEL_BXT 0x0aaa 29 #define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa 30 #define PCI_DEVICE_ID_INTEL_APL 0x5aaa 31 #define PCI_DEVICE_ID_INTEL_KBP 0xa2b0 32 #define PCI_DEVICE_ID_INTEL_CMLLP 0x02ee 33 #define PCI_DEVICE_ID_INTEL_CMLH 0x06ee 34 #define PCI_DEVICE_ID_INTEL_GLK 0x31aa 35 #define PCI_DEVICE_ID_INTEL_CNPLP 0x9dee 36 #define PCI_DEVICE_ID_INTEL_CNPH 0xa36e 37 #define PCI_DEVICE_ID_INTEL_CNPV 0xa3b0 38 #define PCI_DEVICE_ID_INTEL_ICLLP 0x34ee 39 #define PCI_DEVICE_ID_INTEL_EHLLP 0x4b7e 40 #define PCI_DEVICE_ID_INTEL_TGPLP 0xa0ee 41 #define PCI_DEVICE_ID_INTEL_TGPH 0x43ee 42 #define PCI_DEVICE_ID_INTEL_JSP 0x4dee 43 #define PCI_DEVICE_ID_INTEL_ADLS 0x7ae1 44 45 #define PCI_INTEL_BXT_DSM_GUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511" 46 #define PCI_INTEL_BXT_FUNC_PMU_PWR 4 47 #define PCI_INTEL_BXT_STATE_D0 0 48 #define PCI_INTEL_BXT_STATE_D3 3 49 50 #define GP_RWBAR 1 51 #define GP_RWREG1 0xa0 52 #define GP_RWREG1_ULPI_REFCLK_DISABLE (1 << 17) 53 54 /** 55 * struct dwc3_pci - Driver private structure 56 * @dwc3: child dwc3 platform_device 57 * @pci: our link to PCI bus 58 * @guid: _DSM GUID 59 * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM 60 * @wakeup_work: work for asynchronous resume 61 */ 62 struct dwc3_pci { 63 struct platform_device *dwc3; 64 struct pci_dev *pci; 65 66 guid_t guid; 67 68 unsigned int has_dsm_for_pm:1; 69 struct work_struct wakeup_work; 70 }; 71 72 static const struct acpi_gpio_params reset_gpios = { 0, 0, false }; 73 static const struct acpi_gpio_params cs_gpios = { 1, 0, false }; 74 75 static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = { 76 { "reset-gpios", &reset_gpios, 1 }, 77 { "cs-gpios", &cs_gpios, 1 }, 78 { }, 79 }; 80 81 static struct gpiod_lookup_table platform_bytcr_gpios = { 82 .dev_id = "0000:00:16.0", 83 .table = { 84 GPIO_LOOKUP("INT33FC:00", 54, "reset", GPIO_ACTIVE_HIGH), 85 GPIO_LOOKUP("INT33FC:02", 14, "cs", GPIO_ACTIVE_HIGH), 86 {} 87 }, 88 }; 89 90 static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci) 91 { 92 void __iomem *reg; 93 u32 value; 94 95 reg = pcim_iomap(pci, GP_RWBAR, 0); 96 if (!reg) 97 return -ENOMEM; 98 99 value = readl(reg + GP_RWREG1); 100 if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE)) 101 goto unmap; /* ULPI refclk already enabled */ 102 103 value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE; 104 writel(value, reg + GP_RWREG1); 105 /* This comes from the Intel Android x86 tree w/o any explanation */ 106 msleep(100); 107 unmap: 108 pcim_iounmap(pci, reg); 109 return 0; 110 } 111 112 static const struct property_entry dwc3_pci_intel_properties[] = { 113 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"), 114 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 115 {} 116 }; 117 118 static const struct property_entry dwc3_pci_mrfld_properties[] = { 119 PROPERTY_ENTRY_STRING("dr_mode", "otg"), 120 PROPERTY_ENTRY_STRING("linux,extcon-name", "mrfld_bcove_pwrsrc"), 121 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 122 {} 123 }; 124 125 static const struct property_entry dwc3_pci_amd_properties[] = { 126 PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"), 127 PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf), 128 PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"), 129 PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"), 130 PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"), 131 PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"), 132 PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"), 133 PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"), 134 PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"), 135 PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"), 136 PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1), 137 /* FIXME these quirks should be removed when AMD NL tapes out */ 138 PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"), 139 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"), 140 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), 141 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 142 {} 143 }; 144 145 static int dwc3_pci_quirks(struct dwc3_pci *dwc) 146 { 147 struct pci_dev *pdev = dwc->pci; 148 149 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 150 if (pdev->device == PCI_DEVICE_ID_INTEL_BXT || 151 pdev->device == PCI_DEVICE_ID_INTEL_BXT_M || 152 pdev->device == PCI_DEVICE_ID_INTEL_EHLLP) { 153 guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid); 154 dwc->has_dsm_for_pm = true; 155 } 156 157 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) { 158 struct gpio_desc *gpio; 159 int ret; 160 161 /* On BYT the FW does not always enable the refclock */ 162 ret = dwc3_byt_enable_ulpi_refclock(pdev); 163 if (ret) 164 return ret; 165 166 ret = devm_acpi_dev_add_driver_gpios(&pdev->dev, 167 acpi_dwc3_byt_gpios); 168 if (ret) 169 dev_dbg(&pdev->dev, "failed to add mapping table\n"); 170 171 /* 172 * A lot of BYT devices lack ACPI resource entries for 173 * the GPIOs, add a fallback mapping to the reference 174 * design GPIOs which all boards seem to use. 175 */ 176 gpiod_add_lookup_table(&platform_bytcr_gpios); 177 178 /* 179 * These GPIOs will turn on the USB2 PHY. Note that we have to 180 * put the gpio descriptors again here because the phy driver 181 * might want to grab them, too. 182 */ 183 gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW); 184 if (IS_ERR(gpio)) 185 return PTR_ERR(gpio); 186 187 gpiod_set_value_cansleep(gpio, 1); 188 gpiod_put(gpio); 189 190 gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW); 191 if (IS_ERR(gpio)) 192 return PTR_ERR(gpio); 193 194 if (gpio) { 195 gpiod_set_value_cansleep(gpio, 1); 196 gpiod_put(gpio); 197 usleep_range(10000, 11000); 198 } 199 } 200 } 201 202 return 0; 203 } 204 205 #ifdef CONFIG_PM 206 static void dwc3_pci_resume_work(struct work_struct *work) 207 { 208 struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work); 209 struct platform_device *dwc3 = dwc->dwc3; 210 int ret; 211 212 ret = pm_runtime_get_sync(&dwc3->dev); 213 if (ret) { 214 pm_runtime_put_sync_autosuspend(&dwc3->dev); 215 return; 216 } 217 218 pm_runtime_mark_last_busy(&dwc3->dev); 219 pm_runtime_put_sync_autosuspend(&dwc3->dev); 220 } 221 #endif 222 223 static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id) 224 { 225 struct property_entry *p = (struct property_entry *)id->driver_data; 226 struct dwc3_pci *dwc; 227 struct resource res[2]; 228 int ret; 229 struct device *dev = &pci->dev; 230 231 ret = pcim_enable_device(pci); 232 if (ret) { 233 dev_err(dev, "failed to enable pci device\n"); 234 return -ENODEV; 235 } 236 237 pci_set_master(pci); 238 239 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 240 if (!dwc) 241 return -ENOMEM; 242 243 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); 244 if (!dwc->dwc3) 245 return -ENOMEM; 246 247 memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res)); 248 249 res[0].start = pci_resource_start(pci, 0); 250 res[0].end = pci_resource_end(pci, 0); 251 res[0].name = "dwc_usb3"; 252 res[0].flags = IORESOURCE_MEM; 253 254 res[1].start = pci->irq; 255 res[1].name = "dwc_usb3"; 256 res[1].flags = IORESOURCE_IRQ; 257 258 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res)); 259 if (ret) { 260 dev_err(dev, "couldn't add resources to dwc3 device\n"); 261 goto err; 262 } 263 264 dwc->pci = pci; 265 dwc->dwc3->dev.parent = dev; 266 ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev)); 267 268 ret = platform_device_add_properties(dwc->dwc3, p); 269 if (ret < 0) 270 goto err; 271 272 ret = dwc3_pci_quirks(dwc); 273 if (ret) 274 goto err; 275 276 ret = platform_device_add(dwc->dwc3); 277 if (ret) { 278 dev_err(dev, "failed to register dwc3 device\n"); 279 goto err; 280 } 281 282 device_init_wakeup(dev, true); 283 pci_set_drvdata(pci, dwc); 284 pm_runtime_put(dev); 285 #ifdef CONFIG_PM 286 INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work); 287 #endif 288 289 return 0; 290 err: 291 platform_device_put(dwc->dwc3); 292 return ret; 293 } 294 295 static void dwc3_pci_remove(struct pci_dev *pci) 296 { 297 struct dwc3_pci *dwc = pci_get_drvdata(pci); 298 struct pci_dev *pdev = dwc->pci; 299 300 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) 301 gpiod_remove_lookup_table(&platform_bytcr_gpios); 302 #ifdef CONFIG_PM 303 cancel_work_sync(&dwc->wakeup_work); 304 #endif 305 device_init_wakeup(&pci->dev, false); 306 pm_runtime_get(&pci->dev); 307 platform_device_unregister(dwc->dwc3); 308 } 309 310 static const struct pci_device_id dwc3_pci_id_table[] = { 311 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BSW), 312 (kernel_ulong_t) &dwc3_pci_intel_properties }, 313 314 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BYT), 315 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 316 317 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD), 318 (kernel_ulong_t) &dwc3_pci_mrfld_properties, }, 319 320 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLLP), 321 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 322 323 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLH), 324 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 325 326 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTLP), 327 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 328 329 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTH), 330 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 331 332 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT), 333 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 334 335 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT_M), 336 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 337 338 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_APL), 339 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 340 341 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_KBP), 342 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 343 344 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_GLK), 345 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 346 347 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPLP), 348 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 349 350 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPH), 351 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 352 353 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPV), 354 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 355 356 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICLLP), 357 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 358 359 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_EHLLP), 360 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 361 362 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPLP), 363 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 364 365 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPH), 366 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 367 368 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_JSP), 369 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 370 371 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLS), 372 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 373 374 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_NL_USB), 375 (kernel_ulong_t) &dwc3_pci_amd_properties, }, 376 { } /* Terminating Entry */ 377 }; 378 MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table); 379 380 #if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP) 381 static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param) 382 { 383 union acpi_object *obj; 384 union acpi_object tmp; 385 union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp); 386 387 if (!dwc->has_dsm_for_pm) 388 return 0; 389 390 tmp.type = ACPI_TYPE_INTEGER; 391 tmp.integer.value = param; 392 393 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid, 394 1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4); 395 if (!obj) { 396 dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n"); 397 return -EIO; 398 } 399 400 ACPI_FREE(obj); 401 402 return 0; 403 } 404 #endif /* CONFIG_PM || CONFIG_PM_SLEEP */ 405 406 #ifdef CONFIG_PM 407 static int dwc3_pci_runtime_suspend(struct device *dev) 408 { 409 struct dwc3_pci *dwc = dev_get_drvdata(dev); 410 411 if (device_can_wakeup(dev)) 412 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3); 413 414 return -EBUSY; 415 } 416 417 static int dwc3_pci_runtime_resume(struct device *dev) 418 { 419 struct dwc3_pci *dwc = dev_get_drvdata(dev); 420 int ret; 421 422 ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0); 423 if (ret) 424 return ret; 425 426 queue_work(pm_wq, &dwc->wakeup_work); 427 428 return 0; 429 } 430 #endif /* CONFIG_PM */ 431 432 #ifdef CONFIG_PM_SLEEP 433 static int dwc3_pci_suspend(struct device *dev) 434 { 435 struct dwc3_pci *dwc = dev_get_drvdata(dev); 436 437 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3); 438 } 439 440 static int dwc3_pci_resume(struct device *dev) 441 { 442 struct dwc3_pci *dwc = dev_get_drvdata(dev); 443 444 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0); 445 } 446 #endif /* CONFIG_PM_SLEEP */ 447 448 static const struct dev_pm_ops dwc3_pci_dev_pm_ops = { 449 SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume) 450 SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume, 451 NULL) 452 }; 453 454 static struct pci_driver dwc3_pci_driver = { 455 .name = "dwc3-pci", 456 .id_table = dwc3_pci_id_table, 457 .probe = dwc3_pci_probe, 458 .remove = dwc3_pci_remove, 459 .driver = { 460 .pm = &dwc3_pci_dev_pm_ops, 461 } 462 }; 463 464 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 465 MODULE_LICENSE("GPL v2"); 466 MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer"); 467 468 module_pci_driver(dwc3_pci_driver); 469