1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * dwc3-pci.c - PCI Specific glue layer 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11 #include <linux/dmi.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/slab.h> 15 #include <linux/pci.h> 16 #include <linux/workqueue.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/platform_device.h> 19 #include <linux/gpio/consumer.h> 20 #include <linux/gpio/machine.h> 21 #include <linux/acpi.h> 22 #include <linux/delay.h> 23 24 #define PCI_DEVICE_ID_INTEL_CMLLP 0x02ee 25 #define PCI_DEVICE_ID_INTEL_CMLH 0x06ee 26 #define PCI_DEVICE_ID_INTEL_BXT 0x0aaa 27 #define PCI_DEVICE_ID_INTEL_BYT 0x0f37 28 #define PCI_DEVICE_ID_INTEL_MRFLD 0x119e 29 #define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa 30 #define PCI_DEVICE_ID_INTEL_BSW 0x22b7 31 #define PCI_DEVICE_ID_INTEL_GLK 0x31aa 32 #define PCI_DEVICE_ID_INTEL_ICLLP 0x34ee 33 #define PCI_DEVICE_ID_INTEL_TGPH 0x43ee 34 #define PCI_DEVICE_ID_INTEL_ADL 0x460e 35 #define PCI_DEVICE_ID_INTEL_ADLN 0x465e 36 #define PCI_DEVICE_ID_INTEL_EHL 0x4b7e 37 #define PCI_DEVICE_ID_INTEL_WCL 0x4d7e 38 #define PCI_DEVICE_ID_INTEL_JSP 0x4dee 39 #define PCI_DEVICE_ID_INTEL_ADL_PCH 0x51ee 40 #define PCI_DEVICE_ID_INTEL_ADLN_PCH 0x54ee 41 #define PCI_DEVICE_ID_INTEL_APL 0x5aaa 42 #define PCI_DEVICE_ID_INTEL_NVLS_PCH 0x6e6f 43 #define PCI_DEVICE_ID_INTEL_ARLH_PCH 0x777e 44 #define PCI_DEVICE_ID_INTEL_RPLS 0x7a61 45 #define PCI_DEVICE_ID_INTEL_MTL 0x7e7e 46 #define PCI_DEVICE_ID_INTEL_ADLS 0x7ae1 47 #define PCI_DEVICE_ID_INTEL_MTLM 0x7eb1 48 #define PCI_DEVICE_ID_INTEL_MTLP 0x7ec1 49 #define PCI_DEVICE_ID_INTEL_MTLS 0x7f6f 50 #define PCI_DEVICE_ID_INTEL_TGL 0x9a15 51 #define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30 52 #define PCI_DEVICE_ID_INTEL_CNPLP 0x9dee 53 #define PCI_DEVICE_ID_INTEL_TGPLP 0xa0ee 54 #define PCI_DEVICE_ID_INTEL_SPTH 0xa130 55 #define PCI_DEVICE_ID_INTEL_KBP 0xa2b0 56 #define PCI_DEVICE_ID_INTEL_CNPH 0xa36e 57 #define PCI_DEVICE_ID_INTEL_CNPV 0xa3b0 58 #define PCI_DEVICE_ID_INTEL_RPL 0xa70e 59 #define PCI_DEVICE_ID_INTEL_PTLH 0xe332 60 #define PCI_DEVICE_ID_INTEL_PTLH_PCH 0xe37e 61 #define PCI_DEVICE_ID_INTEL_PTLU 0xe432 62 #define PCI_DEVICE_ID_INTEL_PTLU_PCH 0xe47e 63 #define PCI_DEVICE_ID_AMD_MR 0x163a 64 65 #define PCI_INTEL_BXT_DSM_GUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511" 66 #define PCI_INTEL_BXT_FUNC_PMU_PWR 4 67 #define PCI_INTEL_BXT_STATE_D0 0 68 #define PCI_INTEL_BXT_STATE_D3 3 69 70 #define GP_RWBAR 1 71 #define GP_RWREG1 0xa0 72 #define GP_RWREG1_ULPI_REFCLK_DISABLE (1 << 17) 73 74 /** 75 * struct dwc3_pci - Driver private structure 76 * @dwc3: child dwc3 platform_device 77 * @pci: our link to PCI bus 78 * @guid: _DSM GUID 79 * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM 80 * @wakeup_work: work for asynchronous resume 81 */ 82 struct dwc3_pci { 83 struct platform_device *dwc3; 84 struct pci_dev *pci; 85 86 guid_t guid; 87 88 unsigned int has_dsm_for_pm:1; 89 struct work_struct wakeup_work; 90 }; 91 92 static const struct acpi_gpio_params reset_gpios = { 0, 0, false }; 93 static const struct acpi_gpio_params cs_gpios = { 1, 0, false }; 94 95 static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = { 96 { "reset-gpios", &reset_gpios, 1 }, 97 { "cs-gpios", &cs_gpios, 1 }, 98 { }, 99 }; 100 101 static struct gpiod_lookup_table platform_bytcr_gpios = { 102 .dev_id = "0000:00:16.0", 103 .table = { 104 GPIO_LOOKUP("INT33FC:00", 54, "cs", GPIO_ACTIVE_HIGH), 105 GPIO_LOOKUP("INT33FC:02", 14, "reset", GPIO_ACTIVE_HIGH), 106 {} 107 }, 108 }; 109 110 static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci) 111 { 112 void __iomem *reg; 113 u32 value; 114 115 reg = pcim_iomap(pci, GP_RWBAR, 0); 116 if (!reg) 117 return -ENOMEM; 118 119 value = readl(reg + GP_RWREG1); 120 if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE)) 121 goto unmap; /* ULPI refclk already enabled */ 122 123 value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE; 124 writel(value, reg + GP_RWREG1); 125 /* This comes from the Intel Android x86 tree w/o any explanation */ 126 msleep(100); 127 unmap: 128 pcim_iounmap(pci, reg); 129 return 0; 130 } 131 132 static const struct property_entry dwc3_pci_intel_properties[] = { 133 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"), 134 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 135 {} 136 }; 137 138 static const struct property_entry dwc3_pci_intel_phy_charger_detect_properties[] = { 139 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"), 140 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), 141 PROPERTY_ENTRY_BOOL("linux,phy_charger_detect"), 142 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 143 {} 144 }; 145 146 static const struct property_entry dwc3_pci_intel_byt_properties[] = { 147 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"), 148 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), 149 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 150 {} 151 }; 152 153 /* 154 * Intel Merrifield SoC uses these endpoints for tracing and they cannot 155 * be re-allocated if being used because the side band flow control signals 156 * are hard wired to certain endpoints: 157 * - 1 High BW Bulk IN (IN#1) (RTIT) 158 * - 1 1KB BW Bulk IN (IN#8) + 1 1KB BW Bulk OUT (Run Control) (OUT#8) 159 */ 160 static const u8 dwc3_pci_mrfld_reserved_endpoints[] = { 3, 16, 17 }; 161 162 static const struct property_entry dwc3_pci_mrfld_properties[] = { 163 PROPERTY_ENTRY_STRING("dr_mode", "otg"), 164 PROPERTY_ENTRY_STRING("linux,extcon-name", "mrfld_bcove_pwrsrc"), 165 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"), 166 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), 167 PROPERTY_ENTRY_U8_ARRAY("snps,reserved-endpoints", dwc3_pci_mrfld_reserved_endpoints), 168 PROPERTY_ENTRY_BOOL("snps,usb2-gadget-lpm-disable"), 169 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 170 {} 171 }; 172 173 static const struct property_entry dwc3_pci_amd_properties[] = { 174 PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"), 175 PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf), 176 PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"), 177 PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"), 178 PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"), 179 PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"), 180 PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"), 181 PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"), 182 PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"), 183 PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"), 184 PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1), 185 /* FIXME these quirks should be removed when AMD NL tapes out */ 186 PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"), 187 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"), 188 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), 189 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 190 {} 191 }; 192 193 static const struct property_entry dwc3_pci_mr_properties[] = { 194 PROPERTY_ENTRY_STRING("dr_mode", "otg"), 195 PROPERTY_ENTRY_BOOL("usb-role-switch"), 196 PROPERTY_ENTRY_STRING("role-switch-default-mode", "host"), 197 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 198 {} 199 }; 200 201 static const struct software_node dwc3_pci_intel_swnode = { 202 .properties = dwc3_pci_intel_properties, 203 }; 204 205 static const struct software_node dwc3_pci_intel_phy_charger_detect_swnode = { 206 .properties = dwc3_pci_intel_phy_charger_detect_properties, 207 }; 208 209 static const struct software_node dwc3_pci_intel_byt_swnode = { 210 .properties = dwc3_pci_intel_byt_properties, 211 }; 212 213 static const struct software_node dwc3_pci_intel_mrfld_swnode = { 214 .properties = dwc3_pci_mrfld_properties, 215 }; 216 217 static const struct software_node dwc3_pci_amd_swnode = { 218 .properties = dwc3_pci_amd_properties, 219 }; 220 221 static const struct software_node dwc3_pci_amd_mr_swnode = { 222 .properties = dwc3_pci_mr_properties, 223 }; 224 225 static int dwc3_pci_quirks(struct dwc3_pci *dwc, 226 const struct software_node *swnode) 227 { 228 struct pci_dev *pdev = dwc->pci; 229 230 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 231 if (pdev->device == PCI_DEVICE_ID_INTEL_BXT || 232 pdev->device == PCI_DEVICE_ID_INTEL_BXT_M || 233 pdev->device == PCI_DEVICE_ID_INTEL_EHL) { 234 guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid); 235 dwc->has_dsm_for_pm = true; 236 } 237 238 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) { 239 struct gpio_desc *gpio; 240 const char *bios_ver; 241 int ret; 242 243 /* On BYT the FW does not always enable the refclock */ 244 ret = dwc3_byt_enable_ulpi_refclock(pdev); 245 if (ret) 246 return ret; 247 248 ret = devm_acpi_dev_add_driver_gpios(&pdev->dev, 249 acpi_dwc3_byt_gpios); 250 if (ret) 251 dev_dbg(&pdev->dev, "failed to add mapping table\n"); 252 253 /* 254 * A lot of BYT devices lack ACPI resource entries for 255 * the GPIOs. If the ACPI entry for the GPIO controller 256 * is present add a fallback mapping to the reference 257 * design GPIOs which all boards seem to use. 258 */ 259 if (acpi_dev_present("INT33FC", NULL, -1)) 260 gpiod_add_lookup_table(&platform_bytcr_gpios); 261 262 /* 263 * These GPIOs will turn on the USB2 PHY. Note that we have to 264 * put the gpio descriptors again here because the phy driver 265 * might want to grab them, too. 266 */ 267 gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW); 268 if (IS_ERR(gpio)) 269 return PTR_ERR(gpio); 270 271 gpiod_set_value_cansleep(gpio, 1); 272 gpiod_put(gpio); 273 274 gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW); 275 if (IS_ERR(gpio)) 276 return PTR_ERR(gpio); 277 278 if (gpio) { 279 gpiod_set_value_cansleep(gpio, 1); 280 gpiod_put(gpio); 281 usleep_range(10000, 11000); 282 } 283 284 /* 285 * Make the pdev name predictable (only 1 DWC3 on BYT) 286 * and patch the phy dev-name into the lookup table so 287 * that the phy-driver can get the GPIOs. 288 */ 289 dwc->dwc3->id = PLATFORM_DEVID_NONE; 290 platform_bytcr_gpios.dev_id = "dwc3.ulpi"; 291 292 /* 293 * Some Android tablets with a Crystal Cove PMIC 294 * (INT33FD), rely on the TUSB1211 phy for charger 295 * detection. These can be identified by them _not_ 296 * using the standard ACPI battery and ac drivers. 297 */ 298 bios_ver = dmi_get_system_info(DMI_BIOS_VERSION); 299 if (acpi_dev_present("INT33FD", "1", 2) && 300 acpi_quirk_skip_acpi_ac_and_battery() && 301 /* Lenovo Yoga Tablet 2 Pro 1380 uses LC824206XA instead */ 302 !(bios_ver && 303 strstarts(bios_ver, "BLADE_21.X64.0005.R00.1504101516"))) { 304 dev_info(&pdev->dev, "Using TUSB1211 phy for charger detection\n"); 305 swnode = &dwc3_pci_intel_phy_charger_detect_swnode; 306 } 307 } 308 } 309 310 return device_add_software_node(&dwc->dwc3->dev, swnode); 311 } 312 313 #ifdef CONFIG_PM 314 static void dwc3_pci_resume_work(struct work_struct *work) 315 { 316 struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work); 317 struct platform_device *dwc3 = dwc->dwc3; 318 int ret; 319 320 ret = pm_runtime_get_sync(&dwc3->dev); 321 if (ret < 0) { 322 pm_runtime_put_sync_autosuspend(&dwc3->dev); 323 return; 324 } 325 326 pm_runtime_mark_last_busy(&dwc3->dev); 327 pm_runtime_put_sync_autosuspend(&dwc3->dev); 328 } 329 #endif 330 331 static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id) 332 { 333 struct dwc3_pci *dwc; 334 struct resource res[2]; 335 int ret; 336 struct device *dev = &pci->dev; 337 338 ret = pcim_enable_device(pci); 339 if (ret) { 340 dev_err(dev, "failed to enable pci device\n"); 341 return -ENODEV; 342 } 343 344 pci_set_master(pci); 345 346 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 347 if (!dwc) 348 return -ENOMEM; 349 350 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); 351 if (!dwc->dwc3) 352 return -ENOMEM; 353 354 memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res)); 355 356 res[0].start = pci_resource_start(pci, 0); 357 res[0].end = pci_resource_end(pci, 0); 358 res[0].name = "dwc_usb3"; 359 res[0].flags = IORESOURCE_MEM; 360 361 res[1].start = pci->irq; 362 res[1].name = "dwc_usb3"; 363 res[1].flags = IORESOURCE_IRQ; 364 365 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res)); 366 if (ret) { 367 dev_err(dev, "couldn't add resources to dwc3 device\n"); 368 goto err; 369 } 370 371 dwc->pci = pci; 372 dwc->dwc3->dev.parent = dev; 373 ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev)); 374 375 ret = dwc3_pci_quirks(dwc, (void *)id->driver_data); 376 if (ret) 377 goto err; 378 379 ret = platform_device_add(dwc->dwc3); 380 if (ret) { 381 dev_err(dev, "failed to register dwc3 device\n"); 382 goto err; 383 } 384 385 device_init_wakeup(dev, true); 386 pci_set_drvdata(pci, dwc); 387 pm_runtime_put(dev); 388 #ifdef CONFIG_PM 389 INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work); 390 #endif 391 392 return 0; 393 err: 394 device_remove_software_node(&dwc->dwc3->dev); 395 platform_device_put(dwc->dwc3); 396 return ret; 397 } 398 399 static void dwc3_pci_remove(struct pci_dev *pci) 400 { 401 struct dwc3_pci *dwc = pci_get_drvdata(pci); 402 struct pci_dev *pdev = dwc->pci; 403 404 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) 405 gpiod_remove_lookup_table(&platform_bytcr_gpios); 406 #ifdef CONFIG_PM 407 cancel_work_sync(&dwc->wakeup_work); 408 #endif 409 device_init_wakeup(&pci->dev, false); 410 pm_runtime_get(&pci->dev); 411 device_remove_software_node(&dwc->dwc3->dev); 412 platform_device_unregister(dwc->dwc3); 413 } 414 415 static const struct pci_device_id dwc3_pci_id_table[] = { 416 { PCI_DEVICE_DATA(INTEL, CMLLP, &dwc3_pci_intel_swnode) }, 417 { PCI_DEVICE_DATA(INTEL, CMLH, &dwc3_pci_intel_swnode) }, 418 { PCI_DEVICE_DATA(INTEL, BXT, &dwc3_pci_intel_swnode) }, 419 { PCI_DEVICE_DATA(INTEL, BYT, &dwc3_pci_intel_byt_swnode) }, 420 { PCI_DEVICE_DATA(INTEL, MRFLD, &dwc3_pci_intel_mrfld_swnode) }, 421 { PCI_DEVICE_DATA(INTEL, BXT_M, &dwc3_pci_intel_swnode) }, 422 { PCI_DEVICE_DATA(INTEL, BSW, &dwc3_pci_intel_swnode) }, 423 { PCI_DEVICE_DATA(INTEL, GLK, &dwc3_pci_intel_swnode) }, 424 { PCI_DEVICE_DATA(INTEL, ICLLP, &dwc3_pci_intel_swnode) }, 425 { PCI_DEVICE_DATA(INTEL, TGPH, &dwc3_pci_intel_swnode) }, 426 { PCI_DEVICE_DATA(INTEL, ADL, &dwc3_pci_intel_swnode) }, 427 { PCI_DEVICE_DATA(INTEL, ADLN, &dwc3_pci_intel_swnode) }, 428 { PCI_DEVICE_DATA(INTEL, EHL, &dwc3_pci_intel_swnode) }, 429 { PCI_DEVICE_DATA(INTEL, WCL, &dwc3_pci_intel_swnode) }, 430 { PCI_DEVICE_DATA(INTEL, JSP, &dwc3_pci_intel_swnode) }, 431 { PCI_DEVICE_DATA(INTEL, ADL_PCH, &dwc3_pci_intel_swnode) }, 432 { PCI_DEVICE_DATA(INTEL, ADLN_PCH, &dwc3_pci_intel_swnode) }, 433 { PCI_DEVICE_DATA(INTEL, APL, &dwc3_pci_intel_swnode) }, 434 { PCI_DEVICE_DATA(INTEL, NVLS_PCH, &dwc3_pci_intel_swnode) }, 435 { PCI_DEVICE_DATA(INTEL, ARLH_PCH, &dwc3_pci_intel_swnode) }, 436 { PCI_DEVICE_DATA(INTEL, RPLS, &dwc3_pci_intel_swnode) }, 437 { PCI_DEVICE_DATA(INTEL, MTL, &dwc3_pci_intel_swnode) }, 438 { PCI_DEVICE_DATA(INTEL, ADLS, &dwc3_pci_intel_swnode) }, 439 { PCI_DEVICE_DATA(INTEL, MTLM, &dwc3_pci_intel_swnode) }, 440 { PCI_DEVICE_DATA(INTEL, MTLP, &dwc3_pci_intel_swnode) }, 441 { PCI_DEVICE_DATA(INTEL, MTLS, &dwc3_pci_intel_swnode) }, 442 { PCI_DEVICE_DATA(INTEL, TGL, &dwc3_pci_intel_swnode) }, 443 { PCI_DEVICE_DATA(INTEL, SPTLP, &dwc3_pci_intel_swnode) }, 444 { PCI_DEVICE_DATA(INTEL, CNPLP, &dwc3_pci_intel_swnode) }, 445 { PCI_DEVICE_DATA(INTEL, TGPLP, &dwc3_pci_intel_swnode) }, 446 { PCI_DEVICE_DATA(INTEL, SPTH, &dwc3_pci_intel_swnode) }, 447 { PCI_DEVICE_DATA(INTEL, KBP, &dwc3_pci_intel_swnode) }, 448 { PCI_DEVICE_DATA(INTEL, CNPH, &dwc3_pci_intel_swnode) }, 449 { PCI_DEVICE_DATA(INTEL, CNPV, &dwc3_pci_intel_swnode) }, 450 { PCI_DEVICE_DATA(INTEL, RPL, &dwc3_pci_intel_swnode) }, 451 { PCI_DEVICE_DATA(INTEL, PTLH, &dwc3_pci_intel_swnode) }, 452 { PCI_DEVICE_DATA(INTEL, PTLH_PCH, &dwc3_pci_intel_swnode) }, 453 { PCI_DEVICE_DATA(INTEL, PTLU, &dwc3_pci_intel_swnode) }, 454 { PCI_DEVICE_DATA(INTEL, PTLU_PCH, &dwc3_pci_intel_swnode) }, 455 456 { PCI_DEVICE_DATA(AMD, NL_USB, &dwc3_pci_amd_swnode) }, 457 { PCI_DEVICE_DATA(AMD, MR, &dwc3_pci_amd_mr_swnode) }, 458 459 { } /* Terminating Entry */ 460 }; 461 MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table); 462 463 #if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP) 464 static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param) 465 { 466 union acpi_object *obj; 467 union acpi_object tmp; 468 union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp); 469 470 if (!dwc->has_dsm_for_pm) 471 return 0; 472 473 tmp.type = ACPI_TYPE_INTEGER; 474 tmp.integer.value = param; 475 476 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid, 477 1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4); 478 if (!obj) { 479 dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n"); 480 return -EIO; 481 } 482 483 ACPI_FREE(obj); 484 485 return 0; 486 } 487 #endif /* CONFIG_PM || CONFIG_PM_SLEEP */ 488 489 #ifdef CONFIG_PM 490 static int dwc3_pci_runtime_suspend(struct device *dev) 491 { 492 struct dwc3_pci *dwc = dev_get_drvdata(dev); 493 494 if (device_can_wakeup(dev)) 495 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3); 496 497 return -EBUSY; 498 } 499 500 static int dwc3_pci_runtime_resume(struct device *dev) 501 { 502 struct dwc3_pci *dwc = dev_get_drvdata(dev); 503 int ret; 504 505 ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0); 506 if (ret) 507 return ret; 508 509 queue_work(pm_wq, &dwc->wakeup_work); 510 511 return 0; 512 } 513 #endif /* CONFIG_PM */ 514 515 #ifdef CONFIG_PM_SLEEP 516 static int dwc3_pci_suspend(struct device *dev) 517 { 518 struct dwc3_pci *dwc = dev_get_drvdata(dev); 519 520 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3); 521 } 522 523 static int dwc3_pci_resume(struct device *dev) 524 { 525 struct dwc3_pci *dwc = dev_get_drvdata(dev); 526 527 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0); 528 } 529 #endif /* CONFIG_PM_SLEEP */ 530 531 static const struct dev_pm_ops dwc3_pci_dev_pm_ops = { 532 SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume) 533 SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume, 534 NULL) 535 }; 536 537 static struct pci_driver dwc3_pci_driver = { 538 .name = "dwc3-pci", 539 .id_table = dwc3_pci_id_table, 540 .probe = dwc3_pci_probe, 541 .remove = dwc3_pci_remove, 542 .driver = { 543 .pm = &dwc3_pci_dev_pm_ops, 544 } 545 }; 546 547 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 548 MODULE_LICENSE("GPL v2"); 549 MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer"); 550 551 module_pci_driver(dwc3_pci_driver); 552