1 /** 2 * dwc3-omap.c - OMAP Specific Glue layer 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The names of the above-listed copyright holders may not be used 19 * to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * ALTERNATIVELY, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2, as published by the Free 24 * Software Foundation. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <linux/module.h> 40 #include <linux/kernel.h> 41 #include <linux/slab.h> 42 #include <linux/interrupt.h> 43 #include <linux/spinlock.h> 44 #include <linux/platform_device.h> 45 #include <linux/platform_data/dwc3-omap.h> 46 #include <linux/dma-mapping.h> 47 #include <linux/ioport.h> 48 #include <linux/io.h> 49 #include <linux/module.h> 50 51 #include "io.h" 52 53 /* 54 * All these registers belong to OMAP's Wrapper around the 55 * DesignWare USB3 Core. 56 */ 57 58 #define USBOTGSS_REVISION 0x0000 59 #define USBOTGSS_SYSCONFIG 0x0010 60 #define USBOTGSS_IRQ_EOI 0x0020 61 #define USBOTGSS_IRQSTATUS_RAW_0 0x0024 62 #define USBOTGSS_IRQSTATUS_0 0x0028 63 #define USBOTGSS_IRQENABLE_SET_0 0x002c 64 #define USBOTGSS_IRQENABLE_CLR_0 0x0030 65 #define USBOTGSS_IRQSTATUS_RAW_1 0x0034 66 #define USBOTGSS_IRQSTATUS_1 0x0038 67 #define USBOTGSS_IRQENABLE_SET_1 0x003c 68 #define USBOTGSS_IRQENABLE_CLR_1 0x0040 69 #define USBOTGSS_UTMI_OTG_CTRL 0x0080 70 #define USBOTGSS_UTMI_OTG_STATUS 0x0084 71 #define USBOTGSS_MMRAM_OFFSET 0x0100 72 #define USBOTGSS_FLADJ 0x0104 73 #define USBOTGSS_DEBUG_CFG 0x0108 74 #define USBOTGSS_DEBUG_DATA 0x010c 75 76 /* SYSCONFIG REGISTER */ 77 #define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16) 78 #define USBOTGSS_SYSCONFIG_STANDBYMODE(x) ((x) << 4) 79 80 #define USBOTGSS_STANDBYMODE_FORCE_STANDBY 0 81 #define USBOTGSS_STANDBYMODE_NO_STANDBY 1 82 #define USBOTGSS_STANDBYMODE_SMART_STANDBY 2 83 #define USBOTGSS_STANDBYMODE_SMART_WAKEUP 3 84 85 #define USBOTGSS_STANDBYMODE_MASK (0x03 << 4) 86 87 #define USBOTGSS_SYSCONFIG_IDLEMODE(x) ((x) << 2) 88 89 #define USBOTGSS_IDLEMODE_FORCE_IDLE 0 90 #define USBOTGSS_IDLEMODE_NO_IDLE 1 91 #define USBOTGSS_IDLEMODE_SMART_IDLE 2 92 #define USBOTGSS_IDLEMODE_SMART_WAKEUP 3 93 94 #define USBOTGSS_IDLEMODE_MASK (0x03 << 2) 95 96 /* IRQ_EOI REGISTER */ 97 #define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0) 98 99 /* IRQS0 BITS */ 100 #define USBOTGSS_IRQO_COREIRQ_ST (1 << 0) 101 102 /* IRQ1 BITS */ 103 #define USBOTGSS_IRQ1_DMADISABLECLR (1 << 17) 104 #define USBOTGSS_IRQ1_OEVT (1 << 16) 105 #define USBOTGSS_IRQ1_DRVVBUS_RISE (1 << 13) 106 #define USBOTGSS_IRQ1_CHRGVBUS_RISE (1 << 12) 107 #define USBOTGSS_IRQ1_DISCHRGVBUS_RISE (1 << 11) 108 #define USBOTGSS_IRQ1_IDPULLUP_RISE (1 << 8) 109 #define USBOTGSS_IRQ1_DRVVBUS_FALL (1 << 5) 110 #define USBOTGSS_IRQ1_CHRGVBUS_FALL (1 << 4) 111 #define USBOTGSS_IRQ1_DISCHRGVBUS_FALL (1 << 3) 112 #define USBOTGSS_IRQ1_IDPULLUP_FALL (1 << 0) 113 114 /* UTMI_OTG_CTRL REGISTER */ 115 #define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS (1 << 5) 116 #define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS (1 << 4) 117 #define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS (1 << 3) 118 #define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP (1 << 0) 119 120 /* UTMI_OTG_STATUS REGISTER */ 121 #define USBOTGSS_UTMI_OTG_STATUS_SW_MODE (1 << 31) 122 #define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT (1 << 9) 123 #define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8) 124 #define USBOTGSS_UTMI_OTG_STATUS_IDDIG (1 << 4) 125 #define USBOTGSS_UTMI_OTG_STATUS_SESSEND (1 << 3) 126 #define USBOTGSS_UTMI_OTG_STATUS_SESSVALID (1 << 2) 127 #define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID (1 << 1) 128 129 struct dwc3_omap { 130 /* device lock */ 131 spinlock_t lock; 132 133 struct platform_device *dwc3; 134 struct device *dev; 135 136 int irq; 137 void __iomem *base; 138 139 void *context; 140 u32 resource_size; 141 142 u32 dma_status:1; 143 }; 144 145 static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap) 146 { 147 struct dwc3_omap *omap = _omap; 148 u32 reg; 149 150 spin_lock(&omap->lock); 151 152 reg = dwc3_readl(omap->base, USBOTGSS_IRQSTATUS_1); 153 154 if (reg & USBOTGSS_IRQ1_DMADISABLECLR) { 155 dev_dbg(omap->dev, "DMA Disable was Cleared\n"); 156 omap->dma_status = false; 157 } 158 159 if (reg & USBOTGSS_IRQ1_OEVT) 160 dev_dbg(omap->dev, "OTG Event\n"); 161 162 if (reg & USBOTGSS_IRQ1_DRVVBUS_RISE) 163 dev_dbg(omap->dev, "DRVVBUS Rise\n"); 164 165 if (reg & USBOTGSS_IRQ1_CHRGVBUS_RISE) 166 dev_dbg(omap->dev, "CHRGVBUS Rise\n"); 167 168 if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_RISE) 169 dev_dbg(omap->dev, "DISCHRGVBUS Rise\n"); 170 171 if (reg & USBOTGSS_IRQ1_IDPULLUP_RISE) 172 dev_dbg(omap->dev, "IDPULLUP Rise\n"); 173 174 if (reg & USBOTGSS_IRQ1_DRVVBUS_FALL) 175 dev_dbg(omap->dev, "DRVVBUS Fall\n"); 176 177 if (reg & USBOTGSS_IRQ1_CHRGVBUS_FALL) 178 dev_dbg(omap->dev, "CHRGVBUS Fall\n"); 179 180 if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_FALL) 181 dev_dbg(omap->dev, "DISCHRGVBUS Fall\n"); 182 183 if (reg & USBOTGSS_IRQ1_IDPULLUP_FALL) 184 dev_dbg(omap->dev, "IDPULLUP Fall\n"); 185 186 dwc3_writel(omap->base, USBOTGSS_IRQSTATUS_1, reg); 187 188 reg = dwc3_readl(omap->base, USBOTGSS_IRQSTATUS_0); 189 dwc3_writel(omap->base, USBOTGSS_IRQSTATUS_0, reg); 190 191 spin_unlock(&omap->lock); 192 193 return IRQ_HANDLED; 194 } 195 196 static int __devinit dwc3_omap_probe(struct platform_device *pdev) 197 { 198 struct dwc3_omap_data *pdata = pdev->dev.platform_data; 199 struct platform_device *dwc3; 200 struct dwc3_omap *omap; 201 struct resource *res; 202 203 int ret = -ENOMEM; 204 int irq; 205 206 u32 reg; 207 208 void __iomem *base; 209 void *context; 210 211 omap = kzalloc(sizeof(*omap), GFP_KERNEL); 212 if (!omap) { 213 dev_err(&pdev->dev, "not enough memory\n"); 214 goto err0; 215 } 216 217 platform_set_drvdata(pdev, omap); 218 219 irq = platform_get_irq(pdev, 1); 220 if (irq < 0) { 221 dev_err(&pdev->dev, "missing IRQ resource\n"); 222 ret = -EINVAL; 223 goto err1; 224 } 225 226 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 227 if (!res) { 228 dev_err(&pdev->dev, "missing memory base resource\n"); 229 ret = -EINVAL; 230 goto err1; 231 } 232 233 base = ioremap_nocache(res->start, resource_size(res)); 234 if (!base) { 235 dev_err(&pdev->dev, "ioremap failed\n"); 236 goto err1; 237 } 238 239 dwc3 = platform_device_alloc("dwc3-omap", -1); 240 if (!dwc3) { 241 dev_err(&pdev->dev, "couldn't allocate dwc3 device\n"); 242 goto err2; 243 } 244 245 context = kzalloc(resource_size(res), GFP_KERNEL); 246 if (!context) { 247 dev_err(&pdev->dev, "couldn't allocate dwc3 context memory\n"); 248 goto err3; 249 } 250 251 spin_lock_init(&omap->lock); 252 dma_set_coherent_mask(&dwc3->dev, pdev->dev.coherent_dma_mask); 253 254 dwc3->dev.parent = &pdev->dev; 255 dwc3->dev.dma_mask = pdev->dev.dma_mask; 256 dwc3->dev.dma_parms = pdev->dev.dma_parms; 257 omap->resource_size = resource_size(res); 258 omap->context = context; 259 omap->dev = &pdev->dev; 260 omap->irq = irq; 261 omap->base = base; 262 omap->dwc3 = dwc3; 263 264 reg = dwc3_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS); 265 266 if (!pdata) { 267 dev_dbg(&pdev->dev, "missing platform data\n"); 268 } else { 269 switch (pdata->utmi_mode) { 270 case DWC3_OMAP_UTMI_MODE_SW: 271 reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE; 272 break; 273 case DWC3_OMAP_UTMI_MODE_HW: 274 reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE; 275 break; 276 default: 277 dev_dbg(&pdev->dev, "UNKNOWN utmi mode %d\n", 278 pdata->utmi_mode); 279 } 280 } 281 282 dwc3_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, reg); 283 284 /* check the DMA Status */ 285 reg = dwc3_readl(omap->base, USBOTGSS_SYSCONFIG); 286 omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE); 287 288 /* Set No-Idle and No-Standby */ 289 reg &= ~(USBOTGSS_STANDBYMODE_MASK 290 | USBOTGSS_IDLEMODE_MASK); 291 292 reg |= (USBOTGSS_SYSCONFIG_STANDBYMODE(USBOTGSS_STANDBYMODE_NO_STANDBY) 293 | USBOTGSS_SYSCONFIG_IDLEMODE(USBOTGSS_IDLEMODE_NO_IDLE)); 294 295 dwc3_writel(omap->base, USBOTGSS_SYSCONFIG, reg); 296 297 ret = request_irq(omap->irq, dwc3_omap_interrupt, 0, 298 "dwc3-omap", omap); 299 if (ret) { 300 dev_err(&pdev->dev, "failed to request IRQ #%d --> %d\n", 301 omap->irq, ret); 302 goto err4; 303 } 304 305 /* enable all IRQs */ 306 reg = USBOTGSS_IRQO_COREIRQ_ST; 307 dwc3_writel(omap->base, USBOTGSS_IRQENABLE_SET_0, reg); 308 309 reg = (USBOTGSS_IRQ1_OEVT | 310 USBOTGSS_IRQ1_DRVVBUS_RISE | 311 USBOTGSS_IRQ1_CHRGVBUS_RISE | 312 USBOTGSS_IRQ1_DISCHRGVBUS_RISE | 313 USBOTGSS_IRQ1_IDPULLUP_RISE | 314 USBOTGSS_IRQ1_DRVVBUS_FALL | 315 USBOTGSS_IRQ1_CHRGVBUS_FALL | 316 USBOTGSS_IRQ1_DISCHRGVBUS_FALL | 317 USBOTGSS_IRQ1_IDPULLUP_FALL); 318 319 dwc3_writel(omap->base, USBOTGSS_IRQENABLE_SET_1, reg); 320 321 ret = platform_device_add_resources(dwc3, pdev->resource, 322 pdev->num_resources); 323 if (ret) { 324 dev_err(&pdev->dev, "couldn't add resources to dwc3 device\n"); 325 goto err5; 326 } 327 328 ret = platform_device_add(dwc3); 329 if (ret) { 330 dev_err(&pdev->dev, "failed to register dwc3 device\n"); 331 goto err5; 332 } 333 334 return 0; 335 336 err5: 337 free_irq(omap->irq, omap); 338 339 err4: 340 kfree(omap->context); 341 342 err3: 343 platform_device_put(dwc3); 344 345 err2: 346 iounmap(base); 347 348 err1: 349 kfree(omap); 350 351 err0: 352 return ret; 353 } 354 355 static int __devexit dwc3_omap_remove(struct platform_device *pdev) 356 { 357 struct dwc3_omap *omap = platform_get_drvdata(pdev); 358 359 platform_device_unregister(omap->dwc3); 360 361 free_irq(omap->irq, omap); 362 iounmap(omap->base); 363 364 kfree(omap->context); 365 kfree(omap); 366 367 return 0; 368 } 369 370 static const struct of_device_id of_dwc3_matach[] = { 371 { 372 "ti,dwc3", 373 }, 374 { }, 375 }; 376 MODULE_DEVICE_TABLE(of, of_dwc3_matach); 377 378 static struct platform_driver dwc3_omap_driver = { 379 .probe = dwc3_omap_probe, 380 .remove = __devexit_p(dwc3_omap_remove), 381 .driver = { 382 .name = "omap-dwc3", 383 .of_match_table = of_dwc3_matach, 384 }, 385 }; 386 387 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 388 MODULE_LICENSE("Dual BSD/GPL"); 389 MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer"); 390 391 static int __devinit dwc3_omap_init(void) 392 { 393 return platform_driver_register(&dwc3_omap_driver); 394 } 395 module_init(dwc3_omap_init); 396 397 static void __exit dwc3_omap_exit(void) 398 { 399 platform_driver_unregister(&dwc3_omap_driver); 400 } 401 module_exit(dwc3_omap_exit); 402