1 /** 2 * dwc3-omap.c - OMAP Specific Glue layer 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * This program is free software: you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 of 11 * the License as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include <linux/module.h> 20 #include <linux/kernel.h> 21 #include <linux/slab.h> 22 #include <linux/irq.h> 23 #include <linux/interrupt.h> 24 #include <linux/platform_device.h> 25 #include <linux/platform_data/dwc3-omap.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/ioport.h> 29 #include <linux/io.h> 30 #include <linux/of.h> 31 #include <linux/of_platform.h> 32 #include <linux/extcon.h> 33 #include <linux/regulator/consumer.h> 34 35 #include <linux/usb/otg.h> 36 37 /* 38 * All these registers belong to OMAP's Wrapper around the 39 * DesignWare USB3 Core. 40 */ 41 42 #define USBOTGSS_REVISION 0x0000 43 #define USBOTGSS_SYSCONFIG 0x0010 44 #define USBOTGSS_IRQ_EOI 0x0020 45 #define USBOTGSS_EOI_OFFSET 0x0008 46 #define USBOTGSS_IRQSTATUS_RAW_0 0x0024 47 #define USBOTGSS_IRQSTATUS_0 0x0028 48 #define USBOTGSS_IRQENABLE_SET_0 0x002c 49 #define USBOTGSS_IRQENABLE_CLR_0 0x0030 50 #define USBOTGSS_IRQ0_OFFSET 0x0004 51 #define USBOTGSS_IRQSTATUS_RAW_1 0x0030 52 #define USBOTGSS_IRQSTATUS_1 0x0034 53 #define USBOTGSS_IRQENABLE_SET_1 0x0038 54 #define USBOTGSS_IRQENABLE_CLR_1 0x003c 55 #define USBOTGSS_IRQSTATUS_RAW_2 0x0040 56 #define USBOTGSS_IRQSTATUS_2 0x0044 57 #define USBOTGSS_IRQENABLE_SET_2 0x0048 58 #define USBOTGSS_IRQENABLE_CLR_2 0x004c 59 #define USBOTGSS_IRQSTATUS_RAW_3 0x0050 60 #define USBOTGSS_IRQSTATUS_3 0x0054 61 #define USBOTGSS_IRQENABLE_SET_3 0x0058 62 #define USBOTGSS_IRQENABLE_CLR_3 0x005c 63 #define USBOTGSS_IRQSTATUS_EOI_MISC 0x0030 64 #define USBOTGSS_IRQSTATUS_RAW_MISC 0x0034 65 #define USBOTGSS_IRQSTATUS_MISC 0x0038 66 #define USBOTGSS_IRQENABLE_SET_MISC 0x003c 67 #define USBOTGSS_IRQENABLE_CLR_MISC 0x0040 68 #define USBOTGSS_IRQMISC_OFFSET 0x03fc 69 #define USBOTGSS_UTMI_OTG_STATUS 0x0080 70 #define USBOTGSS_UTMI_OTG_CTRL 0x0084 71 #define USBOTGSS_UTMI_OTG_OFFSET 0x0480 72 #define USBOTGSS_TXFIFO_DEPTH 0x0508 73 #define USBOTGSS_RXFIFO_DEPTH 0x050c 74 #define USBOTGSS_MMRAM_OFFSET 0x0100 75 #define USBOTGSS_FLADJ 0x0104 76 #define USBOTGSS_DEBUG_CFG 0x0108 77 #define USBOTGSS_DEBUG_DATA 0x010c 78 #define USBOTGSS_DEV_EBC_EN 0x0110 79 #define USBOTGSS_DEBUG_OFFSET 0x0600 80 81 /* SYSCONFIG REGISTER */ 82 #define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16) 83 84 /* IRQ_EOI REGISTER */ 85 #define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0) 86 87 /* IRQS0 BITS */ 88 #define USBOTGSS_IRQO_COREIRQ_ST (1 << 0) 89 90 /* IRQMISC BITS */ 91 #define USBOTGSS_IRQMISC_DMADISABLECLR (1 << 17) 92 #define USBOTGSS_IRQMISC_OEVT (1 << 16) 93 #define USBOTGSS_IRQMISC_DRVVBUS_RISE (1 << 13) 94 #define USBOTGSS_IRQMISC_CHRGVBUS_RISE (1 << 12) 95 #define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE (1 << 11) 96 #define USBOTGSS_IRQMISC_IDPULLUP_RISE (1 << 8) 97 #define USBOTGSS_IRQMISC_DRVVBUS_FALL (1 << 5) 98 #define USBOTGSS_IRQMISC_CHRGVBUS_FALL (1 << 4) 99 #define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL (1 << 3) 100 #define USBOTGSS_IRQMISC_IDPULLUP_FALL (1 << 0) 101 102 /* UTMI_OTG_STATUS REGISTER */ 103 #define USBOTGSS_UTMI_OTG_STATUS_DRVVBUS (1 << 5) 104 #define USBOTGSS_UTMI_OTG_STATUS_CHRGVBUS (1 << 4) 105 #define USBOTGSS_UTMI_OTG_STATUS_DISCHRGVBUS (1 << 3) 106 #define USBOTGSS_UTMI_OTG_STATUS_IDPULLUP (1 << 0) 107 108 /* UTMI_OTG_CTRL REGISTER */ 109 #define USBOTGSS_UTMI_OTG_CTRL_SW_MODE (1 << 31) 110 #define USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT (1 << 9) 111 #define USBOTGSS_UTMI_OTG_CTRL_TXBITSTUFFENABLE (1 << 8) 112 #define USBOTGSS_UTMI_OTG_CTRL_IDDIG (1 << 4) 113 #define USBOTGSS_UTMI_OTG_CTRL_SESSEND (1 << 3) 114 #define USBOTGSS_UTMI_OTG_CTRL_SESSVALID (1 << 2) 115 #define USBOTGSS_UTMI_OTG_CTRL_VBUSVALID (1 << 1) 116 117 struct dwc3_omap { 118 struct device *dev; 119 120 int irq; 121 void __iomem *base; 122 123 u32 utmi_otg_ctrl; 124 u32 utmi_otg_offset; 125 u32 irqmisc_offset; 126 u32 irq_eoi_offset; 127 u32 debug_offset; 128 u32 irq0_offset; 129 130 struct extcon_dev *edev; 131 struct notifier_block vbus_nb; 132 struct notifier_block id_nb; 133 134 struct regulator *vbus_reg; 135 }; 136 137 enum omap_dwc3_vbus_id_status { 138 OMAP_DWC3_ID_FLOAT, 139 OMAP_DWC3_ID_GROUND, 140 OMAP_DWC3_VBUS_OFF, 141 OMAP_DWC3_VBUS_VALID, 142 }; 143 144 static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset) 145 { 146 return readl(base + offset); 147 } 148 149 static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value) 150 { 151 writel(value, base + offset); 152 } 153 154 static u32 dwc3_omap_read_utmi_ctrl(struct dwc3_omap *omap) 155 { 156 return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_CTRL + 157 omap->utmi_otg_offset); 158 } 159 160 static void dwc3_omap_write_utmi_ctrl(struct dwc3_omap *omap, u32 value) 161 { 162 dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_CTRL + 163 omap->utmi_otg_offset, value); 164 165 } 166 167 static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap) 168 { 169 return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_RAW_0 - 170 omap->irq0_offset); 171 } 172 173 static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value) 174 { 175 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 - 176 omap->irq0_offset, value); 177 178 } 179 180 static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap) 181 { 182 return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_RAW_MISC + 183 omap->irqmisc_offset); 184 } 185 186 static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value) 187 { 188 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC + 189 omap->irqmisc_offset, value); 190 191 } 192 193 static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value) 194 { 195 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC + 196 omap->irqmisc_offset, value); 197 198 } 199 200 static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value) 201 { 202 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 - 203 omap->irq0_offset, value); 204 } 205 206 static void dwc3_omap_write_irqmisc_clr(struct dwc3_omap *omap, u32 value) 207 { 208 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_MISC + 209 omap->irqmisc_offset, value); 210 } 211 212 static void dwc3_omap_write_irq0_clr(struct dwc3_omap *omap, u32 value) 213 { 214 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_0 - 215 omap->irq0_offset, value); 216 } 217 218 static void dwc3_omap_set_mailbox(struct dwc3_omap *omap, 219 enum omap_dwc3_vbus_id_status status) 220 { 221 int ret; 222 u32 val; 223 224 switch (status) { 225 case OMAP_DWC3_ID_GROUND: 226 if (omap->vbus_reg) { 227 ret = regulator_enable(omap->vbus_reg); 228 if (ret) { 229 dev_err(omap->dev, "regulator enable failed\n"); 230 return; 231 } 232 } 233 234 val = dwc3_omap_read_utmi_ctrl(omap); 235 val &= ~USBOTGSS_UTMI_OTG_CTRL_IDDIG; 236 dwc3_omap_write_utmi_ctrl(omap, val); 237 break; 238 239 case OMAP_DWC3_VBUS_VALID: 240 val = dwc3_omap_read_utmi_ctrl(omap); 241 val &= ~USBOTGSS_UTMI_OTG_CTRL_SESSEND; 242 val |= USBOTGSS_UTMI_OTG_CTRL_VBUSVALID 243 | USBOTGSS_UTMI_OTG_CTRL_SESSVALID; 244 dwc3_omap_write_utmi_ctrl(omap, val); 245 break; 246 247 case OMAP_DWC3_ID_FLOAT: 248 if (omap->vbus_reg) 249 regulator_disable(omap->vbus_reg); 250 val = dwc3_omap_read_utmi_ctrl(omap); 251 val |= USBOTGSS_UTMI_OTG_CTRL_IDDIG; 252 dwc3_omap_write_utmi_ctrl(omap, val); 253 254 case OMAP_DWC3_VBUS_OFF: 255 val = dwc3_omap_read_utmi_ctrl(omap); 256 val &= ~(USBOTGSS_UTMI_OTG_CTRL_SESSVALID 257 | USBOTGSS_UTMI_OTG_CTRL_VBUSVALID); 258 val |= USBOTGSS_UTMI_OTG_CTRL_SESSEND; 259 dwc3_omap_write_utmi_ctrl(omap, val); 260 break; 261 262 default: 263 dev_WARN(omap->dev, "invalid state\n"); 264 } 265 } 266 267 static void dwc3_omap_enable_irqs(struct dwc3_omap *omap); 268 static void dwc3_omap_disable_irqs(struct dwc3_omap *omap); 269 270 static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap) 271 { 272 struct dwc3_omap *omap = _omap; 273 274 if (dwc3_omap_read_irqmisc_status(omap) || 275 dwc3_omap_read_irq0_status(omap)) { 276 /* mask irqs */ 277 dwc3_omap_disable_irqs(omap); 278 return IRQ_WAKE_THREAD; 279 } 280 281 return IRQ_NONE; 282 } 283 284 static irqreturn_t dwc3_omap_interrupt_thread(int irq, void *_omap) 285 { 286 struct dwc3_omap *omap = _omap; 287 u32 reg; 288 289 /* clear irq status flags */ 290 reg = dwc3_omap_read_irqmisc_status(omap); 291 dwc3_omap_write_irqmisc_status(omap, reg); 292 293 reg = dwc3_omap_read_irq0_status(omap); 294 dwc3_omap_write_irq0_status(omap, reg); 295 296 /* unmask irqs */ 297 dwc3_omap_enable_irqs(omap); 298 299 return IRQ_HANDLED; 300 } 301 302 static void dwc3_omap_enable_irqs(struct dwc3_omap *omap) 303 { 304 u32 reg; 305 306 /* enable all IRQs */ 307 reg = USBOTGSS_IRQO_COREIRQ_ST; 308 dwc3_omap_write_irq0_set(omap, reg); 309 310 reg = (USBOTGSS_IRQMISC_OEVT | 311 USBOTGSS_IRQMISC_DRVVBUS_RISE | 312 USBOTGSS_IRQMISC_CHRGVBUS_RISE | 313 USBOTGSS_IRQMISC_DISCHRGVBUS_RISE | 314 USBOTGSS_IRQMISC_IDPULLUP_RISE | 315 USBOTGSS_IRQMISC_DRVVBUS_FALL | 316 USBOTGSS_IRQMISC_CHRGVBUS_FALL | 317 USBOTGSS_IRQMISC_DISCHRGVBUS_FALL | 318 USBOTGSS_IRQMISC_IDPULLUP_FALL); 319 320 dwc3_omap_write_irqmisc_set(omap, reg); 321 } 322 323 static void dwc3_omap_disable_irqs(struct dwc3_omap *omap) 324 { 325 u32 reg; 326 327 /* disable all IRQs */ 328 reg = USBOTGSS_IRQO_COREIRQ_ST; 329 dwc3_omap_write_irq0_clr(omap, reg); 330 331 reg = (USBOTGSS_IRQMISC_OEVT | 332 USBOTGSS_IRQMISC_DRVVBUS_RISE | 333 USBOTGSS_IRQMISC_CHRGVBUS_RISE | 334 USBOTGSS_IRQMISC_DISCHRGVBUS_RISE | 335 USBOTGSS_IRQMISC_IDPULLUP_RISE | 336 USBOTGSS_IRQMISC_DRVVBUS_FALL | 337 USBOTGSS_IRQMISC_CHRGVBUS_FALL | 338 USBOTGSS_IRQMISC_DISCHRGVBUS_FALL | 339 USBOTGSS_IRQMISC_IDPULLUP_FALL); 340 341 dwc3_omap_write_irqmisc_clr(omap, reg); 342 } 343 344 static int dwc3_omap_id_notifier(struct notifier_block *nb, 345 unsigned long event, void *ptr) 346 { 347 struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, id_nb); 348 349 if (event) 350 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND); 351 else 352 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT); 353 354 return NOTIFY_DONE; 355 } 356 357 static int dwc3_omap_vbus_notifier(struct notifier_block *nb, 358 unsigned long event, void *ptr) 359 { 360 struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, vbus_nb); 361 362 if (event) 363 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID); 364 else 365 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF); 366 367 return NOTIFY_DONE; 368 } 369 370 static void dwc3_omap_map_offset(struct dwc3_omap *omap) 371 { 372 struct device_node *node = omap->dev->of_node; 373 374 /* 375 * Differentiate between OMAP5 and AM437x. 376 * 377 * For OMAP5(ES2.0) and AM437x wrapper revision is same, even 378 * though there are changes in wrapper register offsets. 379 * 380 * Using dt compatible to differentiate AM437x. 381 */ 382 if (of_device_is_compatible(node, "ti,am437x-dwc3")) { 383 omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET; 384 omap->irq0_offset = USBOTGSS_IRQ0_OFFSET; 385 omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET; 386 omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET; 387 omap->debug_offset = USBOTGSS_DEBUG_OFFSET; 388 } 389 } 390 391 static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap) 392 { 393 u32 reg; 394 struct device_node *node = omap->dev->of_node; 395 int utmi_mode = 0; 396 397 reg = dwc3_omap_read_utmi_ctrl(omap); 398 399 of_property_read_u32(node, "utmi-mode", &utmi_mode); 400 401 switch (utmi_mode) { 402 case DWC3_OMAP_UTMI_MODE_SW: 403 reg |= USBOTGSS_UTMI_OTG_CTRL_SW_MODE; 404 break; 405 case DWC3_OMAP_UTMI_MODE_HW: 406 reg &= ~USBOTGSS_UTMI_OTG_CTRL_SW_MODE; 407 break; 408 default: 409 dev_WARN(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode); 410 } 411 412 dwc3_omap_write_utmi_ctrl(omap, reg); 413 } 414 415 static int dwc3_omap_extcon_register(struct dwc3_omap *omap) 416 { 417 int ret; 418 struct device_node *node = omap->dev->of_node; 419 struct extcon_dev *edev; 420 421 if (of_property_read_bool(node, "extcon")) { 422 edev = extcon_get_edev_by_phandle(omap->dev, 0); 423 if (IS_ERR(edev)) { 424 dev_vdbg(omap->dev, "couldn't get extcon device\n"); 425 return -EPROBE_DEFER; 426 } 427 428 omap->vbus_nb.notifier_call = dwc3_omap_vbus_notifier; 429 ret = devm_extcon_register_notifier(omap->dev, edev, 430 EXTCON_USB, &omap->vbus_nb); 431 if (ret < 0) 432 dev_vdbg(omap->dev, "failed to register notifier for USB\n"); 433 434 omap->id_nb.notifier_call = dwc3_omap_id_notifier; 435 ret = devm_extcon_register_notifier(omap->dev, edev, 436 EXTCON_USB_HOST, &omap->id_nb); 437 if (ret < 0) 438 dev_vdbg(omap->dev, "failed to register notifier for USB-HOST\n"); 439 440 if (extcon_get_state(edev, EXTCON_USB) == true) 441 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID); 442 if (extcon_get_state(edev, EXTCON_USB_HOST) == true) 443 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND); 444 445 omap->edev = edev; 446 } 447 448 return 0; 449 } 450 451 static int dwc3_omap_probe(struct platform_device *pdev) 452 { 453 struct device_node *node = pdev->dev.of_node; 454 455 struct dwc3_omap *omap; 456 struct resource *res; 457 struct device *dev = &pdev->dev; 458 struct regulator *vbus_reg = NULL; 459 460 int ret; 461 int irq; 462 463 u32 reg; 464 465 void __iomem *base; 466 467 if (!node) { 468 dev_err(dev, "device node not found\n"); 469 return -EINVAL; 470 } 471 472 omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL); 473 if (!omap) 474 return -ENOMEM; 475 476 platform_set_drvdata(pdev, omap); 477 478 irq = platform_get_irq(pdev, 0); 479 if (irq < 0) { 480 dev_err(dev, "missing IRQ resource\n"); 481 return -EINVAL; 482 } 483 484 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 485 base = devm_ioremap_resource(dev, res); 486 if (IS_ERR(base)) 487 return PTR_ERR(base); 488 489 if (of_property_read_bool(node, "vbus-supply")) { 490 vbus_reg = devm_regulator_get(dev, "vbus"); 491 if (IS_ERR(vbus_reg)) { 492 dev_err(dev, "vbus init failed\n"); 493 return PTR_ERR(vbus_reg); 494 } 495 } 496 497 omap->dev = dev; 498 omap->irq = irq; 499 omap->base = base; 500 omap->vbus_reg = vbus_reg; 501 502 pm_runtime_enable(dev); 503 ret = pm_runtime_get_sync(dev); 504 if (ret < 0) { 505 dev_err(dev, "get_sync failed with err %d\n", ret); 506 goto err1; 507 } 508 509 dwc3_omap_map_offset(omap); 510 dwc3_omap_set_utmi_mode(omap); 511 512 /* check the DMA Status */ 513 reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG); 514 irq_set_status_flags(omap->irq, IRQ_NOAUTOEN); 515 ret = devm_request_threaded_irq(dev, omap->irq, dwc3_omap_interrupt, 516 dwc3_omap_interrupt_thread, IRQF_SHARED, 517 "dwc3-omap", omap); 518 if (ret) { 519 dev_err(dev, "failed to request IRQ #%d --> %d\n", 520 omap->irq, ret); 521 goto err1; 522 } 523 524 ret = dwc3_omap_extcon_register(omap); 525 if (ret < 0) 526 goto err1; 527 528 ret = of_platform_populate(node, NULL, NULL, dev); 529 if (ret) { 530 dev_err(&pdev->dev, "failed to create dwc3 core\n"); 531 goto err1; 532 } 533 534 dwc3_omap_enable_irqs(omap); 535 enable_irq(omap->irq); 536 return 0; 537 538 err1: 539 pm_runtime_put_sync(dev); 540 pm_runtime_disable(dev); 541 542 return ret; 543 } 544 545 static int dwc3_omap_remove(struct platform_device *pdev) 546 { 547 struct dwc3_omap *omap = platform_get_drvdata(pdev); 548 549 dwc3_omap_disable_irqs(omap); 550 disable_irq(omap->irq); 551 of_platform_depopulate(omap->dev); 552 pm_runtime_put_sync(&pdev->dev); 553 pm_runtime_disable(&pdev->dev); 554 555 return 0; 556 } 557 558 static const struct of_device_id of_dwc3_match[] = { 559 { 560 .compatible = "ti,dwc3" 561 }, 562 { 563 .compatible = "ti,am437x-dwc3" 564 }, 565 { }, 566 }; 567 MODULE_DEVICE_TABLE(of, of_dwc3_match); 568 569 #ifdef CONFIG_PM_SLEEP 570 static int dwc3_omap_suspend(struct device *dev) 571 { 572 struct dwc3_omap *omap = dev_get_drvdata(dev); 573 574 omap->utmi_otg_ctrl = dwc3_omap_read_utmi_ctrl(omap); 575 dwc3_omap_disable_irqs(omap); 576 577 return 0; 578 } 579 580 static int dwc3_omap_resume(struct device *dev) 581 { 582 struct dwc3_omap *omap = dev_get_drvdata(dev); 583 584 dwc3_omap_write_utmi_ctrl(omap, omap->utmi_otg_ctrl); 585 dwc3_omap_enable_irqs(omap); 586 587 pm_runtime_disable(dev); 588 pm_runtime_set_active(dev); 589 pm_runtime_enable(dev); 590 591 return 0; 592 } 593 594 static const struct dev_pm_ops dwc3_omap_dev_pm_ops = { 595 596 SET_SYSTEM_SLEEP_PM_OPS(dwc3_omap_suspend, dwc3_omap_resume) 597 }; 598 599 #define DEV_PM_OPS (&dwc3_omap_dev_pm_ops) 600 #else 601 #define DEV_PM_OPS NULL 602 #endif /* CONFIG_PM_SLEEP */ 603 604 static struct platform_driver dwc3_omap_driver = { 605 .probe = dwc3_omap_probe, 606 .remove = dwc3_omap_remove, 607 .driver = { 608 .name = "omap-dwc3", 609 .of_match_table = of_dwc3_match, 610 .pm = DEV_PM_OPS, 611 }, 612 }; 613 614 module_platform_driver(dwc3_omap_driver); 615 616 MODULE_ALIAS("platform:omap-dwc3"); 617 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 618 MODULE_LICENSE("GPL v2"); 619 MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer"); 620