1 /** 2 * dwc3-omap.c - OMAP Specific Glue layer 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The names of the above-listed copyright holders may not be used 19 * to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * ALTERNATIVELY, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2, as published by the Free 24 * Software Foundation. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <linux/module.h> 40 #include <linux/kernel.h> 41 #include <linux/slab.h> 42 #include <linux/interrupt.h> 43 #include <linux/spinlock.h> 44 #include <linux/platform_device.h> 45 #include <linux/platform_data/dwc3-omap.h> 46 #include <linux/dma-mapping.h> 47 #include <linux/ioport.h> 48 #include <linux/io.h> 49 #include <linux/of.h> 50 51 #include "core.h" 52 53 /* 54 * All these registers belong to OMAP's Wrapper around the 55 * DesignWare USB3 Core. 56 */ 57 58 #define USBOTGSS_REVISION 0x0000 59 #define USBOTGSS_SYSCONFIG 0x0010 60 #define USBOTGSS_IRQ_EOI 0x0020 61 #define USBOTGSS_IRQSTATUS_RAW_0 0x0024 62 #define USBOTGSS_IRQSTATUS_0 0x0028 63 #define USBOTGSS_IRQENABLE_SET_0 0x002c 64 #define USBOTGSS_IRQENABLE_CLR_0 0x0030 65 #define USBOTGSS_IRQSTATUS_RAW_1 0x0034 66 #define USBOTGSS_IRQSTATUS_1 0x0038 67 #define USBOTGSS_IRQENABLE_SET_1 0x003c 68 #define USBOTGSS_IRQENABLE_CLR_1 0x0040 69 #define USBOTGSS_UTMI_OTG_CTRL 0x0080 70 #define USBOTGSS_UTMI_OTG_STATUS 0x0084 71 #define USBOTGSS_MMRAM_OFFSET 0x0100 72 #define USBOTGSS_FLADJ 0x0104 73 #define USBOTGSS_DEBUG_CFG 0x0108 74 #define USBOTGSS_DEBUG_DATA 0x010c 75 76 /* SYSCONFIG REGISTER */ 77 #define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16) 78 #define USBOTGSS_SYSCONFIG_STANDBYMODE(x) ((x) << 4) 79 80 #define USBOTGSS_STANDBYMODE_FORCE_STANDBY 0 81 #define USBOTGSS_STANDBYMODE_NO_STANDBY 1 82 #define USBOTGSS_STANDBYMODE_SMART_STANDBY 2 83 #define USBOTGSS_STANDBYMODE_SMART_WAKEUP 3 84 85 #define USBOTGSS_STANDBYMODE_MASK (0x03 << 4) 86 87 #define USBOTGSS_SYSCONFIG_IDLEMODE(x) ((x) << 2) 88 89 #define USBOTGSS_IDLEMODE_FORCE_IDLE 0 90 #define USBOTGSS_IDLEMODE_NO_IDLE 1 91 #define USBOTGSS_IDLEMODE_SMART_IDLE 2 92 #define USBOTGSS_IDLEMODE_SMART_WAKEUP 3 93 94 #define USBOTGSS_IDLEMODE_MASK (0x03 << 2) 95 96 /* IRQ_EOI REGISTER */ 97 #define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0) 98 99 /* IRQS0 BITS */ 100 #define USBOTGSS_IRQO_COREIRQ_ST (1 << 0) 101 102 /* IRQ1 BITS */ 103 #define USBOTGSS_IRQ1_DMADISABLECLR (1 << 17) 104 #define USBOTGSS_IRQ1_OEVT (1 << 16) 105 #define USBOTGSS_IRQ1_DRVVBUS_RISE (1 << 13) 106 #define USBOTGSS_IRQ1_CHRGVBUS_RISE (1 << 12) 107 #define USBOTGSS_IRQ1_DISCHRGVBUS_RISE (1 << 11) 108 #define USBOTGSS_IRQ1_IDPULLUP_RISE (1 << 8) 109 #define USBOTGSS_IRQ1_DRVVBUS_FALL (1 << 5) 110 #define USBOTGSS_IRQ1_CHRGVBUS_FALL (1 << 4) 111 #define USBOTGSS_IRQ1_DISCHRGVBUS_FALL (1 << 3) 112 #define USBOTGSS_IRQ1_IDPULLUP_FALL (1 << 0) 113 114 /* UTMI_OTG_CTRL REGISTER */ 115 #define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS (1 << 5) 116 #define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS (1 << 4) 117 #define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS (1 << 3) 118 #define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP (1 << 0) 119 120 /* UTMI_OTG_STATUS REGISTER */ 121 #define USBOTGSS_UTMI_OTG_STATUS_SW_MODE (1 << 31) 122 #define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT (1 << 9) 123 #define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8) 124 #define USBOTGSS_UTMI_OTG_STATUS_IDDIG (1 << 4) 125 #define USBOTGSS_UTMI_OTG_STATUS_SESSEND (1 << 3) 126 #define USBOTGSS_UTMI_OTG_STATUS_SESSVALID (1 << 2) 127 #define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID (1 << 1) 128 129 struct dwc3_omap { 130 /* device lock */ 131 spinlock_t lock; 132 133 struct platform_device *dwc3; 134 struct device *dev; 135 136 int irq; 137 void __iomem *base; 138 139 void *context; 140 u32 resource_size; 141 142 u32 dma_status:1; 143 }; 144 145 static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset) 146 { 147 return readl(base + offset); 148 } 149 150 static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value) 151 { 152 writel(value, base + offset); 153 } 154 155 156 static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap) 157 { 158 struct dwc3_omap *omap = _omap; 159 u32 reg; 160 161 spin_lock(&omap->lock); 162 163 reg = dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_1); 164 165 if (reg & USBOTGSS_IRQ1_DMADISABLECLR) { 166 dev_dbg(omap->dev, "DMA Disable was Cleared\n"); 167 omap->dma_status = false; 168 } 169 170 if (reg & USBOTGSS_IRQ1_OEVT) 171 dev_dbg(omap->dev, "OTG Event\n"); 172 173 if (reg & USBOTGSS_IRQ1_DRVVBUS_RISE) 174 dev_dbg(omap->dev, "DRVVBUS Rise\n"); 175 176 if (reg & USBOTGSS_IRQ1_CHRGVBUS_RISE) 177 dev_dbg(omap->dev, "CHRGVBUS Rise\n"); 178 179 if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_RISE) 180 dev_dbg(omap->dev, "DISCHRGVBUS Rise\n"); 181 182 if (reg & USBOTGSS_IRQ1_IDPULLUP_RISE) 183 dev_dbg(omap->dev, "IDPULLUP Rise\n"); 184 185 if (reg & USBOTGSS_IRQ1_DRVVBUS_FALL) 186 dev_dbg(omap->dev, "DRVVBUS Fall\n"); 187 188 if (reg & USBOTGSS_IRQ1_CHRGVBUS_FALL) 189 dev_dbg(omap->dev, "CHRGVBUS Fall\n"); 190 191 if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_FALL) 192 dev_dbg(omap->dev, "DISCHRGVBUS Fall\n"); 193 194 if (reg & USBOTGSS_IRQ1_IDPULLUP_FALL) 195 dev_dbg(omap->dev, "IDPULLUP Fall\n"); 196 197 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_1, reg); 198 199 reg = dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0); 200 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0, reg); 201 202 spin_unlock(&omap->lock); 203 204 return IRQ_HANDLED; 205 } 206 207 static int __devinit dwc3_omap_probe(struct platform_device *pdev) 208 { 209 struct dwc3_omap_data *pdata = pdev->dev.platform_data; 210 struct device_node *node = pdev->dev.of_node; 211 212 struct platform_device *dwc3; 213 struct dwc3_omap *omap; 214 struct resource *res; 215 struct device *dev = &pdev->dev; 216 217 int devid; 218 int size; 219 int ret = -ENOMEM; 220 int irq; 221 222 const u32 *utmi_mode; 223 u32 reg; 224 225 void __iomem *base; 226 void *context; 227 228 omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL); 229 if (!omap) { 230 dev_err(dev, "not enough memory\n"); 231 return -ENOMEM; 232 } 233 234 platform_set_drvdata(pdev, omap); 235 236 irq = platform_get_irq(pdev, 1); 237 if (irq < 0) { 238 dev_err(dev, "missing IRQ resource\n"); 239 return -EINVAL; 240 } 241 242 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 243 if (!res) { 244 dev_err(dev, "missing memory base resource\n"); 245 return -EINVAL; 246 } 247 248 base = devm_ioremap_nocache(dev, res->start, resource_size(res)); 249 if (!base) { 250 dev_err(dev, "ioremap failed\n"); 251 return -ENOMEM; 252 } 253 254 devid = dwc3_get_device_id(); 255 if (devid < 0) 256 return -ENODEV; 257 258 dwc3 = platform_device_alloc("dwc3", devid); 259 if (!dwc3) { 260 dev_err(dev, "couldn't allocate dwc3 device\n"); 261 goto err1; 262 } 263 264 context = devm_kzalloc(dev, resource_size(res), GFP_KERNEL); 265 if (!context) { 266 dev_err(dev, "couldn't allocate dwc3 context memory\n"); 267 goto err2; 268 } 269 270 spin_lock_init(&omap->lock); 271 dma_set_coherent_mask(&dwc3->dev, dev->coherent_dma_mask); 272 273 dwc3->dev.parent = dev; 274 dwc3->dev.dma_mask = dev->dma_mask; 275 dwc3->dev.dma_parms = dev->dma_parms; 276 omap->resource_size = resource_size(res); 277 omap->context = context; 278 omap->dev = dev; 279 omap->irq = irq; 280 omap->base = base; 281 omap->dwc3 = dwc3; 282 283 reg = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS); 284 285 utmi_mode = of_get_property(node, "utmi-mode", &size); 286 if (utmi_mode && size == sizeof(*utmi_mode)) { 287 reg |= *utmi_mode; 288 } else { 289 if (!pdata) { 290 dev_dbg(dev, "missing platform data\n"); 291 } else { 292 switch (pdata->utmi_mode) { 293 case DWC3_OMAP_UTMI_MODE_SW: 294 reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE; 295 break; 296 case DWC3_OMAP_UTMI_MODE_HW: 297 reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE; 298 break; 299 default: 300 dev_dbg(dev, "UNKNOWN utmi mode %d\n", 301 pdata->utmi_mode); 302 } 303 } 304 } 305 306 dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, reg); 307 308 /* check the DMA Status */ 309 reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG); 310 omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE); 311 312 /* Set No-Idle and No-Standby */ 313 reg &= ~(USBOTGSS_STANDBYMODE_MASK 314 | USBOTGSS_IDLEMODE_MASK); 315 316 reg |= (USBOTGSS_SYSCONFIG_STANDBYMODE(USBOTGSS_STANDBYMODE_NO_STANDBY) 317 | USBOTGSS_SYSCONFIG_IDLEMODE(USBOTGSS_IDLEMODE_NO_IDLE)); 318 319 dwc3_omap_writel(omap->base, USBOTGSS_SYSCONFIG, reg); 320 321 ret = devm_request_irq(dev, omap->irq, dwc3_omap_interrupt, 0, 322 "dwc3-omap", omap); 323 if (ret) { 324 dev_err(dev, "failed to request IRQ #%d --> %d\n", 325 omap->irq, ret); 326 goto err2; 327 } 328 329 /* enable all IRQs */ 330 reg = USBOTGSS_IRQO_COREIRQ_ST; 331 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0, reg); 332 333 reg = (USBOTGSS_IRQ1_OEVT | 334 USBOTGSS_IRQ1_DRVVBUS_RISE | 335 USBOTGSS_IRQ1_CHRGVBUS_RISE | 336 USBOTGSS_IRQ1_DISCHRGVBUS_RISE | 337 USBOTGSS_IRQ1_IDPULLUP_RISE | 338 USBOTGSS_IRQ1_DRVVBUS_FALL | 339 USBOTGSS_IRQ1_CHRGVBUS_FALL | 340 USBOTGSS_IRQ1_DISCHRGVBUS_FALL | 341 USBOTGSS_IRQ1_IDPULLUP_FALL); 342 343 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_1, reg); 344 345 ret = platform_device_add_resources(dwc3, pdev->resource, 346 pdev->num_resources); 347 if (ret) { 348 dev_err(dev, "couldn't add resources to dwc3 device\n"); 349 goto err2; 350 } 351 352 ret = platform_device_add(dwc3); 353 if (ret) { 354 dev_err(dev, "failed to register dwc3 device\n"); 355 goto err2; 356 } 357 358 return 0; 359 360 err2: 361 platform_device_put(dwc3); 362 363 err1: 364 dwc3_put_device_id(devid); 365 366 return ret; 367 } 368 369 static int __devexit dwc3_omap_remove(struct platform_device *pdev) 370 { 371 struct dwc3_omap *omap = platform_get_drvdata(pdev); 372 373 platform_device_unregister(omap->dwc3); 374 375 dwc3_put_device_id(omap->dwc3->id); 376 377 return 0; 378 } 379 380 static const struct of_device_id of_dwc3_matach[] = { 381 { 382 "ti,dwc3", 383 }, 384 { }, 385 }; 386 MODULE_DEVICE_TABLE(of, of_dwc3_matach); 387 388 static struct platform_driver dwc3_omap_driver = { 389 .probe = dwc3_omap_probe, 390 .remove = __devexit_p(dwc3_omap_remove), 391 .driver = { 392 .name = "omap-dwc3", 393 .of_match_table = of_dwc3_matach, 394 }, 395 }; 396 397 module_platform_driver(dwc3_omap_driver); 398 399 MODULE_ALIAS("platform:omap-dwc3"); 400 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 401 MODULE_LICENSE("Dual BSD/GPL"); 402 MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer"); 403