1 /** 2 * dwc3-omap.c - OMAP Specific Glue layer 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * This program is free software: you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 of 11 * the License as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include <linux/module.h> 20 #include <linux/kernel.h> 21 #include <linux/slab.h> 22 #include <linux/interrupt.h> 23 #include <linux/platform_device.h> 24 #include <linux/platform_data/dwc3-omap.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/ioport.h> 28 #include <linux/io.h> 29 #include <linux/of.h> 30 #include <linux/of_platform.h> 31 #include <linux/extcon.h> 32 #include <linux/regulator/consumer.h> 33 34 #include <linux/usb/otg.h> 35 36 /* 37 * All these registers belong to OMAP's Wrapper around the 38 * DesignWare USB3 Core. 39 */ 40 41 #define USBOTGSS_REVISION 0x0000 42 #define USBOTGSS_SYSCONFIG 0x0010 43 #define USBOTGSS_IRQ_EOI 0x0020 44 #define USBOTGSS_EOI_OFFSET 0x0008 45 #define USBOTGSS_IRQSTATUS_RAW_0 0x0024 46 #define USBOTGSS_IRQSTATUS_0 0x0028 47 #define USBOTGSS_IRQENABLE_SET_0 0x002c 48 #define USBOTGSS_IRQENABLE_CLR_0 0x0030 49 #define USBOTGSS_IRQ0_OFFSET 0x0004 50 #define USBOTGSS_IRQSTATUS_RAW_1 0x0030 51 #define USBOTGSS_IRQSTATUS_1 0x0034 52 #define USBOTGSS_IRQENABLE_SET_1 0x0038 53 #define USBOTGSS_IRQENABLE_CLR_1 0x003c 54 #define USBOTGSS_IRQSTATUS_RAW_2 0x0040 55 #define USBOTGSS_IRQSTATUS_2 0x0044 56 #define USBOTGSS_IRQENABLE_SET_2 0x0048 57 #define USBOTGSS_IRQENABLE_CLR_2 0x004c 58 #define USBOTGSS_IRQSTATUS_RAW_3 0x0050 59 #define USBOTGSS_IRQSTATUS_3 0x0054 60 #define USBOTGSS_IRQENABLE_SET_3 0x0058 61 #define USBOTGSS_IRQENABLE_CLR_3 0x005c 62 #define USBOTGSS_IRQSTATUS_EOI_MISC 0x0030 63 #define USBOTGSS_IRQSTATUS_RAW_MISC 0x0034 64 #define USBOTGSS_IRQSTATUS_MISC 0x0038 65 #define USBOTGSS_IRQENABLE_SET_MISC 0x003c 66 #define USBOTGSS_IRQENABLE_CLR_MISC 0x0040 67 #define USBOTGSS_IRQMISC_OFFSET 0x03fc 68 #define USBOTGSS_UTMI_OTG_STATUS 0x0080 69 #define USBOTGSS_UTMI_OTG_CTRL 0x0084 70 #define USBOTGSS_UTMI_OTG_OFFSET 0x0480 71 #define USBOTGSS_TXFIFO_DEPTH 0x0508 72 #define USBOTGSS_RXFIFO_DEPTH 0x050c 73 #define USBOTGSS_MMRAM_OFFSET 0x0100 74 #define USBOTGSS_FLADJ 0x0104 75 #define USBOTGSS_DEBUG_CFG 0x0108 76 #define USBOTGSS_DEBUG_DATA 0x010c 77 #define USBOTGSS_DEV_EBC_EN 0x0110 78 #define USBOTGSS_DEBUG_OFFSET 0x0600 79 80 /* SYSCONFIG REGISTER */ 81 #define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16) 82 83 /* IRQ_EOI REGISTER */ 84 #define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0) 85 86 /* IRQS0 BITS */ 87 #define USBOTGSS_IRQO_COREIRQ_ST (1 << 0) 88 89 /* IRQMISC BITS */ 90 #define USBOTGSS_IRQMISC_DMADISABLECLR (1 << 17) 91 #define USBOTGSS_IRQMISC_OEVT (1 << 16) 92 #define USBOTGSS_IRQMISC_DRVVBUS_RISE (1 << 13) 93 #define USBOTGSS_IRQMISC_CHRGVBUS_RISE (1 << 12) 94 #define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE (1 << 11) 95 #define USBOTGSS_IRQMISC_IDPULLUP_RISE (1 << 8) 96 #define USBOTGSS_IRQMISC_DRVVBUS_FALL (1 << 5) 97 #define USBOTGSS_IRQMISC_CHRGVBUS_FALL (1 << 4) 98 #define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL (1 << 3) 99 #define USBOTGSS_IRQMISC_IDPULLUP_FALL (1 << 0) 100 101 /* UTMI_OTG_STATUS REGISTER */ 102 #define USBOTGSS_UTMI_OTG_STATUS_DRVVBUS (1 << 5) 103 #define USBOTGSS_UTMI_OTG_STATUS_CHRGVBUS (1 << 4) 104 #define USBOTGSS_UTMI_OTG_STATUS_DISCHRGVBUS (1 << 3) 105 #define USBOTGSS_UTMI_OTG_STATUS_IDPULLUP (1 << 0) 106 107 /* UTMI_OTG_CTRL REGISTER */ 108 #define USBOTGSS_UTMI_OTG_CTRL_SW_MODE (1 << 31) 109 #define USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT (1 << 9) 110 #define USBOTGSS_UTMI_OTG_CTRL_TXBITSTUFFENABLE (1 << 8) 111 #define USBOTGSS_UTMI_OTG_CTRL_IDDIG (1 << 4) 112 #define USBOTGSS_UTMI_OTG_CTRL_SESSEND (1 << 3) 113 #define USBOTGSS_UTMI_OTG_CTRL_SESSVALID (1 << 2) 114 #define USBOTGSS_UTMI_OTG_CTRL_VBUSVALID (1 << 1) 115 116 struct dwc3_omap { 117 struct device *dev; 118 119 int irq; 120 void __iomem *base; 121 122 u32 utmi_otg_ctrl; 123 u32 utmi_otg_offset; 124 u32 irqmisc_offset; 125 u32 irq_eoi_offset; 126 u32 debug_offset; 127 u32 irq0_offset; 128 129 struct extcon_dev *edev; 130 struct notifier_block vbus_nb; 131 struct notifier_block id_nb; 132 133 struct regulator *vbus_reg; 134 }; 135 136 enum omap_dwc3_vbus_id_status { 137 OMAP_DWC3_ID_FLOAT, 138 OMAP_DWC3_ID_GROUND, 139 OMAP_DWC3_VBUS_OFF, 140 OMAP_DWC3_VBUS_VALID, 141 }; 142 143 static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset) 144 { 145 return readl(base + offset); 146 } 147 148 static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value) 149 { 150 writel(value, base + offset); 151 } 152 153 static u32 dwc3_omap_read_utmi_ctrl(struct dwc3_omap *omap) 154 { 155 return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_CTRL + 156 omap->utmi_otg_offset); 157 } 158 159 static void dwc3_omap_write_utmi_ctrl(struct dwc3_omap *omap, u32 value) 160 { 161 dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_CTRL + 162 omap->utmi_otg_offset, value); 163 164 } 165 166 static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap) 167 { 168 return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_RAW_0 - 169 omap->irq0_offset); 170 } 171 172 static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value) 173 { 174 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 - 175 omap->irq0_offset, value); 176 177 } 178 179 static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap) 180 { 181 return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_RAW_MISC + 182 omap->irqmisc_offset); 183 } 184 185 static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value) 186 { 187 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC + 188 omap->irqmisc_offset, value); 189 190 } 191 192 static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value) 193 { 194 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC + 195 omap->irqmisc_offset, value); 196 197 } 198 199 static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value) 200 { 201 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 - 202 omap->irq0_offset, value); 203 } 204 205 static void dwc3_omap_write_irqmisc_clr(struct dwc3_omap *omap, u32 value) 206 { 207 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_MISC + 208 omap->irqmisc_offset, value); 209 } 210 211 static void dwc3_omap_write_irq0_clr(struct dwc3_omap *omap, u32 value) 212 { 213 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_0 - 214 omap->irq0_offset, value); 215 } 216 217 static void dwc3_omap_set_mailbox(struct dwc3_omap *omap, 218 enum omap_dwc3_vbus_id_status status) 219 { 220 int ret; 221 u32 val; 222 223 switch (status) { 224 case OMAP_DWC3_ID_GROUND: 225 if (omap->vbus_reg) { 226 ret = regulator_enable(omap->vbus_reg); 227 if (ret) { 228 dev_err(omap->dev, "regulator enable failed\n"); 229 return; 230 } 231 } 232 233 val = dwc3_omap_read_utmi_ctrl(omap); 234 val &= ~USBOTGSS_UTMI_OTG_CTRL_IDDIG; 235 dwc3_omap_write_utmi_ctrl(omap, val); 236 break; 237 238 case OMAP_DWC3_VBUS_VALID: 239 val = dwc3_omap_read_utmi_ctrl(omap); 240 val &= ~USBOTGSS_UTMI_OTG_CTRL_SESSEND; 241 val |= USBOTGSS_UTMI_OTG_CTRL_VBUSVALID 242 | USBOTGSS_UTMI_OTG_CTRL_SESSVALID; 243 dwc3_omap_write_utmi_ctrl(omap, val); 244 break; 245 246 case OMAP_DWC3_ID_FLOAT: 247 if (omap->vbus_reg) 248 regulator_disable(omap->vbus_reg); 249 val = dwc3_omap_read_utmi_ctrl(omap); 250 val |= USBOTGSS_UTMI_OTG_CTRL_IDDIG; 251 dwc3_omap_write_utmi_ctrl(omap, val); 252 253 case OMAP_DWC3_VBUS_OFF: 254 val = dwc3_omap_read_utmi_ctrl(omap); 255 val &= ~(USBOTGSS_UTMI_OTG_CTRL_SESSVALID 256 | USBOTGSS_UTMI_OTG_CTRL_VBUSVALID); 257 val |= USBOTGSS_UTMI_OTG_CTRL_SESSEND; 258 dwc3_omap_write_utmi_ctrl(omap, val); 259 break; 260 261 default: 262 dev_WARN(omap->dev, "invalid state\n"); 263 } 264 } 265 266 static void dwc3_omap_enable_irqs(struct dwc3_omap *omap); 267 static void dwc3_omap_disable_irqs(struct dwc3_omap *omap); 268 269 static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap) 270 { 271 struct dwc3_omap *omap = _omap; 272 273 if (dwc3_omap_read_irqmisc_status(omap) || 274 dwc3_omap_read_irq0_status(omap)) { 275 /* mask irqs */ 276 dwc3_omap_disable_irqs(omap); 277 return IRQ_WAKE_THREAD; 278 } 279 280 return IRQ_NONE; 281 } 282 283 static irqreturn_t dwc3_omap_interrupt_thread(int irq, void *_omap) 284 { 285 struct dwc3_omap *omap = _omap; 286 u32 reg; 287 288 /* clear irq status flags */ 289 reg = dwc3_omap_read_irqmisc_status(omap); 290 dwc3_omap_write_irqmisc_status(omap, reg); 291 292 reg = dwc3_omap_read_irq0_status(omap); 293 dwc3_omap_write_irq0_status(omap, reg); 294 295 /* unmask irqs */ 296 dwc3_omap_enable_irqs(omap); 297 298 return IRQ_HANDLED; 299 } 300 301 static void dwc3_omap_enable_irqs(struct dwc3_omap *omap) 302 { 303 u32 reg; 304 305 /* enable all IRQs */ 306 reg = USBOTGSS_IRQO_COREIRQ_ST; 307 dwc3_omap_write_irq0_set(omap, reg); 308 309 reg = (USBOTGSS_IRQMISC_OEVT | 310 USBOTGSS_IRQMISC_DRVVBUS_RISE | 311 USBOTGSS_IRQMISC_CHRGVBUS_RISE | 312 USBOTGSS_IRQMISC_DISCHRGVBUS_RISE | 313 USBOTGSS_IRQMISC_IDPULLUP_RISE | 314 USBOTGSS_IRQMISC_DRVVBUS_FALL | 315 USBOTGSS_IRQMISC_CHRGVBUS_FALL | 316 USBOTGSS_IRQMISC_DISCHRGVBUS_FALL | 317 USBOTGSS_IRQMISC_IDPULLUP_FALL); 318 319 dwc3_omap_write_irqmisc_set(omap, reg); 320 } 321 322 static void dwc3_omap_disable_irqs(struct dwc3_omap *omap) 323 { 324 u32 reg; 325 326 /* disable all IRQs */ 327 reg = USBOTGSS_IRQO_COREIRQ_ST; 328 dwc3_omap_write_irq0_clr(omap, reg); 329 330 reg = (USBOTGSS_IRQMISC_OEVT | 331 USBOTGSS_IRQMISC_DRVVBUS_RISE | 332 USBOTGSS_IRQMISC_CHRGVBUS_RISE | 333 USBOTGSS_IRQMISC_DISCHRGVBUS_RISE | 334 USBOTGSS_IRQMISC_IDPULLUP_RISE | 335 USBOTGSS_IRQMISC_DRVVBUS_FALL | 336 USBOTGSS_IRQMISC_CHRGVBUS_FALL | 337 USBOTGSS_IRQMISC_DISCHRGVBUS_FALL | 338 USBOTGSS_IRQMISC_IDPULLUP_FALL); 339 340 dwc3_omap_write_irqmisc_clr(omap, reg); 341 } 342 343 static int dwc3_omap_id_notifier(struct notifier_block *nb, 344 unsigned long event, void *ptr) 345 { 346 struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, id_nb); 347 348 if (event) 349 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND); 350 else 351 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT); 352 353 return NOTIFY_DONE; 354 } 355 356 static int dwc3_omap_vbus_notifier(struct notifier_block *nb, 357 unsigned long event, void *ptr) 358 { 359 struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, vbus_nb); 360 361 if (event) 362 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID); 363 else 364 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF); 365 366 return NOTIFY_DONE; 367 } 368 369 static void dwc3_omap_map_offset(struct dwc3_omap *omap) 370 { 371 struct device_node *node = omap->dev->of_node; 372 373 /* 374 * Differentiate between OMAP5 and AM437x. 375 * 376 * For OMAP5(ES2.0) and AM437x wrapper revision is same, even 377 * though there are changes in wrapper register offsets. 378 * 379 * Using dt compatible to differentiate AM437x. 380 */ 381 if (of_device_is_compatible(node, "ti,am437x-dwc3")) { 382 omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET; 383 omap->irq0_offset = USBOTGSS_IRQ0_OFFSET; 384 omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET; 385 omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET; 386 omap->debug_offset = USBOTGSS_DEBUG_OFFSET; 387 } 388 } 389 390 static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap) 391 { 392 u32 reg; 393 struct device_node *node = omap->dev->of_node; 394 int utmi_mode = 0; 395 396 reg = dwc3_omap_read_utmi_ctrl(omap); 397 398 of_property_read_u32(node, "utmi-mode", &utmi_mode); 399 400 switch (utmi_mode) { 401 case DWC3_OMAP_UTMI_MODE_SW: 402 reg |= USBOTGSS_UTMI_OTG_CTRL_SW_MODE; 403 break; 404 case DWC3_OMAP_UTMI_MODE_HW: 405 reg &= ~USBOTGSS_UTMI_OTG_CTRL_SW_MODE; 406 break; 407 default: 408 dev_WARN(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode); 409 } 410 411 dwc3_omap_write_utmi_ctrl(omap, reg); 412 } 413 414 static int dwc3_omap_extcon_register(struct dwc3_omap *omap) 415 { 416 int ret; 417 struct device_node *node = omap->dev->of_node; 418 struct extcon_dev *edev; 419 420 if (of_property_read_bool(node, "extcon")) { 421 edev = extcon_get_edev_by_phandle(omap->dev, 0); 422 if (IS_ERR(edev)) { 423 dev_vdbg(omap->dev, "couldn't get extcon device\n"); 424 return -EPROBE_DEFER; 425 } 426 427 omap->vbus_nb.notifier_call = dwc3_omap_vbus_notifier; 428 ret = extcon_register_notifier(edev, EXTCON_USB, 429 &omap->vbus_nb); 430 if (ret < 0) 431 dev_vdbg(omap->dev, "failed to register notifier for USB\n"); 432 433 omap->id_nb.notifier_call = dwc3_omap_id_notifier; 434 ret = extcon_register_notifier(edev, EXTCON_USB_HOST, 435 &omap->id_nb); 436 if (ret < 0) 437 dev_vdbg(omap->dev, "failed to register notifier for USB-HOST\n"); 438 439 if (extcon_get_cable_state_(edev, EXTCON_USB) == true) 440 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID); 441 if (extcon_get_cable_state_(edev, EXTCON_USB_HOST) == true) 442 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND); 443 444 omap->edev = edev; 445 } 446 447 return 0; 448 } 449 450 static int dwc3_omap_probe(struct platform_device *pdev) 451 { 452 struct device_node *node = pdev->dev.of_node; 453 454 struct dwc3_omap *omap; 455 struct resource *res; 456 struct device *dev = &pdev->dev; 457 struct regulator *vbus_reg = NULL; 458 459 int ret; 460 int irq; 461 462 u32 reg; 463 464 void __iomem *base; 465 466 if (!node) { 467 dev_err(dev, "device node not found\n"); 468 return -EINVAL; 469 } 470 471 omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL); 472 if (!omap) 473 return -ENOMEM; 474 475 platform_set_drvdata(pdev, omap); 476 477 irq = platform_get_irq(pdev, 0); 478 if (irq < 0) { 479 dev_err(dev, "missing IRQ resource\n"); 480 return -EINVAL; 481 } 482 483 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 484 base = devm_ioremap_resource(dev, res); 485 if (IS_ERR(base)) 486 return PTR_ERR(base); 487 488 if (of_property_read_bool(node, "vbus-supply")) { 489 vbus_reg = devm_regulator_get(dev, "vbus"); 490 if (IS_ERR(vbus_reg)) { 491 dev_err(dev, "vbus init failed\n"); 492 return PTR_ERR(vbus_reg); 493 } 494 } 495 496 omap->dev = dev; 497 omap->irq = irq; 498 omap->base = base; 499 omap->vbus_reg = vbus_reg; 500 501 pm_runtime_enable(dev); 502 ret = pm_runtime_get_sync(dev); 503 if (ret < 0) { 504 dev_err(dev, "get_sync failed with err %d\n", ret); 505 goto err1; 506 } 507 508 dwc3_omap_map_offset(omap); 509 dwc3_omap_set_utmi_mode(omap); 510 511 /* check the DMA Status */ 512 reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG); 513 514 ret = devm_request_threaded_irq(dev, omap->irq, dwc3_omap_interrupt, 515 dwc3_omap_interrupt_thread, IRQF_SHARED, 516 "dwc3-omap", omap); 517 if (ret) { 518 dev_err(dev, "failed to request IRQ #%d --> %d\n", 519 omap->irq, ret); 520 goto err1; 521 } 522 523 ret = dwc3_omap_extcon_register(omap); 524 if (ret < 0) 525 goto err1; 526 527 ret = of_platform_populate(node, NULL, NULL, dev); 528 if (ret) { 529 dev_err(&pdev->dev, "failed to create dwc3 core\n"); 530 goto err2; 531 } 532 533 dwc3_omap_enable_irqs(omap); 534 535 return 0; 536 537 err2: 538 extcon_unregister_notifier(omap->edev, EXTCON_USB, &omap->vbus_nb); 539 extcon_unregister_notifier(omap->edev, EXTCON_USB_HOST, &omap->id_nb); 540 541 err1: 542 pm_runtime_put_sync(dev); 543 pm_runtime_disable(dev); 544 545 return ret; 546 } 547 548 static int dwc3_omap_remove(struct platform_device *pdev) 549 { 550 struct dwc3_omap *omap = platform_get_drvdata(pdev); 551 552 extcon_unregister_notifier(omap->edev, EXTCON_USB, &omap->vbus_nb); 553 extcon_unregister_notifier(omap->edev, EXTCON_USB_HOST, &omap->id_nb); 554 dwc3_omap_disable_irqs(omap); 555 of_platform_depopulate(omap->dev); 556 pm_runtime_put_sync(&pdev->dev); 557 pm_runtime_disable(&pdev->dev); 558 559 return 0; 560 } 561 562 static const struct of_device_id of_dwc3_match[] = { 563 { 564 .compatible = "ti,dwc3" 565 }, 566 { 567 .compatible = "ti,am437x-dwc3" 568 }, 569 { }, 570 }; 571 MODULE_DEVICE_TABLE(of, of_dwc3_match); 572 573 #ifdef CONFIG_PM_SLEEP 574 static int dwc3_omap_suspend(struct device *dev) 575 { 576 struct dwc3_omap *omap = dev_get_drvdata(dev); 577 578 omap->utmi_otg_ctrl = dwc3_omap_read_utmi_ctrl(omap); 579 dwc3_omap_disable_irqs(omap); 580 581 return 0; 582 } 583 584 static int dwc3_omap_resume(struct device *dev) 585 { 586 struct dwc3_omap *omap = dev_get_drvdata(dev); 587 588 dwc3_omap_write_utmi_ctrl(omap, omap->utmi_otg_ctrl); 589 dwc3_omap_enable_irqs(omap); 590 591 pm_runtime_disable(dev); 592 pm_runtime_set_active(dev); 593 pm_runtime_enable(dev); 594 595 return 0; 596 } 597 598 static const struct dev_pm_ops dwc3_omap_dev_pm_ops = { 599 600 SET_SYSTEM_SLEEP_PM_OPS(dwc3_omap_suspend, dwc3_omap_resume) 601 }; 602 603 #define DEV_PM_OPS (&dwc3_omap_dev_pm_ops) 604 #else 605 #define DEV_PM_OPS NULL 606 #endif /* CONFIG_PM_SLEEP */ 607 608 static struct platform_driver dwc3_omap_driver = { 609 .probe = dwc3_omap_probe, 610 .remove = dwc3_omap_remove, 611 .driver = { 612 .name = "omap-dwc3", 613 .of_match_table = of_dwc3_match, 614 .pm = DEV_PM_OPS, 615 }, 616 }; 617 618 module_platform_driver(dwc3_omap_driver); 619 620 MODULE_ALIAS("platform:omap-dwc3"); 621 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 622 MODULE_LICENSE("GPL v2"); 623 MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer"); 624