1 // SPDX-License-Identifier: GPL-2.0 2 /** 3 * dwc3-omap.c - OMAP Specific Glue layer 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 * 10 * This program is free software: you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 of 12 * the License as published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 */ 19 20 #include <linux/module.h> 21 #include <linux/kernel.h> 22 #include <linux/slab.h> 23 #include <linux/irq.h> 24 #include <linux/interrupt.h> 25 #include <linux/platform_device.h> 26 #include <linux/platform_data/dwc3-omap.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/ioport.h> 30 #include <linux/io.h> 31 #include <linux/of.h> 32 #include <linux/of_platform.h> 33 #include <linux/extcon.h> 34 #include <linux/regulator/consumer.h> 35 36 #include <linux/usb/otg.h> 37 38 /* 39 * All these registers belong to OMAP's Wrapper around the 40 * DesignWare USB3 Core. 41 */ 42 43 #define USBOTGSS_REVISION 0x0000 44 #define USBOTGSS_SYSCONFIG 0x0010 45 #define USBOTGSS_IRQ_EOI 0x0020 46 #define USBOTGSS_EOI_OFFSET 0x0008 47 #define USBOTGSS_IRQSTATUS_RAW_0 0x0024 48 #define USBOTGSS_IRQSTATUS_0 0x0028 49 #define USBOTGSS_IRQENABLE_SET_0 0x002c 50 #define USBOTGSS_IRQENABLE_CLR_0 0x0030 51 #define USBOTGSS_IRQ0_OFFSET 0x0004 52 #define USBOTGSS_IRQSTATUS_RAW_1 0x0030 53 #define USBOTGSS_IRQSTATUS_1 0x0034 54 #define USBOTGSS_IRQENABLE_SET_1 0x0038 55 #define USBOTGSS_IRQENABLE_CLR_1 0x003c 56 #define USBOTGSS_IRQSTATUS_RAW_2 0x0040 57 #define USBOTGSS_IRQSTATUS_2 0x0044 58 #define USBOTGSS_IRQENABLE_SET_2 0x0048 59 #define USBOTGSS_IRQENABLE_CLR_2 0x004c 60 #define USBOTGSS_IRQSTATUS_RAW_3 0x0050 61 #define USBOTGSS_IRQSTATUS_3 0x0054 62 #define USBOTGSS_IRQENABLE_SET_3 0x0058 63 #define USBOTGSS_IRQENABLE_CLR_3 0x005c 64 #define USBOTGSS_IRQSTATUS_EOI_MISC 0x0030 65 #define USBOTGSS_IRQSTATUS_RAW_MISC 0x0034 66 #define USBOTGSS_IRQSTATUS_MISC 0x0038 67 #define USBOTGSS_IRQENABLE_SET_MISC 0x003c 68 #define USBOTGSS_IRQENABLE_CLR_MISC 0x0040 69 #define USBOTGSS_IRQMISC_OFFSET 0x03fc 70 #define USBOTGSS_UTMI_OTG_STATUS 0x0080 71 #define USBOTGSS_UTMI_OTG_CTRL 0x0084 72 #define USBOTGSS_UTMI_OTG_OFFSET 0x0480 73 #define USBOTGSS_TXFIFO_DEPTH 0x0508 74 #define USBOTGSS_RXFIFO_DEPTH 0x050c 75 #define USBOTGSS_MMRAM_OFFSET 0x0100 76 #define USBOTGSS_FLADJ 0x0104 77 #define USBOTGSS_DEBUG_CFG 0x0108 78 #define USBOTGSS_DEBUG_DATA 0x010c 79 #define USBOTGSS_DEV_EBC_EN 0x0110 80 #define USBOTGSS_DEBUG_OFFSET 0x0600 81 82 /* SYSCONFIG REGISTER */ 83 #define USBOTGSS_SYSCONFIG_DMADISABLE BIT(16) 84 85 /* IRQ_EOI REGISTER */ 86 #define USBOTGSS_IRQ_EOI_LINE_NUMBER BIT(0) 87 88 /* IRQS0 BITS */ 89 #define USBOTGSS_IRQO_COREIRQ_ST BIT(0) 90 91 /* IRQMISC BITS */ 92 #define USBOTGSS_IRQMISC_DMADISABLECLR BIT(17) 93 #define USBOTGSS_IRQMISC_OEVT BIT(16) 94 #define USBOTGSS_IRQMISC_DRVVBUS_RISE BIT(13) 95 #define USBOTGSS_IRQMISC_CHRGVBUS_RISE BIT(12) 96 #define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE BIT(11) 97 #define USBOTGSS_IRQMISC_IDPULLUP_RISE BIT(8) 98 #define USBOTGSS_IRQMISC_DRVVBUS_FALL BIT(5) 99 #define USBOTGSS_IRQMISC_CHRGVBUS_FALL BIT(4) 100 #define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL BIT(3) 101 #define USBOTGSS_IRQMISC_IDPULLUP_FALL BIT(0) 102 103 /* UTMI_OTG_STATUS REGISTER */ 104 #define USBOTGSS_UTMI_OTG_STATUS_DRVVBUS BIT(5) 105 #define USBOTGSS_UTMI_OTG_STATUS_CHRGVBUS BIT(4) 106 #define USBOTGSS_UTMI_OTG_STATUS_DISCHRGVBUS BIT(3) 107 #define USBOTGSS_UTMI_OTG_STATUS_IDPULLUP BIT(0) 108 109 /* UTMI_OTG_CTRL REGISTER */ 110 #define USBOTGSS_UTMI_OTG_CTRL_SW_MODE BIT(31) 111 #define USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT BIT(9) 112 #define USBOTGSS_UTMI_OTG_CTRL_TXBITSTUFFENABLE BIT(8) 113 #define USBOTGSS_UTMI_OTG_CTRL_IDDIG BIT(4) 114 #define USBOTGSS_UTMI_OTG_CTRL_SESSEND BIT(3) 115 #define USBOTGSS_UTMI_OTG_CTRL_SESSVALID BIT(2) 116 #define USBOTGSS_UTMI_OTG_CTRL_VBUSVALID BIT(1) 117 118 struct dwc3_omap { 119 struct device *dev; 120 121 int irq; 122 void __iomem *base; 123 124 u32 utmi_otg_ctrl; 125 u32 utmi_otg_offset; 126 u32 irqmisc_offset; 127 u32 irq_eoi_offset; 128 u32 debug_offset; 129 u32 irq0_offset; 130 131 struct extcon_dev *edev; 132 struct notifier_block vbus_nb; 133 struct notifier_block id_nb; 134 135 struct regulator *vbus_reg; 136 }; 137 138 enum omap_dwc3_vbus_id_status { 139 OMAP_DWC3_ID_FLOAT, 140 OMAP_DWC3_ID_GROUND, 141 OMAP_DWC3_VBUS_OFF, 142 OMAP_DWC3_VBUS_VALID, 143 }; 144 145 static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset) 146 { 147 return readl(base + offset); 148 } 149 150 static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value) 151 { 152 writel(value, base + offset); 153 } 154 155 static u32 dwc3_omap_read_utmi_ctrl(struct dwc3_omap *omap) 156 { 157 return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_CTRL + 158 omap->utmi_otg_offset); 159 } 160 161 static void dwc3_omap_write_utmi_ctrl(struct dwc3_omap *omap, u32 value) 162 { 163 dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_CTRL + 164 omap->utmi_otg_offset, value); 165 166 } 167 168 static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap) 169 { 170 return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_RAW_0 - 171 omap->irq0_offset); 172 } 173 174 static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value) 175 { 176 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 - 177 omap->irq0_offset, value); 178 179 } 180 181 static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap) 182 { 183 return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_RAW_MISC + 184 omap->irqmisc_offset); 185 } 186 187 static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value) 188 { 189 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC + 190 omap->irqmisc_offset, value); 191 192 } 193 194 static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value) 195 { 196 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC + 197 omap->irqmisc_offset, value); 198 199 } 200 201 static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value) 202 { 203 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 - 204 omap->irq0_offset, value); 205 } 206 207 static void dwc3_omap_write_irqmisc_clr(struct dwc3_omap *omap, u32 value) 208 { 209 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_MISC + 210 omap->irqmisc_offset, value); 211 } 212 213 static void dwc3_omap_write_irq0_clr(struct dwc3_omap *omap, u32 value) 214 { 215 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_0 - 216 omap->irq0_offset, value); 217 } 218 219 static void dwc3_omap_set_mailbox(struct dwc3_omap *omap, 220 enum omap_dwc3_vbus_id_status status) 221 { 222 int ret; 223 u32 val; 224 225 switch (status) { 226 case OMAP_DWC3_ID_GROUND: 227 if (omap->vbus_reg) { 228 ret = regulator_enable(omap->vbus_reg); 229 if (ret) { 230 dev_err(omap->dev, "regulator enable failed\n"); 231 return; 232 } 233 } 234 235 val = dwc3_omap_read_utmi_ctrl(omap); 236 val &= ~USBOTGSS_UTMI_OTG_CTRL_IDDIG; 237 dwc3_omap_write_utmi_ctrl(omap, val); 238 break; 239 240 case OMAP_DWC3_VBUS_VALID: 241 val = dwc3_omap_read_utmi_ctrl(omap); 242 val &= ~USBOTGSS_UTMI_OTG_CTRL_SESSEND; 243 val |= USBOTGSS_UTMI_OTG_CTRL_VBUSVALID 244 | USBOTGSS_UTMI_OTG_CTRL_SESSVALID; 245 dwc3_omap_write_utmi_ctrl(omap, val); 246 break; 247 248 case OMAP_DWC3_ID_FLOAT: 249 if (omap->vbus_reg) 250 regulator_disable(omap->vbus_reg); 251 val = dwc3_omap_read_utmi_ctrl(omap); 252 val |= USBOTGSS_UTMI_OTG_CTRL_IDDIG; 253 dwc3_omap_write_utmi_ctrl(omap, val); 254 break; 255 256 case OMAP_DWC3_VBUS_OFF: 257 val = dwc3_omap_read_utmi_ctrl(omap); 258 val &= ~(USBOTGSS_UTMI_OTG_CTRL_SESSVALID 259 | USBOTGSS_UTMI_OTG_CTRL_VBUSVALID); 260 val |= USBOTGSS_UTMI_OTG_CTRL_SESSEND; 261 dwc3_omap_write_utmi_ctrl(omap, val); 262 break; 263 264 default: 265 dev_WARN(omap->dev, "invalid state\n"); 266 } 267 } 268 269 static void dwc3_omap_enable_irqs(struct dwc3_omap *omap); 270 static void dwc3_omap_disable_irqs(struct dwc3_omap *omap); 271 272 static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap) 273 { 274 struct dwc3_omap *omap = _omap; 275 276 if (dwc3_omap_read_irqmisc_status(omap) || 277 dwc3_omap_read_irq0_status(omap)) { 278 /* mask irqs */ 279 dwc3_omap_disable_irqs(omap); 280 return IRQ_WAKE_THREAD; 281 } 282 283 return IRQ_NONE; 284 } 285 286 static irqreturn_t dwc3_omap_interrupt_thread(int irq, void *_omap) 287 { 288 struct dwc3_omap *omap = _omap; 289 u32 reg; 290 291 /* clear irq status flags */ 292 reg = dwc3_omap_read_irqmisc_status(omap); 293 dwc3_omap_write_irqmisc_status(omap, reg); 294 295 reg = dwc3_omap_read_irq0_status(omap); 296 dwc3_omap_write_irq0_status(omap, reg); 297 298 /* unmask irqs */ 299 dwc3_omap_enable_irqs(omap); 300 301 return IRQ_HANDLED; 302 } 303 304 static void dwc3_omap_enable_irqs(struct dwc3_omap *omap) 305 { 306 u32 reg; 307 308 /* enable all IRQs */ 309 reg = USBOTGSS_IRQO_COREIRQ_ST; 310 dwc3_omap_write_irq0_set(omap, reg); 311 312 reg = (USBOTGSS_IRQMISC_OEVT | 313 USBOTGSS_IRQMISC_DRVVBUS_RISE | 314 USBOTGSS_IRQMISC_CHRGVBUS_RISE | 315 USBOTGSS_IRQMISC_DISCHRGVBUS_RISE | 316 USBOTGSS_IRQMISC_IDPULLUP_RISE | 317 USBOTGSS_IRQMISC_DRVVBUS_FALL | 318 USBOTGSS_IRQMISC_CHRGVBUS_FALL | 319 USBOTGSS_IRQMISC_DISCHRGVBUS_FALL | 320 USBOTGSS_IRQMISC_IDPULLUP_FALL); 321 322 dwc3_omap_write_irqmisc_set(omap, reg); 323 } 324 325 static void dwc3_omap_disable_irqs(struct dwc3_omap *omap) 326 { 327 u32 reg; 328 329 /* disable all IRQs */ 330 reg = USBOTGSS_IRQO_COREIRQ_ST; 331 dwc3_omap_write_irq0_clr(omap, reg); 332 333 reg = (USBOTGSS_IRQMISC_OEVT | 334 USBOTGSS_IRQMISC_DRVVBUS_RISE | 335 USBOTGSS_IRQMISC_CHRGVBUS_RISE | 336 USBOTGSS_IRQMISC_DISCHRGVBUS_RISE | 337 USBOTGSS_IRQMISC_IDPULLUP_RISE | 338 USBOTGSS_IRQMISC_DRVVBUS_FALL | 339 USBOTGSS_IRQMISC_CHRGVBUS_FALL | 340 USBOTGSS_IRQMISC_DISCHRGVBUS_FALL | 341 USBOTGSS_IRQMISC_IDPULLUP_FALL); 342 343 dwc3_omap_write_irqmisc_clr(omap, reg); 344 } 345 346 static int dwc3_omap_id_notifier(struct notifier_block *nb, 347 unsigned long event, void *ptr) 348 { 349 struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, id_nb); 350 351 if (event) 352 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND); 353 else 354 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT); 355 356 return NOTIFY_DONE; 357 } 358 359 static int dwc3_omap_vbus_notifier(struct notifier_block *nb, 360 unsigned long event, void *ptr) 361 { 362 struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, vbus_nb); 363 364 if (event) 365 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID); 366 else 367 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF); 368 369 return NOTIFY_DONE; 370 } 371 372 static void dwc3_omap_map_offset(struct dwc3_omap *omap) 373 { 374 struct device_node *node = omap->dev->of_node; 375 376 /* 377 * Differentiate between OMAP5 and AM437x. 378 * 379 * For OMAP5(ES2.0) and AM437x wrapper revision is same, even 380 * though there are changes in wrapper register offsets. 381 * 382 * Using dt compatible to differentiate AM437x. 383 */ 384 if (of_device_is_compatible(node, "ti,am437x-dwc3")) { 385 omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET; 386 omap->irq0_offset = USBOTGSS_IRQ0_OFFSET; 387 omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET; 388 omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET; 389 omap->debug_offset = USBOTGSS_DEBUG_OFFSET; 390 } 391 } 392 393 static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap) 394 { 395 u32 reg; 396 struct device_node *node = omap->dev->of_node; 397 u32 utmi_mode = 0; 398 399 reg = dwc3_omap_read_utmi_ctrl(omap); 400 401 of_property_read_u32(node, "utmi-mode", &utmi_mode); 402 403 switch (utmi_mode) { 404 case DWC3_OMAP_UTMI_MODE_SW: 405 reg |= USBOTGSS_UTMI_OTG_CTRL_SW_MODE; 406 break; 407 case DWC3_OMAP_UTMI_MODE_HW: 408 reg &= ~USBOTGSS_UTMI_OTG_CTRL_SW_MODE; 409 break; 410 default: 411 dev_WARN(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode); 412 } 413 414 dwc3_omap_write_utmi_ctrl(omap, reg); 415 } 416 417 static int dwc3_omap_extcon_register(struct dwc3_omap *omap) 418 { 419 int ret; 420 struct device_node *node = omap->dev->of_node; 421 struct extcon_dev *edev; 422 423 if (of_property_read_bool(node, "extcon")) { 424 edev = extcon_get_edev_by_phandle(omap->dev, 0); 425 if (IS_ERR(edev)) { 426 dev_vdbg(omap->dev, "couldn't get extcon device\n"); 427 return -EPROBE_DEFER; 428 } 429 430 omap->vbus_nb.notifier_call = dwc3_omap_vbus_notifier; 431 ret = devm_extcon_register_notifier(omap->dev, edev, 432 EXTCON_USB, &omap->vbus_nb); 433 if (ret < 0) 434 dev_vdbg(omap->dev, "failed to register notifier for USB\n"); 435 436 omap->id_nb.notifier_call = dwc3_omap_id_notifier; 437 ret = devm_extcon_register_notifier(omap->dev, edev, 438 EXTCON_USB_HOST, &omap->id_nb); 439 if (ret < 0) 440 dev_vdbg(omap->dev, "failed to register notifier for USB-HOST\n"); 441 442 if (extcon_get_state(edev, EXTCON_USB) == true) 443 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID); 444 if (extcon_get_state(edev, EXTCON_USB_HOST) == true) 445 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND); 446 447 omap->edev = edev; 448 } 449 450 return 0; 451 } 452 453 static int dwc3_omap_probe(struct platform_device *pdev) 454 { 455 struct device_node *node = pdev->dev.of_node; 456 457 struct dwc3_omap *omap; 458 struct resource *res; 459 struct device *dev = &pdev->dev; 460 struct regulator *vbus_reg = NULL; 461 462 int ret; 463 int irq; 464 465 u32 reg; 466 467 void __iomem *base; 468 469 if (!node) { 470 dev_err(dev, "device node not found\n"); 471 return -EINVAL; 472 } 473 474 omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL); 475 if (!omap) 476 return -ENOMEM; 477 478 platform_set_drvdata(pdev, omap); 479 480 irq = platform_get_irq(pdev, 0); 481 if (irq < 0) { 482 dev_err(dev, "missing IRQ resource: %d\n", irq); 483 return irq; 484 } 485 486 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 487 base = devm_ioremap_resource(dev, res); 488 if (IS_ERR(base)) 489 return PTR_ERR(base); 490 491 if (of_property_read_bool(node, "vbus-supply")) { 492 vbus_reg = devm_regulator_get(dev, "vbus"); 493 if (IS_ERR(vbus_reg)) { 494 dev_err(dev, "vbus init failed\n"); 495 return PTR_ERR(vbus_reg); 496 } 497 } 498 499 omap->dev = dev; 500 omap->irq = irq; 501 omap->base = base; 502 omap->vbus_reg = vbus_reg; 503 504 pm_runtime_enable(dev); 505 ret = pm_runtime_get_sync(dev); 506 if (ret < 0) { 507 dev_err(dev, "get_sync failed with err %d\n", ret); 508 goto err1; 509 } 510 511 dwc3_omap_map_offset(omap); 512 dwc3_omap_set_utmi_mode(omap); 513 514 /* check the DMA Status */ 515 reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG); 516 517 ret = dwc3_omap_extcon_register(omap); 518 if (ret < 0) 519 goto err1; 520 521 ret = of_platform_populate(node, NULL, NULL, dev); 522 if (ret) { 523 dev_err(&pdev->dev, "failed to create dwc3 core\n"); 524 goto err1; 525 } 526 527 ret = devm_request_threaded_irq(dev, omap->irq, dwc3_omap_interrupt, 528 dwc3_omap_interrupt_thread, IRQF_SHARED, 529 "dwc3-omap", omap); 530 if (ret) { 531 dev_err(dev, "failed to request IRQ #%d --> %d\n", 532 omap->irq, ret); 533 goto err1; 534 } 535 dwc3_omap_enable_irqs(omap); 536 return 0; 537 538 err1: 539 pm_runtime_put_sync(dev); 540 pm_runtime_disable(dev); 541 542 return ret; 543 } 544 545 static int dwc3_omap_remove(struct platform_device *pdev) 546 { 547 struct dwc3_omap *omap = platform_get_drvdata(pdev); 548 549 dwc3_omap_disable_irqs(omap); 550 disable_irq(omap->irq); 551 of_platform_depopulate(omap->dev); 552 pm_runtime_put_sync(&pdev->dev); 553 pm_runtime_disable(&pdev->dev); 554 555 return 0; 556 } 557 558 static const struct of_device_id of_dwc3_match[] = { 559 { 560 .compatible = "ti,dwc3" 561 }, 562 { 563 .compatible = "ti,am437x-dwc3" 564 }, 565 { }, 566 }; 567 MODULE_DEVICE_TABLE(of, of_dwc3_match); 568 569 #ifdef CONFIG_PM_SLEEP 570 static int dwc3_omap_suspend(struct device *dev) 571 { 572 struct dwc3_omap *omap = dev_get_drvdata(dev); 573 574 omap->utmi_otg_ctrl = dwc3_omap_read_utmi_ctrl(omap); 575 dwc3_omap_disable_irqs(omap); 576 577 return 0; 578 } 579 580 static int dwc3_omap_resume(struct device *dev) 581 { 582 struct dwc3_omap *omap = dev_get_drvdata(dev); 583 584 dwc3_omap_write_utmi_ctrl(omap, omap->utmi_otg_ctrl); 585 dwc3_omap_enable_irqs(omap); 586 587 pm_runtime_disable(dev); 588 pm_runtime_set_active(dev); 589 pm_runtime_enable(dev); 590 591 return 0; 592 } 593 594 static const struct dev_pm_ops dwc3_omap_dev_pm_ops = { 595 596 SET_SYSTEM_SLEEP_PM_OPS(dwc3_omap_suspend, dwc3_omap_resume) 597 }; 598 599 #define DEV_PM_OPS (&dwc3_omap_dev_pm_ops) 600 #else 601 #define DEV_PM_OPS NULL 602 #endif /* CONFIG_PM_SLEEP */ 603 604 static struct platform_driver dwc3_omap_driver = { 605 .probe = dwc3_omap_probe, 606 .remove = dwc3_omap_remove, 607 .driver = { 608 .name = "omap-dwc3", 609 .of_match_table = of_dwc3_match, 610 .pm = DEV_PM_OPS, 611 }, 612 }; 613 614 module_platform_driver(dwc3_omap_driver); 615 616 MODULE_ALIAS("platform:omap-dwc3"); 617 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 618 MODULE_LICENSE("GPL v2"); 619 MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer"); 620