1 /** 2 * dwc3-omap.c - OMAP Specific Glue layer 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * This program is free software: you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 of 11 * the License as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include <linux/module.h> 20 #include <linux/kernel.h> 21 #include <linux/slab.h> 22 #include <linux/interrupt.h> 23 #include <linux/platform_device.h> 24 #include <linux/platform_data/dwc3-omap.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/ioport.h> 28 #include <linux/io.h> 29 #include <linux/of.h> 30 #include <linux/of_platform.h> 31 #include <linux/extcon.h> 32 #include <linux/regulator/consumer.h> 33 34 #include <linux/usb/otg.h> 35 36 /* 37 * All these registers belong to OMAP's Wrapper around the 38 * DesignWare USB3 Core. 39 */ 40 41 #define USBOTGSS_REVISION 0x0000 42 #define USBOTGSS_SYSCONFIG 0x0010 43 #define USBOTGSS_IRQ_EOI 0x0020 44 #define USBOTGSS_EOI_OFFSET 0x0008 45 #define USBOTGSS_IRQSTATUS_RAW_0 0x0024 46 #define USBOTGSS_IRQSTATUS_0 0x0028 47 #define USBOTGSS_IRQENABLE_SET_0 0x002c 48 #define USBOTGSS_IRQENABLE_CLR_0 0x0030 49 #define USBOTGSS_IRQ0_OFFSET 0x0004 50 #define USBOTGSS_IRQSTATUS_RAW_1 0x0030 51 #define USBOTGSS_IRQSTATUS_1 0x0034 52 #define USBOTGSS_IRQENABLE_SET_1 0x0038 53 #define USBOTGSS_IRQENABLE_CLR_1 0x003c 54 #define USBOTGSS_IRQSTATUS_RAW_2 0x0040 55 #define USBOTGSS_IRQSTATUS_2 0x0044 56 #define USBOTGSS_IRQENABLE_SET_2 0x0048 57 #define USBOTGSS_IRQENABLE_CLR_2 0x004c 58 #define USBOTGSS_IRQSTATUS_RAW_3 0x0050 59 #define USBOTGSS_IRQSTATUS_3 0x0054 60 #define USBOTGSS_IRQENABLE_SET_3 0x0058 61 #define USBOTGSS_IRQENABLE_CLR_3 0x005c 62 #define USBOTGSS_IRQSTATUS_EOI_MISC 0x0030 63 #define USBOTGSS_IRQSTATUS_RAW_MISC 0x0034 64 #define USBOTGSS_IRQSTATUS_MISC 0x0038 65 #define USBOTGSS_IRQENABLE_SET_MISC 0x003c 66 #define USBOTGSS_IRQENABLE_CLR_MISC 0x0040 67 #define USBOTGSS_IRQMISC_OFFSET 0x03fc 68 #define USBOTGSS_UTMI_OTG_STATUS 0x0080 69 #define USBOTGSS_UTMI_OTG_CTRL 0x0084 70 #define USBOTGSS_UTMI_OTG_OFFSET 0x0480 71 #define USBOTGSS_TXFIFO_DEPTH 0x0508 72 #define USBOTGSS_RXFIFO_DEPTH 0x050c 73 #define USBOTGSS_MMRAM_OFFSET 0x0100 74 #define USBOTGSS_FLADJ 0x0104 75 #define USBOTGSS_DEBUG_CFG 0x0108 76 #define USBOTGSS_DEBUG_DATA 0x010c 77 #define USBOTGSS_DEV_EBC_EN 0x0110 78 #define USBOTGSS_DEBUG_OFFSET 0x0600 79 80 /* SYSCONFIG REGISTER */ 81 #define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16) 82 83 /* IRQ_EOI REGISTER */ 84 #define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0) 85 86 /* IRQS0 BITS */ 87 #define USBOTGSS_IRQO_COREIRQ_ST (1 << 0) 88 89 /* IRQMISC BITS */ 90 #define USBOTGSS_IRQMISC_DMADISABLECLR (1 << 17) 91 #define USBOTGSS_IRQMISC_OEVT (1 << 16) 92 #define USBOTGSS_IRQMISC_DRVVBUS_RISE (1 << 13) 93 #define USBOTGSS_IRQMISC_CHRGVBUS_RISE (1 << 12) 94 #define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE (1 << 11) 95 #define USBOTGSS_IRQMISC_IDPULLUP_RISE (1 << 8) 96 #define USBOTGSS_IRQMISC_DRVVBUS_FALL (1 << 5) 97 #define USBOTGSS_IRQMISC_CHRGVBUS_FALL (1 << 4) 98 #define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL (1 << 3) 99 #define USBOTGSS_IRQMISC_IDPULLUP_FALL (1 << 0) 100 101 /* UTMI_OTG_STATUS REGISTER */ 102 #define USBOTGSS_UTMI_OTG_STATUS_DRVVBUS (1 << 5) 103 #define USBOTGSS_UTMI_OTG_STATUS_CHRGVBUS (1 << 4) 104 #define USBOTGSS_UTMI_OTG_STATUS_DISCHRGVBUS (1 << 3) 105 #define USBOTGSS_UTMI_OTG_STATUS_IDPULLUP (1 << 0) 106 107 /* UTMI_OTG_CTRL REGISTER */ 108 #define USBOTGSS_UTMI_OTG_CTRL_SW_MODE (1 << 31) 109 #define USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT (1 << 9) 110 #define USBOTGSS_UTMI_OTG_CTRL_TXBITSTUFFENABLE (1 << 8) 111 #define USBOTGSS_UTMI_OTG_CTRL_IDDIG (1 << 4) 112 #define USBOTGSS_UTMI_OTG_CTRL_SESSEND (1 << 3) 113 #define USBOTGSS_UTMI_OTG_CTRL_SESSVALID (1 << 2) 114 #define USBOTGSS_UTMI_OTG_CTRL_VBUSVALID (1 << 1) 115 116 struct dwc3_omap { 117 struct device *dev; 118 119 int irq; 120 void __iomem *base; 121 122 u32 utmi_otg_ctrl; 123 u32 utmi_otg_offset; 124 u32 irqmisc_offset; 125 u32 irq_eoi_offset; 126 u32 debug_offset; 127 u32 irq0_offset; 128 129 struct extcon_dev *edev; 130 struct notifier_block vbus_nb; 131 struct notifier_block id_nb; 132 133 struct regulator *vbus_reg; 134 }; 135 136 enum omap_dwc3_vbus_id_status { 137 OMAP_DWC3_ID_FLOAT, 138 OMAP_DWC3_ID_GROUND, 139 OMAP_DWC3_VBUS_OFF, 140 OMAP_DWC3_VBUS_VALID, 141 }; 142 143 static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset) 144 { 145 return readl(base + offset); 146 } 147 148 static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value) 149 { 150 writel(value, base + offset); 151 } 152 153 static u32 dwc3_omap_read_utmi_ctrl(struct dwc3_omap *omap) 154 { 155 return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_CTRL + 156 omap->utmi_otg_offset); 157 } 158 159 static void dwc3_omap_write_utmi_ctrl(struct dwc3_omap *omap, u32 value) 160 { 161 dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_CTRL + 162 omap->utmi_otg_offset, value); 163 164 } 165 166 static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap) 167 { 168 return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0 - 169 omap->irq0_offset); 170 } 171 172 static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value) 173 { 174 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 - 175 omap->irq0_offset, value); 176 177 } 178 179 static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap) 180 { 181 return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_MISC + 182 omap->irqmisc_offset); 183 } 184 185 static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value) 186 { 187 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC + 188 omap->irqmisc_offset, value); 189 190 } 191 192 static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value) 193 { 194 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC + 195 omap->irqmisc_offset, value); 196 197 } 198 199 static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value) 200 { 201 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 - 202 omap->irq0_offset, value); 203 } 204 205 static void dwc3_omap_write_irqmisc_clr(struct dwc3_omap *omap, u32 value) 206 { 207 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_MISC + 208 omap->irqmisc_offset, value); 209 } 210 211 static void dwc3_omap_write_irq0_clr(struct dwc3_omap *omap, u32 value) 212 { 213 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_0 - 214 omap->irq0_offset, value); 215 } 216 217 static void dwc3_omap_set_mailbox(struct dwc3_omap *omap, 218 enum omap_dwc3_vbus_id_status status) 219 { 220 int ret; 221 u32 val; 222 223 switch (status) { 224 case OMAP_DWC3_ID_GROUND: 225 if (omap->vbus_reg) { 226 ret = regulator_enable(omap->vbus_reg); 227 if (ret) { 228 dev_err(omap->dev, "regulator enable failed\n"); 229 return; 230 } 231 } 232 233 val = dwc3_omap_read_utmi_ctrl(omap); 234 val &= ~(USBOTGSS_UTMI_OTG_CTRL_IDDIG 235 | USBOTGSS_UTMI_OTG_CTRL_VBUSVALID 236 | USBOTGSS_UTMI_OTG_CTRL_SESSEND); 237 val |= USBOTGSS_UTMI_OTG_CTRL_SESSVALID 238 | USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT; 239 dwc3_omap_write_utmi_ctrl(omap, val); 240 break; 241 242 case OMAP_DWC3_VBUS_VALID: 243 val = dwc3_omap_read_utmi_ctrl(omap); 244 val &= ~USBOTGSS_UTMI_OTG_CTRL_SESSEND; 245 val |= USBOTGSS_UTMI_OTG_CTRL_IDDIG 246 | USBOTGSS_UTMI_OTG_CTRL_VBUSVALID 247 | USBOTGSS_UTMI_OTG_CTRL_SESSVALID 248 | USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT; 249 dwc3_omap_write_utmi_ctrl(omap, val); 250 break; 251 252 case OMAP_DWC3_ID_FLOAT: 253 if (omap->vbus_reg) 254 regulator_disable(omap->vbus_reg); 255 256 case OMAP_DWC3_VBUS_OFF: 257 val = dwc3_omap_read_utmi_ctrl(omap); 258 val &= ~(USBOTGSS_UTMI_OTG_CTRL_SESSVALID 259 | USBOTGSS_UTMI_OTG_CTRL_VBUSVALID 260 | USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT); 261 val |= USBOTGSS_UTMI_OTG_CTRL_SESSEND 262 | USBOTGSS_UTMI_OTG_CTRL_IDDIG; 263 dwc3_omap_write_utmi_ctrl(omap, val); 264 break; 265 266 default: 267 dev_WARN(omap->dev, "invalid state\n"); 268 } 269 } 270 271 static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap) 272 { 273 struct dwc3_omap *omap = _omap; 274 u32 reg; 275 276 reg = dwc3_omap_read_irqmisc_status(omap); 277 278 dwc3_omap_write_irqmisc_status(omap, reg); 279 280 reg = dwc3_omap_read_irq0_status(omap); 281 282 dwc3_omap_write_irq0_status(omap, reg); 283 284 return IRQ_HANDLED; 285 } 286 287 static void dwc3_omap_enable_irqs(struct dwc3_omap *omap) 288 { 289 u32 reg; 290 291 /* enable all IRQs */ 292 reg = USBOTGSS_IRQO_COREIRQ_ST; 293 dwc3_omap_write_irq0_set(omap, reg); 294 295 reg = (USBOTGSS_IRQMISC_OEVT | 296 USBOTGSS_IRQMISC_DRVVBUS_RISE | 297 USBOTGSS_IRQMISC_CHRGVBUS_RISE | 298 USBOTGSS_IRQMISC_DISCHRGVBUS_RISE | 299 USBOTGSS_IRQMISC_IDPULLUP_RISE | 300 USBOTGSS_IRQMISC_DRVVBUS_FALL | 301 USBOTGSS_IRQMISC_CHRGVBUS_FALL | 302 USBOTGSS_IRQMISC_DISCHRGVBUS_FALL | 303 USBOTGSS_IRQMISC_IDPULLUP_FALL); 304 305 dwc3_omap_write_irqmisc_set(omap, reg); 306 } 307 308 static void dwc3_omap_disable_irqs(struct dwc3_omap *omap) 309 { 310 u32 reg; 311 312 /* disable all IRQs */ 313 reg = USBOTGSS_IRQO_COREIRQ_ST; 314 dwc3_omap_write_irq0_clr(omap, reg); 315 316 reg = (USBOTGSS_IRQMISC_OEVT | 317 USBOTGSS_IRQMISC_DRVVBUS_RISE | 318 USBOTGSS_IRQMISC_CHRGVBUS_RISE | 319 USBOTGSS_IRQMISC_DISCHRGVBUS_RISE | 320 USBOTGSS_IRQMISC_IDPULLUP_RISE | 321 USBOTGSS_IRQMISC_DRVVBUS_FALL | 322 USBOTGSS_IRQMISC_CHRGVBUS_FALL | 323 USBOTGSS_IRQMISC_DISCHRGVBUS_FALL | 324 USBOTGSS_IRQMISC_IDPULLUP_FALL); 325 326 dwc3_omap_write_irqmisc_clr(omap, reg); 327 } 328 329 static int dwc3_omap_id_notifier(struct notifier_block *nb, 330 unsigned long event, void *ptr) 331 { 332 struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, id_nb); 333 334 if (event) 335 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND); 336 else 337 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT); 338 339 return NOTIFY_DONE; 340 } 341 342 static int dwc3_omap_vbus_notifier(struct notifier_block *nb, 343 unsigned long event, void *ptr) 344 { 345 struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, vbus_nb); 346 347 if (event) 348 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID); 349 else 350 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF); 351 352 return NOTIFY_DONE; 353 } 354 355 static void dwc3_omap_map_offset(struct dwc3_omap *omap) 356 { 357 struct device_node *node = omap->dev->of_node; 358 359 /* 360 * Differentiate between OMAP5 and AM437x. 361 * 362 * For OMAP5(ES2.0) and AM437x wrapper revision is same, even 363 * though there are changes in wrapper register offsets. 364 * 365 * Using dt compatible to differentiate AM437x. 366 */ 367 if (of_device_is_compatible(node, "ti,am437x-dwc3")) { 368 omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET; 369 omap->irq0_offset = USBOTGSS_IRQ0_OFFSET; 370 omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET; 371 omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET; 372 omap->debug_offset = USBOTGSS_DEBUG_OFFSET; 373 } 374 } 375 376 static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap) 377 { 378 u32 reg; 379 struct device_node *node = omap->dev->of_node; 380 int utmi_mode = 0; 381 382 reg = dwc3_omap_read_utmi_ctrl(omap); 383 384 of_property_read_u32(node, "utmi-mode", &utmi_mode); 385 386 switch (utmi_mode) { 387 case DWC3_OMAP_UTMI_MODE_SW: 388 reg |= USBOTGSS_UTMI_OTG_CTRL_SW_MODE; 389 break; 390 case DWC3_OMAP_UTMI_MODE_HW: 391 reg &= ~USBOTGSS_UTMI_OTG_CTRL_SW_MODE; 392 break; 393 default: 394 dev_WARN(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode); 395 } 396 397 dwc3_omap_write_utmi_ctrl(omap, reg); 398 } 399 400 static int dwc3_omap_extcon_register(struct dwc3_omap *omap) 401 { 402 int ret; 403 struct device_node *node = omap->dev->of_node; 404 struct extcon_dev *edev; 405 406 if (of_property_read_bool(node, "extcon")) { 407 edev = extcon_get_edev_by_phandle(omap->dev, 0); 408 if (IS_ERR(edev)) { 409 dev_vdbg(omap->dev, "couldn't get extcon device\n"); 410 return -EPROBE_DEFER; 411 } 412 413 omap->vbus_nb.notifier_call = dwc3_omap_vbus_notifier; 414 ret = extcon_register_notifier(edev, EXTCON_USB, 415 &omap->vbus_nb); 416 if (ret < 0) 417 dev_vdbg(omap->dev, "failed to register notifier for USB\n"); 418 419 omap->id_nb.notifier_call = dwc3_omap_id_notifier; 420 ret = extcon_register_notifier(edev, EXTCON_USB_HOST, 421 &omap->id_nb); 422 if (ret < 0) 423 dev_vdbg(omap->dev, "failed to register notifier for USB-HOST\n"); 424 425 if (extcon_get_cable_state_(edev, EXTCON_USB) == true) 426 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID); 427 if (extcon_get_cable_state_(edev, EXTCON_USB_HOST) == true) 428 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND); 429 430 omap->edev = edev; 431 } 432 433 return 0; 434 } 435 436 static int dwc3_omap_probe(struct platform_device *pdev) 437 { 438 struct device_node *node = pdev->dev.of_node; 439 440 struct dwc3_omap *omap; 441 struct resource *res; 442 struct device *dev = &pdev->dev; 443 struct regulator *vbus_reg = NULL; 444 445 int ret; 446 int irq; 447 448 u32 reg; 449 450 void __iomem *base; 451 452 if (!node) { 453 dev_err(dev, "device node not found\n"); 454 return -EINVAL; 455 } 456 457 omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL); 458 if (!omap) 459 return -ENOMEM; 460 461 platform_set_drvdata(pdev, omap); 462 463 irq = platform_get_irq(pdev, 0); 464 if (irq < 0) { 465 dev_err(dev, "missing IRQ resource\n"); 466 return -EINVAL; 467 } 468 469 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 470 base = devm_ioremap_resource(dev, res); 471 if (IS_ERR(base)) 472 return PTR_ERR(base); 473 474 if (of_property_read_bool(node, "vbus-supply")) { 475 vbus_reg = devm_regulator_get(dev, "vbus"); 476 if (IS_ERR(vbus_reg)) { 477 dev_err(dev, "vbus init failed\n"); 478 return PTR_ERR(vbus_reg); 479 } 480 } 481 482 omap->dev = dev; 483 omap->irq = irq; 484 omap->base = base; 485 omap->vbus_reg = vbus_reg; 486 487 pm_runtime_enable(dev); 488 ret = pm_runtime_get_sync(dev); 489 if (ret < 0) { 490 dev_err(dev, "get_sync failed with err %d\n", ret); 491 goto err1; 492 } 493 494 dwc3_omap_map_offset(omap); 495 dwc3_omap_set_utmi_mode(omap); 496 497 /* check the DMA Status */ 498 reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG); 499 500 ret = devm_request_irq(dev, omap->irq, dwc3_omap_interrupt, 0, 501 "dwc3-omap", omap); 502 if (ret) { 503 dev_err(dev, "failed to request IRQ #%d --> %d\n", 504 omap->irq, ret); 505 goto err1; 506 } 507 508 ret = dwc3_omap_extcon_register(omap); 509 if (ret < 0) 510 goto err1; 511 512 ret = of_platform_populate(node, NULL, NULL, dev); 513 if (ret) { 514 dev_err(&pdev->dev, "failed to create dwc3 core\n"); 515 goto err2; 516 } 517 518 dwc3_omap_enable_irqs(omap); 519 520 return 0; 521 522 err2: 523 extcon_unregister_notifier(omap->edev, EXTCON_USB, &omap->vbus_nb); 524 extcon_unregister_notifier(omap->edev, EXTCON_USB_HOST, &omap->id_nb); 525 526 err1: 527 pm_runtime_put_sync(dev); 528 pm_runtime_disable(dev); 529 530 return ret; 531 } 532 533 static int dwc3_omap_remove(struct platform_device *pdev) 534 { 535 struct dwc3_omap *omap = platform_get_drvdata(pdev); 536 537 extcon_unregister_notifier(omap->edev, EXTCON_USB, &omap->vbus_nb); 538 extcon_unregister_notifier(omap->edev, EXTCON_USB_HOST, &omap->id_nb); 539 dwc3_omap_disable_irqs(omap); 540 of_platform_depopulate(omap->dev); 541 pm_runtime_put_sync(&pdev->dev); 542 pm_runtime_disable(&pdev->dev); 543 544 return 0; 545 } 546 547 static const struct of_device_id of_dwc3_match[] = { 548 { 549 .compatible = "ti,dwc3" 550 }, 551 { 552 .compatible = "ti,am437x-dwc3" 553 }, 554 { }, 555 }; 556 MODULE_DEVICE_TABLE(of, of_dwc3_match); 557 558 #ifdef CONFIG_PM_SLEEP 559 static int dwc3_omap_suspend(struct device *dev) 560 { 561 struct dwc3_omap *omap = dev_get_drvdata(dev); 562 563 omap->utmi_otg_ctrl = dwc3_omap_read_utmi_ctrl(omap); 564 dwc3_omap_disable_irqs(omap); 565 566 return 0; 567 } 568 569 static int dwc3_omap_resume(struct device *dev) 570 { 571 struct dwc3_omap *omap = dev_get_drvdata(dev); 572 573 dwc3_omap_write_utmi_ctrl(omap, omap->utmi_otg_ctrl); 574 dwc3_omap_enable_irqs(omap); 575 576 pm_runtime_disable(dev); 577 pm_runtime_set_active(dev); 578 pm_runtime_enable(dev); 579 580 return 0; 581 } 582 583 static const struct dev_pm_ops dwc3_omap_dev_pm_ops = { 584 585 SET_SYSTEM_SLEEP_PM_OPS(dwc3_omap_suspend, dwc3_omap_resume) 586 }; 587 588 #define DEV_PM_OPS (&dwc3_omap_dev_pm_ops) 589 #else 590 #define DEV_PM_OPS NULL 591 #endif /* CONFIG_PM_SLEEP */ 592 593 static struct platform_driver dwc3_omap_driver = { 594 .probe = dwc3_omap_probe, 595 .remove = dwc3_omap_remove, 596 .driver = { 597 .name = "omap-dwc3", 598 .of_match_table = of_dwc3_match, 599 .pm = DEV_PM_OPS, 600 }, 601 }; 602 603 module_platform_driver(dwc3_omap_driver); 604 605 MODULE_ALIAS("platform:omap-dwc3"); 606 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 607 MODULE_LICENSE("GPL v2"); 608 MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer"); 609