1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * DWC3 glue for Cavium Octeon III SOCs. 4 * 5 * Copyright (C) 2010-2017 Cavium Networks 6 * Copyright (C) 2023 RACOM s.r.o. 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/bits.h> 11 #include <linux/device.h> 12 #include <linux/delay.h> 13 #include <linux/io.h> 14 #include <linux/module.h> 15 #include <linux/mutex.h> 16 #include <linux/of_platform.h> 17 18 /* 19 * USB Control Register 20 */ 21 #define USBDRD_UCTL_CTL 0x00 22 /* BIST fast-clear mode select. A BIST run with this bit set 23 * clears all entries in USBH RAMs to 0x0. 24 */ 25 # define USBDRD_UCTL_CTL_CLEAR_BIST BIT_ULL(63) 26 /* 1 = Start BIST and cleared by hardware */ 27 # define USBDRD_UCTL_CTL_START_BIST BIT_ULL(62) 28 /* Reference clock select for SuperSpeed and HighSpeed PLLs: 29 * 0x0 = Both PLLs use DLMC_REF_CLK0 for reference clock 30 * 0x1 = Both PLLs use DLMC_REF_CLK1 for reference clock 31 * 0x2 = SuperSpeed PLL uses DLMC_REF_CLK0 for reference clock & 32 * HighSpeed PLL uses PLL_REF_CLK for reference clck 33 * 0x3 = SuperSpeed PLL uses DLMC_REF_CLK1 for reference clock & 34 * HighSpeed PLL uses PLL_REF_CLK for reference clck 35 */ 36 # define USBDRD_UCTL_CTL_REF_CLK_SEL GENMASK_ULL(61, 60) 37 /* 1 = Spread-spectrum clock enable, 0 = SS clock disable */ 38 # define USBDRD_UCTL_CTL_SSC_EN BIT_ULL(59) 39 /* Spread-spectrum clock modulation range: 40 * 0x0 = -4980 ppm downspread 41 * 0x1 = -4492 ppm downspread 42 * 0x2 = -4003 ppm downspread 43 * 0x3 - 0x7 = Reserved 44 */ 45 # define USBDRD_UCTL_CTL_SSC_RANGE GENMASK_ULL(58, 56) 46 /* Enable non-standard oscillator frequencies: 47 * [55:53] = modules -1 48 * [52:47] = 2's complement push amount, 0 = Feature disabled 49 */ 50 # define USBDRD_UCTL_CTL_SSC_REF_CLK_SEL GENMASK_ULL(55, 47) 51 /* Reference clock multiplier for non-standard frequencies: 52 * 0x19 = 100MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1 53 * 0x28 = 125MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1 54 * 0x32 = 50MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1 55 * Other Values = Reserved 56 */ 57 # define USBDRD_UCTL_CTL_MPLL_MULTIPLIER GENMASK_ULL(46, 40) 58 /* Enable reference clock to prescaler for SuperSpeed functionality. 59 * Should always be set to "1" 60 */ 61 # define USBDRD_UCTL_CTL_REF_SSP_EN BIT_ULL(39) 62 /* Divide the reference clock by 2 before entering the 63 * REF_CLK_FSEL divider: 64 * If REF_CLK_SEL = 0x0 or 0x1, then only 0x0 is legal 65 * If REF_CLK_SEL = 0x2 or 0x3, then: 66 * 0x1 = DLMC_REF_CLK* is 125MHz 67 * 0x0 = DLMC_REF_CLK* is another supported frequency 68 */ 69 # define USBDRD_UCTL_CTL_REF_CLK_DIV2 BIT_ULL(38) 70 /* Select reference clock freqnuency for both PLL blocks: 71 * 0x27 = REF_CLK_SEL is 0x0 or 0x1 72 * 0x07 = REF_CLK_SEL is 0x2 or 0x3 73 */ 74 # define USBDRD_UCTL_CTL_REF_CLK_FSEL GENMASK_ULL(37, 32) 75 /* Controller clock enable. */ 76 # define USBDRD_UCTL_CTL_H_CLK_EN BIT_ULL(30) 77 /* Select bypass input to controller clock divider: 78 * 0x0 = Use divided coprocessor clock from H_CLKDIV 79 * 0x1 = Use clock from GPIO pins 80 */ 81 # define USBDRD_UCTL_CTL_H_CLK_BYP_SEL BIT_ULL(29) 82 /* Reset controller clock divider. */ 83 # define USBDRD_UCTL_CTL_H_CLKDIV_RST BIT_ULL(28) 84 /* Clock divider select: 85 * 0x0 = divide by 1 86 * 0x1 = divide by 2 87 * 0x2 = divide by 4 88 * 0x3 = divide by 6 89 * 0x4 = divide by 8 90 * 0x5 = divide by 16 91 * 0x6 = divide by 24 92 * 0x7 = divide by 32 93 */ 94 # define USBDRD_UCTL_CTL_H_CLKDIV_SEL GENMASK_ULL(26, 24) 95 /* USB3 port permanently attached: 0x0 = No, 0x1 = Yes */ 96 # define USBDRD_UCTL_CTL_USB3_PORT_PERM_ATTACH BIT_ULL(21) 97 /* USB2 port permanently attached: 0x0 = No, 0x1 = Yes */ 98 # define USBDRD_UCTL_CTL_USB2_PORT_PERM_ATTACH BIT_ULL(20) 99 /* Disable SuperSpeed PHY: 0x0 = No, 0x1 = Yes */ 100 # define USBDRD_UCTL_CTL_USB3_PORT_DISABLE BIT_ULL(18) 101 /* Disable HighSpeed PHY: 0x0 = No, 0x1 = Yes */ 102 # define USBDRD_UCTL_CTL_USB2_PORT_DISABLE BIT_ULL(16) 103 /* Enable PHY SuperSpeed block power: 0x0 = No, 0x1 = Yes */ 104 # define USBDRD_UCTL_CTL_SS_POWER_EN BIT_ULL(14) 105 /* Enable PHY HighSpeed block power: 0x0 = No, 0x1 = Yes */ 106 # define USBDRD_UCTL_CTL_HS_POWER_EN BIT_ULL(12) 107 /* Enable USB UCTL interface clock: 0xx = No, 0x1 = Yes */ 108 # define USBDRD_UCTL_CTL_CSCLK_EN BIT_ULL(4) 109 /* Controller mode: 0x0 = Host, 0x1 = Device */ 110 # define USBDRD_UCTL_CTL_DRD_MODE BIT_ULL(3) 111 /* PHY reset */ 112 # define USBDRD_UCTL_CTL_UPHY_RST BIT_ULL(2) 113 /* Software reset UAHC */ 114 # define USBDRD_UCTL_CTL_UAHC_RST BIT_ULL(1) 115 /* Software resets UCTL */ 116 # define USBDRD_UCTL_CTL_UCTL_RST BIT_ULL(0) 117 118 #define USBDRD_UCTL_BIST_STATUS 0x08 119 #define USBDRD_UCTL_SPARE0 0x10 120 #define USBDRD_UCTL_INTSTAT 0x30 121 #define USBDRD_UCTL_PORT_CFG_HS(port) (0x40 + (0x20 * port)) 122 #define USBDRD_UCTL_PORT_CFG_SS(port) (0x48 + (0x20 * port)) 123 #define USBDRD_UCTL_PORT_CR_DBG_CFG(port) (0x50 + (0x20 * port)) 124 #define USBDRD_UCTL_PORT_CR_DBG_STATUS(port) (0x58 + (0x20 * port)) 125 126 /* 127 * UCTL Configuration Register 128 */ 129 #define USBDRD_UCTL_HOST_CFG 0xe0 130 /* Indicates minimum value of all received BELT values */ 131 # define USBDRD_UCTL_HOST_CFG_HOST_CURRENT_BELT GENMASK_ULL(59, 48) 132 /* HS jitter adjustment */ 133 # define USBDRD_UCTL_HOST_CFG_FLA GENMASK_ULL(37, 32) 134 /* Bus-master enable: 0x0 = Disabled (stall DMAs), 0x1 = enabled */ 135 # define USBDRD_UCTL_HOST_CFG_BME BIT_ULL(28) 136 /* Overcurrent protection enable: 0x0 = unavailable, 0x1 = available */ 137 # define USBDRD_UCTL_HOST_OCI_EN BIT_ULL(27) 138 /* Overcurrent sene selection: 139 * 0x0 = Overcurrent indication from off-chip is active-low 140 * 0x1 = Overcurrent indication from off-chip is active-high 141 */ 142 # define USBDRD_UCTL_HOST_OCI_ACTIVE_HIGH_EN BIT_ULL(26) 143 /* Port power control enable: 0x0 = unavailable, 0x1 = available */ 144 # define USBDRD_UCTL_HOST_PPC_EN BIT_ULL(25) 145 /* Port power control sense selection: 146 * 0x0 = Port power to off-chip is active-low 147 * 0x1 = Port power to off-chip is active-high 148 */ 149 # define USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN BIT_ULL(24) 150 151 /* 152 * UCTL Shim Features Register 153 */ 154 #define USBDRD_UCTL_SHIM_CFG 0xe8 155 /* Out-of-bound UAHC register access: 0 = read, 1 = write */ 156 # define USBDRD_UCTL_SHIM_CFG_XS_NCB_OOB_WRN BIT_ULL(63) 157 /* SRCID error log for out-of-bound UAHC register access: 158 * [59:58] = chipID 159 * [57] = Request source: 0 = core, 1 = NCB-device 160 * [56:51] = Core/NCB-device number, [56] always 0 for NCB devices 161 * [50:48] = SubID 162 */ 163 # define USBDRD_UCTL_SHIM_CFG_XS_NCB_OOB_OSRC GENMASK_ULL(59, 48) 164 /* Error log for bad UAHC DMA access: 0 = Read log, 1 = Write log */ 165 # define USBDRD_UCTL_SHIM_CFG_XM_BAD_DMA_WRN BIT_ULL(47) 166 /* Encoded error type for bad UAHC DMA */ 167 # define USBDRD_UCTL_SHIM_CFG_XM_BAD_DMA_TYPE GENMASK_ULL(43, 40) 168 /* Select the IOI read command used by DMA accesses */ 169 # define USBDRD_UCTL_SHIM_CFG_DMA_READ_CMD BIT_ULL(12) 170 /* Select endian format for DMA accesses to the L2C: 171 * 0x0 = Little endian 172 * 0x1 = Big endian 173 * 0x2 = Reserved 174 * 0x3 = Reserved 175 */ 176 # define USBDRD_UCTL_SHIM_CFG_DMA_ENDIAN_MODE GENMASK_ULL(9, 8) 177 /* Select endian format for IOI CSR access to UAHC: 178 * 0x0 = Little endian 179 * 0x1 = Big endian 180 * 0x2 = Reserved 181 * 0x3 = Reserved 182 */ 183 # define USBDRD_UCTL_SHIM_CFG_CSR_ENDIAN_MODE GENMASK_ULL(1, 0) 184 185 #define USBDRD_UCTL_ECC 0xf0 186 #define USBDRD_UCTL_SPARE1 0xf8 187 188 struct dwc3_octeon { 189 struct device *dev; 190 void __iomem *base; 191 }; 192 193 #define DWC3_GPIO_POWER_NONE (-1) 194 195 #ifdef CONFIG_CAVIUM_OCTEON_SOC 196 #include <asm/octeon/octeon.h> 197 static inline uint64_t dwc3_octeon_readq(void __iomem *addr) 198 { 199 return cvmx_readq_csr(addr); 200 } 201 202 static inline void dwc3_octeon_writeq(void __iomem *base, uint64_t val) 203 { 204 cvmx_writeq_csr(base, val); 205 } 206 207 static void dwc3_octeon_config_gpio(int index, int gpio) 208 { 209 union cvmx_gpio_bit_cfgx gpio_bit; 210 211 if ((OCTEON_IS_MODEL(OCTEON_CN73XX) || 212 OCTEON_IS_MODEL(OCTEON_CNF75XX)) 213 && gpio <= 31) { 214 gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio)); 215 gpio_bit.s.tx_oe = 1; 216 gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x15); 217 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64); 218 } else if (gpio <= 15) { 219 gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio)); 220 gpio_bit.s.tx_oe = 1; 221 gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x19); 222 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64); 223 } else { 224 gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_XBIT_CFGX(gpio)); 225 gpio_bit.s.tx_oe = 1; 226 gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x19); 227 cvmx_write_csr(CVMX_GPIO_XBIT_CFGX(gpio), gpio_bit.u64); 228 } 229 } 230 #else 231 static inline uint64_t dwc3_octeon_readq(void __iomem *addr) 232 { 233 return 0; 234 } 235 236 static inline void dwc3_octeon_writeq(void __iomem *base, uint64_t val) { } 237 238 static inline void dwc3_octeon_config_gpio(int index, int gpio) { } 239 240 static uint64_t octeon_get_io_clock_rate(void) 241 { 242 return 150000000; 243 } 244 #endif 245 246 static int dwc3_octeon_get_divider(void) 247 { 248 static const uint8_t clk_div[] = { 1, 2, 4, 6, 8, 16, 24, 32 }; 249 int div = 0; 250 251 while (div < ARRAY_SIZE(clk_div)) { 252 uint64_t rate = octeon_get_io_clock_rate() / clk_div[div]; 253 if (rate <= 300000000 && rate >= 150000000) 254 return div; 255 div++; 256 } 257 258 return -EINVAL; 259 } 260 261 static int dwc3_octeon_setup(struct dwc3_octeon *octeon, 262 int ref_clk_sel, int ref_clk_fsel, int mpll_mul, 263 int power_gpio, int power_active_low) 264 { 265 u64 val; 266 int div; 267 struct device *dev = octeon->dev; 268 void __iomem *uctl_ctl_reg = octeon->base + USBDRD_UCTL_CTL; 269 void __iomem *uctl_host_cfg_reg = octeon->base + USBDRD_UCTL_HOST_CFG; 270 271 /* 272 * Step 1: Wait for all voltages to be stable...that surely 273 * happened before starting the kernel. SKIP 274 */ 275 276 /* Step 2: Select GPIO for overcurrent indication, if desired. SKIP */ 277 278 /* Step 3: Assert all resets. */ 279 val = dwc3_octeon_readq(uctl_ctl_reg); 280 val |= USBDRD_UCTL_CTL_UPHY_RST | 281 USBDRD_UCTL_CTL_UAHC_RST | 282 USBDRD_UCTL_CTL_UCTL_RST; 283 dwc3_octeon_writeq(uctl_ctl_reg, val); 284 285 /* Step 4a: Reset the clock dividers. */ 286 val = dwc3_octeon_readq(uctl_ctl_reg); 287 val |= USBDRD_UCTL_CTL_H_CLKDIV_RST; 288 dwc3_octeon_writeq(uctl_ctl_reg, val); 289 290 /* Step 4b: Select controller clock frequency. */ 291 div = dwc3_octeon_get_divider(); 292 if (div < 0) { 293 dev_err(dev, "clock divider invalid\n"); 294 return div; 295 } 296 val = dwc3_octeon_readq(uctl_ctl_reg); 297 val &= ~USBDRD_UCTL_CTL_H_CLKDIV_SEL; 298 val |= FIELD_PREP(USBDRD_UCTL_CTL_H_CLKDIV_SEL, div); 299 val |= USBDRD_UCTL_CTL_H_CLK_EN; 300 dwc3_octeon_writeq(uctl_ctl_reg, val); 301 val = dwc3_octeon_readq(uctl_ctl_reg); 302 if ((div != FIELD_GET(USBDRD_UCTL_CTL_H_CLKDIV_SEL, val)) || 303 (!(FIELD_GET(USBDRD_UCTL_CTL_H_CLK_EN, val)))) { 304 dev_err(dev, "clock init failure (UCTL_CTL=%016llx)\n", val); 305 return -EINVAL; 306 } 307 308 /* Step 4c: Deassert the controller clock divider reset. */ 309 val &= ~USBDRD_UCTL_CTL_H_CLKDIV_RST; 310 dwc3_octeon_writeq(uctl_ctl_reg, val); 311 312 /* Step 5a: Reference clock configuration. */ 313 val = dwc3_octeon_readq(uctl_ctl_reg); 314 val &= ~USBDRD_UCTL_CTL_REF_CLK_DIV2; 315 val &= ~USBDRD_UCTL_CTL_REF_CLK_SEL; 316 val |= FIELD_PREP(USBDRD_UCTL_CTL_REF_CLK_SEL, ref_clk_sel); 317 318 val &= ~USBDRD_UCTL_CTL_REF_CLK_FSEL; 319 val |= FIELD_PREP(USBDRD_UCTL_CTL_REF_CLK_FSEL, ref_clk_fsel); 320 321 val &= ~USBDRD_UCTL_CTL_MPLL_MULTIPLIER; 322 val |= FIELD_PREP(USBDRD_UCTL_CTL_MPLL_MULTIPLIER, mpll_mul); 323 324 /* Step 5b: Configure and enable spread-spectrum for SuperSpeed. */ 325 val |= USBDRD_UCTL_CTL_SSC_EN; 326 327 /* Step 5c: Enable SuperSpeed. */ 328 val |= USBDRD_UCTL_CTL_REF_SSP_EN; 329 330 /* Step 5d: Configure PHYs. SKIP */ 331 332 /* Step 6a & 6b: Power up PHYs. */ 333 val |= USBDRD_UCTL_CTL_HS_POWER_EN; 334 val |= USBDRD_UCTL_CTL_SS_POWER_EN; 335 dwc3_octeon_writeq(uctl_ctl_reg, val); 336 337 /* Step 7: Wait 10 controller-clock cycles to take effect. */ 338 udelay(10); 339 340 /* Step 8a: Deassert UCTL reset signal. */ 341 val = dwc3_octeon_readq(uctl_ctl_reg); 342 val &= ~USBDRD_UCTL_CTL_UCTL_RST; 343 dwc3_octeon_writeq(uctl_ctl_reg, val); 344 345 /* Step 8b: Wait 10 controller-clock cycles. */ 346 udelay(10); 347 348 /* Step 8c: Setup power control. */ 349 val = dwc3_octeon_readq(uctl_host_cfg_reg); 350 val |= USBDRD_UCTL_HOST_PPC_EN; 351 if (power_gpio == DWC3_GPIO_POWER_NONE) { 352 val &= ~USBDRD_UCTL_HOST_PPC_EN; 353 } else { 354 val |= USBDRD_UCTL_HOST_PPC_EN; 355 dwc3_octeon_config_gpio(((__force uintptr_t)octeon->base >> 24) & 1, 356 power_gpio); 357 dev_dbg(dev, "power control is using gpio%d\n", power_gpio); 358 } 359 if (power_active_low) 360 val &= ~USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN; 361 else 362 val |= USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN; 363 dwc3_octeon_writeq(uctl_host_cfg_reg, val); 364 365 /* Step 8d: Deassert UAHC reset signal. */ 366 val = dwc3_octeon_readq(uctl_ctl_reg); 367 val &= ~USBDRD_UCTL_CTL_UAHC_RST; 368 dwc3_octeon_writeq(uctl_ctl_reg, val); 369 370 /* Step 8e: Wait 10 controller-clock cycles. */ 371 udelay(10); 372 373 /* Step 9: Enable conditional coprocessor clock of UCTL. */ 374 val = dwc3_octeon_readq(uctl_ctl_reg); 375 val |= USBDRD_UCTL_CTL_CSCLK_EN; 376 dwc3_octeon_writeq(uctl_ctl_reg, val); 377 378 /*Step 10: Set for host mode only. */ 379 val = dwc3_octeon_readq(uctl_ctl_reg); 380 val &= ~USBDRD_UCTL_CTL_DRD_MODE; 381 dwc3_octeon_writeq(uctl_ctl_reg, val); 382 383 return 0; 384 } 385 386 static void dwc3_octeon_set_endian_mode(struct dwc3_octeon *octeon) 387 { 388 u64 val; 389 void __iomem *uctl_shim_cfg_reg = octeon->base + USBDRD_UCTL_SHIM_CFG; 390 391 val = dwc3_octeon_readq(uctl_shim_cfg_reg); 392 val &= ~USBDRD_UCTL_SHIM_CFG_DMA_ENDIAN_MODE; 393 val &= ~USBDRD_UCTL_SHIM_CFG_CSR_ENDIAN_MODE; 394 #ifdef __BIG_ENDIAN 395 val |= FIELD_PREP(USBDRD_UCTL_SHIM_CFG_DMA_ENDIAN_MODE, 1); 396 val |= FIELD_PREP(USBDRD_UCTL_SHIM_CFG_CSR_ENDIAN_MODE, 1); 397 #endif 398 dwc3_octeon_writeq(uctl_shim_cfg_reg, val); 399 } 400 401 static void dwc3_octeon_phy_reset(struct dwc3_octeon *octeon) 402 { 403 u64 val; 404 void __iomem *uctl_ctl_reg = octeon->base + USBDRD_UCTL_CTL; 405 406 val = dwc3_octeon_readq(uctl_ctl_reg); 407 val &= ~USBDRD_UCTL_CTL_UPHY_RST; 408 dwc3_octeon_writeq(uctl_ctl_reg, val); 409 } 410 411 static int dwc3_octeon_probe(struct platform_device *pdev) 412 { 413 struct device *dev = &pdev->dev; 414 struct device_node *node = dev->of_node; 415 struct dwc3_octeon *octeon; 416 const char *hs_clock_type, *ss_clock_type; 417 int ref_clk_sel, ref_clk_fsel, mpll_mul; 418 int power_active_low, power_gpio; 419 int err, len; 420 u32 clock_rate; 421 422 if (of_property_read_u32(node, "refclk-frequency", &clock_rate)) { 423 dev_err(dev, "No UCTL \"refclk-frequency\"\n"); 424 return -EINVAL; 425 } 426 if (of_property_read_string(node, "refclk-type-ss", &ss_clock_type)) { 427 dev_err(dev, "No UCTL \"refclk-type-ss\"\n"); 428 return -EINVAL; 429 } 430 if (of_property_read_string(node, "refclk-type-hs", &hs_clock_type)) { 431 dev_err(dev, "No UCTL \"refclk-type-hs\"\n"); 432 return -EINVAL; 433 } 434 435 ref_clk_sel = 2; 436 if (strcmp("dlmc_ref_clk0", ss_clock_type) == 0) { 437 if (strcmp(hs_clock_type, "dlmc_ref_clk0") == 0) 438 ref_clk_sel = 0; 439 else if (strcmp(hs_clock_type, "pll_ref_clk")) 440 dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n", 441 hs_clock_type); 442 } else if (strcmp(ss_clock_type, "dlmc_ref_clk1") == 0) { 443 if (strcmp(hs_clock_type, "dlmc_ref_clk1") == 0) { 444 ref_clk_sel = 1; 445 } else { 446 ref_clk_sel = 3; 447 if (strcmp(hs_clock_type, "pll_ref_clk")) 448 dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n", 449 hs_clock_type); 450 } 451 } else { 452 dev_warn(dev, "Invalid SS clock type %s, using dlmc_ref_clk0 instead\n", 453 ss_clock_type); 454 } 455 456 ref_clk_fsel = 0x07; 457 switch (clock_rate) { 458 default: 459 dev_warn(dev, "Invalid ref_clk %u, using 100000000 instead\n", 460 clock_rate); 461 fallthrough; 462 case 100000000: 463 mpll_mul = 0x19; 464 if (ref_clk_sel < 2) 465 ref_clk_fsel = 0x27; 466 break; 467 case 50000000: 468 mpll_mul = 0x32; 469 break; 470 case 125000000: 471 mpll_mul = 0x28; 472 break; 473 } 474 475 power_gpio = DWC3_GPIO_POWER_NONE; 476 power_active_low = 0; 477 if (of_find_property(node, "power", &len)) { 478 u32 gpio_pwr[3]; 479 480 switch (len) { 481 case 8: 482 of_property_read_u32_array(node, "power", gpio_pwr, 2); 483 break; 484 case 12: 485 of_property_read_u32_array(node, "power", gpio_pwr, 3); 486 power_active_low = gpio_pwr[2] & 0x01; 487 break; 488 default: 489 dev_err(dev, "invalid power configuration\n"); 490 return -EINVAL; 491 } 492 power_gpio = gpio_pwr[1]; 493 } 494 495 octeon = devm_kzalloc(dev, sizeof(*octeon), GFP_KERNEL); 496 if (!octeon) 497 return -ENOMEM; 498 499 octeon->dev = dev; 500 octeon->base = devm_platform_ioremap_resource(pdev, 0); 501 if (IS_ERR(octeon->base)) 502 return PTR_ERR(octeon->base); 503 504 err = dwc3_octeon_setup(octeon, ref_clk_sel, ref_clk_fsel, mpll_mul, 505 power_gpio, power_active_low); 506 if (err) 507 return err; 508 509 dwc3_octeon_set_endian_mode(octeon); 510 dwc3_octeon_phy_reset(octeon); 511 512 platform_set_drvdata(pdev, octeon); 513 514 return of_platform_populate(node, NULL, NULL, dev); 515 } 516 517 static void dwc3_octeon_remove(struct platform_device *pdev) 518 { 519 struct dwc3_octeon *octeon = platform_get_drvdata(pdev); 520 521 of_platform_depopulate(octeon->dev); 522 } 523 524 static const struct of_device_id dwc3_octeon_of_match[] = { 525 { .compatible = "cavium,octeon-7130-usb-uctl" }, 526 { }, 527 }; 528 MODULE_DEVICE_TABLE(of, dwc3_octeon_of_match); 529 530 static struct platform_driver dwc3_octeon_driver = { 531 .probe = dwc3_octeon_probe, 532 .remove_new = dwc3_octeon_remove, 533 .driver = { 534 .name = "dwc3-octeon", 535 .of_match_table = dwc3_octeon_of_match, 536 }, 537 }; 538 module_platform_driver(dwc3_octeon_driver); 539 540 MODULE_ALIAS("platform:dwc3-octeon"); 541 MODULE_AUTHOR("Ladislav Michl <ladis@linux-mips.org>"); 542 MODULE_LICENSE("GPL"); 543 MODULE_DESCRIPTION("DesignWare USB3 OCTEON III Glue Layer"); 544