1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * dwc3-google.c - Google DWC3 Specific Glue Layer 4 * 5 * Copyright (c) 2025, Google LLC 6 * Author: Roy Luo <royluo@google.com> 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/clk.h> 11 #include <linux/iopoll.h> 12 #include <linux/irq.h> 13 #include <linux/kernel.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_domain.h> 19 #include <linux/regmap.h> 20 #include <linux/reset.h> 21 #include "core.h" 22 #include "glue.h" 23 24 /* HOST CFG registers */ 25 #define HC_STATUS_OFFSET 0x0 26 #define HC_STATUS_CURRENT_POWER_STATE_U2PMU GENMASK(1, 0) 27 #define HC_STATUS_CURRENT_POWER_STATE_U3PMU GENMASK(4, 3) 28 29 #define HOST_CFG1_OFFSET 0x4 30 #define HOST_CFG1_PME_EN BIT(3) 31 #define HOST_CFG1_PM_POWER_STATE_REQUEST GENMASK(5, 4) 32 #define HOST_CFG1_PM_POWER_STATE_D0 0x0 33 #define HOST_CFG1_PM_POWER_STATE_D3 0x3 34 35 /* USBINT registers */ 36 #define USBINT_CFG1_OFFSET 0x0 37 #define USBINT_CFG1_USBDRD_PME_GEN_U2P_INTR_MSK BIT(2) 38 #define USBINT_CFG1_USBDRD_PME_GEN_U3P_INTR_MSK BIT(3) 39 #define USBINT_CFG1_USBDRD_PME_GEN_U2P_INTR_INT_EN BIT(8) 40 #define USBINT_CFG1_USBDRD_PME_GEN_U3P_INTR_INT_EN BIT(9) 41 #define USBINT_CFG1_USBDRD_PME_GEN_U2_INTR_CLR BIT(14) 42 #define USBINT_CFG1_USBDRD_PME_GEN_U3_INTR_CLR BIT(15) 43 44 #define USBINT_STATUS_OFFSET 0x4 45 #define USBINT_STATUS_USBDRD_PME_GEN_U2P_INTR_STS_RAW BIT(2) 46 #define USBINT_STATUS_USBDRD_PME_GEN_U3P_INTR_STS_RAW BIT(3) 47 48 #define USBCS_TOP_CTRL_CFG1_OFFSET 0xc 49 #define USBCS_TOP_CTRL_CFG1_USB2ONLY_MODE BIT(5) 50 51 #define DWC3_GOOGLE_MAX_RESETS 4 52 53 struct dwc3_google { 54 struct device *dev; 55 struct dwc3 dwc; 56 struct clk_bulk_data *clks; 57 int num_clks; 58 struct reset_control_bulk_data rsts[DWC3_GOOGLE_MAX_RESETS]; 59 int num_rsts; 60 struct reset_control *non_sticky_rst; 61 struct device *usb_psw_pd; 62 struct device_link *usb_psw_pd_dl; 63 struct notifier_block usb_psw_pd_nb; 64 struct device *usb_top_pd; 65 struct device_link *usb_top_pd_dl; 66 struct regmap *usb_cfg_regmap; 67 unsigned int host_cfg_offset; 68 unsigned int usbint_cfg_offset; 69 int hs_pme_irq; 70 int ss_pme_irq; 71 bool is_usb2only; 72 bool is_hibernation; 73 }; 74 75 #define to_dwc3_google(d) container_of_const((d), struct dwc3_google, dwc) 76 77 static int dwc3_google_rst_init(struct dwc3_google *google) 78 { 79 int ret; 80 81 google->num_rsts = 4; 82 google->rsts[0].id = "non_sticky"; 83 google->rsts[1].id = "sticky"; 84 google->rsts[2].id = "drd_bus"; 85 google->rsts[3].id = "top"; 86 87 ret = devm_reset_control_bulk_get_exclusive(google->dev, 88 google->num_rsts, 89 google->rsts); 90 91 if (ret < 0) 92 return ret; 93 94 google->non_sticky_rst = google->rsts[0].rstc; 95 96 return 0; 97 } 98 99 static int dwc3_google_set_pmu_state(struct dwc3_google *google, int state) 100 { 101 u32 reg; 102 int ret; 103 104 regmap_read(google->usb_cfg_regmap, 105 google->host_cfg_offset + HOST_CFG1_OFFSET, ®); 106 107 reg &= ~HOST_CFG1_PM_POWER_STATE_REQUEST; 108 reg |= (FIELD_PREP(HOST_CFG1_PM_POWER_STATE_REQUEST, state) | 109 HOST_CFG1_PME_EN); 110 regmap_write(google->usb_cfg_regmap, 111 google->host_cfg_offset + HOST_CFG1_OFFSET, reg); 112 113 ret = regmap_read_poll_timeout(google->usb_cfg_regmap, 114 google->host_cfg_offset + HC_STATUS_OFFSET, reg, 115 (FIELD_GET(HC_STATUS_CURRENT_POWER_STATE_U2PMU, 116 reg) == state && 117 FIELD_GET(HC_STATUS_CURRENT_POWER_STATE_U3PMU, 118 reg) == state), 119 10, 10000); 120 121 if (ret) 122 dev_err(google->dev, "failed to set PMU state %d\n", state); 123 124 return ret; 125 } 126 127 /* 128 * Clear pme interrupts and report their status. 129 * The hardware requires write-1 then write-0 sequence to clear the interrupt bits. 130 */ 131 static u32 dwc3_google_clear_pme_irqs(struct dwc3_google *google) 132 { 133 u32 irq_status, reg_set, reg_clear; 134 135 regmap_read(google->usb_cfg_regmap, 136 google->usbint_cfg_offset + USBINT_STATUS_OFFSET, &irq_status); 137 138 irq_status &= (USBINT_STATUS_USBDRD_PME_GEN_U2P_INTR_STS_RAW | 139 USBINT_STATUS_USBDRD_PME_GEN_U3P_INTR_STS_RAW); 140 if (!irq_status) 141 return irq_status; 142 143 regmap_read(google->usb_cfg_regmap, 144 google->usbint_cfg_offset + USBINT_CFG1_OFFSET, ®_set); 145 146 reg_clear = reg_set; 147 if (irq_status & USBINT_STATUS_USBDRD_PME_GEN_U2P_INTR_STS_RAW) { 148 reg_set |= USBINT_CFG1_USBDRD_PME_GEN_U2_INTR_CLR; 149 reg_clear &= ~USBINT_CFG1_USBDRD_PME_GEN_U2_INTR_CLR; 150 } 151 if (irq_status & USBINT_STATUS_USBDRD_PME_GEN_U3P_INTR_STS_RAW) { 152 reg_set |= USBINT_CFG1_USBDRD_PME_GEN_U3_INTR_CLR; 153 reg_clear &= ~USBINT_CFG1_USBDRD_PME_GEN_U3_INTR_CLR; 154 } 155 156 regmap_write(google->usb_cfg_regmap, 157 google->usbint_cfg_offset + USBINT_CFG1_OFFSET, reg_set); 158 regmap_write(google->usb_cfg_regmap, 159 google->usbint_cfg_offset + USBINT_CFG1_OFFSET, reg_clear); 160 161 return irq_status; 162 } 163 164 static void dwc3_google_enable_pme_irq(struct dwc3_google *google) 165 { 166 u32 reg; 167 168 regmap_read(google->usb_cfg_regmap, 169 google->usbint_cfg_offset + USBINT_CFG1_OFFSET, ®); 170 reg &= ~(USBINT_CFG1_USBDRD_PME_GEN_U2P_INTR_MSK | 171 USBINT_CFG1_USBDRD_PME_GEN_U3P_INTR_MSK); 172 reg |= (USBINT_CFG1_USBDRD_PME_GEN_U2P_INTR_INT_EN | 173 USBINT_CFG1_USBDRD_PME_GEN_U3P_INTR_INT_EN); 174 regmap_write(google->usb_cfg_regmap, 175 google->usbint_cfg_offset + USBINT_CFG1_OFFSET, reg); 176 177 enable_irq(google->hs_pme_irq); 178 enable_irq(google->ss_pme_irq); 179 enable_irq_wake(google->hs_pme_irq); 180 enable_irq_wake(google->ss_pme_irq); 181 } 182 183 static void dwc3_google_disable_pme_irq(struct dwc3_google *google) 184 { 185 u32 reg; 186 187 regmap_read(google->usb_cfg_regmap, 188 google->usbint_cfg_offset + USBINT_CFG1_OFFSET, ®); 189 reg &= ~(USBINT_CFG1_USBDRD_PME_GEN_U2P_INTR_INT_EN | 190 USBINT_CFG1_USBDRD_PME_GEN_U3P_INTR_INT_EN); 191 reg |= (USBINT_CFG1_USBDRD_PME_GEN_U2P_INTR_MSK | 192 USBINT_CFG1_USBDRD_PME_GEN_U3P_INTR_MSK); 193 regmap_write(google->usb_cfg_regmap, 194 google->usbint_cfg_offset + USBINT_CFG1_OFFSET, reg); 195 196 disable_irq_wake(google->hs_pme_irq); 197 disable_irq_wake(google->ss_pme_irq); 198 disable_irq_nosync(google->hs_pme_irq); 199 disable_irq_nosync(google->ss_pme_irq); 200 } 201 202 static irqreturn_t dwc3_google_resume_irq(int irq, void *data) 203 { 204 struct dwc3_google *google = data; 205 struct dwc3 *dwc = &google->dwc; 206 u32 irq_status, dr_role; 207 208 irq_status = dwc3_google_clear_pme_irqs(google); 209 dr_role = dwc->current_dr_role; 210 211 if (!irq_status || !google->is_hibernation || 212 dr_role != DWC3_GCTL_PRTCAP_HOST) { 213 dev_dbg(google->dev, "spurious pme irq %d, hibernation %d, dr_role %u\n", 214 irq, google->is_hibernation, dr_role); 215 return IRQ_HANDLED; 216 } 217 218 if (dwc->xhci) 219 pm_runtime_resume(&dwc->xhci->dev); 220 221 return IRQ_HANDLED; 222 } 223 224 static int dwc3_google_request_irq(struct dwc3_google *google, struct platform_device *pdev, 225 const char *irq_name, const char *req_name) 226 { 227 int ret; 228 int irq; 229 230 irq = platform_get_irq_byname(pdev, irq_name); 231 if (irq < 0) 232 return irq; 233 234 irq_set_status_flags(irq, IRQ_NOAUTOEN); 235 ret = devm_request_threaded_irq(google->dev, irq, NULL, 236 dwc3_google_resume_irq, 237 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 238 req_name, google); 239 if (ret < 0) { 240 dev_err(google->dev, "failed to request irq %s\n", req_name); 241 return ret; 242 } 243 244 return irq; 245 } 246 247 static int dwc3_google_usb_psw_pd_notifier(struct notifier_block *nb, unsigned long action, void *d) 248 { 249 struct dwc3_google *google = container_of(nb, struct dwc3_google, usb_psw_pd_nb); 250 int ret; 251 252 if (!google->is_hibernation) 253 return NOTIFY_OK; 254 255 if (action == GENPD_NOTIFY_OFF) { 256 dev_dbg(google->dev, "enter D3 power state\n"); 257 dwc3_google_set_pmu_state(google, HOST_CFG1_PM_POWER_STATE_D3); 258 ret = reset_control_assert(google->non_sticky_rst); 259 if (ret) 260 dev_err(google->dev, "non sticky reset assert failed: %d\n", ret); 261 } else if (action == GENPD_NOTIFY_ON) { 262 dev_dbg(google->dev, "enter D0 power state\n"); 263 dwc3_google_clear_pme_irqs(google); 264 ret = reset_control_deassert(google->non_sticky_rst); 265 if (ret) 266 dev_err(google->dev, "non sticky reset deassert failed: %d\n", ret); 267 dwc3_google_set_pmu_state(google, HOST_CFG1_PM_POWER_STATE_D0); 268 } 269 270 return NOTIFY_OK; 271 } 272 273 static void dwc3_google_pm_domain_deinit(struct dwc3_google *google) 274 { 275 if (google->usb_top_pd_dl) 276 device_link_del(google->usb_top_pd_dl); 277 278 if (!IS_ERR_OR_NULL(google->usb_top_pd)) { 279 device_set_wakeup_capable(google->usb_top_pd, false); 280 dev_pm_domain_detach(google->usb_top_pd, true); 281 } 282 283 if (google->usb_psw_pd_dl) 284 device_link_del(google->usb_psw_pd_dl); 285 286 if (!IS_ERR_OR_NULL(google->usb_psw_pd)) { 287 dev_pm_genpd_remove_notifier(google->usb_psw_pd); 288 dev_pm_domain_detach(google->usb_psw_pd, true); 289 } 290 } 291 292 static int dwc3_google_pm_domain_init(struct dwc3_google *google) 293 { 294 int ret; 295 296 /* 297 * Establish PM RUNTIME link between dwc dev and its power domain usb_psw_pd, 298 * register notifier block to handle hibernation. 299 */ 300 google->usb_psw_pd = dev_pm_domain_attach_by_name(google->dev, "psw"); 301 if (IS_ERR_OR_NULL(google->usb_psw_pd)) { 302 dev_err(google->dev, "failed to get psw pd"); 303 ret = google->usb_psw_pd ? PTR_ERR(google->usb_psw_pd) : -ENODATA; 304 return ret; 305 } 306 307 google->usb_psw_pd_nb.notifier_call = dwc3_google_usb_psw_pd_notifier; 308 ret = dev_pm_genpd_add_notifier(google->usb_psw_pd, &google->usb_psw_pd_nb); 309 if (ret) { 310 dev_err(google->dev, "failed to add psw pd notifier"); 311 goto err; 312 } 313 314 google->usb_psw_pd_dl = device_link_add(google->dev, google->usb_psw_pd, 315 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME | 316 DL_FLAG_RPM_ACTIVE); 317 if (!google->usb_psw_pd_dl) { 318 dev_err(google->usb_psw_pd, "failed to add device link"); 319 ret = -ENODEV; 320 goto err; 321 } 322 323 /* 324 * usb_top_pd is the parent power domain of usb_psw_pd. Keeping usb_top_pd on 325 * while usb_psw_pd is off places the controller in a power-gated state, 326 * essential for hibernation. Acquire a handle to usb_top_pd and sets it as 327 * wakeup-capable to allow the domain to be left on during system suspend. 328 */ 329 google->usb_top_pd = dev_pm_domain_attach_by_name(google->dev, "top"); 330 if (IS_ERR_OR_NULL(google->usb_top_pd)) { 331 dev_err(google->dev, "failed to get top pd"); 332 ret = google->usb_top_pd ? PTR_ERR(google->usb_top_pd) : -ENODATA; 333 goto err; 334 } 335 device_set_wakeup_capable(google->usb_top_pd, true); 336 337 google->usb_top_pd_dl = device_link_add(google->dev, google->usb_top_pd, 338 DL_FLAG_STATELESS); 339 if (!google->usb_top_pd_dl) { 340 dev_err(google->usb_top_pd, "failed to add device link"); 341 ret = -ENODEV; 342 goto err; 343 } 344 345 return 0; 346 347 err: 348 dwc3_google_pm_domain_deinit(google); 349 350 return ret; 351 } 352 353 static void dwc3_google_program_usb2only(struct dwc3_google *google) 354 { 355 u32 reg; 356 357 regmap_read(google->usb_cfg_regmap, 358 google->usbint_cfg_offset + USBCS_TOP_CTRL_CFG1_OFFSET, ®); 359 reg |= USBCS_TOP_CTRL_CFG1_USB2ONLY_MODE; 360 regmap_write(google->usb_cfg_regmap, 361 google->usbint_cfg_offset + USBCS_TOP_CTRL_CFG1_OFFSET, reg); 362 } 363 364 static int dwc3_google_probe(struct platform_device *pdev) 365 { 366 struct dwc3_probe_data probe_data = {}; 367 struct device *dev = &pdev->dev; 368 struct dwc3_google *google; 369 struct resource *res; 370 int ret; 371 u32 args[2]; 372 373 google = devm_kzalloc(&pdev->dev, sizeof(*google), GFP_KERNEL); 374 if (!google) 375 return -ENOMEM; 376 377 google->dev = &pdev->dev; 378 379 ret = dwc3_google_pm_domain_init(google); 380 if (ret < 0) 381 return dev_err_probe(dev, ret, "failed to init pdom\n"); 382 383 google->usb_cfg_regmap = 384 syscon_regmap_lookup_by_phandle_args(dev->of_node, 385 "google,usb-cfg-csr", 386 ARRAY_SIZE(args), args); 387 if (IS_ERR(google->usb_cfg_regmap)) { 388 return dev_err_probe(dev, PTR_ERR(google->usb_cfg_regmap), 389 "invalid usb cfg csr\n"); 390 } 391 392 google->host_cfg_offset = args[0]; 393 google->usbint_cfg_offset = args[1]; 394 395 if (device_property_match_string(dev, "phy-names", "usb3-phy") < 0) { 396 google->is_usb2only = true; 397 dwc3_google_program_usb2only(google); 398 } 399 400 ret = devm_clk_bulk_get_all_enabled(dev, &google->clks); 401 if (ret < 0) { 402 ret = dev_err_probe(dev, ret, "failed to get and enable clks\n"); 403 goto err_deinit_pdom; 404 } 405 google->num_clks = ret; 406 407 ret = dwc3_google_rst_init(google); 408 if (ret) { 409 ret = dev_err_probe(dev, ret, "failed to get resets\n"); 410 goto err_deinit_pdom; 411 } 412 413 ret = reset_control_bulk_deassert(google->num_rsts, google->rsts); 414 if (ret) { 415 ret = dev_err_probe(dev, ret, "failed to deassert rsts\n"); 416 goto err_deinit_pdom; 417 } 418 419 ret = dwc3_google_request_irq(google, pdev, "hs_pme", "USB HS wakeup"); 420 if (ret < 0) { 421 ret = dev_err_probe(dev, ret, "failed to request hs pme irq"); 422 goto err_reset_assert; 423 } 424 google->hs_pme_irq = ret; 425 426 ret = dwc3_google_request_irq(google, pdev, "ss_pme", "USB SS wakeup"); 427 if (ret < 0) { 428 ret = dev_err_probe(dev, ret, "failed to request ss pme irq"); 429 goto err_reset_assert; 430 } 431 google->ss_pme_irq = ret; 432 433 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 434 if (!res) { 435 ret = dev_err_probe(dev, -ENODEV, "invalid memory\n"); 436 goto err_reset_assert; 437 } 438 439 device_init_wakeup(dev, true); 440 441 google->dwc.dev = dev; 442 probe_data.dwc = &google->dwc; 443 probe_data.res = res; 444 probe_data.ignore_clocks_and_resets = true; 445 ret = dwc3_core_probe(&probe_data); 446 if (ret) { 447 ret = dev_err_probe(dev, ret, "failed to register DWC3 Core\n"); 448 goto err_reset_assert; 449 } 450 451 return 0; 452 453 err_reset_assert: 454 reset_control_bulk_assert(google->num_rsts, google->rsts); 455 456 err_deinit_pdom: 457 dwc3_google_pm_domain_deinit(google); 458 459 return ret; 460 } 461 462 static void dwc3_google_remove(struct platform_device *pdev) 463 { 464 struct dwc3 *dwc = platform_get_drvdata(pdev); 465 struct dwc3_google *google = to_dwc3_google(dwc); 466 467 dwc3_core_remove(&google->dwc); 468 469 reset_control_bulk_assert(google->num_rsts, google->rsts); 470 471 dwc3_google_pm_domain_deinit(google); 472 } 473 474 static int dwc3_google_suspend(struct dwc3_google *google, pm_message_t msg) 475 { 476 if (pm_runtime_suspended(google->dev)) 477 return 0; 478 479 if (google->dwc.current_dr_role == DWC3_GCTL_PRTCAP_HOST) { 480 /* 481 * Follow dwc3_suspend_common() guidelines for deciding between 482 * a full teardown and hibernation. 483 */ 484 if (PMSG_IS_AUTO(msg) || device_may_wakeup(google->dev)) { 485 dev_dbg(google->dev, "enter hibernation"); 486 pm_runtime_get_sync(google->usb_top_pd); 487 device_wakeup_enable(google->usb_top_pd); 488 dwc3_google_enable_pme_irq(google); 489 google->is_hibernation = true; 490 return 0; 491 } 492 } 493 494 reset_control_bulk_assert(google->num_rsts, google->rsts); 495 clk_bulk_disable_unprepare(google->num_clks, google->clks); 496 497 return 0; 498 } 499 500 static int dwc3_google_resume(struct dwc3_google *google, pm_message_t msg) 501 { 502 int ret; 503 504 if (google->is_hibernation) { 505 dev_dbg(google->dev, "exit hibernation"); 506 dwc3_google_disable_pme_irq(google); 507 device_wakeup_disable(google->usb_top_pd); 508 pm_runtime_put_sync(google->usb_top_pd); 509 google->is_hibernation = false; 510 return 0; 511 } 512 513 if (google->is_usb2only) 514 dwc3_google_program_usb2only(google); 515 516 ret = clk_bulk_prepare_enable(google->num_clks, google->clks); 517 if (ret) 518 return ret; 519 520 ret = reset_control_bulk_deassert(google->num_rsts, google->rsts); 521 if (ret) { 522 clk_bulk_disable_unprepare(google->num_clks, google->clks); 523 return ret; 524 } 525 526 return 0; 527 } 528 529 static int dwc3_google_pm_suspend(struct device *dev) 530 { 531 struct dwc3 *dwc = dev_get_drvdata(dev); 532 struct dwc3_google *google = to_dwc3_google(dwc); 533 int ret; 534 535 ret = dwc3_pm_suspend(&google->dwc); 536 if (ret) 537 return ret; 538 539 return dwc3_google_suspend(google, PMSG_SUSPEND); 540 } 541 542 static int dwc3_google_pm_resume(struct device *dev) 543 { 544 struct dwc3 *dwc = dev_get_drvdata(dev); 545 struct dwc3_google *google = to_dwc3_google(dwc); 546 int ret; 547 548 ret = dwc3_google_resume(google, PMSG_RESUME); 549 if (ret) 550 return ret; 551 552 return dwc3_pm_resume(&google->dwc); 553 } 554 555 static void dwc3_google_complete(struct device *dev) 556 { 557 struct dwc3 *dwc = dev_get_drvdata(dev); 558 559 dwc3_pm_complete(dwc); 560 } 561 562 static int dwc3_google_prepare(struct device *dev) 563 { 564 struct dwc3 *dwc = dev_get_drvdata(dev); 565 566 return dwc3_pm_prepare(dwc); 567 } 568 569 static int dwc3_google_runtime_suspend(struct device *dev) 570 { 571 struct dwc3 *dwc = dev_get_drvdata(dev); 572 struct dwc3_google *google = to_dwc3_google(dwc); 573 int ret; 574 575 ret = dwc3_runtime_suspend(&google->dwc); 576 if (ret) 577 return ret; 578 579 return dwc3_google_suspend(google, PMSG_AUTO_SUSPEND); 580 } 581 582 static int dwc3_google_runtime_resume(struct device *dev) 583 { 584 struct dwc3 *dwc = dev_get_drvdata(dev); 585 struct dwc3_google *google = to_dwc3_google(dwc); 586 int ret; 587 588 ret = dwc3_google_resume(google, PMSG_AUTO_RESUME); 589 if (ret) 590 return ret; 591 592 return dwc3_runtime_resume(&google->dwc); 593 } 594 595 static int dwc3_google_runtime_idle(struct device *dev) 596 { 597 return dwc3_runtime_idle(dev_get_drvdata(dev)); 598 } 599 600 static const struct dev_pm_ops dwc3_google_dev_pm_ops = { 601 SYSTEM_SLEEP_PM_OPS(dwc3_google_pm_suspend, dwc3_google_pm_resume) 602 RUNTIME_PM_OPS(dwc3_google_runtime_suspend, dwc3_google_runtime_resume, 603 dwc3_google_runtime_idle) 604 .complete = pm_sleep_ptr(dwc3_google_complete), 605 .prepare = pm_sleep_ptr(dwc3_google_prepare), 606 }; 607 608 static const struct of_device_id dwc3_google_of_match[] = { 609 { .compatible = "google,lga-dwc3" }, 610 { } 611 }; 612 MODULE_DEVICE_TABLE(of, dwc3_google_of_match); 613 614 static struct platform_driver dwc3_google_driver = { 615 .probe = dwc3_google_probe, 616 .remove = dwc3_google_remove, 617 .driver = { 618 .name = "dwc3-google", 619 .pm = pm_ptr(&dwc3_google_dev_pm_ops), 620 .of_match_table = dwc3_google_of_match, 621 }, 622 }; 623 624 module_platform_driver(dwc3_google_driver); 625 MODULE_LICENSE("GPL"); 626 MODULE_DESCRIPTION("DesignWare DWC3 Google Glue Driver"); 627