1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * dwc3-google.c - Google DWC3 Specific Glue Layer 4 * 5 * Copyright (c) 2025, Google LLC 6 * Author: Roy Luo <royluo@google.com> 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/clk.h> 11 #include <linux/iopoll.h> 12 #include <linux/irq.h> 13 #include <linux/kernel.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_domain.h> 19 #include <linux/regmap.h> 20 #include <linux/reset.h> 21 #include "core.h" 22 #include "glue.h" 23 24 /* HOST CFG registers */ 25 #define HC_STATUS_OFFSET 0x0 26 #define HC_STATUS_CURRENT_POWER_STATE_U2PMU GENMASK(1, 0) 27 #define HC_STATUS_CURRENT_POWER_STATE_U3PMU GENMASK(4, 3) 28 29 #define HOST_CFG1_OFFSET 0x4 30 #define HOST_CFG1_PME_EN BIT(3) 31 #define HOST_CFG1_PM_POWER_STATE_REQUEST GENMASK(5, 4) 32 #define HOST_CFG1_PM_POWER_STATE_D0 0x0 33 #define HOST_CFG1_PM_POWER_STATE_D3 0x3 34 35 /* USBINT registers */ 36 #define USBINT_CFG1_OFFSET 0x0 37 #define USBINT_CFG1_USBDRD_PME_GEN_U2P_INTR_MSK BIT(2) 38 #define USBINT_CFG1_USBDRD_PME_GEN_U3P_INTR_MSK BIT(3) 39 #define USBINT_CFG1_USBDRD_PME_GEN_U2P_INTR_INT_EN BIT(8) 40 #define USBINT_CFG1_USBDRD_PME_GEN_U3P_INTR_INT_EN BIT(9) 41 #define USBINT_CFG1_USBDRD_PME_GEN_U2_INTR_CLR BIT(14) 42 #define USBINT_CFG1_USBDRD_PME_GEN_U3_INTR_CLR BIT(15) 43 44 #define USBINT_STATUS_OFFSET 0x4 45 #define USBINT_STATUS_USBDRD_PME_GEN_U2P_INTR_STS_RAW BIT(2) 46 #define USBINT_STATUS_USBDRD_PME_GEN_U3P_INTR_STS_RAW BIT(3) 47 48 #define USBCS_TOP_CTRL_CFG1_OFFSET 0xc 49 #define USBCS_TOP_CTRL_CFG1_USB2ONLY_MODE BIT(5) 50 51 #define DWC3_GOOGLE_MAX_RESETS 4 52 53 struct dwc3_google { 54 struct device *dev; 55 struct dwc3 dwc; 56 struct clk_bulk_data *clks; 57 int num_clks; 58 struct reset_control_bulk_data rsts[DWC3_GOOGLE_MAX_RESETS]; 59 int num_rsts; 60 struct reset_control *non_sticky_rst; 61 struct device *usb_psw_pd; 62 struct device_link *usb_psw_pd_dl; 63 struct notifier_block usb_psw_pd_nb; 64 struct device *usb_top_pd; 65 struct device_link *usb_top_pd_dl; 66 struct regmap *usb_cfg_regmap; 67 unsigned int host_cfg_offset; 68 unsigned int usbint_cfg_offset; 69 int hs_pme_irq; 70 int ss_pme_irq; 71 bool is_usb2only; 72 bool is_hibernation; 73 }; 74 75 #define to_dwc3_google(d) container_of_const((d), struct dwc3_google, dwc) 76 77 static int dwc3_google_rst_init(struct dwc3_google *google) 78 { 79 int ret; 80 81 google->num_rsts = 4; 82 google->rsts[0].id = "non_sticky"; 83 google->rsts[1].id = "sticky"; 84 google->rsts[2].id = "drd_bus"; 85 google->rsts[3].id = "top"; 86 87 ret = devm_reset_control_bulk_get_exclusive(google->dev, 88 google->num_rsts, 89 google->rsts); 90 91 if (ret < 0) 92 return ret; 93 94 google->non_sticky_rst = google->rsts[0].rstc; 95 96 return 0; 97 } 98 99 static int dwc3_google_set_pmu_state(struct dwc3_google *google, int state) 100 { 101 u32 reg; 102 int ret; 103 104 regmap_read(google->usb_cfg_regmap, 105 google->host_cfg_offset + HOST_CFG1_OFFSET, ®); 106 107 FIELD_MODIFY(HOST_CFG1_PM_POWER_STATE_REQUEST, ®, state); 108 reg |= HOST_CFG1_PME_EN; 109 regmap_write(google->usb_cfg_regmap, 110 google->host_cfg_offset + HOST_CFG1_OFFSET, reg); 111 112 ret = regmap_read_poll_timeout(google->usb_cfg_regmap, 113 google->host_cfg_offset + HC_STATUS_OFFSET, reg, 114 (FIELD_GET(HC_STATUS_CURRENT_POWER_STATE_U2PMU, 115 reg) == state && 116 FIELD_GET(HC_STATUS_CURRENT_POWER_STATE_U3PMU, 117 reg) == state), 118 10, 10000); 119 120 if (ret) 121 dev_err(google->dev, "failed to set PMU state %d\n", state); 122 123 return ret; 124 } 125 126 /* 127 * Clear pme interrupts and report their status. 128 * The hardware requires write-1 then write-0 sequence to clear the interrupt bits. 129 */ 130 static u32 dwc3_google_clear_pme_irqs(struct dwc3_google *google) 131 { 132 u32 irq_status, reg_set, reg_clear; 133 134 regmap_read(google->usb_cfg_regmap, 135 google->usbint_cfg_offset + USBINT_STATUS_OFFSET, &irq_status); 136 137 irq_status &= (USBINT_STATUS_USBDRD_PME_GEN_U2P_INTR_STS_RAW | 138 USBINT_STATUS_USBDRD_PME_GEN_U3P_INTR_STS_RAW); 139 if (!irq_status) 140 return irq_status; 141 142 regmap_read(google->usb_cfg_regmap, 143 google->usbint_cfg_offset + USBINT_CFG1_OFFSET, ®_set); 144 145 reg_clear = reg_set; 146 if (irq_status & USBINT_STATUS_USBDRD_PME_GEN_U2P_INTR_STS_RAW) { 147 reg_set |= USBINT_CFG1_USBDRD_PME_GEN_U2_INTR_CLR; 148 reg_clear &= ~USBINT_CFG1_USBDRD_PME_GEN_U2_INTR_CLR; 149 } 150 if (irq_status & USBINT_STATUS_USBDRD_PME_GEN_U3P_INTR_STS_RAW) { 151 reg_set |= USBINT_CFG1_USBDRD_PME_GEN_U3_INTR_CLR; 152 reg_clear &= ~USBINT_CFG1_USBDRD_PME_GEN_U3_INTR_CLR; 153 } 154 155 regmap_write(google->usb_cfg_regmap, 156 google->usbint_cfg_offset + USBINT_CFG1_OFFSET, reg_set); 157 regmap_write(google->usb_cfg_regmap, 158 google->usbint_cfg_offset + USBINT_CFG1_OFFSET, reg_clear); 159 160 return irq_status; 161 } 162 163 static void dwc3_google_enable_pme_irq(struct dwc3_google *google) 164 { 165 u32 reg; 166 167 regmap_read(google->usb_cfg_regmap, 168 google->usbint_cfg_offset + USBINT_CFG1_OFFSET, ®); 169 reg &= ~(USBINT_CFG1_USBDRD_PME_GEN_U2P_INTR_MSK | 170 USBINT_CFG1_USBDRD_PME_GEN_U3P_INTR_MSK); 171 reg |= (USBINT_CFG1_USBDRD_PME_GEN_U2P_INTR_INT_EN | 172 USBINT_CFG1_USBDRD_PME_GEN_U3P_INTR_INT_EN); 173 regmap_write(google->usb_cfg_regmap, 174 google->usbint_cfg_offset + USBINT_CFG1_OFFSET, reg); 175 176 enable_irq(google->hs_pme_irq); 177 enable_irq(google->ss_pme_irq); 178 enable_irq_wake(google->hs_pme_irq); 179 enable_irq_wake(google->ss_pme_irq); 180 } 181 182 static void dwc3_google_disable_pme_irq(struct dwc3_google *google) 183 { 184 u32 reg; 185 186 regmap_read(google->usb_cfg_regmap, 187 google->usbint_cfg_offset + USBINT_CFG1_OFFSET, ®); 188 reg &= ~(USBINT_CFG1_USBDRD_PME_GEN_U2P_INTR_INT_EN | 189 USBINT_CFG1_USBDRD_PME_GEN_U3P_INTR_INT_EN); 190 reg |= (USBINT_CFG1_USBDRD_PME_GEN_U2P_INTR_MSK | 191 USBINT_CFG1_USBDRD_PME_GEN_U3P_INTR_MSK); 192 regmap_write(google->usb_cfg_regmap, 193 google->usbint_cfg_offset + USBINT_CFG1_OFFSET, reg); 194 195 disable_irq_wake(google->hs_pme_irq); 196 disable_irq_wake(google->ss_pme_irq); 197 disable_irq_nosync(google->hs_pme_irq); 198 disable_irq_nosync(google->ss_pme_irq); 199 } 200 201 static irqreturn_t dwc3_google_resume_irq(int irq, void *data) 202 { 203 struct dwc3_google *google = data; 204 struct dwc3 *dwc = &google->dwc; 205 u32 irq_status, dr_role; 206 207 irq_status = dwc3_google_clear_pme_irqs(google); 208 dr_role = dwc->current_dr_role; 209 210 if (!irq_status || !google->is_hibernation || 211 dr_role != DWC3_GCTL_PRTCAP_HOST) { 212 dev_dbg(google->dev, "spurious pme irq %d, hibernation %d, dr_role %u\n", 213 irq, google->is_hibernation, dr_role); 214 return IRQ_HANDLED; 215 } 216 217 if (dwc->xhci) 218 pm_runtime_resume(&dwc->xhci->dev); 219 220 return IRQ_HANDLED; 221 } 222 223 static int dwc3_google_request_irq(struct dwc3_google *google, struct platform_device *pdev, 224 const char *irq_name, const char *req_name) 225 { 226 int ret; 227 int irq; 228 229 irq = platform_get_irq_byname(pdev, irq_name); 230 if (irq < 0) 231 return irq; 232 233 irq_set_status_flags(irq, IRQ_NOAUTOEN); 234 ret = devm_request_threaded_irq(google->dev, irq, NULL, 235 dwc3_google_resume_irq, 236 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 237 req_name, google); 238 if (ret < 0) { 239 dev_err(google->dev, "failed to request irq %s\n", req_name); 240 return ret; 241 } 242 243 return irq; 244 } 245 246 static int dwc3_google_usb_psw_pd_notifier(struct notifier_block *nb, unsigned long action, void *d) 247 { 248 struct dwc3_google *google = container_of(nb, struct dwc3_google, usb_psw_pd_nb); 249 int ret; 250 251 if (!google->is_hibernation) 252 return NOTIFY_OK; 253 254 if (action == GENPD_NOTIFY_OFF) { 255 dev_dbg(google->dev, "enter D3 power state\n"); 256 dwc3_google_set_pmu_state(google, HOST_CFG1_PM_POWER_STATE_D3); 257 ret = reset_control_assert(google->non_sticky_rst); 258 if (ret) 259 dev_err(google->dev, "non sticky reset assert failed: %d\n", ret); 260 } else if (action == GENPD_NOTIFY_ON) { 261 dev_dbg(google->dev, "enter D0 power state\n"); 262 dwc3_google_clear_pme_irqs(google); 263 ret = reset_control_deassert(google->non_sticky_rst); 264 if (ret) 265 dev_err(google->dev, "non sticky reset deassert failed: %d\n", ret); 266 dwc3_google_set_pmu_state(google, HOST_CFG1_PM_POWER_STATE_D0); 267 } 268 269 return NOTIFY_OK; 270 } 271 272 static void dwc3_google_pm_domain_deinit(struct dwc3_google *google) 273 { 274 if (google->usb_top_pd_dl) 275 device_link_del(google->usb_top_pd_dl); 276 277 if (!IS_ERR_OR_NULL(google->usb_top_pd)) { 278 device_set_wakeup_capable(google->usb_top_pd, false); 279 dev_pm_domain_detach(google->usb_top_pd, true); 280 } 281 282 if (google->usb_psw_pd_dl) 283 device_link_del(google->usb_psw_pd_dl); 284 285 if (!IS_ERR_OR_NULL(google->usb_psw_pd)) { 286 dev_pm_genpd_remove_notifier(google->usb_psw_pd); 287 dev_pm_domain_detach(google->usb_psw_pd, true); 288 } 289 } 290 291 static int dwc3_google_pm_domain_init(struct dwc3_google *google) 292 { 293 int ret; 294 295 /* 296 * Establish PM RUNTIME link between dwc dev and its power domain usb_psw_pd, 297 * register notifier block to handle hibernation. 298 */ 299 google->usb_psw_pd = dev_pm_domain_attach_by_name(google->dev, "psw"); 300 if (IS_ERR_OR_NULL(google->usb_psw_pd)) { 301 dev_err(google->dev, "failed to get psw pd"); 302 ret = google->usb_psw_pd ? PTR_ERR(google->usb_psw_pd) : -ENODATA; 303 return ret; 304 } 305 306 google->usb_psw_pd_nb.notifier_call = dwc3_google_usb_psw_pd_notifier; 307 ret = dev_pm_genpd_add_notifier(google->usb_psw_pd, &google->usb_psw_pd_nb); 308 if (ret) { 309 dev_err(google->dev, "failed to add psw pd notifier"); 310 goto err; 311 } 312 313 google->usb_psw_pd_dl = device_link_add(google->dev, google->usb_psw_pd, 314 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME | 315 DL_FLAG_RPM_ACTIVE); 316 if (!google->usb_psw_pd_dl) { 317 dev_err(google->usb_psw_pd, "failed to add device link"); 318 ret = -ENODEV; 319 goto err; 320 } 321 322 /* 323 * usb_top_pd is the parent power domain of usb_psw_pd. Keeping usb_top_pd on 324 * while usb_psw_pd is off places the controller in a power-gated state, 325 * essential for hibernation. Acquire a handle to usb_top_pd and sets it as 326 * wakeup-capable to allow the domain to be left on during system suspend. 327 */ 328 google->usb_top_pd = dev_pm_domain_attach_by_name(google->dev, "top"); 329 if (IS_ERR_OR_NULL(google->usb_top_pd)) { 330 dev_err(google->dev, "failed to get top pd"); 331 ret = google->usb_top_pd ? PTR_ERR(google->usb_top_pd) : -ENODATA; 332 goto err; 333 } 334 device_set_wakeup_capable(google->usb_top_pd, true); 335 336 google->usb_top_pd_dl = device_link_add(google->dev, google->usb_top_pd, 337 DL_FLAG_STATELESS); 338 if (!google->usb_top_pd_dl) { 339 dev_err(google->usb_top_pd, "failed to add device link"); 340 ret = -ENODEV; 341 goto err; 342 } 343 344 return 0; 345 346 err: 347 dwc3_google_pm_domain_deinit(google); 348 349 return ret; 350 } 351 352 static void dwc3_google_program_usb2only(struct dwc3_google *google) 353 { 354 u32 reg; 355 356 regmap_read(google->usb_cfg_regmap, 357 google->usbint_cfg_offset + USBCS_TOP_CTRL_CFG1_OFFSET, ®); 358 reg |= USBCS_TOP_CTRL_CFG1_USB2ONLY_MODE; 359 regmap_write(google->usb_cfg_regmap, 360 google->usbint_cfg_offset + USBCS_TOP_CTRL_CFG1_OFFSET, reg); 361 } 362 363 static int dwc3_google_probe(struct platform_device *pdev) 364 { 365 struct dwc3_probe_data probe_data = {}; 366 struct device *dev = &pdev->dev; 367 struct dwc3_google *google; 368 struct resource *res; 369 int ret; 370 u32 args[2]; 371 372 google = devm_kzalloc(&pdev->dev, sizeof(*google), GFP_KERNEL); 373 if (!google) 374 return -ENOMEM; 375 376 google->dev = &pdev->dev; 377 378 ret = dwc3_google_pm_domain_init(google); 379 if (ret < 0) 380 return dev_err_probe(dev, ret, "failed to init pdom\n"); 381 382 google->usb_cfg_regmap = 383 syscon_regmap_lookup_by_phandle_args(dev->of_node, 384 "google,usb-cfg-csr", 385 ARRAY_SIZE(args), args); 386 if (IS_ERR(google->usb_cfg_regmap)) { 387 ret = dev_err_probe(dev, PTR_ERR(google->usb_cfg_regmap), 388 "invalid usb cfg csr\n"); 389 goto err_deinit_pdom; 390 } 391 392 google->host_cfg_offset = args[0]; 393 google->usbint_cfg_offset = args[1]; 394 395 if (device_property_match_string(dev, "phy-names", "usb3-phy") < 0) { 396 google->is_usb2only = true; 397 dwc3_google_program_usb2only(google); 398 } 399 400 ret = devm_clk_bulk_get_all_enabled(dev, &google->clks); 401 if (ret < 0) { 402 ret = dev_err_probe(dev, ret, "failed to get and enable clks\n"); 403 goto err_deinit_pdom; 404 } 405 google->num_clks = ret; 406 407 ret = dwc3_google_rst_init(google); 408 if (ret) { 409 ret = dev_err_probe(dev, ret, "failed to get resets\n"); 410 goto err_deinit_pdom; 411 } 412 413 ret = reset_control_bulk_deassert(google->num_rsts, google->rsts); 414 if (ret) { 415 ret = dev_err_probe(dev, ret, "failed to deassert rsts\n"); 416 goto err_deinit_pdom; 417 } 418 419 ret = dwc3_google_request_irq(google, pdev, "hs_pme", "USB HS wakeup"); 420 if (ret < 0) { 421 ret = dev_err_probe(dev, ret, "failed to request hs pme irq"); 422 goto err_reset_assert; 423 } 424 google->hs_pme_irq = ret; 425 426 ret = dwc3_google_request_irq(google, pdev, "ss_pme", "USB SS wakeup"); 427 if (ret < 0) { 428 ret = dev_err_probe(dev, ret, "failed to request ss pme irq"); 429 goto err_reset_assert; 430 } 431 google->ss_pme_irq = ret; 432 433 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 434 if (!res) { 435 ret = dev_err_probe(dev, -ENODEV, "invalid memory\n"); 436 goto err_reset_assert; 437 } 438 439 device_init_wakeup(dev, true); 440 441 google->dwc.dev = dev; 442 probe_data.dwc = &google->dwc; 443 probe_data.res = res; 444 probe_data.ignore_clocks_and_resets = true; 445 probe_data.properties = DWC3_DEFAULT_PROPERTIES; 446 ret = dwc3_core_probe(&probe_data); 447 if (ret) { 448 ret = dev_err_probe(dev, ret, "failed to register DWC3 Core\n"); 449 goto err_reset_assert; 450 } 451 452 return 0; 453 454 err_reset_assert: 455 reset_control_bulk_assert(google->num_rsts, google->rsts); 456 457 err_deinit_pdom: 458 dwc3_google_pm_domain_deinit(google); 459 460 return ret; 461 } 462 463 static void dwc3_google_remove(struct platform_device *pdev) 464 { 465 struct dwc3 *dwc = platform_get_drvdata(pdev); 466 struct dwc3_google *google = to_dwc3_google(dwc); 467 468 dwc3_core_remove(&google->dwc); 469 470 reset_control_bulk_assert(google->num_rsts, google->rsts); 471 472 dwc3_google_pm_domain_deinit(google); 473 } 474 475 static int dwc3_google_suspend(struct dwc3_google *google, pm_message_t msg) 476 { 477 if (pm_runtime_suspended(google->dev)) 478 return 0; 479 480 if (google->dwc.current_dr_role == DWC3_GCTL_PRTCAP_HOST) { 481 /* 482 * Follow dwc3_suspend_common() guidelines for deciding between 483 * a full teardown and hibernation. 484 */ 485 if (PMSG_IS_AUTO(msg) || device_may_wakeup(google->dev)) { 486 dev_dbg(google->dev, "enter hibernation"); 487 pm_runtime_get_sync(google->usb_top_pd); 488 device_wakeup_enable(google->usb_top_pd); 489 dwc3_google_enable_pme_irq(google); 490 google->is_hibernation = true; 491 return 0; 492 } 493 } 494 495 reset_control_bulk_assert(google->num_rsts, google->rsts); 496 clk_bulk_disable_unprepare(google->num_clks, google->clks); 497 498 return 0; 499 } 500 501 static int dwc3_google_resume(struct dwc3_google *google, pm_message_t msg) 502 { 503 int ret; 504 505 if (google->is_hibernation) { 506 dev_dbg(google->dev, "exit hibernation"); 507 dwc3_google_disable_pme_irq(google); 508 device_wakeup_disable(google->usb_top_pd); 509 pm_runtime_put_sync(google->usb_top_pd); 510 google->is_hibernation = false; 511 return 0; 512 } 513 514 if (google->is_usb2only) 515 dwc3_google_program_usb2only(google); 516 517 ret = clk_bulk_prepare_enable(google->num_clks, google->clks); 518 if (ret) 519 return ret; 520 521 ret = reset_control_bulk_deassert(google->num_rsts, google->rsts); 522 if (ret) { 523 clk_bulk_disable_unprepare(google->num_clks, google->clks); 524 return ret; 525 } 526 527 return 0; 528 } 529 530 static int dwc3_google_pm_suspend(struct device *dev) 531 { 532 struct dwc3 *dwc = dev_get_drvdata(dev); 533 struct dwc3_google *google = to_dwc3_google(dwc); 534 int ret; 535 536 ret = dwc3_pm_suspend(&google->dwc); 537 if (ret) 538 return ret; 539 540 return dwc3_google_suspend(google, PMSG_SUSPEND); 541 } 542 543 static int dwc3_google_pm_resume(struct device *dev) 544 { 545 struct dwc3 *dwc = dev_get_drvdata(dev); 546 struct dwc3_google *google = to_dwc3_google(dwc); 547 int ret; 548 549 ret = dwc3_google_resume(google, PMSG_RESUME); 550 if (ret) 551 return ret; 552 553 return dwc3_pm_resume(&google->dwc); 554 } 555 556 static void dwc3_google_complete(struct device *dev) 557 { 558 struct dwc3 *dwc = dev_get_drvdata(dev); 559 560 dwc3_pm_complete(dwc); 561 } 562 563 static int dwc3_google_prepare(struct device *dev) 564 { 565 struct dwc3 *dwc = dev_get_drvdata(dev); 566 567 return dwc3_pm_prepare(dwc); 568 } 569 570 static int dwc3_google_runtime_suspend(struct device *dev) 571 { 572 struct dwc3 *dwc = dev_get_drvdata(dev); 573 struct dwc3_google *google = to_dwc3_google(dwc); 574 int ret; 575 576 ret = dwc3_runtime_suspend(&google->dwc); 577 if (ret) 578 return ret; 579 580 return dwc3_google_suspend(google, PMSG_AUTO_SUSPEND); 581 } 582 583 static int dwc3_google_runtime_resume(struct device *dev) 584 { 585 struct dwc3 *dwc = dev_get_drvdata(dev); 586 struct dwc3_google *google = to_dwc3_google(dwc); 587 int ret; 588 589 ret = dwc3_google_resume(google, PMSG_AUTO_RESUME); 590 if (ret) 591 return ret; 592 593 return dwc3_runtime_resume(&google->dwc); 594 } 595 596 static int dwc3_google_runtime_idle(struct device *dev) 597 { 598 return dwc3_runtime_idle(dev_get_drvdata(dev)); 599 } 600 601 static const struct dev_pm_ops dwc3_google_dev_pm_ops = { 602 SYSTEM_SLEEP_PM_OPS(dwc3_google_pm_suspend, dwc3_google_pm_resume) 603 RUNTIME_PM_OPS(dwc3_google_runtime_suspend, dwc3_google_runtime_resume, 604 dwc3_google_runtime_idle) 605 .complete = pm_sleep_ptr(dwc3_google_complete), 606 .prepare = pm_sleep_ptr(dwc3_google_prepare), 607 }; 608 609 static const struct of_device_id dwc3_google_of_match[] = { 610 { .compatible = "google,lga-dwc3" }, 611 { } 612 }; 613 MODULE_DEVICE_TABLE(of, dwc3_google_of_match); 614 615 static struct platform_driver dwc3_google_driver = { 616 .probe = dwc3_google_probe, 617 .remove = dwc3_google_remove, 618 .driver = { 619 .name = "dwc3-google", 620 .pm = pm_ptr(&dwc3_google_dev_pm_ops), 621 .of_match_table = dwc3_google_of_match, 622 }, 623 }; 624 625 module_platform_driver(dwc3_google_driver); 626 MODULE_LICENSE("GPL"); 627 MODULE_DESCRIPTION("DesignWare DWC3 Google Glue Driver"); 628