1 /** 2 * core.h - DesignWare USB3 DRD Core Header 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The names of the above-listed copyright holders may not be used 19 * to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * ALTERNATIVELY, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2, as published by the Free 24 * Software Foundation. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef __DRIVERS_USB_DWC3_CORE_H 40 #define __DRIVERS_USB_DWC3_CORE_H 41 42 #include <linux/device.h> 43 #include <linux/spinlock.h> 44 #include <linux/list.h> 45 #include <linux/dma-mapping.h> 46 #include <linux/mm.h> 47 #include <linux/debugfs.h> 48 49 #include <linux/usb/ch9.h> 50 #include <linux/usb/gadget.h> 51 52 /* Global constants */ 53 #define DWC3_ENDPOINTS_NUM 32 54 55 #define DWC3_EVENT_BUFFERS_NUM 2 56 #define DWC3_EVENT_BUFFERS_SIZE PAGE_SIZE 57 #define DWC3_EVENT_TYPE_MASK 0xfe 58 59 #define DWC3_EVENT_TYPE_DEV 0 60 #define DWC3_EVENT_TYPE_CARKIT 3 61 #define DWC3_EVENT_TYPE_I2C 4 62 63 #define DWC3_DEVICE_EVENT_DISCONNECT 0 64 #define DWC3_DEVICE_EVENT_RESET 1 65 #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 66 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 67 #define DWC3_DEVICE_EVENT_WAKEUP 4 68 #define DWC3_DEVICE_EVENT_EOPF 6 69 #define DWC3_DEVICE_EVENT_SOF 7 70 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 71 #define DWC3_DEVICE_EVENT_CMD_CMPL 10 72 #define DWC3_DEVICE_EVENT_OVERFLOW 11 73 74 #define DWC3_GEVNTCOUNT_MASK 0xfffc 75 #define DWC3_GSNPSID_MASK 0xffff0000 76 #define DWC3_GSNPSREV_MASK 0xffff 77 78 /* Global Registers */ 79 #define DWC3_GSBUSCFG0 0xc100 80 #define DWC3_GSBUSCFG1 0xc104 81 #define DWC3_GTXTHRCFG 0xc108 82 #define DWC3_GRXTHRCFG 0xc10c 83 #define DWC3_GCTL 0xc110 84 #define DWC3_GEVTEN 0xc114 85 #define DWC3_GSTS 0xc118 86 #define DWC3_GSNPSID 0xc120 87 #define DWC3_GGPIO 0xc124 88 #define DWC3_GUID 0xc128 89 #define DWC3_GUCTL 0xc12c 90 #define DWC3_GBUSERRADDR0 0xc130 91 #define DWC3_GBUSERRADDR1 0xc134 92 #define DWC3_GPRTBIMAP0 0xc138 93 #define DWC3_GPRTBIMAP1 0xc13c 94 #define DWC3_GHWPARAMS0 0xc140 95 #define DWC3_GHWPARAMS1 0xc144 96 #define DWC3_GHWPARAMS2 0xc148 97 #define DWC3_GHWPARAMS3 0xc14c 98 #define DWC3_GHWPARAMS4 0xc150 99 #define DWC3_GHWPARAMS5 0xc154 100 #define DWC3_GHWPARAMS6 0xc158 101 #define DWC3_GHWPARAMS7 0xc15c 102 #define DWC3_GDBGFIFOSPACE 0xc160 103 #define DWC3_GDBGLTSSM 0xc164 104 #define DWC3_GPRTBIMAP_HS0 0xc180 105 #define DWC3_GPRTBIMAP_HS1 0xc184 106 #define DWC3_GPRTBIMAP_FS0 0xc188 107 #define DWC3_GPRTBIMAP_FS1 0xc18c 108 109 #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04)) 110 #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04)) 111 112 #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04)) 113 114 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04)) 115 116 #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04)) 117 #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04)) 118 119 #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10)) 120 #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10)) 121 #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10)) 122 #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) 123 124 #define DWC3_GHWPARAMS8 0xc600 125 126 /* Device Registers */ 127 #define DWC3_DCFG 0xc700 128 #define DWC3_DCTL 0xc704 129 #define DWC3_DEVTEN 0xc708 130 #define DWC3_DSTS 0xc70c 131 #define DWC3_DGCMDPAR 0xc710 132 #define DWC3_DGCMD 0xc714 133 #define DWC3_DALEPENA 0xc720 134 #define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10)) 135 #define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10)) 136 #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10)) 137 #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10)) 138 139 /* OTG Registers */ 140 #define DWC3_OCFG 0xcc00 141 #define DWC3_OCTL 0xcc04 142 #define DWC3_OEVTEN 0xcc08 143 #define DWC3_OSTS 0xcc0C 144 145 /* Bit fields */ 146 147 /* Global Configuration Register */ 148 #define DWC3_GCTL_PWRDNSCALE(n) (n << 19) 149 #define DWC3_GCTL_U2RSTECN (1 << 16) 150 #define DWC3_GCTL_RAMCLKSEL(x) ((x & DWC3_GCTL_CLK_MASK) << 6) 151 #define DWC3_GCTL_CLK_BUS (0) 152 #define DWC3_GCTL_CLK_PIPE (1) 153 #define DWC3_GCTL_CLK_PIPEHALF (2) 154 #define DWC3_GCTL_CLK_MASK (3) 155 156 #define DWC3_GCTL_PRTCAPDIR(n) (n << 12) 157 #define DWC3_GCTL_PRTCAP_HOST 1 158 #define DWC3_GCTL_PRTCAP_DEVICE 2 159 #define DWC3_GCTL_PRTCAP_OTG 3 160 161 #define DWC3_GCTL_CORESOFTRESET (1 << 11) 162 #define DWC3_GCTL_SCALEDOWN(n) (n << 4) 163 #define DWC3_GCTL_DISSCRAMBLE (1 << 3) 164 #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) 165 166 /* Global USB2 PHY Configuration Register */ 167 #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) 168 #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) 169 170 /* Global USB3 PIPE Control Register */ 171 #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) 172 #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) 173 174 /* Global HWPARAMS1 Register */ 175 #define DWC3_GHWPARAMS1_EN_PWROPT(n) ((n & (3 << 24)) >> 24) 176 #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 177 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 178 179 /* Device Configuration Register */ 180 #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) 181 #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) 182 183 #define DWC3_DCFG_SPEED_MASK (7 << 0) 184 #define DWC3_DCFG_SUPERSPEED (4 << 0) 185 #define DWC3_DCFG_HIGHSPEED (0 << 0) 186 #define DWC3_DCFG_FULLSPEED2 (1 << 0) 187 #define DWC3_DCFG_LOWSPEED (2 << 0) 188 #define DWC3_DCFG_FULLSPEED1 (3 << 0) 189 190 /* Device Control Register */ 191 #define DWC3_DCTL_RUN_STOP (1 << 31) 192 #define DWC3_DCTL_CSFTRST (1 << 30) 193 #define DWC3_DCTL_LSFTRST (1 << 29) 194 195 #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) 196 #define DWC3_DCTL_HIRD_THRES(n) (((n) & DWC3_DCTL_HIRD_THRES_MASK) >> 24) 197 198 #define DWC3_DCTL_APPL1RES (1 << 23) 199 200 #define DWC3_DCTL_INITU2ENA (1 << 12) 201 #define DWC3_DCTL_ACCEPTU2ENA (1 << 11) 202 #define DWC3_DCTL_INITU1ENA (1 << 10) 203 #define DWC3_DCTL_ACCEPTU1ENA (1 << 9) 204 #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) 205 206 #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) 207 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) 208 209 #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) 210 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) 211 #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) 212 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) 213 #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) 214 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) 215 #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) 216 217 /* Device Event Enable Register */ 218 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12) 219 #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11) 220 #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10) 221 #define DWC3_DEVTEN_ERRTICERREN (1 << 9) 222 #define DWC3_DEVTEN_SOFEN (1 << 7) 223 #define DWC3_DEVTEN_EOPFEN (1 << 6) 224 #define DWC3_DEVTEN_WKUPEVTEN (1 << 4) 225 #define DWC3_DEVTEN_ULSTCNGEN (1 << 3) 226 #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2) 227 #define DWC3_DEVTEN_USBRSTEN (1 << 1) 228 #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0) 229 230 /* Device Status Register */ 231 #define DWC3_DSTS_PWRUPREQ (1 << 24) 232 #define DWC3_DSTS_COREIDLE (1 << 23) 233 #define DWC3_DSTS_DEVCTRLHLT (1 << 22) 234 235 #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) 236 #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) 237 238 #define DWC3_DSTS_RXFIFOEMPTY (1 << 17) 239 240 #define DWC3_DSTS_SOFFN_MASK (0x3ff << 3) 241 #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) 242 243 #define DWC3_DSTS_CONNECTSPD (7 << 0) 244 245 #define DWC3_DSTS_SUPERSPEED (4 << 0) 246 #define DWC3_DSTS_HIGHSPEED (0 << 0) 247 #define DWC3_DSTS_FULLSPEED2 (1 << 0) 248 #define DWC3_DSTS_LOWSPEED (2 << 0) 249 #define DWC3_DSTS_FULLSPEED1 (3 << 0) 250 251 /* Device Generic Command Register */ 252 #define DWC3_DGCMD_SET_LMP 0x01 253 #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 254 #define DWC3_DGCMD_XMIT_FUNCTION 0x03 255 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 256 #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a 257 #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c 258 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 259 260 /* Device Endpoint Command Register */ 261 #define DWC3_DEPCMD_PARAM_SHIFT 16 262 #define DWC3_DEPCMD_PARAM(x) (x << DWC3_DEPCMD_PARAM_SHIFT) 263 #define DWC3_DEPCMD_GET_RSC_IDX(x) ((x >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) 264 #define DWC3_DEPCMD_STATUS_MASK (0x0f << 12) 265 #define DWC3_DEPCMD_STATUS(x) ((x & DWC3_DEPCMD_STATUS_MASK) >> 12) 266 #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11) 267 #define DWC3_DEPCMD_CMDACT (1 << 10) 268 #define DWC3_DEPCMD_CMDIOC (1 << 8) 269 270 #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) 271 #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) 272 #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) 273 #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) 274 #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) 275 #define DWC3_DEPCMD_SETSTALL (0x04 << 0) 276 #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) 277 #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) 278 #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) 279 280 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ 281 #define DWC3_DALEPENA_EP(n) (1 << n) 282 283 #define DWC3_DEPCMD_TYPE_CONTROL 0 284 #define DWC3_DEPCMD_TYPE_ISOC 1 285 #define DWC3_DEPCMD_TYPE_BULK 2 286 #define DWC3_DEPCMD_TYPE_INTR 3 287 288 /* Structures */ 289 290 struct dwc3_trb_hw; 291 292 /** 293 * struct dwc3_event_buffer - Software event buffer representation 294 * @list: a list of event buffers 295 * @buf: _THE_ buffer 296 * @length: size of this buffer 297 * @dma: dma_addr_t 298 * @dwc: pointer to DWC controller 299 */ 300 struct dwc3_event_buffer { 301 void *buf; 302 unsigned length; 303 unsigned int lpos; 304 305 dma_addr_t dma; 306 307 struct dwc3 *dwc; 308 }; 309 310 #define DWC3_EP_FLAG_STALLED (1 << 0) 311 #define DWC3_EP_FLAG_WEDGED (1 << 1) 312 313 #define DWC3_EP_DIRECTION_TX true 314 #define DWC3_EP_DIRECTION_RX false 315 316 #define DWC3_TRB_NUM 32 317 #define DWC3_TRB_MASK (DWC3_TRB_NUM - 1) 318 319 /** 320 * struct dwc3_ep - device side endpoint representation 321 * @endpoint: usb endpoint 322 * @request_list: list of requests for this endpoint 323 * @req_queued: list of requests on this ep which have TRBs setup 324 * @trb_pool: array of transaction buffers 325 * @trb_pool_dma: dma address of @trb_pool 326 * @free_slot: next slot which is going to be used 327 * @busy_slot: first slot which is owned by HW 328 * @desc: usb_endpoint_descriptor pointer 329 * @dwc: pointer to DWC controller 330 * @flags: endpoint flags (wedged, stalled, ...) 331 * @current_trb: index of current used trb 332 * @number: endpoint number (1 - 15) 333 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK 334 * @res_trans_idx: Resource transfer index 335 * @interval: the intervall on which the ISOC transfer is started 336 * @name: a human readable name e.g. ep1out-bulk 337 * @direction: true for TX, false for RX 338 * @stream_capable: true when streams are enabled 339 */ 340 struct dwc3_ep { 341 struct usb_ep endpoint; 342 struct list_head request_list; 343 struct list_head req_queued; 344 345 struct dwc3_trb_hw *trb_pool; 346 dma_addr_t trb_pool_dma; 347 u32 free_slot; 348 u32 busy_slot; 349 const struct usb_endpoint_descriptor *desc; 350 struct dwc3 *dwc; 351 352 unsigned flags; 353 #define DWC3_EP_ENABLED (1 << 0) 354 #define DWC3_EP_STALL (1 << 1) 355 #define DWC3_EP_WEDGE (1 << 2) 356 #define DWC3_EP_BUSY (1 << 4) 357 #define DWC3_EP_PENDING_REQUEST (1 << 5) 358 359 /* This last one is specific to EP0 */ 360 #define DWC3_EP0_DIR_IN (1 << 31) 361 362 unsigned current_trb; 363 364 u8 number; 365 u8 type; 366 u8 res_trans_idx; 367 u32 interval; 368 369 char name[20]; 370 371 unsigned direction:1; 372 unsigned stream_capable:1; 373 }; 374 375 enum dwc3_phy { 376 DWC3_PHY_UNKNOWN = 0, 377 DWC3_PHY_USB3, 378 DWC3_PHY_USB2, 379 }; 380 381 enum dwc3_ep0_next { 382 DWC3_EP0_UNKNOWN = 0, 383 DWC3_EP0_COMPLETE, 384 DWC3_EP0_NRDY_SETUP, 385 DWC3_EP0_NRDY_DATA, 386 DWC3_EP0_NRDY_STATUS, 387 }; 388 389 enum dwc3_ep0_state { 390 EP0_UNCONNECTED = 0, 391 EP0_SETUP_PHASE, 392 EP0_DATA_PHASE, 393 EP0_STATUS_PHASE, 394 }; 395 396 enum dwc3_link_state { 397 /* In SuperSpeed */ 398 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ 399 DWC3_LINK_STATE_U1 = 0x01, 400 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ 401 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ 402 DWC3_LINK_STATE_SS_DIS = 0x04, 403 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ 404 DWC3_LINK_STATE_SS_INACT = 0x06, 405 DWC3_LINK_STATE_POLL = 0x07, 406 DWC3_LINK_STATE_RECOV = 0x08, 407 DWC3_LINK_STATE_HRESET = 0x09, 408 DWC3_LINK_STATE_CMPLY = 0x0a, 409 DWC3_LINK_STATE_LPBK = 0x0b, 410 DWC3_LINK_STATE_MASK = 0x0f, 411 }; 412 413 enum dwc3_device_state { 414 DWC3_DEFAULT_STATE, 415 DWC3_ADDRESS_STATE, 416 DWC3_CONFIGURED_STATE, 417 }; 418 419 /** 420 * struct dwc3_trb - transfer request block 421 * @bpl: lower 32bit of the buffer 422 * @bph: higher 32bit of the buffer 423 * @length: buffer size (up to 16mb - 1) 424 * @pcm1: packet count m1 425 * @trbsts: trb status 426 * 0 = ok 427 * 1 = missed isoc 428 * 2 = setup pending 429 * @hwo: hardware owner of descriptor 430 * @lst: last trb 431 * @chn: chain buffers 432 * @csp: continue on short packets (only supported on isoc eps) 433 * @trbctl: trb control 434 * 1 = normal 435 * 2 = control-setup 436 * 3 = control-status-2 437 * 4 = control-status-3 438 * 5 = control-data (first trb of data stage) 439 * 6 = isochronous-first (first trb of service interval) 440 * 7 = isochronous 441 * 8 = link trb 442 * others = reserved 443 * @isp_imi: interrupt on short packet / interrupt on missed isoc 444 * @ioc: interrupt on complete 445 * @sid_sofn: Stream ID / SOF Number 446 */ 447 struct dwc3_trb { 448 u64 bplh; 449 450 union { 451 struct { 452 u32 length:24; 453 u32 pcm1:2; 454 u32 reserved27_26:2; 455 u32 trbsts:4; 456 #define DWC3_TRB_STS_OKAY 0 457 #define DWC3_TRB_STS_MISSED_ISOC 1 458 #define DWC3_TRB_STS_SETUP_PENDING 2 459 }; 460 u32 len_pcm; 461 }; 462 463 union { 464 struct { 465 u32 hwo:1; 466 u32 lst:1; 467 u32 chn:1; 468 u32 csp:1; 469 u32 trbctl:6; 470 u32 isp_imi:1; 471 u32 ioc:1; 472 u32 reserved13_12:2; 473 u32 sid_sofn:16; 474 u32 reserved31_30:2; 475 }; 476 u32 control; 477 }; 478 } __packed; 479 480 /** 481 * struct dwc3_trb_hw - transfer request block (hw format) 482 * @bpl: DW0-3 483 * @bph: DW4-7 484 * @size: DW8-B 485 * @trl: DWC-F 486 */ 487 struct dwc3_trb_hw { 488 __le32 bpl; 489 __le32 bph; 490 __le32 size; 491 __le32 ctrl; 492 } __packed; 493 494 static inline void dwc3_trb_to_hw(struct dwc3_trb *nat, struct dwc3_trb_hw *hw) 495 { 496 hw->bpl = cpu_to_le32(lower_32_bits(nat->bplh)); 497 hw->bph = cpu_to_le32(upper_32_bits(nat->bplh)); 498 hw->size = cpu_to_le32p(&nat->len_pcm); 499 /* HWO is written last */ 500 hw->ctrl = cpu_to_le32p(&nat->control); 501 } 502 503 static inline void dwc3_trb_to_nat(struct dwc3_trb_hw *hw, struct dwc3_trb *nat) 504 { 505 u64 bplh; 506 507 bplh = le32_to_cpup(&hw->bpl); 508 bplh |= (u64) le32_to_cpup(&hw->bph) << 32; 509 nat->bplh = bplh; 510 511 nat->len_pcm = le32_to_cpup(&hw->size); 512 nat->control = le32_to_cpup(&hw->ctrl); 513 } 514 515 /** 516 * dwc3_hwparams - copy of HWPARAMS registers 517 * @hwparams0 - GHWPARAMS0 518 * @hwparams1 - GHWPARAMS1 519 * @hwparams2 - GHWPARAMS2 520 * @hwparams3 - GHWPARAMS3 521 * @hwparams4 - GHWPARAMS4 522 * @hwparams5 - GHWPARAMS5 523 * @hwparams6 - GHWPARAMS6 524 * @hwparams7 - GHWPARAMS7 525 * @hwparams8 - GHWPARAMS8 526 */ 527 struct dwc3_hwparams { 528 u32 hwparams0; 529 u32 hwparams1; 530 u32 hwparams2; 531 u32 hwparams3; 532 u32 hwparams4; 533 u32 hwparams5; 534 u32 hwparams6; 535 u32 hwparams7; 536 u32 hwparams8; 537 }; 538 539 /** 540 * struct dwc3 - representation of our controller 541 * @ctrl_req: usb control request which is used for ep0 542 * @ep0_trb: trb which is used for the ctrl_req 543 * @ep0_bounce: bounce buffer for ep0 544 * @setup_buf: used while precessing STD USB requests 545 * @ctrl_req_addr: dma address of ctrl_req 546 * @ep0_trb: dma address of ep0_trb 547 * @ep0_usb_req: dummy req used while handling STD USB requests 548 * @setup_buf_addr: dma address of setup_buf 549 * @ep0_bounce_addr: dma address of ep0_bounce 550 * @lock: for synchronizing 551 * @dev: pointer to our struct device 552 * @event_buffer_list: a list of event buffers 553 * @gadget: device side representation of the peripheral controller 554 * @gadget_driver: pointer to the gadget driver 555 * @regs: base address for our registers 556 * @regs_size: address space size 557 * @irq: IRQ number 558 * @revision: revision register contents 559 * @is_selfpowered: true when we are selfpowered 560 * @three_stage_setup: set if we perform a three phase setup 561 * @ep0_status_pending: ep0 status response without a req is pending 562 * @ep0_bounced: true when we used bounce buffer 563 * @ep0_expect_in: true when we expect a DATA IN transfer 564 * @start_config_issued: true when StartConfig command has been issued 565 * @ep0_next_event: hold the next expected event 566 * @ep0state: state of endpoint zero 567 * @link_state: link state 568 * @speed: device speed (super, high, full, low) 569 * @mem: points to start of memory which is used for this struct. 570 * @hwparams: copy of hwparams registers 571 * @root: debugfs root folder pointer 572 */ 573 struct dwc3 { 574 struct usb_ctrlrequest *ctrl_req; 575 struct dwc3_trb_hw *ep0_trb; 576 void *ep0_bounce; 577 u8 *setup_buf; 578 dma_addr_t ctrl_req_addr; 579 dma_addr_t ep0_trb_addr; 580 dma_addr_t setup_buf_addr; 581 dma_addr_t ep0_bounce_addr; 582 struct usb_request ep0_usb_req; 583 /* device lock */ 584 spinlock_t lock; 585 struct device *dev; 586 587 struct dwc3_event_buffer *ev_buffs[DWC3_EVENT_BUFFERS_NUM]; 588 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; 589 590 struct usb_gadget gadget; 591 struct usb_gadget_driver *gadget_driver; 592 593 void __iomem *regs; 594 size_t regs_size; 595 596 int irq; 597 598 u32 revision; 599 600 #define DWC3_REVISION_173A 0x5533173a 601 #define DWC3_REVISION_175A 0x5533175a 602 #define DWC3_REVISION_180A 0x5533180a 603 #define DWC3_REVISION_183A 0x5533183a 604 #define DWC3_REVISION_185A 0x5533185a 605 #define DWC3_REVISION_188A 0x5533188a 606 #define DWC3_REVISION_190A 0x5533190a 607 608 unsigned is_selfpowered:1; 609 unsigned three_stage_setup:1; 610 unsigned ep0_status_pending:1; 611 unsigned ep0_bounced:1; 612 unsigned ep0_expect_in:1; 613 unsigned start_config_issued:1; 614 615 enum dwc3_ep0_next ep0_next_event; 616 enum dwc3_ep0_state ep0state; 617 enum dwc3_link_state link_state; 618 enum dwc3_device_state dev_state; 619 620 u8 speed; 621 void *mem; 622 623 struct dwc3_hwparams hwparams; 624 struct dentry *root; 625 }; 626 627 /* -------------------------------------------------------------------------- */ 628 629 #define DWC3_TRBSTS_OK 0 630 #define DWC3_TRBSTS_MISSED_ISOC 1 631 #define DWC3_TRBSTS_SETUP_PENDING 2 632 633 #define DWC3_TRBCTL_NORMAL 1 634 #define DWC3_TRBCTL_CONTROL_SETUP 2 635 #define DWC3_TRBCTL_CONTROL_STATUS2 3 636 #define DWC3_TRBCTL_CONTROL_STATUS3 4 637 #define DWC3_TRBCTL_CONTROL_DATA 5 638 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST 6 639 #define DWC3_TRBCTL_ISOCHRONOUS 7 640 #define DWC3_TRBCTL_LINK_TRB 8 641 642 /* -------------------------------------------------------------------------- */ 643 644 struct dwc3_event_type { 645 u32 is_devspec:1; 646 u32 type:6; 647 u32 reserved8_31:25; 648 } __packed; 649 650 #define DWC3_DEPEVT_XFERCOMPLETE 0x01 651 #define DWC3_DEPEVT_XFERINPROGRESS 0x02 652 #define DWC3_DEPEVT_XFERNOTREADY 0x03 653 #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 654 #define DWC3_DEPEVT_STREAMEVT 0x06 655 #define DWC3_DEPEVT_EPCMDCMPLT 0x07 656 657 /** 658 * struct dwc3_event_depvt - Device Endpoint Events 659 * @one_bit: indicates this is an endpoint event (not used) 660 * @endpoint_number: number of the endpoint 661 * @endpoint_event: The event we have: 662 * 0x00 - Reserved 663 * 0x01 - XferComplete 664 * 0x02 - XferInProgress 665 * 0x03 - XferNotReady 666 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) 667 * 0x05 - Reserved 668 * 0x06 - StreamEvt 669 * 0x07 - EPCmdCmplt 670 * @reserved11_10: Reserved, don't use. 671 * @status: Indicates the status of the event. Refer to databook for 672 * more information. 673 * @parameters: Parameters of the current event. Refer to databook for 674 * more information. 675 */ 676 struct dwc3_event_depevt { 677 u32 one_bit:1; 678 u32 endpoint_number:5; 679 u32 endpoint_event:4; 680 u32 reserved11_10:2; 681 u32 status:4; 682 #define DEPEVT_STATUS_BUSERR (1 << 0) 683 #define DEPEVT_STATUS_SHORT (1 << 1) 684 #define DEPEVT_STATUS_IOC (1 << 2) 685 #define DEPEVT_STATUS_LST (1 << 3) 686 687 /* Stream event only */ 688 #define DEPEVT_STREAMEVT_FOUND 1 689 #define DEPEVT_STREAMEVT_NOTFOUND 2 690 691 /* Control-only Status */ 692 #define DEPEVT_STATUS_CONTROL_SETUP 0 693 #define DEPEVT_STATUS_CONTROL_DATA 1 694 #define DEPEVT_STATUS_CONTROL_STATUS 2 695 696 u32 parameters:16; 697 } __packed; 698 699 /** 700 * struct dwc3_event_devt - Device Events 701 * @one_bit: indicates this is a non-endpoint event (not used) 702 * @device_event: indicates it's a device event. Should read as 0x00 703 * @type: indicates the type of device event. 704 * 0 - DisconnEvt 705 * 1 - USBRst 706 * 2 - ConnectDone 707 * 3 - ULStChng 708 * 4 - WkUpEvt 709 * 5 - Reserved 710 * 6 - EOPF 711 * 7 - SOF 712 * 8 - Reserved 713 * 9 - ErrticErr 714 * 10 - CmdCmplt 715 * 11 - EvntOverflow 716 * 12 - VndrDevTstRcved 717 * @reserved15_12: Reserved, not used 718 * @event_info: Information about this event 719 * @reserved31_24: Reserved, not used 720 */ 721 struct dwc3_event_devt { 722 u32 one_bit:1; 723 u32 device_event:7; 724 u32 type:4; 725 u32 reserved15_12:4; 726 u32 event_info:8; 727 u32 reserved31_24:8; 728 } __packed; 729 730 /** 731 * struct dwc3_event_gevt - Other Core Events 732 * @one_bit: indicates this is a non-endpoint event (not used) 733 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. 734 * @phy_port_number: self-explanatory 735 * @reserved31_12: Reserved, not used. 736 */ 737 struct dwc3_event_gevt { 738 u32 one_bit:1; 739 u32 device_event:7; 740 u32 phy_port_number:4; 741 u32 reserved31_12:20; 742 } __packed; 743 744 /** 745 * union dwc3_event - representation of Event Buffer contents 746 * @raw: raw 32-bit event 747 * @type: the type of the event 748 * @depevt: Device Endpoint Event 749 * @devt: Device Event 750 * @gevt: Global Event 751 */ 752 union dwc3_event { 753 u32 raw; 754 struct dwc3_event_type type; 755 struct dwc3_event_depevt depevt; 756 struct dwc3_event_devt devt; 757 struct dwc3_event_gevt gevt; 758 }; 759 760 /* 761 * DWC3 Features to be used as Driver Data 762 */ 763 764 #define DWC3_HAS_PERIPHERAL BIT(0) 765 #define DWC3_HAS_XHCI BIT(1) 766 #define DWC3_HAS_OTG BIT(3) 767 768 #endif /* __DRIVERS_USB_DWC3_CORE_H */ 769