1 /** 2 * core.h - DesignWare USB3 DRD Core Header 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * This program is free software: you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 of 11 * the License as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #ifndef __DRIVERS_USB_DWC3_CORE_H 20 #define __DRIVERS_USB_DWC3_CORE_H 21 22 #include <linux/device.h> 23 #include <linux/spinlock.h> 24 #include <linux/ioport.h> 25 #include <linux/list.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/mm.h> 28 #include <linux/debugfs.h> 29 30 #include <linux/usb/ch9.h> 31 #include <linux/usb/gadget.h> 32 #include <linux/usb/otg.h> 33 34 #include <linux/phy/phy.h> 35 36 /* Global constants */ 37 #define DWC3_EP0_BOUNCE_SIZE 512 38 #define DWC3_ENDPOINTS_NUM 32 39 #define DWC3_XHCI_RESOURCES_NUM 2 40 41 #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */ 42 #define DWC3_EVENT_SIZE 4 /* bytes */ 43 #define DWC3_EVENT_MAX_NUM 64 /* 2 events/endpoint */ 44 #define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM) 45 #define DWC3_EVENT_TYPE_MASK 0xfe 46 47 #define DWC3_EVENT_TYPE_DEV 0 48 #define DWC3_EVENT_TYPE_CARKIT 3 49 #define DWC3_EVENT_TYPE_I2C 4 50 51 #define DWC3_DEVICE_EVENT_DISCONNECT 0 52 #define DWC3_DEVICE_EVENT_RESET 1 53 #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 54 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 55 #define DWC3_DEVICE_EVENT_WAKEUP 4 56 #define DWC3_DEVICE_EVENT_HIBER_REQ 5 57 #define DWC3_DEVICE_EVENT_EOPF 6 58 #define DWC3_DEVICE_EVENT_SOF 7 59 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 60 #define DWC3_DEVICE_EVENT_CMD_CMPL 10 61 #define DWC3_DEVICE_EVENT_OVERFLOW 11 62 63 #define DWC3_GEVNTCOUNT_MASK 0xfffc 64 #define DWC3_GSNPSID_MASK 0xffff0000 65 #define DWC3_GSNPSREV_MASK 0xffff 66 67 /* DWC3 registers memory space boundries */ 68 #define DWC3_XHCI_REGS_START 0x0 69 #define DWC3_XHCI_REGS_END 0x7fff 70 #define DWC3_GLOBALS_REGS_START 0xc100 71 #define DWC3_GLOBALS_REGS_END 0xc6ff 72 #define DWC3_DEVICE_REGS_START 0xc700 73 #define DWC3_DEVICE_REGS_END 0xcbff 74 #define DWC3_OTG_REGS_START 0xcc00 75 #define DWC3_OTG_REGS_END 0xccff 76 77 /* Global Registers */ 78 #define DWC3_GSBUSCFG0 0xc100 79 #define DWC3_GSBUSCFG1 0xc104 80 #define DWC3_GTXTHRCFG 0xc108 81 #define DWC3_GRXTHRCFG 0xc10c 82 #define DWC3_GCTL 0xc110 83 #define DWC3_GEVTEN 0xc114 84 #define DWC3_GSTS 0xc118 85 #define DWC3_GSNPSID 0xc120 86 #define DWC3_GGPIO 0xc124 87 #define DWC3_GUID 0xc128 88 #define DWC3_GUCTL 0xc12c 89 #define DWC3_GBUSERRADDR0 0xc130 90 #define DWC3_GBUSERRADDR1 0xc134 91 #define DWC3_GPRTBIMAP0 0xc138 92 #define DWC3_GPRTBIMAP1 0xc13c 93 #define DWC3_GHWPARAMS0 0xc140 94 #define DWC3_GHWPARAMS1 0xc144 95 #define DWC3_GHWPARAMS2 0xc148 96 #define DWC3_GHWPARAMS3 0xc14c 97 #define DWC3_GHWPARAMS4 0xc150 98 #define DWC3_GHWPARAMS5 0xc154 99 #define DWC3_GHWPARAMS6 0xc158 100 #define DWC3_GHWPARAMS7 0xc15c 101 #define DWC3_GDBGFIFOSPACE 0xc160 102 #define DWC3_GDBGLTSSM 0xc164 103 #define DWC3_GPRTBIMAP_HS0 0xc180 104 #define DWC3_GPRTBIMAP_HS1 0xc184 105 #define DWC3_GPRTBIMAP_FS0 0xc188 106 #define DWC3_GPRTBIMAP_FS1 0xc18c 107 108 #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04)) 109 #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04)) 110 111 #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04)) 112 113 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04)) 114 115 #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04)) 116 #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04)) 117 118 #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10)) 119 #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10)) 120 #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10)) 121 #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) 122 123 #define DWC3_GHWPARAMS8 0xc600 124 125 /* Device Registers */ 126 #define DWC3_DCFG 0xc700 127 #define DWC3_DCTL 0xc704 128 #define DWC3_DEVTEN 0xc708 129 #define DWC3_DSTS 0xc70c 130 #define DWC3_DGCMDPAR 0xc710 131 #define DWC3_DGCMD 0xc714 132 #define DWC3_DALEPENA 0xc720 133 #define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10)) 134 #define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10)) 135 #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10)) 136 #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10)) 137 138 /* OTG Registers */ 139 #define DWC3_OCFG 0xcc00 140 #define DWC3_OCTL 0xcc04 141 #define DWC3_OEVT 0xcc08 142 #define DWC3_OEVTEN 0xcc0C 143 #define DWC3_OSTS 0xcc10 144 145 /* Bit fields */ 146 147 /* Global Configuration Register */ 148 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) 149 #define DWC3_GCTL_U2RSTECN (1 << 16) 150 #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) 151 #define DWC3_GCTL_CLK_BUS (0) 152 #define DWC3_GCTL_CLK_PIPE (1) 153 #define DWC3_GCTL_CLK_PIPEHALF (2) 154 #define DWC3_GCTL_CLK_MASK (3) 155 156 #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) 157 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) 158 #define DWC3_GCTL_PRTCAP_HOST 1 159 #define DWC3_GCTL_PRTCAP_DEVICE 2 160 #define DWC3_GCTL_PRTCAP_OTG 3 161 162 #define DWC3_GCTL_CORESOFTRESET (1 << 11) 163 #define DWC3_GCTL_SOFITPSYNC (1 << 10) 164 #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) 165 #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) 166 #define DWC3_GCTL_DISSCRAMBLE (1 << 3) 167 #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1) 168 #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) 169 170 /* Global USB2 PHY Configuration Register */ 171 #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) 172 #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) 173 174 /* Global USB3 PIPE Control Register */ 175 #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) 176 #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) 177 178 /* Global TX Fifo Size Register */ 179 #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) 180 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) 181 182 /* Global Event Size Registers */ 183 #define DWC3_GEVNTSIZ_INTMASK (1 << 31) 184 #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff) 185 186 /* Global HWPARAMS1 Register */ 187 #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) 188 #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 189 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 190 #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2 191 #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) 192 #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) 193 194 /* Global HWPARAMS4 Register */ 195 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) 196 #define DWC3_MAX_HIBER_SCRATCHBUFS 15 197 198 /* Device Configuration Register */ 199 #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) 200 #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) 201 202 #define DWC3_DCFG_SPEED_MASK (7 << 0) 203 #define DWC3_DCFG_SUPERSPEED (4 << 0) 204 #define DWC3_DCFG_HIGHSPEED (0 << 0) 205 #define DWC3_DCFG_FULLSPEED2 (1 << 0) 206 #define DWC3_DCFG_LOWSPEED (2 << 0) 207 #define DWC3_DCFG_FULLSPEED1 (3 << 0) 208 209 #define DWC3_DCFG_LPM_CAP (1 << 22) 210 211 /* Device Control Register */ 212 #define DWC3_DCTL_RUN_STOP (1 << 31) 213 #define DWC3_DCTL_CSFTRST (1 << 30) 214 #define DWC3_DCTL_LSFTRST (1 << 29) 215 216 #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) 217 #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) 218 219 #define DWC3_DCTL_APPL1RES (1 << 23) 220 221 /* These apply for core versions 1.87a and earlier */ 222 #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) 223 #define DWC3_DCTL_TRGTULST(n) ((n) << 17) 224 #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) 225 #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) 226 #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) 227 #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) 228 #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) 229 230 /* These apply for core versions 1.94a and later */ 231 #define DWC3_DCTL_KEEP_CONNECT (1 << 19) 232 #define DWC3_DCTL_L1_HIBER_EN (1 << 18) 233 #define DWC3_DCTL_CRS (1 << 17) 234 #define DWC3_DCTL_CSS (1 << 16) 235 236 #define DWC3_DCTL_INITU2ENA (1 << 12) 237 #define DWC3_DCTL_ACCEPTU2ENA (1 << 11) 238 #define DWC3_DCTL_INITU1ENA (1 << 10) 239 #define DWC3_DCTL_ACCEPTU1ENA (1 << 9) 240 #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) 241 242 #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) 243 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) 244 245 #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) 246 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) 247 #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) 248 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) 249 #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) 250 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) 251 #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) 252 253 /* Device Event Enable Register */ 254 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12) 255 #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11) 256 #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10) 257 #define DWC3_DEVTEN_ERRTICERREN (1 << 9) 258 #define DWC3_DEVTEN_SOFEN (1 << 7) 259 #define DWC3_DEVTEN_EOPFEN (1 << 6) 260 #define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5) 261 #define DWC3_DEVTEN_WKUPEVTEN (1 << 4) 262 #define DWC3_DEVTEN_ULSTCNGEN (1 << 3) 263 #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2) 264 #define DWC3_DEVTEN_USBRSTEN (1 << 1) 265 #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0) 266 267 /* Device Status Register */ 268 #define DWC3_DSTS_DCNRD (1 << 29) 269 270 /* This applies for core versions 1.87a and earlier */ 271 #define DWC3_DSTS_PWRUPREQ (1 << 24) 272 273 /* These apply for core versions 1.94a and later */ 274 #define DWC3_DSTS_RSS (1 << 25) 275 #define DWC3_DSTS_SSS (1 << 24) 276 277 #define DWC3_DSTS_COREIDLE (1 << 23) 278 #define DWC3_DSTS_DEVCTRLHLT (1 << 22) 279 280 #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) 281 #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) 282 283 #define DWC3_DSTS_RXFIFOEMPTY (1 << 17) 284 285 #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) 286 #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) 287 288 #define DWC3_DSTS_CONNECTSPD (7 << 0) 289 290 #define DWC3_DSTS_SUPERSPEED (4 << 0) 291 #define DWC3_DSTS_HIGHSPEED (0 << 0) 292 #define DWC3_DSTS_FULLSPEED2 (1 << 0) 293 #define DWC3_DSTS_LOWSPEED (2 << 0) 294 #define DWC3_DSTS_FULLSPEED1 (3 << 0) 295 296 /* Device Generic Command Register */ 297 #define DWC3_DGCMD_SET_LMP 0x01 298 #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 299 #define DWC3_DGCMD_XMIT_FUNCTION 0x03 300 301 /* These apply for core versions 1.94a and later */ 302 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 303 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05 304 305 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 306 #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a 307 #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c 308 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 309 310 #define DWC3_DGCMD_STATUS(n) (((n) >> 15) & 1) 311 #define DWC3_DGCMD_CMDACT (1 << 10) 312 #define DWC3_DGCMD_CMDIOC (1 << 8) 313 314 /* Device Generic Command Parameter Register */ 315 #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0) 316 #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0) 317 #define DWC3_DGCMDPAR_RX_FIFO (0 << 5) 318 #define DWC3_DGCMDPAR_TX_FIFO (1 << 5) 319 #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0) 320 #define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0) 321 322 /* Device Endpoint Command Register */ 323 #define DWC3_DEPCMD_PARAM_SHIFT 16 324 #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) 325 #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) 326 #define DWC3_DEPCMD_STATUS(x) (((x) >> 15) & 1) 327 #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11) 328 #define DWC3_DEPCMD_CMDACT (1 << 10) 329 #define DWC3_DEPCMD_CMDIOC (1 << 8) 330 331 #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) 332 #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) 333 #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) 334 #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) 335 #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) 336 #define DWC3_DEPCMD_SETSTALL (0x04 << 0) 337 /* This applies for core versions 1.90a and earlier */ 338 #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) 339 /* This applies for core versions 1.94a and later */ 340 #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0) 341 #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) 342 #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) 343 344 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ 345 #define DWC3_DALEPENA_EP(n) (1 << n) 346 347 #define DWC3_DEPCMD_TYPE_CONTROL 0 348 #define DWC3_DEPCMD_TYPE_ISOC 1 349 #define DWC3_DEPCMD_TYPE_BULK 2 350 #define DWC3_DEPCMD_TYPE_INTR 3 351 352 /* Structures */ 353 354 struct dwc3_trb; 355 356 /** 357 * struct dwc3_event_buffer - Software event buffer representation 358 * @buf: _THE_ buffer 359 * @length: size of this buffer 360 * @lpos: event offset 361 * @count: cache of last read event count register 362 * @flags: flags related to this event buffer 363 * @dma: dma_addr_t 364 * @dwc: pointer to DWC controller 365 */ 366 struct dwc3_event_buffer { 367 void *buf; 368 unsigned length; 369 unsigned int lpos; 370 unsigned int count; 371 unsigned int flags; 372 373 #define DWC3_EVENT_PENDING BIT(0) 374 375 dma_addr_t dma; 376 377 struct dwc3 *dwc; 378 }; 379 380 #define DWC3_EP_FLAG_STALLED (1 << 0) 381 #define DWC3_EP_FLAG_WEDGED (1 << 1) 382 383 #define DWC3_EP_DIRECTION_TX true 384 #define DWC3_EP_DIRECTION_RX false 385 386 #define DWC3_TRB_NUM 32 387 #define DWC3_TRB_MASK (DWC3_TRB_NUM - 1) 388 389 /** 390 * struct dwc3_ep - device side endpoint representation 391 * @endpoint: usb endpoint 392 * @request_list: list of requests for this endpoint 393 * @req_queued: list of requests on this ep which have TRBs setup 394 * @trb_pool: array of transaction buffers 395 * @trb_pool_dma: dma address of @trb_pool 396 * @free_slot: next slot which is going to be used 397 * @busy_slot: first slot which is owned by HW 398 * @desc: usb_endpoint_descriptor pointer 399 * @dwc: pointer to DWC controller 400 * @saved_state: ep state saved during hibernation 401 * @flags: endpoint flags (wedged, stalled, ...) 402 * @current_trb: index of current used trb 403 * @number: endpoint number (1 - 15) 404 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK 405 * @resource_index: Resource transfer index 406 * @interval: the interval on which the ISOC transfer is started 407 * @name: a human readable name e.g. ep1out-bulk 408 * @direction: true for TX, false for RX 409 * @stream_capable: true when streams are enabled 410 */ 411 struct dwc3_ep { 412 struct usb_ep endpoint; 413 struct list_head request_list; 414 struct list_head req_queued; 415 416 struct dwc3_trb *trb_pool; 417 dma_addr_t trb_pool_dma; 418 u32 free_slot; 419 u32 busy_slot; 420 const struct usb_ss_ep_comp_descriptor *comp_desc; 421 struct dwc3 *dwc; 422 423 u32 saved_state; 424 unsigned flags; 425 #define DWC3_EP_ENABLED (1 << 0) 426 #define DWC3_EP_STALL (1 << 1) 427 #define DWC3_EP_WEDGE (1 << 2) 428 #define DWC3_EP_BUSY (1 << 4) 429 #define DWC3_EP_PENDING_REQUEST (1 << 5) 430 #define DWC3_EP_MISSED_ISOC (1 << 6) 431 432 /* This last one is specific to EP0 */ 433 #define DWC3_EP0_DIR_IN (1 << 31) 434 435 unsigned current_trb; 436 437 u8 number; 438 u8 type; 439 u8 resource_index; 440 u32 interval; 441 442 char name[20]; 443 444 unsigned direction:1; 445 unsigned stream_capable:1; 446 }; 447 448 enum dwc3_phy { 449 DWC3_PHY_UNKNOWN = 0, 450 DWC3_PHY_USB3, 451 DWC3_PHY_USB2, 452 }; 453 454 enum dwc3_ep0_next { 455 DWC3_EP0_UNKNOWN = 0, 456 DWC3_EP0_COMPLETE, 457 DWC3_EP0_NRDY_DATA, 458 DWC3_EP0_NRDY_STATUS, 459 }; 460 461 enum dwc3_ep0_state { 462 EP0_UNCONNECTED = 0, 463 EP0_SETUP_PHASE, 464 EP0_DATA_PHASE, 465 EP0_STATUS_PHASE, 466 }; 467 468 enum dwc3_link_state { 469 /* In SuperSpeed */ 470 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ 471 DWC3_LINK_STATE_U1 = 0x01, 472 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ 473 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ 474 DWC3_LINK_STATE_SS_DIS = 0x04, 475 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ 476 DWC3_LINK_STATE_SS_INACT = 0x06, 477 DWC3_LINK_STATE_POLL = 0x07, 478 DWC3_LINK_STATE_RECOV = 0x08, 479 DWC3_LINK_STATE_HRESET = 0x09, 480 DWC3_LINK_STATE_CMPLY = 0x0a, 481 DWC3_LINK_STATE_LPBK = 0x0b, 482 DWC3_LINK_STATE_RESET = 0x0e, 483 DWC3_LINK_STATE_RESUME = 0x0f, 484 DWC3_LINK_STATE_MASK = 0x0f, 485 }; 486 487 /* TRB Length, PCM and Status */ 488 #define DWC3_TRB_SIZE_MASK (0x00ffffff) 489 #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) 490 #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) 491 #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28) 492 493 #define DWC3_TRBSTS_OK 0 494 #define DWC3_TRBSTS_MISSED_ISOC 1 495 #define DWC3_TRBSTS_SETUP_PENDING 2 496 #define DWC3_TRB_STS_XFER_IN_PROG 4 497 498 /* TRB Control */ 499 #define DWC3_TRB_CTRL_HWO (1 << 0) 500 #define DWC3_TRB_CTRL_LST (1 << 1) 501 #define DWC3_TRB_CTRL_CHN (1 << 2) 502 #define DWC3_TRB_CTRL_CSP (1 << 3) 503 #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) 504 #define DWC3_TRB_CTRL_ISP_IMI (1 << 10) 505 #define DWC3_TRB_CTRL_IOC (1 << 11) 506 #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) 507 508 #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) 509 #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) 510 #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) 511 #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) 512 #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) 513 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) 514 #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) 515 #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) 516 517 /** 518 * struct dwc3_trb - transfer request block (hw format) 519 * @bpl: DW0-3 520 * @bph: DW4-7 521 * @size: DW8-B 522 * @trl: DWC-F 523 */ 524 struct dwc3_trb { 525 u32 bpl; 526 u32 bph; 527 u32 size; 528 u32 ctrl; 529 } __packed; 530 531 /** 532 * dwc3_hwparams - copy of HWPARAMS registers 533 * @hwparams0 - GHWPARAMS0 534 * @hwparams1 - GHWPARAMS1 535 * @hwparams2 - GHWPARAMS2 536 * @hwparams3 - GHWPARAMS3 537 * @hwparams4 - GHWPARAMS4 538 * @hwparams5 - GHWPARAMS5 539 * @hwparams6 - GHWPARAMS6 540 * @hwparams7 - GHWPARAMS7 541 * @hwparams8 - GHWPARAMS8 542 */ 543 struct dwc3_hwparams { 544 u32 hwparams0; 545 u32 hwparams1; 546 u32 hwparams2; 547 u32 hwparams3; 548 u32 hwparams4; 549 u32 hwparams5; 550 u32 hwparams6; 551 u32 hwparams7; 552 u32 hwparams8; 553 }; 554 555 /* HWPARAMS0 */ 556 #define DWC3_MODE(n) ((n) & 0x7) 557 558 #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8) 559 560 /* HWPARAMS1 */ 561 #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) 562 563 /* HWPARAMS3 */ 564 #define DWC3_NUM_IN_EPS_MASK (0x1f << 18) 565 #define DWC3_NUM_EPS_MASK (0x3f << 12) 566 #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \ 567 (DWC3_NUM_EPS_MASK)) >> 12) 568 #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \ 569 (DWC3_NUM_IN_EPS_MASK)) >> 18) 570 571 /* HWPARAMS7 */ 572 #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) 573 574 struct dwc3_request { 575 struct usb_request request; 576 struct list_head list; 577 struct dwc3_ep *dep; 578 u32 start_slot; 579 580 u8 epnum; 581 struct dwc3_trb *trb; 582 dma_addr_t trb_dma; 583 584 unsigned direction:1; 585 unsigned mapped:1; 586 unsigned queued:1; 587 }; 588 589 /* 590 * struct dwc3_scratchpad_array - hibernation scratchpad array 591 * (format defined by hw) 592 */ 593 struct dwc3_scratchpad_array { 594 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; 595 }; 596 597 /** 598 * struct dwc3 - representation of our controller 599 * @ctrl_req: usb control request which is used for ep0 600 * @ep0_trb: trb which is used for the ctrl_req 601 * @ep0_bounce: bounce buffer for ep0 602 * @setup_buf: used while precessing STD USB requests 603 * @ctrl_req_addr: dma address of ctrl_req 604 * @ep0_trb: dma address of ep0_trb 605 * @ep0_usb_req: dummy req used while handling STD USB requests 606 * @ep0_bounce_addr: dma address of ep0_bounce 607 * @scratch_addr: dma address of scratchbuf 608 * @lock: for synchronizing 609 * @dev: pointer to our struct device 610 * @xhci: pointer to our xHCI child 611 * @event_buffer_list: a list of event buffers 612 * @gadget: device side representation of the peripheral controller 613 * @gadget_driver: pointer to the gadget driver 614 * @regs: base address for our registers 615 * @regs_size: address space size 616 * @nr_scratch: number of scratch buffers 617 * @num_event_buffers: calculated number of event buffers 618 * @u1u2: only used on revisions <1.83a for workaround 619 * @maximum_speed: maximum speed requested (mainly for testing purposes) 620 * @revision: revision register contents 621 * @dr_mode: requested mode of operation 622 * @usb2_phy: pointer to USB2 PHY 623 * @usb3_phy: pointer to USB3 PHY 624 * @usb2_generic_phy: pointer to USB2 PHY 625 * @usb3_generic_phy: pointer to USB3 PHY 626 * @dcfg: saved contents of DCFG register 627 * @gctl: saved contents of GCTL register 628 * @isoch_delay: wValue from Set Isochronous Delay request; 629 * @u2sel: parameter from Set SEL request. 630 * @u2pel: parameter from Set SEL request. 631 * @u1sel: parameter from Set SEL request. 632 * @u1pel: parameter from Set SEL request. 633 * @num_out_eps: number of out endpoints 634 * @num_in_eps: number of in endpoints 635 * @ep0_next_event: hold the next expected event 636 * @ep0state: state of endpoint zero 637 * @link_state: link state 638 * @speed: device speed (super, high, full, low) 639 * @mem: points to start of memory which is used for this struct. 640 * @hwparams: copy of hwparams registers 641 * @root: debugfs root folder pointer 642 * @regset: debugfs pointer to regdump file 643 * @test_mode: true when we're entering a USB test mode 644 * @test_mode_nr: test feature selector 645 * @delayed_status: true when gadget driver asks for delayed status 646 * @ep0_bounced: true when we used bounce buffer 647 * @ep0_expect_in: true when we expect a DATA IN transfer 648 * @has_hibernation: true when dwc3 was configured with Hibernation 649 * @is_selfpowered: true when we are selfpowered 650 * @needs_fifo_resize: not all users might want fifo resizing, flag it 651 * @pullups_connected: true when Run/Stop bit is set 652 * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes. 653 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround 654 * @start_config_issued: true when StartConfig command has been issued 655 * @three_stage_setup: set if we perform a three phase setup 656 */ 657 struct dwc3 { 658 struct usb_ctrlrequest *ctrl_req; 659 struct dwc3_trb *ep0_trb; 660 void *ep0_bounce; 661 void *scratchbuf; 662 u8 *setup_buf; 663 dma_addr_t ctrl_req_addr; 664 dma_addr_t ep0_trb_addr; 665 dma_addr_t ep0_bounce_addr; 666 dma_addr_t scratch_addr; 667 struct dwc3_request ep0_usb_req; 668 669 /* device lock */ 670 spinlock_t lock; 671 672 struct device *dev; 673 674 struct platform_device *xhci; 675 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; 676 677 struct dwc3_event_buffer **ev_buffs; 678 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; 679 680 struct usb_gadget gadget; 681 struct usb_gadget_driver *gadget_driver; 682 683 struct usb_phy *usb2_phy; 684 struct usb_phy *usb3_phy; 685 686 struct phy *usb2_generic_phy; 687 struct phy *usb3_generic_phy; 688 689 void __iomem *regs; 690 size_t regs_size; 691 692 enum usb_dr_mode dr_mode; 693 694 /* used for suspend/resume */ 695 u32 dcfg; 696 u32 gctl; 697 698 u32 nr_scratch; 699 u32 num_event_buffers; 700 u32 u1u2; 701 u32 maximum_speed; 702 u32 revision; 703 704 #define DWC3_REVISION_173A 0x5533173a 705 #define DWC3_REVISION_175A 0x5533175a 706 #define DWC3_REVISION_180A 0x5533180a 707 #define DWC3_REVISION_183A 0x5533183a 708 #define DWC3_REVISION_185A 0x5533185a 709 #define DWC3_REVISION_187A 0x5533187a 710 #define DWC3_REVISION_188A 0x5533188a 711 #define DWC3_REVISION_190A 0x5533190a 712 #define DWC3_REVISION_194A 0x5533194a 713 #define DWC3_REVISION_200A 0x5533200a 714 #define DWC3_REVISION_202A 0x5533202a 715 #define DWC3_REVISION_210A 0x5533210a 716 #define DWC3_REVISION_220A 0x5533220a 717 #define DWC3_REVISION_230A 0x5533230a 718 #define DWC3_REVISION_240A 0x5533240a 719 #define DWC3_REVISION_250A 0x5533250a 720 #define DWC3_REVISION_260A 0x5533260a 721 #define DWC3_REVISION_270A 0x5533270a 722 #define DWC3_REVISION_280A 0x5533280a 723 724 enum dwc3_ep0_next ep0_next_event; 725 enum dwc3_ep0_state ep0state; 726 enum dwc3_link_state link_state; 727 728 u16 isoch_delay; 729 u16 u2sel; 730 u16 u2pel; 731 u8 u1sel; 732 u8 u1pel; 733 734 u8 speed; 735 736 u8 num_out_eps; 737 u8 num_in_eps; 738 739 void *mem; 740 741 struct dwc3_hwparams hwparams; 742 struct dentry *root; 743 struct debugfs_regset32 *regset; 744 745 u8 test_mode; 746 u8 test_mode_nr; 747 748 unsigned delayed_status:1; 749 unsigned ep0_bounced:1; 750 unsigned ep0_expect_in:1; 751 unsigned has_hibernation:1; 752 unsigned is_selfpowered:1; 753 unsigned needs_fifo_resize:1; 754 unsigned pullups_connected:1; 755 unsigned resize_fifos:1; 756 unsigned setup_packet_pending:1; 757 unsigned start_config_issued:1; 758 unsigned three_stage_setup:1; 759 }; 760 761 /* -------------------------------------------------------------------------- */ 762 763 /* -------------------------------------------------------------------------- */ 764 765 struct dwc3_event_type { 766 u32 is_devspec:1; 767 u32 type:7; 768 u32 reserved8_31:24; 769 } __packed; 770 771 #define DWC3_DEPEVT_XFERCOMPLETE 0x01 772 #define DWC3_DEPEVT_XFERINPROGRESS 0x02 773 #define DWC3_DEPEVT_XFERNOTREADY 0x03 774 #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 775 #define DWC3_DEPEVT_STREAMEVT 0x06 776 #define DWC3_DEPEVT_EPCMDCMPLT 0x07 777 778 /** 779 * struct dwc3_event_depvt - Device Endpoint Events 780 * @one_bit: indicates this is an endpoint event (not used) 781 * @endpoint_number: number of the endpoint 782 * @endpoint_event: The event we have: 783 * 0x00 - Reserved 784 * 0x01 - XferComplete 785 * 0x02 - XferInProgress 786 * 0x03 - XferNotReady 787 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) 788 * 0x05 - Reserved 789 * 0x06 - StreamEvt 790 * 0x07 - EPCmdCmplt 791 * @reserved11_10: Reserved, don't use. 792 * @status: Indicates the status of the event. Refer to databook for 793 * more information. 794 * @parameters: Parameters of the current event. Refer to databook for 795 * more information. 796 */ 797 struct dwc3_event_depevt { 798 u32 one_bit:1; 799 u32 endpoint_number:5; 800 u32 endpoint_event:4; 801 u32 reserved11_10:2; 802 u32 status:4; 803 804 /* Within XferNotReady */ 805 #define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3) 806 807 /* Within XferComplete */ 808 #define DEPEVT_STATUS_BUSERR (1 << 0) 809 #define DEPEVT_STATUS_SHORT (1 << 1) 810 #define DEPEVT_STATUS_IOC (1 << 2) 811 #define DEPEVT_STATUS_LST (1 << 3) 812 813 /* Stream event only */ 814 #define DEPEVT_STREAMEVT_FOUND 1 815 #define DEPEVT_STREAMEVT_NOTFOUND 2 816 817 /* Control-only Status */ 818 #define DEPEVT_STATUS_CONTROL_DATA 1 819 #define DEPEVT_STATUS_CONTROL_STATUS 2 820 821 u32 parameters:16; 822 } __packed; 823 824 /** 825 * struct dwc3_event_devt - Device Events 826 * @one_bit: indicates this is a non-endpoint event (not used) 827 * @device_event: indicates it's a device event. Should read as 0x00 828 * @type: indicates the type of device event. 829 * 0 - DisconnEvt 830 * 1 - USBRst 831 * 2 - ConnectDone 832 * 3 - ULStChng 833 * 4 - WkUpEvt 834 * 5 - Reserved 835 * 6 - EOPF 836 * 7 - SOF 837 * 8 - Reserved 838 * 9 - ErrticErr 839 * 10 - CmdCmplt 840 * 11 - EvntOverflow 841 * 12 - VndrDevTstRcved 842 * @reserved15_12: Reserved, not used 843 * @event_info: Information about this event 844 * @reserved31_25: Reserved, not used 845 */ 846 struct dwc3_event_devt { 847 u32 one_bit:1; 848 u32 device_event:7; 849 u32 type:4; 850 u32 reserved15_12:4; 851 u32 event_info:9; 852 u32 reserved31_25:7; 853 } __packed; 854 855 /** 856 * struct dwc3_event_gevt - Other Core Events 857 * @one_bit: indicates this is a non-endpoint event (not used) 858 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. 859 * @phy_port_number: self-explanatory 860 * @reserved31_12: Reserved, not used. 861 */ 862 struct dwc3_event_gevt { 863 u32 one_bit:1; 864 u32 device_event:7; 865 u32 phy_port_number:4; 866 u32 reserved31_12:20; 867 } __packed; 868 869 /** 870 * union dwc3_event - representation of Event Buffer contents 871 * @raw: raw 32-bit event 872 * @type: the type of the event 873 * @depevt: Device Endpoint Event 874 * @devt: Device Event 875 * @gevt: Global Event 876 */ 877 union dwc3_event { 878 u32 raw; 879 struct dwc3_event_type type; 880 struct dwc3_event_depevt depevt; 881 struct dwc3_event_devt devt; 882 struct dwc3_event_gevt gevt; 883 }; 884 885 /** 886 * struct dwc3_gadget_ep_cmd_params - representation of endpoint command 887 * parameters 888 * @param2: third parameter 889 * @param1: second parameter 890 * @param0: first parameter 891 */ 892 struct dwc3_gadget_ep_cmd_params { 893 u32 param2; 894 u32 param1; 895 u32 param0; 896 }; 897 898 /* 899 * DWC3 Features to be used as Driver Data 900 */ 901 902 #define DWC3_HAS_PERIPHERAL BIT(0) 903 #define DWC3_HAS_XHCI BIT(1) 904 #define DWC3_HAS_OTG BIT(3) 905 906 /* prototypes */ 907 void dwc3_set_mode(struct dwc3 *dwc, u32 mode); 908 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc); 909 910 #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 911 int dwc3_host_init(struct dwc3 *dwc); 912 void dwc3_host_exit(struct dwc3 *dwc); 913 #else 914 static inline int dwc3_host_init(struct dwc3 *dwc) 915 { return 0; } 916 static inline void dwc3_host_exit(struct dwc3 *dwc) 917 { } 918 #endif 919 920 #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 921 int dwc3_gadget_init(struct dwc3 *dwc); 922 void dwc3_gadget_exit(struct dwc3 *dwc); 923 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode); 924 int dwc3_gadget_get_link_state(struct dwc3 *dwc); 925 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state); 926 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 927 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params); 928 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param); 929 #else 930 static inline int dwc3_gadget_init(struct dwc3 *dwc) 931 { return 0; } 932 static inline void dwc3_gadget_exit(struct dwc3 *dwc) 933 { } 934 static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) 935 { return 0; } 936 static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc) 937 { return 0; } 938 static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc, 939 enum dwc3_link_state state) 940 { return 0; } 941 942 static inline int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 943 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) 944 { return 0; } 945 static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc, 946 int cmd, u32 param) 947 { return 0; } 948 #endif 949 950 /* power management interface */ 951 #if !IS_ENABLED(CONFIG_USB_DWC3_HOST) 952 int dwc3_gadget_prepare(struct dwc3 *dwc); 953 void dwc3_gadget_complete(struct dwc3 *dwc); 954 int dwc3_gadget_suspend(struct dwc3 *dwc); 955 int dwc3_gadget_resume(struct dwc3 *dwc); 956 #else 957 static inline int dwc3_gadget_prepare(struct dwc3 *dwc) 958 { 959 return 0; 960 } 961 962 static inline void dwc3_gadget_complete(struct dwc3 *dwc) 963 { 964 } 965 966 static inline int dwc3_gadget_suspend(struct dwc3 *dwc) 967 { 968 return 0; 969 } 970 971 static inline int dwc3_gadget_resume(struct dwc3 *dwc) 972 { 973 return 0; 974 } 975 #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */ 976 977 #endif /* __DRIVERS_USB_DWC3_CORE_H */ 978