1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * core.c - DesignWare USB3 DRD Controller Core file 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/version.h> 13 #include <linux/module.h> 14 #include <linux/kernel.h> 15 #include <linux/slab.h> 16 #include <linux/spinlock.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/interrupt.h> 20 #include <linux/ioport.h> 21 #include <linux/io.h> 22 #include <linux/list.h> 23 #include <linux/delay.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/of.h> 26 #include <linux/of_graph.h> 27 #include <linux/acpi.h> 28 #include <linux/pinctrl/consumer.h> 29 #include <linux/reset.h> 30 #include <linux/bitfield.h> 31 32 #include <linux/usb/ch9.h> 33 #include <linux/usb/gadget.h> 34 #include <linux/usb/of.h> 35 #include <linux/usb/otg.h> 36 37 #include "core.h" 38 #include "gadget.h" 39 #include "io.h" 40 41 #include "debug.h" 42 43 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ 44 45 /** 46 * dwc3_get_dr_mode - Validates and sets dr_mode 47 * @dwc: pointer to our context structure 48 */ 49 static int dwc3_get_dr_mode(struct dwc3 *dwc) 50 { 51 enum usb_dr_mode mode; 52 struct device *dev = dwc->dev; 53 unsigned int hw_mode; 54 55 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 56 dwc->dr_mode = USB_DR_MODE_OTG; 57 58 mode = dwc->dr_mode; 59 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 60 61 switch (hw_mode) { 62 case DWC3_GHWPARAMS0_MODE_GADGET: 63 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) { 64 dev_err(dev, 65 "Controller does not support host mode.\n"); 66 return -EINVAL; 67 } 68 mode = USB_DR_MODE_PERIPHERAL; 69 break; 70 case DWC3_GHWPARAMS0_MODE_HOST: 71 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { 72 dev_err(dev, 73 "Controller does not support device mode.\n"); 74 return -EINVAL; 75 } 76 mode = USB_DR_MODE_HOST; 77 break; 78 default: 79 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 80 mode = USB_DR_MODE_HOST; 81 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 82 mode = USB_DR_MODE_PERIPHERAL; 83 84 /* 85 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG 86 * mode. If the controller supports DRD but the dr_mode is not 87 * specified or set to OTG, then set the mode to peripheral. 88 */ 89 if (mode == USB_DR_MODE_OTG && !dwc->edev && 90 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) || 91 !device_property_read_bool(dwc->dev, "usb-role-switch")) && 92 !DWC3_VER_IS_PRIOR(DWC3, 330A)) 93 mode = USB_DR_MODE_PERIPHERAL; 94 } 95 96 if (mode != dwc->dr_mode) { 97 dev_warn(dev, 98 "Configuration mismatch. dr_mode forced to %s\n", 99 mode == USB_DR_MODE_HOST ? "host" : "gadget"); 100 101 dwc->dr_mode = mode; 102 } 103 104 return 0; 105 } 106 107 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) 108 { 109 u32 reg; 110 111 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 112 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 113 reg |= DWC3_GCTL_PRTCAPDIR(mode); 114 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 115 116 dwc->current_dr_role = mode; 117 } 118 119 static void __dwc3_set_mode(struct work_struct *work) 120 { 121 struct dwc3 *dwc = work_to_dwc(work); 122 unsigned long flags; 123 int ret; 124 u32 reg; 125 u32 desired_dr_role; 126 127 mutex_lock(&dwc->mutex); 128 spin_lock_irqsave(&dwc->lock, flags); 129 desired_dr_role = dwc->desired_dr_role; 130 spin_unlock_irqrestore(&dwc->lock, flags); 131 132 pm_runtime_get_sync(dwc->dev); 133 134 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG) 135 dwc3_otg_update(dwc, 0); 136 137 if (!desired_dr_role) 138 goto out; 139 140 if (desired_dr_role == dwc->current_dr_role) 141 goto out; 142 143 if (desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev) 144 goto out; 145 146 switch (dwc->current_dr_role) { 147 case DWC3_GCTL_PRTCAP_HOST: 148 dwc3_host_exit(dwc); 149 break; 150 case DWC3_GCTL_PRTCAP_DEVICE: 151 dwc3_gadget_exit(dwc); 152 dwc3_event_buffers_cleanup(dwc); 153 break; 154 case DWC3_GCTL_PRTCAP_OTG: 155 dwc3_otg_exit(dwc); 156 spin_lock_irqsave(&dwc->lock, flags); 157 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE; 158 spin_unlock_irqrestore(&dwc->lock, flags); 159 dwc3_otg_update(dwc, 1); 160 break; 161 default: 162 break; 163 } 164 165 /* 166 * When current_dr_role is not set, there's no role switching. 167 * Only perform GCTL.CoreSoftReset when there's DRD role switching. 168 */ 169 if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) || 170 DWC3_VER_IS_PRIOR(DWC31, 190A)) && 171 desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) { 172 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 173 reg |= DWC3_GCTL_CORESOFTRESET; 174 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 175 176 /* 177 * Wait for internal clocks to synchronized. DWC_usb31 and 178 * DWC_usb32 may need at least 50ms (less for DWC_usb3). To 179 * keep it consistent across different IPs, let's wait up to 180 * 100ms before clearing GCTL.CORESOFTRESET. 181 */ 182 msleep(100); 183 184 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 185 reg &= ~DWC3_GCTL_CORESOFTRESET; 186 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 187 } 188 189 spin_lock_irqsave(&dwc->lock, flags); 190 191 dwc3_set_prtcap(dwc, desired_dr_role); 192 193 spin_unlock_irqrestore(&dwc->lock, flags); 194 195 switch (desired_dr_role) { 196 case DWC3_GCTL_PRTCAP_HOST: 197 ret = dwc3_host_init(dwc); 198 if (ret) { 199 dev_err(dwc->dev, "failed to initialize host\n"); 200 } else { 201 if (dwc->usb2_phy) 202 otg_set_vbus(dwc->usb2_phy->otg, true); 203 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 204 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 205 if (dwc->dis_split_quirk) { 206 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 207 reg |= DWC3_GUCTL3_SPLITDISABLE; 208 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 209 } 210 } 211 break; 212 case DWC3_GCTL_PRTCAP_DEVICE: 213 dwc3_core_soft_reset(dwc); 214 215 dwc3_event_buffers_setup(dwc); 216 217 if (dwc->usb2_phy) 218 otg_set_vbus(dwc->usb2_phy->otg, false); 219 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 220 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 221 222 ret = dwc3_gadget_init(dwc); 223 if (ret) 224 dev_err(dwc->dev, "failed to initialize peripheral\n"); 225 break; 226 case DWC3_GCTL_PRTCAP_OTG: 227 dwc3_otg_init(dwc); 228 dwc3_otg_update(dwc, 0); 229 break; 230 default: 231 break; 232 } 233 234 out: 235 pm_runtime_mark_last_busy(dwc->dev); 236 pm_runtime_put_autosuspend(dwc->dev); 237 mutex_unlock(&dwc->mutex); 238 } 239 240 void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 241 { 242 unsigned long flags; 243 244 if (dwc->dr_mode != USB_DR_MODE_OTG) 245 return; 246 247 spin_lock_irqsave(&dwc->lock, flags); 248 dwc->desired_dr_role = mode; 249 spin_unlock_irqrestore(&dwc->lock, flags); 250 251 queue_work(system_freezable_wq, &dwc->drd_work); 252 } 253 254 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) 255 { 256 struct dwc3 *dwc = dep->dwc; 257 u32 reg; 258 259 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, 260 DWC3_GDBGFIFOSPACE_NUM(dep->number) | 261 DWC3_GDBGFIFOSPACE_TYPE(type)); 262 263 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); 264 265 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); 266 } 267 268 /** 269 * dwc3_core_soft_reset - Issues core soft reset and PHY reset 270 * @dwc: pointer to our context structure 271 */ 272 int dwc3_core_soft_reset(struct dwc3 *dwc) 273 { 274 u32 reg; 275 int retries = 1000; 276 277 /* 278 * We're resetting only the device side because, if we're in host mode, 279 * XHCI driver will reset the host block. If dwc3 was configured for 280 * host-only mode or current role is host, then we can return early. 281 */ 282 if (dwc->dr_mode == USB_DR_MODE_HOST || dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) 283 return 0; 284 285 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 286 reg |= DWC3_DCTL_CSFTRST; 287 reg &= ~DWC3_DCTL_RUN_STOP; 288 dwc3_gadget_dctl_write_safe(dwc, reg); 289 290 /* 291 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit 292 * is cleared only after all the clocks are synchronized. This can 293 * take a little more than 50ms. Set the polling rate at 20ms 294 * for 10 times instead. 295 */ 296 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 297 retries = 10; 298 299 do { 300 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 301 if (!(reg & DWC3_DCTL_CSFTRST)) 302 goto done; 303 304 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 305 msleep(20); 306 else 307 udelay(1); 308 } while (--retries); 309 310 dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n"); 311 return -ETIMEDOUT; 312 313 done: 314 /* 315 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit 316 * is cleared, we must wait at least 50ms before accessing the PHY 317 * domain (synchronization delay). 318 */ 319 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A)) 320 msleep(50); 321 322 return 0; 323 } 324 325 /* 326 * dwc3_frame_length_adjustment - Adjusts frame length if required 327 * @dwc3: Pointer to our controller context structure 328 */ 329 static void dwc3_frame_length_adjustment(struct dwc3 *dwc) 330 { 331 u32 reg; 332 u32 dft; 333 334 if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 335 return; 336 337 if (dwc->fladj == 0) 338 return; 339 340 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 341 dft = reg & DWC3_GFLADJ_30MHZ_MASK; 342 if (dft != dwc->fladj) { 343 reg &= ~DWC3_GFLADJ_30MHZ_MASK; 344 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; 345 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 346 } 347 } 348 349 /** 350 * dwc3_ref_clk_period - Reference clock period configuration 351 * Default reference clock period depends on hardware 352 * configuration. For systems with reference clock that differs 353 * from the default, this will set clock period in DWC3_GUCTL 354 * register. 355 * @dwc: Pointer to our controller context structure 356 */ 357 static void dwc3_ref_clk_period(struct dwc3 *dwc) 358 { 359 unsigned long period; 360 unsigned long fladj; 361 unsigned long decr; 362 unsigned long rate; 363 u32 reg; 364 365 if (dwc->ref_clk) { 366 rate = clk_get_rate(dwc->ref_clk); 367 if (!rate) 368 return; 369 period = NSEC_PER_SEC / rate; 370 } else if (dwc->ref_clk_per) { 371 period = dwc->ref_clk_per; 372 rate = NSEC_PER_SEC / period; 373 } else { 374 return; 375 } 376 377 reg = dwc3_readl(dwc->regs, DWC3_GUCTL); 378 reg &= ~DWC3_GUCTL_REFCLKPER_MASK; 379 reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period); 380 dwc3_writel(dwc->regs, DWC3_GUCTL, reg); 381 382 if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 383 return; 384 385 /* 386 * The calculation below is 387 * 388 * 125000 * (NSEC_PER_SEC / (rate * period) - 1) 389 * 390 * but rearranged for fixed-point arithmetic. The division must be 391 * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and 392 * neither does rate * period). 393 * 394 * Note that rate * period ~= NSEC_PER_SECOND, minus the number of 395 * nanoseconds of error caused by the truncation which happened during 396 * the division when calculating rate or period (whichever one was 397 * derived from the other). We first calculate the relative error, then 398 * scale it to units of 8 ppm. 399 */ 400 fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period); 401 fladj -= 125000; 402 403 /* 404 * The documented 240MHz constant is scaled by 2 to get PLS1 as well. 405 */ 406 decr = 480000000 / rate; 407 408 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 409 reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK 410 & ~DWC3_GFLADJ_240MHZDECR 411 & ~DWC3_GFLADJ_240MHZDECR_PLS1; 412 reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj) 413 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1) 414 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1); 415 416 if (dwc->gfladj_refclk_lpm_sel) 417 reg |= DWC3_GFLADJ_REFCLK_LPM_SEL; 418 419 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 420 } 421 422 /** 423 * dwc3_free_one_event_buffer - Frees one event buffer 424 * @dwc: Pointer to our controller context structure 425 * @evt: Pointer to event buffer to be freed 426 */ 427 static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 428 struct dwc3_event_buffer *evt) 429 { 430 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma); 431 } 432 433 /** 434 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 435 * @dwc: Pointer to our controller context structure 436 * @length: size of the event buffer 437 * 438 * Returns a pointer to the allocated event buffer structure on success 439 * otherwise ERR_PTR(errno). 440 */ 441 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 442 unsigned int length) 443 { 444 struct dwc3_event_buffer *evt; 445 446 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 447 if (!evt) 448 return ERR_PTR(-ENOMEM); 449 450 evt->dwc = dwc; 451 evt->length = length; 452 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL); 453 if (!evt->cache) 454 return ERR_PTR(-ENOMEM); 455 456 evt->buf = dma_alloc_coherent(dwc->sysdev, length, 457 &evt->dma, GFP_KERNEL); 458 if (!evt->buf) 459 return ERR_PTR(-ENOMEM); 460 461 return evt; 462 } 463 464 /** 465 * dwc3_free_event_buffers - frees all allocated event buffers 466 * @dwc: Pointer to our controller context structure 467 */ 468 static void dwc3_free_event_buffers(struct dwc3 *dwc) 469 { 470 struct dwc3_event_buffer *evt; 471 472 evt = dwc->ev_buf; 473 if (evt) 474 dwc3_free_one_event_buffer(dwc, evt); 475 } 476 477 /** 478 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 479 * @dwc: pointer to our controller context structure 480 * @length: size of event buffer 481 * 482 * Returns 0 on success otherwise negative errno. In the error case, dwc 483 * may contain some buffers allocated but not all which were requested. 484 */ 485 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length) 486 { 487 struct dwc3_event_buffer *evt; 488 489 evt = dwc3_alloc_one_event_buffer(dwc, length); 490 if (IS_ERR(evt)) { 491 dev_err(dwc->dev, "can't allocate event buffer\n"); 492 return PTR_ERR(evt); 493 } 494 dwc->ev_buf = evt; 495 496 return 0; 497 } 498 499 /** 500 * dwc3_event_buffers_setup - setup our allocated event buffers 501 * @dwc: pointer to our controller context structure 502 * 503 * Returns 0 on success otherwise negative errno. 504 */ 505 int dwc3_event_buffers_setup(struct dwc3 *dwc) 506 { 507 struct dwc3_event_buffer *evt; 508 509 evt = dwc->ev_buf; 510 evt->lpos = 0; 511 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 512 lower_32_bits(evt->dma)); 513 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 514 upper_32_bits(evt->dma)); 515 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), 516 DWC3_GEVNTSIZ_SIZE(evt->length)); 517 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 518 519 return 0; 520 } 521 522 void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 523 { 524 struct dwc3_event_buffer *evt; 525 526 evt = dwc->ev_buf; 527 528 evt->lpos = 0; 529 530 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); 531 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); 532 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK 533 | DWC3_GEVNTSIZ_SIZE(0)); 534 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 535 } 536 537 static void dwc3_core_num_eps(struct dwc3 *dwc) 538 { 539 struct dwc3_hwparams *parms = &dwc->hwparams; 540 541 dwc->num_eps = DWC3_NUM_EPS(parms); 542 } 543 544 static void dwc3_cache_hwparams(struct dwc3 *dwc) 545 { 546 struct dwc3_hwparams *parms = &dwc->hwparams; 547 548 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 549 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 550 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 551 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 552 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 553 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 554 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 555 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 556 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 557 558 if (DWC3_IP_IS(DWC32)) 559 parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9); 560 } 561 562 static int dwc3_core_ulpi_init(struct dwc3 *dwc) 563 { 564 int intf; 565 int ret = 0; 566 567 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3); 568 569 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI || 570 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI && 571 dwc->hsphy_interface && 572 !strncmp(dwc->hsphy_interface, "ulpi", 4))) 573 ret = dwc3_ulpi_init(dwc); 574 575 return ret; 576 } 577 578 /** 579 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 580 * @dwc: Pointer to our controller context structure 581 * 582 * Returns 0 on success. The USB PHY interfaces are configured but not 583 * initialized. The PHY interfaces and the PHYs get initialized together with 584 * the core in dwc3_core_init. 585 */ 586 static int dwc3_phy_setup(struct dwc3 *dwc) 587 { 588 unsigned int hw_mode; 589 u32 reg; 590 591 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 592 593 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 594 595 /* 596 * Make sure UX_EXIT_PX is cleared as that causes issues with some 597 * PHYs. Also, this bit is not supposed to be used in normal operation. 598 */ 599 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; 600 601 /* 602 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 603 * to '0' during coreConsultant configuration. So default value 604 * will be '0' when the core is reset. Application needs to set it 605 * to '1' after the core initialization is completed. 606 */ 607 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) 608 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 609 610 /* 611 * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after 612 * power-on reset, and it can be set after core initialization, which is 613 * after device soft-reset during initialization. 614 */ 615 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 616 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 617 618 if (dwc->u2ss_inp3_quirk) 619 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 620 621 if (dwc->dis_rxdet_inp3_quirk) 622 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; 623 624 if (dwc->req_p1p2p3_quirk) 625 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 626 627 if (dwc->del_p1p2p3_quirk) 628 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 629 630 if (dwc->del_phy_power_chg_quirk) 631 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 632 633 if (dwc->lfps_filter_quirk) 634 reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 635 636 if (dwc->rx_detect_poll_quirk) 637 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 638 639 if (dwc->tx_de_emphasis_quirk) 640 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 641 642 if (dwc->dis_u3_susphy_quirk) 643 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 644 645 if (dwc->dis_del_phy_power_chg_quirk) 646 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; 647 648 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 649 650 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 651 652 /* Select the HS PHY interface */ 653 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { 654 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: 655 if (dwc->hsphy_interface && 656 !strncmp(dwc->hsphy_interface, "utmi", 4)) { 657 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; 658 break; 659 } else if (dwc->hsphy_interface && 660 !strncmp(dwc->hsphy_interface, "ulpi", 4)) { 661 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; 662 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 663 } else { 664 /* Relying on default value. */ 665 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) 666 break; 667 } 668 fallthrough; 669 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: 670 default: 671 break; 672 } 673 674 switch (dwc->hsphy_mode) { 675 case USBPHY_INTERFACE_MODE_UTMI: 676 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 677 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 678 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | 679 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); 680 break; 681 case USBPHY_INTERFACE_MODE_UTMIW: 682 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 683 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 684 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | 685 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 686 break; 687 default: 688 break; 689 } 690 691 /* 692 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 693 * '0' during coreConsultant configuration. So default value will 694 * be '0' when the core is reset. Application needs to set it to 695 * '1' after the core initialization is completed. 696 */ 697 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) 698 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 699 700 /* 701 * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after 702 * power-on reset, and it can be set after core initialization, which is 703 * after device soft-reset during initialization. 704 */ 705 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 706 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 707 708 if (dwc->dis_u2_susphy_quirk) 709 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 710 711 if (dwc->dis_enblslpm_quirk) 712 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 713 else 714 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM; 715 716 if (dwc->dis_u2_freeclk_exists_quirk || dwc->gfladj_refclk_lpm_sel) 717 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 718 719 /* 720 * Some ULPI USB PHY does not support internal VBUS supply, to drive 721 * the CPEN pin requires the configuration of the ULPI DRVVBUSEXTERNAL 722 * bit of OTG_CTRL register. Controller configures the USB2 PHY 723 * ULPIEXTVBUSDRV bit[17] of the GUSB2PHYCFG register to drive vBus 724 * with an external supply. 725 */ 726 if (dwc->ulpi_ext_vbus_drv) 727 reg |= DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV; 728 729 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 730 731 return 0; 732 } 733 734 static int dwc3_phy_init(struct dwc3 *dwc) 735 { 736 int ret; 737 738 usb_phy_init(dwc->usb2_phy); 739 usb_phy_init(dwc->usb3_phy); 740 741 ret = phy_init(dwc->usb2_generic_phy); 742 if (ret < 0) 743 goto err_shutdown_usb3_phy; 744 745 ret = phy_init(dwc->usb3_generic_phy); 746 if (ret < 0) 747 goto err_exit_usb2_phy; 748 749 return 0; 750 751 err_exit_usb2_phy: 752 phy_exit(dwc->usb2_generic_phy); 753 err_shutdown_usb3_phy: 754 usb_phy_shutdown(dwc->usb3_phy); 755 usb_phy_shutdown(dwc->usb2_phy); 756 757 return ret; 758 } 759 760 static void dwc3_phy_exit(struct dwc3 *dwc) 761 { 762 phy_exit(dwc->usb3_generic_phy); 763 phy_exit(dwc->usb2_generic_phy); 764 765 usb_phy_shutdown(dwc->usb3_phy); 766 usb_phy_shutdown(dwc->usb2_phy); 767 } 768 769 static int dwc3_phy_power_on(struct dwc3 *dwc) 770 { 771 int ret; 772 773 usb_phy_set_suspend(dwc->usb2_phy, 0); 774 usb_phy_set_suspend(dwc->usb3_phy, 0); 775 776 ret = phy_power_on(dwc->usb2_generic_phy); 777 if (ret < 0) 778 goto err_suspend_usb3_phy; 779 780 ret = phy_power_on(dwc->usb3_generic_phy); 781 if (ret < 0) 782 goto err_power_off_usb2_phy; 783 784 return 0; 785 786 err_power_off_usb2_phy: 787 phy_power_off(dwc->usb2_generic_phy); 788 err_suspend_usb3_phy: 789 usb_phy_set_suspend(dwc->usb3_phy, 1); 790 usb_phy_set_suspend(dwc->usb2_phy, 1); 791 792 return ret; 793 } 794 795 static void dwc3_phy_power_off(struct dwc3 *dwc) 796 { 797 phy_power_off(dwc->usb3_generic_phy); 798 phy_power_off(dwc->usb2_generic_phy); 799 800 usb_phy_set_suspend(dwc->usb3_phy, 1); 801 usb_phy_set_suspend(dwc->usb2_phy, 1); 802 } 803 804 static int dwc3_clk_enable(struct dwc3 *dwc) 805 { 806 int ret; 807 808 ret = clk_prepare_enable(dwc->bus_clk); 809 if (ret) 810 return ret; 811 812 ret = clk_prepare_enable(dwc->ref_clk); 813 if (ret) 814 goto disable_bus_clk; 815 816 ret = clk_prepare_enable(dwc->susp_clk); 817 if (ret) 818 goto disable_ref_clk; 819 820 return 0; 821 822 disable_ref_clk: 823 clk_disable_unprepare(dwc->ref_clk); 824 disable_bus_clk: 825 clk_disable_unprepare(dwc->bus_clk); 826 return ret; 827 } 828 829 static void dwc3_clk_disable(struct dwc3 *dwc) 830 { 831 clk_disable_unprepare(dwc->susp_clk); 832 clk_disable_unprepare(dwc->ref_clk); 833 clk_disable_unprepare(dwc->bus_clk); 834 } 835 836 static void dwc3_core_exit(struct dwc3 *dwc) 837 { 838 dwc3_event_buffers_cleanup(dwc); 839 dwc3_phy_power_off(dwc); 840 dwc3_phy_exit(dwc); 841 dwc3_clk_disable(dwc); 842 reset_control_assert(dwc->reset); 843 } 844 845 static bool dwc3_core_is_valid(struct dwc3 *dwc) 846 { 847 u32 reg; 848 849 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 850 dwc->ip = DWC3_GSNPS_ID(reg); 851 852 /* This should read as U3 followed by revision number */ 853 if (DWC3_IP_IS(DWC3)) { 854 dwc->revision = reg; 855 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) { 856 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); 857 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE); 858 } else { 859 return false; 860 } 861 862 return true; 863 } 864 865 static void dwc3_core_setup_global_control(struct dwc3 *dwc) 866 { 867 u32 reg; 868 869 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 870 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 871 872 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 873 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 874 /** 875 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 876 * issue which would cause xHCI compliance tests to fail. 877 * 878 * Because of that we cannot enable clock gating on such 879 * configurations. 880 * 881 * Refers to: 882 * 883 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 884 * SOF/ITP Mode Used 885 */ 886 if ((dwc->dr_mode == USB_DR_MODE_HOST || 887 dwc->dr_mode == USB_DR_MODE_OTG) && 888 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A)) 889 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 890 else 891 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 892 break; 893 case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 894 /* 895 * REVISIT Enabling this bit so that host-mode hibernation 896 * will work. Device-mode hibernation is not yet implemented. 897 */ 898 reg |= DWC3_GCTL_GBLHIBERNATIONEN; 899 break; 900 default: 901 /* nothing */ 902 break; 903 } 904 905 /* check if current dwc3 is on simulation board */ 906 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 907 dev_info(dwc->dev, "Running with FPGA optimizations\n"); 908 dwc->is_fpga = true; 909 } 910 911 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, 912 "disable_scramble cannot be used on non-FPGA builds\n"); 913 914 if (dwc->disable_scramble_quirk && dwc->is_fpga) 915 reg |= DWC3_GCTL_DISSCRAMBLE; 916 else 917 reg &= ~DWC3_GCTL_DISSCRAMBLE; 918 919 if (dwc->u2exit_lfps_quirk) 920 reg |= DWC3_GCTL_U2EXIT_LFPS; 921 922 /* 923 * WORKAROUND: DWC3 revisions <1.90a have a bug 924 * where the device can fail to connect at SuperSpeed 925 * and falls back to high-speed mode which causes 926 * the device to enter a Connect/Disconnect loop 927 */ 928 if (DWC3_VER_IS_PRIOR(DWC3, 190A)) 929 reg |= DWC3_GCTL_U2RSTECN; 930 931 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 932 } 933 934 static int dwc3_core_get_phy(struct dwc3 *dwc); 935 static int dwc3_core_ulpi_init(struct dwc3 *dwc); 936 937 /* set global incr burst type configuration registers */ 938 static void dwc3_set_incr_burst_type(struct dwc3 *dwc) 939 { 940 struct device *dev = dwc->dev; 941 /* incrx_mode : for INCR burst type. */ 942 bool incrx_mode; 943 /* incrx_size : for size of INCRX burst. */ 944 u32 incrx_size; 945 u32 *vals; 946 u32 cfg; 947 int ntype; 948 int ret; 949 int i; 950 951 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); 952 953 /* 954 * Handle property "snps,incr-burst-type-adjustment". 955 * Get the number of value from this property: 956 * result <= 0, means this property is not supported. 957 * result = 1, means INCRx burst mode supported. 958 * result > 1, means undefined length burst mode supported. 959 */ 960 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment"); 961 if (ntype <= 0) 962 return; 963 964 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL); 965 if (!vals) 966 return; 967 968 /* Get INCR burst type, and parse it */ 969 ret = device_property_read_u32_array(dev, 970 "snps,incr-burst-type-adjustment", vals, ntype); 971 if (ret) { 972 kfree(vals); 973 dev_err(dev, "Error to get property\n"); 974 return; 975 } 976 977 incrx_size = *vals; 978 979 if (ntype > 1) { 980 /* INCRX (undefined length) burst mode */ 981 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE; 982 for (i = 1; i < ntype; i++) { 983 if (vals[i] > incrx_size) 984 incrx_size = vals[i]; 985 } 986 } else { 987 /* INCRX burst mode */ 988 incrx_mode = INCRX_BURST_MODE; 989 } 990 991 kfree(vals); 992 993 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */ 994 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK; 995 if (incrx_mode) 996 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA; 997 switch (incrx_size) { 998 case 256: 999 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA; 1000 break; 1001 case 128: 1002 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA; 1003 break; 1004 case 64: 1005 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA; 1006 break; 1007 case 32: 1008 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA; 1009 break; 1010 case 16: 1011 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA; 1012 break; 1013 case 8: 1014 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA; 1015 break; 1016 case 4: 1017 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA; 1018 break; 1019 case 1: 1020 break; 1021 default: 1022 dev_err(dev, "Invalid property\n"); 1023 break; 1024 } 1025 1026 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg); 1027 } 1028 1029 static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc) 1030 { 1031 u32 scale; 1032 u32 reg; 1033 1034 if (!dwc->susp_clk) 1035 return; 1036 1037 /* 1038 * The power down scale field specifies how many suspend_clk 1039 * periods fit into a 16KHz clock period. When performing 1040 * the division, round up the remainder. 1041 * 1042 * The power down scale value is calculated using the fastest 1043 * frequency of the suspend_clk. If it isn't fixed (but within 1044 * the accuracy requirement), the driver may not know the max 1045 * rate of the suspend_clk, so only update the power down scale 1046 * if the default is less than the calculated value from 1047 * clk_get_rate() or if the default is questionably high 1048 * (3x or more) to be within the requirement. 1049 */ 1050 scale = DIV_ROUND_UP(clk_get_rate(dwc->susp_clk), 16000); 1051 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 1052 if ((reg & DWC3_GCTL_PWRDNSCALE_MASK) < DWC3_GCTL_PWRDNSCALE(scale) || 1053 (reg & DWC3_GCTL_PWRDNSCALE_MASK) > DWC3_GCTL_PWRDNSCALE(scale*3)) { 1054 reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK); 1055 reg |= DWC3_GCTL_PWRDNSCALE(scale); 1056 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 1057 } 1058 } 1059 1060 /** 1061 * dwc3_core_init - Low-level initialization of DWC3 Core 1062 * @dwc: Pointer to our controller context structure 1063 * 1064 * Returns 0 on success otherwise negative errno. 1065 */ 1066 static int dwc3_core_init(struct dwc3 *dwc) 1067 { 1068 unsigned int hw_mode; 1069 u32 reg; 1070 int ret; 1071 1072 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 1073 1074 /* 1075 * Write Linux Version Code to our GUID register so it's easy to figure 1076 * out which kernel version a bug was found. 1077 */ 1078 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); 1079 1080 ret = dwc3_phy_setup(dwc); 1081 if (ret) 1082 return ret; 1083 1084 if (!dwc->ulpi_ready) { 1085 ret = dwc3_core_ulpi_init(dwc); 1086 if (ret) { 1087 if (ret == -ETIMEDOUT) { 1088 dwc3_core_soft_reset(dwc); 1089 ret = -EPROBE_DEFER; 1090 } 1091 return ret; 1092 } 1093 dwc->ulpi_ready = true; 1094 } 1095 1096 if (!dwc->phys_ready) { 1097 ret = dwc3_core_get_phy(dwc); 1098 if (ret) 1099 goto err_exit_ulpi; 1100 dwc->phys_ready = true; 1101 } 1102 1103 ret = dwc3_phy_init(dwc); 1104 if (ret) 1105 goto err_exit_ulpi; 1106 1107 ret = dwc3_core_soft_reset(dwc); 1108 if (ret) 1109 goto err_exit_phy; 1110 1111 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD && 1112 !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) { 1113 if (!dwc->dis_u3_susphy_quirk) { 1114 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 1115 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 1116 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 1117 } 1118 1119 if (!dwc->dis_u2_susphy_quirk) { 1120 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1121 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 1122 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1123 } 1124 } 1125 1126 dwc3_core_setup_global_control(dwc); 1127 dwc3_core_num_eps(dwc); 1128 1129 /* Set power down scale of suspend_clk */ 1130 dwc3_set_power_down_clk_scale(dwc); 1131 1132 /* Adjust Frame Length */ 1133 dwc3_frame_length_adjustment(dwc); 1134 1135 /* Adjust Reference Clock Period */ 1136 dwc3_ref_clk_period(dwc); 1137 1138 dwc3_set_incr_burst_type(dwc); 1139 1140 ret = dwc3_phy_power_on(dwc); 1141 if (ret) 1142 goto err_exit_phy; 1143 1144 ret = dwc3_event_buffers_setup(dwc); 1145 if (ret) { 1146 dev_err(dwc->dev, "failed to setup event buffers\n"); 1147 goto err_power_off_phy; 1148 } 1149 1150 /* 1151 * ENDXFER polling is available on version 3.10a and later of 1152 * the DWC_usb3 controller. It is NOT available in the 1153 * DWC_usb31 controller. 1154 */ 1155 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) { 1156 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); 1157 reg |= DWC3_GUCTL2_RST_ACTBITLATER; 1158 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); 1159 } 1160 1161 /* 1162 * When configured in HOST mode, after issuing U3/L2 exit controller 1163 * fails to send proper CRC checksum in CRC5 feild. Because of this 1164 * behaviour Transaction Error is generated, resulting in reset and 1165 * re-enumeration of usb device attached. All the termsel, xcvrsel, 1166 * opmode becomes 0 during end of resume. Enabling bit 10 of GUCTL1 1167 * will correct this problem. This option is to support certain 1168 * legacy ULPI PHYs. 1169 */ 1170 if (dwc->resume_hs_terminations) { 1171 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 1172 reg |= DWC3_GUCTL1_RESUME_OPMODE_HS_HOST; 1173 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 1174 } 1175 1176 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) { 1177 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 1178 1179 /* 1180 * Enable hardware control of sending remote wakeup 1181 * in HS when the device is in the L1 state. 1182 */ 1183 if (!DWC3_VER_IS_PRIOR(DWC3, 290A)) 1184 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; 1185 1186 /* 1187 * Decouple USB 2.0 L1 & L2 events which will allow for 1188 * gadget driver to only receive U3/L2 suspend & wakeup 1189 * events and prevent the more frequent L1 LPM transitions 1190 * from interrupting the driver. 1191 */ 1192 if (!DWC3_VER_IS_PRIOR(DWC3, 300A)) 1193 reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT; 1194 1195 if (dwc->dis_tx_ipgap_linecheck_quirk) 1196 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; 1197 1198 if (dwc->parkmode_disable_ss_quirk) 1199 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS; 1200 1201 if (dwc->parkmode_disable_hs_quirk) 1202 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_HS; 1203 1204 if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) && 1205 (dwc->maximum_speed == USB_SPEED_HIGH || 1206 dwc->maximum_speed == USB_SPEED_FULL)) 1207 reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; 1208 1209 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 1210 } 1211 1212 /* 1213 * Must config both number of packets and max burst settings to enable 1214 * RX and/or TX threshold. 1215 */ 1216 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) { 1217 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd; 1218 u8 rx_maxburst = dwc->rx_max_burst_prd; 1219 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd; 1220 u8 tx_maxburst = dwc->tx_max_burst_prd; 1221 1222 if (rx_thr_num && rx_maxburst) { 1223 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1224 reg |= DWC31_RXTHRNUMPKTSEL_PRD; 1225 1226 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0); 1227 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num); 1228 1229 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0); 1230 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst); 1231 1232 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1233 } 1234 1235 if (tx_thr_num && tx_maxburst) { 1236 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1237 reg |= DWC31_TXTHRNUMPKTSEL_PRD; 1238 1239 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0); 1240 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num); 1241 1242 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0); 1243 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst); 1244 1245 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1246 } 1247 } 1248 1249 return 0; 1250 1251 err_power_off_phy: 1252 dwc3_phy_power_off(dwc); 1253 err_exit_phy: 1254 dwc3_phy_exit(dwc); 1255 err_exit_ulpi: 1256 dwc3_ulpi_exit(dwc); 1257 1258 return ret; 1259 } 1260 1261 static int dwc3_core_get_phy(struct dwc3 *dwc) 1262 { 1263 struct device *dev = dwc->dev; 1264 struct device_node *node = dev->of_node; 1265 int ret; 1266 1267 if (node) { 1268 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); 1269 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); 1270 } else { 1271 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 1272 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); 1273 } 1274 1275 if (IS_ERR(dwc->usb2_phy)) { 1276 ret = PTR_ERR(dwc->usb2_phy); 1277 if (ret == -ENXIO || ret == -ENODEV) 1278 dwc->usb2_phy = NULL; 1279 else 1280 return dev_err_probe(dev, ret, "no usb2 phy configured\n"); 1281 } 1282 1283 if (IS_ERR(dwc->usb3_phy)) { 1284 ret = PTR_ERR(dwc->usb3_phy); 1285 if (ret == -ENXIO || ret == -ENODEV) 1286 dwc->usb3_phy = NULL; 1287 else 1288 return dev_err_probe(dev, ret, "no usb3 phy configured\n"); 1289 } 1290 1291 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); 1292 if (IS_ERR(dwc->usb2_generic_phy)) { 1293 ret = PTR_ERR(dwc->usb2_generic_phy); 1294 if (ret == -ENOSYS || ret == -ENODEV) 1295 dwc->usb2_generic_phy = NULL; 1296 else 1297 return dev_err_probe(dev, ret, "no usb2 phy configured\n"); 1298 } 1299 1300 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); 1301 if (IS_ERR(dwc->usb3_generic_phy)) { 1302 ret = PTR_ERR(dwc->usb3_generic_phy); 1303 if (ret == -ENOSYS || ret == -ENODEV) 1304 dwc->usb3_generic_phy = NULL; 1305 else 1306 return dev_err_probe(dev, ret, "no usb3 phy configured\n"); 1307 } 1308 1309 return 0; 1310 } 1311 1312 static int dwc3_core_init_mode(struct dwc3 *dwc) 1313 { 1314 struct device *dev = dwc->dev; 1315 int ret; 1316 1317 switch (dwc->dr_mode) { 1318 case USB_DR_MODE_PERIPHERAL: 1319 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1320 1321 if (dwc->usb2_phy) 1322 otg_set_vbus(dwc->usb2_phy->otg, false); 1323 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 1324 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 1325 1326 ret = dwc3_gadget_init(dwc); 1327 if (ret) 1328 return dev_err_probe(dev, ret, "failed to initialize gadget\n"); 1329 break; 1330 case USB_DR_MODE_HOST: 1331 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1332 1333 if (dwc->usb2_phy) 1334 otg_set_vbus(dwc->usb2_phy->otg, true); 1335 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 1336 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 1337 1338 ret = dwc3_host_init(dwc); 1339 if (ret) 1340 return dev_err_probe(dev, ret, "failed to initialize host\n"); 1341 break; 1342 case USB_DR_MODE_OTG: 1343 INIT_WORK(&dwc->drd_work, __dwc3_set_mode); 1344 ret = dwc3_drd_init(dwc); 1345 if (ret) 1346 return dev_err_probe(dev, ret, "failed to initialize dual-role\n"); 1347 break; 1348 default: 1349 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 1350 return -EINVAL; 1351 } 1352 1353 return 0; 1354 } 1355 1356 static void dwc3_core_exit_mode(struct dwc3 *dwc) 1357 { 1358 switch (dwc->dr_mode) { 1359 case USB_DR_MODE_PERIPHERAL: 1360 dwc3_gadget_exit(dwc); 1361 break; 1362 case USB_DR_MODE_HOST: 1363 dwc3_host_exit(dwc); 1364 break; 1365 case USB_DR_MODE_OTG: 1366 dwc3_drd_exit(dwc); 1367 break; 1368 default: 1369 /* do nothing */ 1370 break; 1371 } 1372 1373 /* de-assert DRVVBUS for HOST and OTG mode */ 1374 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1375 } 1376 1377 static void dwc3_get_properties(struct dwc3 *dwc) 1378 { 1379 struct device *dev = dwc->dev; 1380 u8 lpm_nyet_threshold; 1381 u8 tx_de_emphasis; 1382 u8 hird_threshold; 1383 u8 rx_thr_num_pkt_prd = 0; 1384 u8 rx_max_burst_prd = 0; 1385 u8 tx_thr_num_pkt_prd = 0; 1386 u8 tx_max_burst_prd = 0; 1387 u8 tx_fifo_resize_max_num; 1388 const char *usb_psy_name; 1389 int ret; 1390 1391 /* default to highest possible threshold */ 1392 lpm_nyet_threshold = 0xf; 1393 1394 /* default to -3.5dB de-emphasis */ 1395 tx_de_emphasis = 1; 1396 1397 /* 1398 * default to assert utmi_sleep_n and use maximum allowed HIRD 1399 * threshold value of 0b1100 1400 */ 1401 hird_threshold = 12; 1402 1403 /* 1404 * default to a TXFIFO size large enough to fit 6 max packets. This 1405 * allows for systems with larger bus latencies to have some headroom 1406 * for endpoints that have a large bMaxBurst value. 1407 */ 1408 tx_fifo_resize_max_num = 6; 1409 1410 dwc->maximum_speed = usb_get_maximum_speed(dev); 1411 dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev); 1412 dwc->dr_mode = usb_get_dr_mode(dev); 1413 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); 1414 1415 dwc->sysdev_is_parent = device_property_read_bool(dev, 1416 "linux,sysdev_is_parent"); 1417 if (dwc->sysdev_is_parent) 1418 dwc->sysdev = dwc->dev->parent; 1419 else 1420 dwc->sysdev = dwc->dev; 1421 1422 ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name); 1423 if (ret >= 0) { 1424 dwc->usb_psy = power_supply_get_by_name(usb_psy_name); 1425 if (!dwc->usb_psy) 1426 dev_err(dev, "couldn't get usb power supply\n"); 1427 } 1428 1429 dwc->has_lpm_erratum = device_property_read_bool(dev, 1430 "snps,has-lpm-erratum"); 1431 device_property_read_u8(dev, "snps,lpm-nyet-threshold", 1432 &lpm_nyet_threshold); 1433 dwc->is_utmi_l1_suspend = device_property_read_bool(dev, 1434 "snps,is-utmi-l1-suspend"); 1435 device_property_read_u8(dev, "snps,hird-threshold", 1436 &hird_threshold); 1437 dwc->dis_start_transfer_quirk = device_property_read_bool(dev, 1438 "snps,dis-start-transfer-quirk"); 1439 dwc->usb3_lpm_capable = device_property_read_bool(dev, 1440 "snps,usb3_lpm_capable"); 1441 dwc->usb2_lpm_disable = device_property_read_bool(dev, 1442 "snps,usb2-lpm-disable"); 1443 dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev, 1444 "snps,usb2-gadget-lpm-disable"); 1445 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd", 1446 &rx_thr_num_pkt_prd); 1447 device_property_read_u8(dev, "snps,rx-max-burst-prd", 1448 &rx_max_burst_prd); 1449 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd", 1450 &tx_thr_num_pkt_prd); 1451 device_property_read_u8(dev, "snps,tx-max-burst-prd", 1452 &tx_max_burst_prd); 1453 dwc->do_fifo_resize = device_property_read_bool(dev, 1454 "tx-fifo-resize"); 1455 if (dwc->do_fifo_resize) 1456 device_property_read_u8(dev, "tx-fifo-max-num", 1457 &tx_fifo_resize_max_num); 1458 1459 dwc->disable_scramble_quirk = device_property_read_bool(dev, 1460 "snps,disable_scramble_quirk"); 1461 dwc->u2exit_lfps_quirk = device_property_read_bool(dev, 1462 "snps,u2exit_lfps_quirk"); 1463 dwc->u2ss_inp3_quirk = device_property_read_bool(dev, 1464 "snps,u2ss_inp3_quirk"); 1465 dwc->req_p1p2p3_quirk = device_property_read_bool(dev, 1466 "snps,req_p1p2p3_quirk"); 1467 dwc->del_p1p2p3_quirk = device_property_read_bool(dev, 1468 "snps,del_p1p2p3_quirk"); 1469 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, 1470 "snps,del_phy_power_chg_quirk"); 1471 dwc->lfps_filter_quirk = device_property_read_bool(dev, 1472 "snps,lfps_filter_quirk"); 1473 dwc->rx_detect_poll_quirk = device_property_read_bool(dev, 1474 "snps,rx_detect_poll_quirk"); 1475 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, 1476 "snps,dis_u3_susphy_quirk"); 1477 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, 1478 "snps,dis_u2_susphy_quirk"); 1479 dwc->dis_enblslpm_quirk = device_property_read_bool(dev, 1480 "snps,dis_enblslpm_quirk"); 1481 dwc->dis_u1_entry_quirk = device_property_read_bool(dev, 1482 "snps,dis-u1-entry-quirk"); 1483 dwc->dis_u2_entry_quirk = device_property_read_bool(dev, 1484 "snps,dis-u2-entry-quirk"); 1485 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, 1486 "snps,dis_rxdet_inp3_quirk"); 1487 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, 1488 "snps,dis-u2-freeclk-exists-quirk"); 1489 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, 1490 "snps,dis-del-phy-power-chg-quirk"); 1491 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev, 1492 "snps,dis-tx-ipgap-linecheck-quirk"); 1493 dwc->resume_hs_terminations = device_property_read_bool(dev, 1494 "snps,resume-hs-terminations"); 1495 dwc->ulpi_ext_vbus_drv = device_property_read_bool(dev, 1496 "snps,ulpi-ext-vbus-drv"); 1497 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev, 1498 "snps,parkmode-disable-ss-quirk"); 1499 dwc->parkmode_disable_hs_quirk = device_property_read_bool(dev, 1500 "snps,parkmode-disable-hs-quirk"); 1501 dwc->gfladj_refclk_lpm_sel = device_property_read_bool(dev, 1502 "snps,gfladj-refclk-lpm-sel-quirk"); 1503 1504 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, 1505 "snps,tx_de_emphasis_quirk"); 1506 device_property_read_u8(dev, "snps,tx_de_emphasis", 1507 &tx_de_emphasis); 1508 device_property_read_string(dev, "snps,hsphy_interface", 1509 &dwc->hsphy_interface); 1510 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", 1511 &dwc->fladj); 1512 device_property_read_u32(dev, "snps,ref-clock-period-ns", 1513 &dwc->ref_clk_per); 1514 1515 dwc->dis_metastability_quirk = device_property_read_bool(dev, 1516 "snps,dis_metastability_quirk"); 1517 1518 dwc->dis_split_quirk = device_property_read_bool(dev, 1519 "snps,dis-split-quirk"); 1520 1521 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 1522 dwc->tx_de_emphasis = tx_de_emphasis; 1523 1524 dwc->hird_threshold = hird_threshold; 1525 1526 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd; 1527 dwc->rx_max_burst_prd = rx_max_burst_prd; 1528 1529 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd; 1530 dwc->tx_max_burst_prd = tx_max_burst_prd; 1531 1532 dwc->imod_interval = 0; 1533 1534 dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num; 1535 } 1536 1537 /* check whether the core supports IMOD */ 1538 bool dwc3_has_imod(struct dwc3 *dwc) 1539 { 1540 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) || 1541 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) || 1542 DWC3_IP_IS(DWC32); 1543 } 1544 1545 static void dwc3_check_params(struct dwc3 *dwc) 1546 { 1547 struct device *dev = dwc->dev; 1548 unsigned int hwparam_gen = 1549 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3); 1550 1551 /* Check for proper value of imod_interval */ 1552 if (dwc->imod_interval && !dwc3_has_imod(dwc)) { 1553 dev_warn(dwc->dev, "Interrupt moderation not supported\n"); 1554 dwc->imod_interval = 0; 1555 } 1556 1557 /* 1558 * Workaround for STAR 9000961433 which affects only version 1559 * 3.00a of the DWC_usb3 core. This prevents the controller 1560 * interrupt from being masked while handling events. IMOD 1561 * allows us to work around this issue. Enable it for the 1562 * affected version. 1563 */ 1564 if (!dwc->imod_interval && 1565 DWC3_VER_IS(DWC3, 300A)) 1566 dwc->imod_interval = 1; 1567 1568 /* Check the maximum_speed parameter */ 1569 switch (dwc->maximum_speed) { 1570 case USB_SPEED_FULL: 1571 case USB_SPEED_HIGH: 1572 break; 1573 case USB_SPEED_SUPER: 1574 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) 1575 dev_warn(dev, "UDC doesn't support Gen 1\n"); 1576 break; 1577 case USB_SPEED_SUPER_PLUS: 1578 if ((DWC3_IP_IS(DWC32) && 1579 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) || 1580 (!DWC3_IP_IS(DWC32) && 1581 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) 1582 dev_warn(dev, "UDC doesn't support SSP\n"); 1583 break; 1584 default: 1585 dev_err(dev, "invalid maximum_speed parameter %d\n", 1586 dwc->maximum_speed); 1587 fallthrough; 1588 case USB_SPEED_UNKNOWN: 1589 switch (hwparam_gen) { 1590 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 1591 dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1592 break; 1593 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 1594 if (DWC3_IP_IS(DWC32)) 1595 dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1596 else 1597 dwc->maximum_speed = USB_SPEED_SUPER; 1598 break; 1599 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS: 1600 dwc->maximum_speed = USB_SPEED_HIGH; 1601 break; 1602 default: 1603 dwc->maximum_speed = USB_SPEED_SUPER; 1604 break; 1605 } 1606 break; 1607 } 1608 1609 /* 1610 * Currently the controller does not have visibility into the HW 1611 * parameter to determine the maximum number of lanes the HW supports. 1612 * If the number of lanes is not specified in the device property, then 1613 * set the default to support dual-lane for DWC_usb32 and single-lane 1614 * for DWC_usb31 for super-speed-plus. 1615 */ 1616 if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) { 1617 switch (dwc->max_ssp_rate) { 1618 case USB_SSP_GEN_2x1: 1619 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1) 1620 dev_warn(dev, "UDC only supports Gen 1\n"); 1621 break; 1622 case USB_SSP_GEN_1x2: 1623 case USB_SSP_GEN_2x2: 1624 if (DWC3_IP_IS(DWC31)) 1625 dev_warn(dev, "UDC only supports single lane\n"); 1626 break; 1627 case USB_SSP_GEN_UNKNOWN: 1628 default: 1629 switch (hwparam_gen) { 1630 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 1631 if (DWC3_IP_IS(DWC32)) 1632 dwc->max_ssp_rate = USB_SSP_GEN_2x2; 1633 else 1634 dwc->max_ssp_rate = USB_SSP_GEN_2x1; 1635 break; 1636 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 1637 if (DWC3_IP_IS(DWC32)) 1638 dwc->max_ssp_rate = USB_SSP_GEN_1x2; 1639 break; 1640 } 1641 break; 1642 } 1643 } 1644 } 1645 1646 static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc) 1647 { 1648 struct device *dev = dwc->dev; 1649 struct device_node *np_phy; 1650 struct extcon_dev *edev = NULL; 1651 const char *name; 1652 1653 if (device_property_read_bool(dev, "extcon")) 1654 return extcon_get_edev_by_phandle(dev, 0); 1655 1656 /* 1657 * Device tree platforms should get extcon via phandle. 1658 * On ACPI platforms, we get the name from a device property. 1659 * This device property is for kernel internal use only and 1660 * is expected to be set by the glue code. 1661 */ 1662 if (device_property_read_string(dev, "linux,extcon-name", &name) == 0) 1663 return extcon_get_extcon_dev(name); 1664 1665 /* 1666 * Check explicitly if "usb-role-switch" is used since 1667 * extcon_find_edev_by_node() can not be used to check the absence of 1668 * an extcon device. In the absence of an device it will always return 1669 * EPROBE_DEFER. 1670 */ 1671 if (IS_ENABLED(CONFIG_USB_ROLE_SWITCH) && 1672 device_property_read_bool(dev, "usb-role-switch")) 1673 return NULL; 1674 1675 /* 1676 * Try to get an extcon device from the USB PHY controller's "port" 1677 * node. Check if it has the "port" node first, to avoid printing the 1678 * error message from underlying code, as it's a valid case: extcon 1679 * device (and "port" node) may be missing in case of "usb-role-switch" 1680 * or OTG mode. 1681 */ 1682 np_phy = of_parse_phandle(dev->of_node, "phys", 0); 1683 if (of_graph_is_present(np_phy)) { 1684 struct device_node *np_conn; 1685 1686 np_conn = of_graph_get_remote_node(np_phy, -1, -1); 1687 if (np_conn) 1688 edev = extcon_find_edev_by_node(np_conn); 1689 of_node_put(np_conn); 1690 } 1691 of_node_put(np_phy); 1692 1693 return edev; 1694 } 1695 1696 static int dwc3_get_clocks(struct dwc3 *dwc) 1697 { 1698 struct device *dev = dwc->dev; 1699 1700 if (!dev->of_node) 1701 return 0; 1702 1703 /* 1704 * Clocks are optional, but new DT platforms should support all clocks 1705 * as required by the DT-binding. 1706 * Some devices have different clock names in legacy device trees, 1707 * check for them to retain backwards compatibility. 1708 */ 1709 dwc->bus_clk = devm_clk_get_optional(dev, "bus_early"); 1710 if (IS_ERR(dwc->bus_clk)) { 1711 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk), 1712 "could not get bus clock\n"); 1713 } 1714 1715 if (dwc->bus_clk == NULL) { 1716 dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk"); 1717 if (IS_ERR(dwc->bus_clk)) { 1718 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk), 1719 "could not get bus clock\n"); 1720 } 1721 } 1722 1723 dwc->ref_clk = devm_clk_get_optional(dev, "ref"); 1724 if (IS_ERR(dwc->ref_clk)) { 1725 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk), 1726 "could not get ref clock\n"); 1727 } 1728 1729 if (dwc->ref_clk == NULL) { 1730 dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk"); 1731 if (IS_ERR(dwc->ref_clk)) { 1732 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk), 1733 "could not get ref clock\n"); 1734 } 1735 } 1736 1737 dwc->susp_clk = devm_clk_get_optional(dev, "suspend"); 1738 if (IS_ERR(dwc->susp_clk)) { 1739 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk), 1740 "could not get suspend clock\n"); 1741 } 1742 1743 if (dwc->susp_clk == NULL) { 1744 dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk"); 1745 if (IS_ERR(dwc->susp_clk)) { 1746 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk), 1747 "could not get suspend clock\n"); 1748 } 1749 } 1750 1751 return 0; 1752 } 1753 1754 static int dwc3_probe(struct platform_device *pdev) 1755 { 1756 struct device *dev = &pdev->dev; 1757 struct resource *res, dwc_res; 1758 void __iomem *regs; 1759 struct dwc3 *dwc; 1760 int ret; 1761 1762 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 1763 if (!dwc) 1764 return -ENOMEM; 1765 1766 dwc->dev = dev; 1767 1768 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1769 if (!res) { 1770 dev_err(dev, "missing memory resource\n"); 1771 return -ENODEV; 1772 } 1773 1774 dwc->xhci_resources[0].start = res->start; 1775 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + 1776 DWC3_XHCI_REGS_END; 1777 dwc->xhci_resources[0].flags = res->flags; 1778 dwc->xhci_resources[0].name = res->name; 1779 1780 /* 1781 * Request memory region but exclude xHCI regs, 1782 * since it will be requested by the xhci-plat driver. 1783 */ 1784 dwc_res = *res; 1785 dwc_res.start += DWC3_GLOBALS_REGS_START; 1786 1787 if (dev->of_node) { 1788 struct device_node *parent = of_get_parent(dev->of_node); 1789 1790 if (of_device_is_compatible(parent, "realtek,rtd-dwc3")) { 1791 dwc_res.start -= DWC3_GLOBALS_REGS_START; 1792 dwc_res.start += DWC3_RTK_RTD_GLOBALS_REGS_START; 1793 } 1794 1795 of_node_put(parent); 1796 } 1797 1798 regs = devm_ioremap_resource(dev, &dwc_res); 1799 if (IS_ERR(regs)) 1800 return PTR_ERR(regs); 1801 1802 dwc->regs = regs; 1803 dwc->regs_size = resource_size(&dwc_res); 1804 1805 dwc3_get_properties(dwc); 1806 1807 dwc->reset = devm_reset_control_array_get_optional_shared(dev); 1808 if (IS_ERR(dwc->reset)) { 1809 ret = PTR_ERR(dwc->reset); 1810 goto err_put_psy; 1811 } 1812 1813 ret = dwc3_get_clocks(dwc); 1814 if (ret) 1815 goto err_put_psy; 1816 1817 ret = reset_control_deassert(dwc->reset); 1818 if (ret) 1819 goto err_put_psy; 1820 1821 ret = dwc3_clk_enable(dwc); 1822 if (ret) 1823 goto err_assert_reset; 1824 1825 if (!dwc3_core_is_valid(dwc)) { 1826 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 1827 ret = -ENODEV; 1828 goto err_disable_clks; 1829 } 1830 1831 platform_set_drvdata(pdev, dwc); 1832 dwc3_cache_hwparams(dwc); 1833 1834 if (!dwc->sysdev_is_parent && 1835 DWC3_GHWPARAMS0_AWIDTH(dwc->hwparams.hwparams0) == 64) { 1836 ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64)); 1837 if (ret) 1838 goto err_disable_clks; 1839 } 1840 1841 spin_lock_init(&dwc->lock); 1842 mutex_init(&dwc->mutex); 1843 1844 pm_runtime_get_noresume(dev); 1845 pm_runtime_set_active(dev); 1846 pm_runtime_use_autosuspend(dev); 1847 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); 1848 pm_runtime_enable(dev); 1849 1850 pm_runtime_forbid(dev); 1851 1852 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 1853 if (ret) { 1854 dev_err(dwc->dev, "failed to allocate event buffers\n"); 1855 ret = -ENOMEM; 1856 goto err_allow_rpm; 1857 } 1858 1859 dwc->edev = dwc3_get_extcon(dwc); 1860 if (IS_ERR(dwc->edev)) { 1861 ret = dev_err_probe(dwc->dev, PTR_ERR(dwc->edev), "failed to get extcon\n"); 1862 goto err_free_event_buffers; 1863 } 1864 1865 ret = dwc3_get_dr_mode(dwc); 1866 if (ret) 1867 goto err_free_event_buffers; 1868 1869 ret = dwc3_core_init(dwc); 1870 if (ret) { 1871 dev_err_probe(dev, ret, "failed to initialize core\n"); 1872 goto err_free_event_buffers; 1873 } 1874 1875 dwc3_check_params(dwc); 1876 dwc3_debugfs_init(dwc); 1877 1878 ret = dwc3_core_init_mode(dwc); 1879 if (ret) 1880 goto err_exit_debugfs; 1881 1882 pm_runtime_put(dev); 1883 1884 return 0; 1885 1886 err_exit_debugfs: 1887 dwc3_debugfs_exit(dwc); 1888 dwc3_event_buffers_cleanup(dwc); 1889 dwc3_phy_power_off(dwc); 1890 dwc3_phy_exit(dwc); 1891 dwc3_ulpi_exit(dwc); 1892 err_free_event_buffers: 1893 dwc3_free_event_buffers(dwc); 1894 err_allow_rpm: 1895 pm_runtime_allow(dev); 1896 pm_runtime_disable(dev); 1897 pm_runtime_dont_use_autosuspend(dev); 1898 pm_runtime_set_suspended(dev); 1899 pm_runtime_put_noidle(dev); 1900 err_disable_clks: 1901 dwc3_clk_disable(dwc); 1902 err_assert_reset: 1903 reset_control_assert(dwc->reset); 1904 err_put_psy: 1905 if (dwc->usb_psy) 1906 power_supply_put(dwc->usb_psy); 1907 1908 return ret; 1909 } 1910 1911 static void dwc3_remove(struct platform_device *pdev) 1912 { 1913 struct dwc3 *dwc = platform_get_drvdata(pdev); 1914 1915 pm_runtime_get_sync(&pdev->dev); 1916 1917 dwc3_core_exit_mode(dwc); 1918 dwc3_debugfs_exit(dwc); 1919 1920 dwc3_core_exit(dwc); 1921 dwc3_ulpi_exit(dwc); 1922 1923 pm_runtime_allow(&pdev->dev); 1924 pm_runtime_disable(&pdev->dev); 1925 pm_runtime_dont_use_autosuspend(&pdev->dev); 1926 pm_runtime_put_noidle(&pdev->dev); 1927 /* 1928 * HACK: Clear the driver data, which is currently accessed by parent 1929 * glue drivers, before allowing the parent to suspend. 1930 */ 1931 platform_set_drvdata(pdev, NULL); 1932 pm_runtime_set_suspended(&pdev->dev); 1933 1934 dwc3_free_event_buffers(dwc); 1935 1936 if (dwc->usb_psy) 1937 power_supply_put(dwc->usb_psy); 1938 } 1939 1940 #ifdef CONFIG_PM 1941 static int dwc3_core_init_for_resume(struct dwc3 *dwc) 1942 { 1943 int ret; 1944 1945 ret = reset_control_deassert(dwc->reset); 1946 if (ret) 1947 return ret; 1948 1949 ret = dwc3_clk_enable(dwc); 1950 if (ret) 1951 goto assert_reset; 1952 1953 ret = dwc3_core_init(dwc); 1954 if (ret) 1955 goto disable_clks; 1956 1957 return 0; 1958 1959 disable_clks: 1960 dwc3_clk_disable(dwc); 1961 assert_reset: 1962 reset_control_assert(dwc->reset); 1963 1964 return ret; 1965 } 1966 1967 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) 1968 { 1969 unsigned long flags; 1970 u32 reg; 1971 1972 switch (dwc->current_dr_role) { 1973 case DWC3_GCTL_PRTCAP_DEVICE: 1974 if (pm_runtime_suspended(dwc->dev)) 1975 break; 1976 dwc3_gadget_suspend(dwc); 1977 synchronize_irq(dwc->irq_gadget); 1978 dwc3_core_exit(dwc); 1979 break; 1980 case DWC3_GCTL_PRTCAP_HOST: 1981 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) { 1982 dwc3_core_exit(dwc); 1983 break; 1984 } 1985 1986 /* Let controller to suspend HSPHY before PHY driver suspends */ 1987 if (dwc->dis_u2_susphy_quirk || 1988 dwc->dis_enblslpm_quirk) { 1989 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1990 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM | 1991 DWC3_GUSB2PHYCFG_SUSPHY; 1992 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1993 1994 /* Give some time for USB2 PHY to suspend */ 1995 usleep_range(5000, 6000); 1996 } 1997 1998 phy_pm_runtime_put_sync(dwc->usb2_generic_phy); 1999 phy_pm_runtime_put_sync(dwc->usb3_generic_phy); 2000 break; 2001 case DWC3_GCTL_PRTCAP_OTG: 2002 /* do nothing during runtime_suspend */ 2003 if (PMSG_IS_AUTO(msg)) 2004 break; 2005 2006 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 2007 spin_lock_irqsave(&dwc->lock, flags); 2008 dwc3_gadget_suspend(dwc); 2009 spin_unlock_irqrestore(&dwc->lock, flags); 2010 synchronize_irq(dwc->irq_gadget); 2011 } 2012 2013 dwc3_otg_exit(dwc); 2014 dwc3_core_exit(dwc); 2015 break; 2016 default: 2017 /* do nothing */ 2018 break; 2019 } 2020 2021 return 0; 2022 } 2023 2024 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) 2025 { 2026 unsigned long flags; 2027 int ret; 2028 u32 reg; 2029 2030 switch (dwc->current_dr_role) { 2031 case DWC3_GCTL_PRTCAP_DEVICE: 2032 ret = dwc3_core_init_for_resume(dwc); 2033 if (ret) 2034 return ret; 2035 2036 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 2037 dwc3_gadget_resume(dwc); 2038 break; 2039 case DWC3_GCTL_PRTCAP_HOST: 2040 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) { 2041 ret = dwc3_core_init_for_resume(dwc); 2042 if (ret) 2043 return ret; 2044 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 2045 break; 2046 } 2047 /* Restore GUSB2PHYCFG bits that were modified in suspend */ 2048 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 2049 if (dwc->dis_u2_susphy_quirk) 2050 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 2051 2052 if (dwc->dis_enblslpm_quirk) 2053 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 2054 2055 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 2056 2057 phy_pm_runtime_get_sync(dwc->usb2_generic_phy); 2058 phy_pm_runtime_get_sync(dwc->usb3_generic_phy); 2059 break; 2060 case DWC3_GCTL_PRTCAP_OTG: 2061 /* nothing to do on runtime_resume */ 2062 if (PMSG_IS_AUTO(msg)) 2063 break; 2064 2065 ret = dwc3_core_init_for_resume(dwc); 2066 if (ret) 2067 return ret; 2068 2069 dwc3_set_prtcap(dwc, dwc->current_dr_role); 2070 2071 dwc3_otg_init(dwc); 2072 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) { 2073 dwc3_otg_host_init(dwc); 2074 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 2075 spin_lock_irqsave(&dwc->lock, flags); 2076 dwc3_gadget_resume(dwc); 2077 spin_unlock_irqrestore(&dwc->lock, flags); 2078 } 2079 2080 break; 2081 default: 2082 /* do nothing */ 2083 break; 2084 } 2085 2086 return 0; 2087 } 2088 2089 static int dwc3_runtime_checks(struct dwc3 *dwc) 2090 { 2091 switch (dwc->current_dr_role) { 2092 case DWC3_GCTL_PRTCAP_DEVICE: 2093 if (dwc->connected) 2094 return -EBUSY; 2095 break; 2096 case DWC3_GCTL_PRTCAP_HOST: 2097 default: 2098 /* do nothing */ 2099 break; 2100 } 2101 2102 return 0; 2103 } 2104 2105 static int dwc3_runtime_suspend(struct device *dev) 2106 { 2107 struct dwc3 *dwc = dev_get_drvdata(dev); 2108 int ret; 2109 2110 if (dwc3_runtime_checks(dwc)) 2111 return -EBUSY; 2112 2113 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND); 2114 if (ret) 2115 return ret; 2116 2117 return 0; 2118 } 2119 2120 static int dwc3_runtime_resume(struct device *dev) 2121 { 2122 struct dwc3 *dwc = dev_get_drvdata(dev); 2123 int ret; 2124 2125 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME); 2126 if (ret) 2127 return ret; 2128 2129 switch (dwc->current_dr_role) { 2130 case DWC3_GCTL_PRTCAP_DEVICE: 2131 dwc3_gadget_process_pending_events(dwc); 2132 break; 2133 case DWC3_GCTL_PRTCAP_HOST: 2134 default: 2135 /* do nothing */ 2136 break; 2137 } 2138 2139 pm_runtime_mark_last_busy(dev); 2140 2141 return 0; 2142 } 2143 2144 static int dwc3_runtime_idle(struct device *dev) 2145 { 2146 struct dwc3 *dwc = dev_get_drvdata(dev); 2147 2148 switch (dwc->current_dr_role) { 2149 case DWC3_GCTL_PRTCAP_DEVICE: 2150 if (dwc3_runtime_checks(dwc)) 2151 return -EBUSY; 2152 break; 2153 case DWC3_GCTL_PRTCAP_HOST: 2154 default: 2155 /* do nothing */ 2156 break; 2157 } 2158 2159 pm_runtime_mark_last_busy(dev); 2160 pm_runtime_autosuspend(dev); 2161 2162 return 0; 2163 } 2164 #endif /* CONFIG_PM */ 2165 2166 #ifdef CONFIG_PM_SLEEP 2167 static int dwc3_suspend(struct device *dev) 2168 { 2169 struct dwc3 *dwc = dev_get_drvdata(dev); 2170 int ret; 2171 2172 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND); 2173 if (ret) 2174 return ret; 2175 2176 pinctrl_pm_select_sleep_state(dev); 2177 2178 return 0; 2179 } 2180 2181 static int dwc3_resume(struct device *dev) 2182 { 2183 struct dwc3 *dwc = dev_get_drvdata(dev); 2184 int ret; 2185 2186 pinctrl_pm_select_default_state(dev); 2187 2188 ret = dwc3_resume_common(dwc, PMSG_RESUME); 2189 if (ret) 2190 return ret; 2191 2192 pm_runtime_disable(dev); 2193 pm_runtime_set_active(dev); 2194 pm_runtime_enable(dev); 2195 2196 return 0; 2197 } 2198 2199 static void dwc3_complete(struct device *dev) 2200 { 2201 struct dwc3 *dwc = dev_get_drvdata(dev); 2202 u32 reg; 2203 2204 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST && 2205 dwc->dis_split_quirk) { 2206 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 2207 reg |= DWC3_GUCTL3_SPLITDISABLE; 2208 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 2209 } 2210 } 2211 #else 2212 #define dwc3_complete NULL 2213 #endif /* CONFIG_PM_SLEEP */ 2214 2215 static const struct dev_pm_ops dwc3_dev_pm_ops = { 2216 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) 2217 .complete = dwc3_complete, 2218 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, 2219 dwc3_runtime_idle) 2220 }; 2221 2222 #ifdef CONFIG_OF 2223 static const struct of_device_id of_dwc3_match[] = { 2224 { 2225 .compatible = "snps,dwc3" 2226 }, 2227 { 2228 .compatible = "synopsys,dwc3" 2229 }, 2230 { }, 2231 }; 2232 MODULE_DEVICE_TABLE(of, of_dwc3_match); 2233 #endif 2234 2235 #ifdef CONFIG_ACPI 2236 2237 #define ACPI_ID_INTEL_BSW "808622B7" 2238 2239 static const struct acpi_device_id dwc3_acpi_match[] = { 2240 { ACPI_ID_INTEL_BSW, 0 }, 2241 { }, 2242 }; 2243 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); 2244 #endif 2245 2246 static struct platform_driver dwc3_driver = { 2247 .probe = dwc3_probe, 2248 .remove_new = dwc3_remove, 2249 .driver = { 2250 .name = "dwc3", 2251 .of_match_table = of_match_ptr(of_dwc3_match), 2252 .acpi_match_table = ACPI_PTR(dwc3_acpi_match), 2253 .pm = &dwc3_dev_pm_ops, 2254 }, 2255 }; 2256 2257 module_platform_driver(dwc3_driver); 2258 2259 MODULE_ALIAS("platform:dwc3"); 2260 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 2261 MODULE_LICENSE("GPL v2"); 2262 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 2263