1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * core.c - DesignWare USB3 DRD Controller Core file 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/version.h> 13 #include <linux/module.h> 14 #include <linux/kernel.h> 15 #include <linux/slab.h> 16 #include <linux/spinlock.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/interrupt.h> 20 #include <linux/ioport.h> 21 #include <linux/io.h> 22 #include <linux/list.h> 23 #include <linux/delay.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/of.h> 26 #include <linux/acpi.h> 27 #include <linux/pinctrl/consumer.h> 28 #include <linux/reset.h> 29 30 #include <linux/usb/ch9.h> 31 #include <linux/usb/gadget.h> 32 #include <linux/usb/of.h> 33 #include <linux/usb/otg.h> 34 35 #include "core.h" 36 #include "gadget.h" 37 #include "io.h" 38 39 #include "debug.h" 40 41 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ 42 43 /** 44 * dwc3_get_dr_mode - Validates and sets dr_mode 45 * @dwc: pointer to our context structure 46 */ 47 static int dwc3_get_dr_mode(struct dwc3 *dwc) 48 { 49 enum usb_dr_mode mode; 50 struct device *dev = dwc->dev; 51 unsigned int hw_mode; 52 53 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 54 dwc->dr_mode = USB_DR_MODE_OTG; 55 56 mode = dwc->dr_mode; 57 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 58 59 switch (hw_mode) { 60 case DWC3_GHWPARAMS0_MODE_GADGET: 61 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) { 62 dev_err(dev, 63 "Controller does not support host mode.\n"); 64 return -EINVAL; 65 } 66 mode = USB_DR_MODE_PERIPHERAL; 67 break; 68 case DWC3_GHWPARAMS0_MODE_HOST: 69 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { 70 dev_err(dev, 71 "Controller does not support device mode.\n"); 72 return -EINVAL; 73 } 74 mode = USB_DR_MODE_HOST; 75 break; 76 default: 77 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 78 mode = USB_DR_MODE_HOST; 79 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 80 mode = USB_DR_MODE_PERIPHERAL; 81 82 /* 83 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG 84 * mode. If the controller supports DRD but the dr_mode is not 85 * specified or set to OTG, then set the mode to peripheral. 86 */ 87 if (mode == USB_DR_MODE_OTG && 88 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) || 89 !device_property_read_bool(dwc->dev, "usb-role-switch")) && 90 !DWC3_VER_IS_PRIOR(DWC3, 330A)) 91 mode = USB_DR_MODE_PERIPHERAL; 92 } 93 94 if (mode != dwc->dr_mode) { 95 dev_warn(dev, 96 "Configuration mismatch. dr_mode forced to %s\n", 97 mode == USB_DR_MODE_HOST ? "host" : "gadget"); 98 99 dwc->dr_mode = mode; 100 } 101 102 return 0; 103 } 104 105 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) 106 { 107 u32 reg; 108 109 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 110 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 111 reg |= DWC3_GCTL_PRTCAPDIR(mode); 112 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 113 114 dwc->current_dr_role = mode; 115 } 116 117 static void __dwc3_set_mode(struct work_struct *work) 118 { 119 struct dwc3 *dwc = work_to_dwc(work); 120 unsigned long flags; 121 int ret; 122 u32 reg; 123 124 pm_runtime_get_sync(dwc->dev); 125 126 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG) 127 dwc3_otg_update(dwc, 0); 128 129 if (!dwc->desired_dr_role) 130 goto out; 131 132 if (dwc->desired_dr_role == dwc->current_dr_role) 133 goto out; 134 135 if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev) 136 goto out; 137 138 switch (dwc->current_dr_role) { 139 case DWC3_GCTL_PRTCAP_HOST: 140 dwc3_host_exit(dwc); 141 break; 142 case DWC3_GCTL_PRTCAP_DEVICE: 143 dwc3_gadget_exit(dwc); 144 dwc3_event_buffers_cleanup(dwc); 145 break; 146 case DWC3_GCTL_PRTCAP_OTG: 147 dwc3_otg_exit(dwc); 148 spin_lock_irqsave(&dwc->lock, flags); 149 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE; 150 spin_unlock_irqrestore(&dwc->lock, flags); 151 dwc3_otg_update(dwc, 1); 152 break; 153 default: 154 break; 155 } 156 157 spin_lock_irqsave(&dwc->lock, flags); 158 159 dwc3_set_prtcap(dwc, dwc->desired_dr_role); 160 161 spin_unlock_irqrestore(&dwc->lock, flags); 162 163 switch (dwc->desired_dr_role) { 164 case DWC3_GCTL_PRTCAP_HOST: 165 ret = dwc3_host_init(dwc); 166 if (ret) { 167 dev_err(dwc->dev, "failed to initialize host\n"); 168 } else { 169 if (dwc->usb2_phy) 170 otg_set_vbus(dwc->usb2_phy->otg, true); 171 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 172 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 173 if (dwc->dis_split_quirk) { 174 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 175 reg |= DWC3_GUCTL3_SPLITDISABLE; 176 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 177 } 178 } 179 break; 180 case DWC3_GCTL_PRTCAP_DEVICE: 181 dwc3_event_buffers_setup(dwc); 182 183 if (dwc->usb2_phy) 184 otg_set_vbus(dwc->usb2_phy->otg, false); 185 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 186 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 187 188 ret = dwc3_gadget_init(dwc); 189 if (ret) 190 dev_err(dwc->dev, "failed to initialize peripheral\n"); 191 break; 192 case DWC3_GCTL_PRTCAP_OTG: 193 dwc3_otg_init(dwc); 194 dwc3_otg_update(dwc, 0); 195 break; 196 default: 197 break; 198 } 199 200 out: 201 pm_runtime_mark_last_busy(dwc->dev); 202 pm_runtime_put_autosuspend(dwc->dev); 203 } 204 205 void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 206 { 207 unsigned long flags; 208 209 if (dwc->dr_mode != USB_DR_MODE_OTG) 210 return; 211 212 spin_lock_irqsave(&dwc->lock, flags); 213 dwc->desired_dr_role = mode; 214 spin_unlock_irqrestore(&dwc->lock, flags); 215 216 queue_work(system_freezable_wq, &dwc->drd_work); 217 } 218 219 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) 220 { 221 struct dwc3 *dwc = dep->dwc; 222 u32 reg; 223 224 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, 225 DWC3_GDBGFIFOSPACE_NUM(dep->number) | 226 DWC3_GDBGFIFOSPACE_TYPE(type)); 227 228 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); 229 230 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); 231 } 232 233 /** 234 * dwc3_core_soft_reset - Issues core soft reset and PHY reset 235 * @dwc: pointer to our context structure 236 */ 237 static int dwc3_core_soft_reset(struct dwc3 *dwc) 238 { 239 u32 reg; 240 int retries = 1000; 241 int ret; 242 243 usb_phy_init(dwc->usb2_phy); 244 usb_phy_init(dwc->usb3_phy); 245 ret = phy_init(dwc->usb2_generic_phy); 246 if (ret < 0) 247 return ret; 248 249 ret = phy_init(dwc->usb3_generic_phy); 250 if (ret < 0) { 251 phy_exit(dwc->usb2_generic_phy); 252 return ret; 253 } 254 255 /* 256 * We're resetting only the device side because, if we're in host mode, 257 * XHCI driver will reset the host block. If dwc3 was configured for 258 * host-only mode, then we can return early. 259 */ 260 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) 261 return 0; 262 263 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 264 reg |= DWC3_DCTL_CSFTRST; 265 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 266 267 /* 268 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit 269 * is cleared only after all the clocks are synchronized. This can 270 * take a little more than 50ms. Set the polling rate at 20ms 271 * for 10 times instead. 272 */ 273 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 274 retries = 10; 275 276 do { 277 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 278 if (!(reg & DWC3_DCTL_CSFTRST)) 279 goto done; 280 281 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 282 msleep(20); 283 else 284 udelay(1); 285 } while (--retries); 286 287 phy_exit(dwc->usb3_generic_phy); 288 phy_exit(dwc->usb2_generic_phy); 289 290 return -ETIMEDOUT; 291 292 done: 293 /* 294 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit 295 * is cleared, we must wait at least 50ms before accessing the PHY 296 * domain (synchronization delay). 297 */ 298 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A)) 299 msleep(50); 300 301 return 0; 302 } 303 304 /* 305 * dwc3_frame_length_adjustment - Adjusts frame length if required 306 * @dwc3: Pointer to our controller context structure 307 */ 308 static void dwc3_frame_length_adjustment(struct dwc3 *dwc) 309 { 310 u32 reg; 311 u32 dft; 312 313 if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 314 return; 315 316 if (dwc->fladj == 0) 317 return; 318 319 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 320 dft = reg & DWC3_GFLADJ_30MHZ_MASK; 321 if (dft != dwc->fladj) { 322 reg &= ~DWC3_GFLADJ_30MHZ_MASK; 323 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; 324 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 325 } 326 } 327 328 /** 329 * dwc3_free_one_event_buffer - Frees one event buffer 330 * @dwc: Pointer to our controller context structure 331 * @evt: Pointer to event buffer to be freed 332 */ 333 static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 334 struct dwc3_event_buffer *evt) 335 { 336 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma); 337 } 338 339 /** 340 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 341 * @dwc: Pointer to our controller context structure 342 * @length: size of the event buffer 343 * 344 * Returns a pointer to the allocated event buffer structure on success 345 * otherwise ERR_PTR(errno). 346 */ 347 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 348 unsigned length) 349 { 350 struct dwc3_event_buffer *evt; 351 352 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 353 if (!evt) 354 return ERR_PTR(-ENOMEM); 355 356 evt->dwc = dwc; 357 evt->length = length; 358 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL); 359 if (!evt->cache) 360 return ERR_PTR(-ENOMEM); 361 362 evt->buf = dma_alloc_coherent(dwc->sysdev, length, 363 &evt->dma, GFP_KERNEL); 364 if (!evt->buf) 365 return ERR_PTR(-ENOMEM); 366 367 return evt; 368 } 369 370 /** 371 * dwc3_free_event_buffers - frees all allocated event buffers 372 * @dwc: Pointer to our controller context structure 373 */ 374 static void dwc3_free_event_buffers(struct dwc3 *dwc) 375 { 376 struct dwc3_event_buffer *evt; 377 378 evt = dwc->ev_buf; 379 if (evt) 380 dwc3_free_one_event_buffer(dwc, evt); 381 } 382 383 /** 384 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 385 * @dwc: pointer to our controller context structure 386 * @length: size of event buffer 387 * 388 * Returns 0 on success otherwise negative errno. In the error case, dwc 389 * may contain some buffers allocated but not all which were requested. 390 */ 391 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) 392 { 393 struct dwc3_event_buffer *evt; 394 395 evt = dwc3_alloc_one_event_buffer(dwc, length); 396 if (IS_ERR(evt)) { 397 dev_err(dwc->dev, "can't allocate event buffer\n"); 398 return PTR_ERR(evt); 399 } 400 dwc->ev_buf = evt; 401 402 return 0; 403 } 404 405 /** 406 * dwc3_event_buffers_setup - setup our allocated event buffers 407 * @dwc: pointer to our controller context structure 408 * 409 * Returns 0 on success otherwise negative errno. 410 */ 411 int dwc3_event_buffers_setup(struct dwc3 *dwc) 412 { 413 struct dwc3_event_buffer *evt; 414 415 evt = dwc->ev_buf; 416 evt->lpos = 0; 417 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 418 lower_32_bits(evt->dma)); 419 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 420 upper_32_bits(evt->dma)); 421 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), 422 DWC3_GEVNTSIZ_SIZE(evt->length)); 423 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 424 425 return 0; 426 } 427 428 void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 429 { 430 struct dwc3_event_buffer *evt; 431 432 evt = dwc->ev_buf; 433 434 evt->lpos = 0; 435 436 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); 437 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); 438 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK 439 | DWC3_GEVNTSIZ_SIZE(0)); 440 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 441 } 442 443 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) 444 { 445 if (!dwc->has_hibernation) 446 return 0; 447 448 if (!dwc->nr_scratch) 449 return 0; 450 451 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, 452 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); 453 if (!dwc->scratchbuf) 454 return -ENOMEM; 455 456 return 0; 457 } 458 459 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) 460 { 461 dma_addr_t scratch_addr; 462 u32 param; 463 int ret; 464 465 if (!dwc->has_hibernation) 466 return 0; 467 468 if (!dwc->nr_scratch) 469 return 0; 470 471 /* should never fall here */ 472 if (!WARN_ON(dwc->scratchbuf)) 473 return 0; 474 475 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf, 476 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, 477 DMA_BIDIRECTIONAL); 478 if (dma_mapping_error(dwc->sysdev, scratch_addr)) { 479 dev_err(dwc->sysdev, "failed to map scratch buffer\n"); 480 ret = -EFAULT; 481 goto err0; 482 } 483 484 dwc->scratch_addr = scratch_addr; 485 486 param = lower_32_bits(scratch_addr); 487 488 ret = dwc3_send_gadget_generic_command(dwc, 489 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); 490 if (ret < 0) 491 goto err1; 492 493 param = upper_32_bits(scratch_addr); 494 495 ret = dwc3_send_gadget_generic_command(dwc, 496 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); 497 if (ret < 0) 498 goto err1; 499 500 return 0; 501 502 err1: 503 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 504 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 505 506 err0: 507 return ret; 508 } 509 510 static void dwc3_free_scratch_buffers(struct dwc3 *dwc) 511 { 512 if (!dwc->has_hibernation) 513 return; 514 515 if (!dwc->nr_scratch) 516 return; 517 518 /* should never fall here */ 519 if (!WARN_ON(dwc->scratchbuf)) 520 return; 521 522 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 523 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 524 kfree(dwc->scratchbuf); 525 } 526 527 static void dwc3_core_num_eps(struct dwc3 *dwc) 528 { 529 struct dwc3_hwparams *parms = &dwc->hwparams; 530 531 dwc->num_eps = DWC3_NUM_EPS(parms); 532 } 533 534 static void dwc3_cache_hwparams(struct dwc3 *dwc) 535 { 536 struct dwc3_hwparams *parms = &dwc->hwparams; 537 538 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 539 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 540 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 541 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 542 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 543 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 544 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 545 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 546 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 547 } 548 549 static int dwc3_core_ulpi_init(struct dwc3 *dwc) 550 { 551 int intf; 552 int ret = 0; 553 554 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3); 555 556 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI || 557 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI && 558 dwc->hsphy_interface && 559 !strncmp(dwc->hsphy_interface, "ulpi", 4))) 560 ret = dwc3_ulpi_init(dwc); 561 562 return ret; 563 } 564 565 /** 566 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 567 * @dwc: Pointer to our controller context structure 568 * 569 * Returns 0 on success. The USB PHY interfaces are configured but not 570 * initialized. The PHY interfaces and the PHYs get initialized together with 571 * the core in dwc3_core_init. 572 */ 573 static int dwc3_phy_setup(struct dwc3 *dwc) 574 { 575 unsigned int hw_mode; 576 u32 reg; 577 578 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 579 580 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 581 582 /* 583 * Make sure UX_EXIT_PX is cleared as that causes issues with some 584 * PHYs. Also, this bit is not supposed to be used in normal operation. 585 */ 586 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; 587 588 /* 589 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 590 * to '0' during coreConsultant configuration. So default value 591 * will be '0' when the core is reset. Application needs to set it 592 * to '1' after the core initialization is completed. 593 */ 594 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) 595 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 596 597 /* 598 * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after 599 * power-on reset, and it can be set after core initialization, which is 600 * after device soft-reset during initialization. 601 */ 602 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 603 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 604 605 if (dwc->u2ss_inp3_quirk) 606 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 607 608 if (dwc->dis_rxdet_inp3_quirk) 609 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; 610 611 if (dwc->req_p1p2p3_quirk) 612 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 613 614 if (dwc->del_p1p2p3_quirk) 615 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 616 617 if (dwc->del_phy_power_chg_quirk) 618 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 619 620 if (dwc->lfps_filter_quirk) 621 reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 622 623 if (dwc->rx_detect_poll_quirk) 624 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 625 626 if (dwc->tx_de_emphasis_quirk) 627 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 628 629 if (dwc->dis_u3_susphy_quirk) 630 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 631 632 if (dwc->dis_del_phy_power_chg_quirk) 633 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; 634 635 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 636 637 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 638 639 /* Select the HS PHY interface */ 640 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { 641 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: 642 if (dwc->hsphy_interface && 643 !strncmp(dwc->hsphy_interface, "utmi", 4)) { 644 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; 645 break; 646 } else if (dwc->hsphy_interface && 647 !strncmp(dwc->hsphy_interface, "ulpi", 4)) { 648 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; 649 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 650 } else { 651 /* Relying on default value. */ 652 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) 653 break; 654 } 655 fallthrough; 656 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: 657 default: 658 break; 659 } 660 661 switch (dwc->hsphy_mode) { 662 case USBPHY_INTERFACE_MODE_UTMI: 663 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 664 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 665 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | 666 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); 667 break; 668 case USBPHY_INTERFACE_MODE_UTMIW: 669 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 670 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 671 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | 672 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 673 break; 674 default: 675 break; 676 } 677 678 /* 679 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 680 * '0' during coreConsultant configuration. So default value will 681 * be '0' when the core is reset. Application needs to set it to 682 * '1' after the core initialization is completed. 683 */ 684 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) 685 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 686 687 /* 688 * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after 689 * power-on reset, and it can be set after core initialization, which is 690 * after device soft-reset during initialization. 691 */ 692 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 693 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 694 695 if (dwc->dis_u2_susphy_quirk) 696 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 697 698 if (dwc->dis_enblslpm_quirk) 699 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 700 else 701 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM; 702 703 if (dwc->dis_u2_freeclk_exists_quirk) 704 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 705 706 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 707 708 return 0; 709 } 710 711 static void dwc3_core_exit(struct dwc3 *dwc) 712 { 713 dwc3_event_buffers_cleanup(dwc); 714 715 usb_phy_shutdown(dwc->usb2_phy); 716 usb_phy_shutdown(dwc->usb3_phy); 717 phy_exit(dwc->usb2_generic_phy); 718 phy_exit(dwc->usb3_generic_phy); 719 720 usb_phy_set_suspend(dwc->usb2_phy, 1); 721 usb_phy_set_suspend(dwc->usb3_phy, 1); 722 phy_power_off(dwc->usb2_generic_phy); 723 phy_power_off(dwc->usb3_generic_phy); 724 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks); 725 reset_control_assert(dwc->reset); 726 } 727 728 static bool dwc3_core_is_valid(struct dwc3 *dwc) 729 { 730 u32 reg; 731 732 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 733 dwc->ip = DWC3_GSNPS_ID(reg); 734 735 /* This should read as U3 followed by revision number */ 736 if (DWC3_IP_IS(DWC3)) { 737 dwc->revision = reg; 738 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) { 739 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); 740 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE); 741 } else { 742 return false; 743 } 744 745 return true; 746 } 747 748 static void dwc3_core_setup_global_control(struct dwc3 *dwc) 749 { 750 u32 hwparams4 = dwc->hwparams.hwparams4; 751 u32 reg; 752 753 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 754 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 755 756 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 757 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 758 /** 759 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 760 * issue which would cause xHCI compliance tests to fail. 761 * 762 * Because of that we cannot enable clock gating on such 763 * configurations. 764 * 765 * Refers to: 766 * 767 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 768 * SOF/ITP Mode Used 769 */ 770 if ((dwc->dr_mode == USB_DR_MODE_HOST || 771 dwc->dr_mode == USB_DR_MODE_OTG) && 772 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A)) 773 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 774 else 775 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 776 break; 777 case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 778 /* enable hibernation here */ 779 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); 780 781 /* 782 * REVISIT Enabling this bit so that host-mode hibernation 783 * will work. Device-mode hibernation is not yet implemented. 784 */ 785 reg |= DWC3_GCTL_GBLHIBERNATIONEN; 786 break; 787 default: 788 /* nothing */ 789 break; 790 } 791 792 /* check if current dwc3 is on simulation board */ 793 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 794 dev_info(dwc->dev, "Running with FPGA optimizations\n"); 795 dwc->is_fpga = true; 796 } 797 798 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, 799 "disable_scramble cannot be used on non-FPGA builds\n"); 800 801 if (dwc->disable_scramble_quirk && dwc->is_fpga) 802 reg |= DWC3_GCTL_DISSCRAMBLE; 803 else 804 reg &= ~DWC3_GCTL_DISSCRAMBLE; 805 806 if (dwc->u2exit_lfps_quirk) 807 reg |= DWC3_GCTL_U2EXIT_LFPS; 808 809 /* 810 * WORKAROUND: DWC3 revisions <1.90a have a bug 811 * where the device can fail to connect at SuperSpeed 812 * and falls back to high-speed mode which causes 813 * the device to enter a Connect/Disconnect loop 814 */ 815 if (DWC3_VER_IS_PRIOR(DWC3, 190A)) 816 reg |= DWC3_GCTL_U2RSTECN; 817 818 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 819 } 820 821 static int dwc3_core_get_phy(struct dwc3 *dwc); 822 static int dwc3_core_ulpi_init(struct dwc3 *dwc); 823 824 /* set global incr burst type configuration registers */ 825 static void dwc3_set_incr_burst_type(struct dwc3 *dwc) 826 { 827 struct device *dev = dwc->dev; 828 /* incrx_mode : for INCR burst type. */ 829 bool incrx_mode; 830 /* incrx_size : for size of INCRX burst. */ 831 u32 incrx_size; 832 u32 *vals; 833 u32 cfg; 834 int ntype; 835 int ret; 836 int i; 837 838 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); 839 840 /* 841 * Handle property "snps,incr-burst-type-adjustment". 842 * Get the number of value from this property: 843 * result <= 0, means this property is not supported. 844 * result = 1, means INCRx burst mode supported. 845 * result > 1, means undefined length burst mode supported. 846 */ 847 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment"); 848 if (ntype <= 0) 849 return; 850 851 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL); 852 if (!vals) { 853 dev_err(dev, "Error to get memory\n"); 854 return; 855 } 856 857 /* Get INCR burst type, and parse it */ 858 ret = device_property_read_u32_array(dev, 859 "snps,incr-burst-type-adjustment", vals, ntype); 860 if (ret) { 861 kfree(vals); 862 dev_err(dev, "Error to get property\n"); 863 return; 864 } 865 866 incrx_size = *vals; 867 868 if (ntype > 1) { 869 /* INCRX (undefined length) burst mode */ 870 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE; 871 for (i = 1; i < ntype; i++) { 872 if (vals[i] > incrx_size) 873 incrx_size = vals[i]; 874 } 875 } else { 876 /* INCRX burst mode */ 877 incrx_mode = INCRX_BURST_MODE; 878 } 879 880 kfree(vals); 881 882 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */ 883 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK; 884 if (incrx_mode) 885 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA; 886 switch (incrx_size) { 887 case 256: 888 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA; 889 break; 890 case 128: 891 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA; 892 break; 893 case 64: 894 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA; 895 break; 896 case 32: 897 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA; 898 break; 899 case 16: 900 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA; 901 break; 902 case 8: 903 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA; 904 break; 905 case 4: 906 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA; 907 break; 908 case 1: 909 break; 910 default: 911 dev_err(dev, "Invalid property\n"); 912 break; 913 } 914 915 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg); 916 } 917 918 /** 919 * dwc3_core_init - Low-level initialization of DWC3 Core 920 * @dwc: Pointer to our controller context structure 921 * 922 * Returns 0 on success otherwise negative errno. 923 */ 924 static int dwc3_core_init(struct dwc3 *dwc) 925 { 926 unsigned int hw_mode; 927 u32 reg; 928 int ret; 929 930 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 931 932 /* 933 * Write Linux Version Code to our GUID register so it's easy to figure 934 * out which kernel version a bug was found. 935 */ 936 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); 937 938 ret = dwc3_phy_setup(dwc); 939 if (ret) 940 goto err0; 941 942 if (!dwc->ulpi_ready) { 943 ret = dwc3_core_ulpi_init(dwc); 944 if (ret) 945 goto err0; 946 dwc->ulpi_ready = true; 947 } 948 949 if (!dwc->phys_ready) { 950 ret = dwc3_core_get_phy(dwc); 951 if (ret) 952 goto err0a; 953 dwc->phys_ready = true; 954 } 955 956 ret = dwc3_core_soft_reset(dwc); 957 if (ret) 958 goto err0a; 959 960 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD && 961 !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) { 962 if (!dwc->dis_u3_susphy_quirk) { 963 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 964 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 965 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 966 } 967 968 if (!dwc->dis_u2_susphy_quirk) { 969 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 970 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 971 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 972 } 973 } 974 975 dwc3_core_setup_global_control(dwc); 976 dwc3_core_num_eps(dwc); 977 978 ret = dwc3_setup_scratch_buffers(dwc); 979 if (ret) 980 goto err1; 981 982 /* Adjust Frame Length */ 983 dwc3_frame_length_adjustment(dwc); 984 985 dwc3_set_incr_burst_type(dwc); 986 987 usb_phy_set_suspend(dwc->usb2_phy, 0); 988 usb_phy_set_suspend(dwc->usb3_phy, 0); 989 ret = phy_power_on(dwc->usb2_generic_phy); 990 if (ret < 0) 991 goto err2; 992 993 ret = phy_power_on(dwc->usb3_generic_phy); 994 if (ret < 0) 995 goto err3; 996 997 ret = dwc3_event_buffers_setup(dwc); 998 if (ret) { 999 dev_err(dwc->dev, "failed to setup event buffers\n"); 1000 goto err4; 1001 } 1002 1003 /* 1004 * ENDXFER polling is available on version 3.10a and later of 1005 * the DWC_usb3 controller. It is NOT available in the 1006 * DWC_usb31 controller. 1007 */ 1008 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) { 1009 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); 1010 reg |= DWC3_GUCTL2_RST_ACTBITLATER; 1011 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); 1012 } 1013 1014 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) { 1015 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 1016 1017 /* 1018 * Enable hardware control of sending remote wakeup 1019 * in HS when the device is in the L1 state. 1020 */ 1021 if (!DWC3_VER_IS_PRIOR(DWC3, 290A)) 1022 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; 1023 1024 if (dwc->dis_tx_ipgap_linecheck_quirk) 1025 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; 1026 1027 if (dwc->parkmode_disable_ss_quirk) 1028 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS; 1029 1030 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 1031 } 1032 1033 if (dwc->dr_mode == USB_DR_MODE_HOST || 1034 dwc->dr_mode == USB_DR_MODE_OTG) { 1035 reg = dwc3_readl(dwc->regs, DWC3_GUCTL); 1036 1037 /* 1038 * Enable Auto retry Feature to make the controller operating in 1039 * Host mode on seeing transaction errors(CRC errors or internal 1040 * overrun scenerios) on IN transfers to reply to the device 1041 * with a non-terminating retry ACK (i.e, an ACK transcation 1042 * packet with Retry=1 & Nump != 0) 1043 */ 1044 reg |= DWC3_GUCTL_HSTINAUTORETRY; 1045 1046 dwc3_writel(dwc->regs, DWC3_GUCTL, reg); 1047 } 1048 1049 /* 1050 * Must config both number of packets and max burst settings to enable 1051 * RX and/or TX threshold. 1052 */ 1053 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) { 1054 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd; 1055 u8 rx_maxburst = dwc->rx_max_burst_prd; 1056 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd; 1057 u8 tx_maxburst = dwc->tx_max_burst_prd; 1058 1059 if (rx_thr_num && rx_maxburst) { 1060 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1061 reg |= DWC31_RXTHRNUMPKTSEL_PRD; 1062 1063 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0); 1064 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num); 1065 1066 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0); 1067 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst); 1068 1069 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1070 } 1071 1072 if (tx_thr_num && tx_maxburst) { 1073 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1074 reg |= DWC31_TXTHRNUMPKTSEL_PRD; 1075 1076 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0); 1077 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num); 1078 1079 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0); 1080 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst); 1081 1082 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1083 } 1084 } 1085 1086 return 0; 1087 1088 err4: 1089 phy_power_off(dwc->usb3_generic_phy); 1090 1091 err3: 1092 phy_power_off(dwc->usb2_generic_phy); 1093 1094 err2: 1095 usb_phy_set_suspend(dwc->usb2_phy, 1); 1096 usb_phy_set_suspend(dwc->usb3_phy, 1); 1097 1098 err1: 1099 usb_phy_shutdown(dwc->usb2_phy); 1100 usb_phy_shutdown(dwc->usb3_phy); 1101 phy_exit(dwc->usb2_generic_phy); 1102 phy_exit(dwc->usb3_generic_phy); 1103 1104 err0a: 1105 dwc3_ulpi_exit(dwc); 1106 1107 err0: 1108 return ret; 1109 } 1110 1111 static int dwc3_core_get_phy(struct dwc3 *dwc) 1112 { 1113 struct device *dev = dwc->dev; 1114 struct device_node *node = dev->of_node; 1115 int ret; 1116 1117 if (node) { 1118 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); 1119 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); 1120 } else { 1121 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 1122 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); 1123 } 1124 1125 if (IS_ERR(dwc->usb2_phy)) { 1126 ret = PTR_ERR(dwc->usb2_phy); 1127 if (ret == -ENXIO || ret == -ENODEV) { 1128 dwc->usb2_phy = NULL; 1129 } else { 1130 return dev_err_probe(dev, ret, "no usb2 phy configured\n"); 1131 } 1132 } 1133 1134 if (IS_ERR(dwc->usb3_phy)) { 1135 ret = PTR_ERR(dwc->usb3_phy); 1136 if (ret == -ENXIO || ret == -ENODEV) { 1137 dwc->usb3_phy = NULL; 1138 } else { 1139 return dev_err_probe(dev, ret, "no usb3 phy configured\n"); 1140 } 1141 } 1142 1143 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); 1144 if (IS_ERR(dwc->usb2_generic_phy)) { 1145 ret = PTR_ERR(dwc->usb2_generic_phy); 1146 if (ret == -ENOSYS || ret == -ENODEV) { 1147 dwc->usb2_generic_phy = NULL; 1148 } else { 1149 return dev_err_probe(dev, ret, "no usb2 phy configured\n"); 1150 } 1151 } 1152 1153 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); 1154 if (IS_ERR(dwc->usb3_generic_phy)) { 1155 ret = PTR_ERR(dwc->usb3_generic_phy); 1156 if (ret == -ENOSYS || ret == -ENODEV) { 1157 dwc->usb3_generic_phy = NULL; 1158 } else { 1159 return dev_err_probe(dev, ret, "no usb3 phy configured\n"); 1160 } 1161 } 1162 1163 return 0; 1164 } 1165 1166 static int dwc3_core_init_mode(struct dwc3 *dwc) 1167 { 1168 struct device *dev = dwc->dev; 1169 int ret; 1170 1171 switch (dwc->dr_mode) { 1172 case USB_DR_MODE_PERIPHERAL: 1173 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1174 1175 if (dwc->usb2_phy) 1176 otg_set_vbus(dwc->usb2_phy->otg, false); 1177 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 1178 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 1179 1180 ret = dwc3_gadget_init(dwc); 1181 if (ret) 1182 return dev_err_probe(dev, ret, "failed to initialize gadget\n"); 1183 break; 1184 case USB_DR_MODE_HOST: 1185 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1186 1187 if (dwc->usb2_phy) 1188 otg_set_vbus(dwc->usb2_phy->otg, true); 1189 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 1190 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 1191 1192 ret = dwc3_host_init(dwc); 1193 if (ret) 1194 return dev_err_probe(dev, ret, "failed to initialize host\n"); 1195 break; 1196 case USB_DR_MODE_OTG: 1197 INIT_WORK(&dwc->drd_work, __dwc3_set_mode); 1198 ret = dwc3_drd_init(dwc); 1199 if (ret) 1200 return dev_err_probe(dev, ret, "failed to initialize dual-role\n"); 1201 break; 1202 default: 1203 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 1204 return -EINVAL; 1205 } 1206 1207 return 0; 1208 } 1209 1210 static void dwc3_core_exit_mode(struct dwc3 *dwc) 1211 { 1212 switch (dwc->dr_mode) { 1213 case USB_DR_MODE_PERIPHERAL: 1214 dwc3_gadget_exit(dwc); 1215 break; 1216 case USB_DR_MODE_HOST: 1217 dwc3_host_exit(dwc); 1218 break; 1219 case USB_DR_MODE_OTG: 1220 dwc3_drd_exit(dwc); 1221 break; 1222 default: 1223 /* do nothing */ 1224 break; 1225 } 1226 1227 /* de-assert DRVVBUS for HOST and OTG mode */ 1228 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1229 } 1230 1231 static void dwc3_get_properties(struct dwc3 *dwc) 1232 { 1233 struct device *dev = dwc->dev; 1234 u8 lpm_nyet_threshold; 1235 u8 tx_de_emphasis; 1236 u8 hird_threshold; 1237 u8 rx_thr_num_pkt_prd; 1238 u8 rx_max_burst_prd; 1239 u8 tx_thr_num_pkt_prd; 1240 u8 tx_max_burst_prd; 1241 1242 /* default to highest possible threshold */ 1243 lpm_nyet_threshold = 0xf; 1244 1245 /* default to -3.5dB de-emphasis */ 1246 tx_de_emphasis = 1; 1247 1248 /* 1249 * default to assert utmi_sleep_n and use maximum allowed HIRD 1250 * threshold value of 0b1100 1251 */ 1252 hird_threshold = 12; 1253 1254 dwc->maximum_speed = usb_get_maximum_speed(dev); 1255 dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev); 1256 dwc->dr_mode = usb_get_dr_mode(dev); 1257 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); 1258 1259 dwc->sysdev_is_parent = device_property_read_bool(dev, 1260 "linux,sysdev_is_parent"); 1261 if (dwc->sysdev_is_parent) 1262 dwc->sysdev = dwc->dev->parent; 1263 else 1264 dwc->sysdev = dwc->dev; 1265 1266 dwc->has_lpm_erratum = device_property_read_bool(dev, 1267 "snps,has-lpm-erratum"); 1268 device_property_read_u8(dev, "snps,lpm-nyet-threshold", 1269 &lpm_nyet_threshold); 1270 dwc->is_utmi_l1_suspend = device_property_read_bool(dev, 1271 "snps,is-utmi-l1-suspend"); 1272 device_property_read_u8(dev, "snps,hird-threshold", 1273 &hird_threshold); 1274 dwc->dis_start_transfer_quirk = device_property_read_bool(dev, 1275 "snps,dis-start-transfer-quirk"); 1276 dwc->usb3_lpm_capable = device_property_read_bool(dev, 1277 "snps,usb3_lpm_capable"); 1278 dwc->usb2_lpm_disable = device_property_read_bool(dev, 1279 "snps,usb2-lpm-disable"); 1280 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd", 1281 &rx_thr_num_pkt_prd); 1282 device_property_read_u8(dev, "snps,rx-max-burst-prd", 1283 &rx_max_burst_prd); 1284 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd", 1285 &tx_thr_num_pkt_prd); 1286 device_property_read_u8(dev, "snps,tx-max-burst-prd", 1287 &tx_max_burst_prd); 1288 1289 dwc->disable_scramble_quirk = device_property_read_bool(dev, 1290 "snps,disable_scramble_quirk"); 1291 dwc->u2exit_lfps_quirk = device_property_read_bool(dev, 1292 "snps,u2exit_lfps_quirk"); 1293 dwc->u2ss_inp3_quirk = device_property_read_bool(dev, 1294 "snps,u2ss_inp3_quirk"); 1295 dwc->req_p1p2p3_quirk = device_property_read_bool(dev, 1296 "snps,req_p1p2p3_quirk"); 1297 dwc->del_p1p2p3_quirk = device_property_read_bool(dev, 1298 "snps,del_p1p2p3_quirk"); 1299 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, 1300 "snps,del_phy_power_chg_quirk"); 1301 dwc->lfps_filter_quirk = device_property_read_bool(dev, 1302 "snps,lfps_filter_quirk"); 1303 dwc->rx_detect_poll_quirk = device_property_read_bool(dev, 1304 "snps,rx_detect_poll_quirk"); 1305 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, 1306 "snps,dis_u3_susphy_quirk"); 1307 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, 1308 "snps,dis_u2_susphy_quirk"); 1309 dwc->dis_enblslpm_quirk = device_property_read_bool(dev, 1310 "snps,dis_enblslpm_quirk"); 1311 dwc->dis_u1_entry_quirk = device_property_read_bool(dev, 1312 "snps,dis-u1-entry-quirk"); 1313 dwc->dis_u2_entry_quirk = device_property_read_bool(dev, 1314 "snps,dis-u2-entry-quirk"); 1315 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, 1316 "snps,dis_rxdet_inp3_quirk"); 1317 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, 1318 "snps,dis-u2-freeclk-exists-quirk"); 1319 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, 1320 "snps,dis-del-phy-power-chg-quirk"); 1321 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev, 1322 "snps,dis-tx-ipgap-linecheck-quirk"); 1323 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev, 1324 "snps,parkmode-disable-ss-quirk"); 1325 1326 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, 1327 "snps,tx_de_emphasis_quirk"); 1328 device_property_read_u8(dev, "snps,tx_de_emphasis", 1329 &tx_de_emphasis); 1330 device_property_read_string(dev, "snps,hsphy_interface", 1331 &dwc->hsphy_interface); 1332 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", 1333 &dwc->fladj); 1334 1335 dwc->dis_metastability_quirk = device_property_read_bool(dev, 1336 "snps,dis_metastability_quirk"); 1337 1338 dwc->dis_split_quirk = device_property_read_bool(dev, 1339 "snps,dis-split-quirk"); 1340 1341 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 1342 dwc->tx_de_emphasis = tx_de_emphasis; 1343 1344 dwc->hird_threshold = hird_threshold; 1345 1346 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd; 1347 dwc->rx_max_burst_prd = rx_max_burst_prd; 1348 1349 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd; 1350 dwc->tx_max_burst_prd = tx_max_burst_prd; 1351 1352 dwc->imod_interval = 0; 1353 } 1354 1355 /* check whether the core supports IMOD */ 1356 bool dwc3_has_imod(struct dwc3 *dwc) 1357 { 1358 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) || 1359 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) || 1360 DWC3_IP_IS(DWC32); 1361 } 1362 1363 static void dwc3_check_params(struct dwc3 *dwc) 1364 { 1365 struct device *dev = dwc->dev; 1366 unsigned int hwparam_gen = 1367 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3); 1368 1369 /* Check for proper value of imod_interval */ 1370 if (dwc->imod_interval && !dwc3_has_imod(dwc)) { 1371 dev_warn(dwc->dev, "Interrupt moderation not supported\n"); 1372 dwc->imod_interval = 0; 1373 } 1374 1375 /* 1376 * Workaround for STAR 9000961433 which affects only version 1377 * 3.00a of the DWC_usb3 core. This prevents the controller 1378 * interrupt from being masked while handling events. IMOD 1379 * allows us to work around this issue. Enable it for the 1380 * affected version. 1381 */ 1382 if (!dwc->imod_interval && 1383 DWC3_VER_IS(DWC3, 300A)) 1384 dwc->imod_interval = 1; 1385 1386 /* Check the maximum_speed parameter */ 1387 switch (dwc->maximum_speed) { 1388 case USB_SPEED_LOW: 1389 case USB_SPEED_FULL: 1390 case USB_SPEED_HIGH: 1391 break; 1392 case USB_SPEED_SUPER: 1393 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) 1394 dev_warn(dev, "UDC doesn't support Gen 1\n"); 1395 break; 1396 case USB_SPEED_SUPER_PLUS: 1397 if ((DWC3_IP_IS(DWC32) && 1398 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) || 1399 (!DWC3_IP_IS(DWC32) && 1400 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) 1401 dev_warn(dev, "UDC doesn't support SSP\n"); 1402 break; 1403 default: 1404 dev_err(dev, "invalid maximum_speed parameter %d\n", 1405 dwc->maximum_speed); 1406 fallthrough; 1407 case USB_SPEED_UNKNOWN: 1408 switch (hwparam_gen) { 1409 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 1410 dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1411 break; 1412 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 1413 if (DWC3_IP_IS(DWC32)) 1414 dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1415 else 1416 dwc->maximum_speed = USB_SPEED_SUPER; 1417 break; 1418 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS: 1419 dwc->maximum_speed = USB_SPEED_HIGH; 1420 break; 1421 default: 1422 dwc->maximum_speed = USB_SPEED_SUPER; 1423 break; 1424 } 1425 break; 1426 } 1427 1428 /* 1429 * Currently the controller does not have visibility into the HW 1430 * parameter to determine the maximum number of lanes the HW supports. 1431 * If the number of lanes is not specified in the device property, then 1432 * set the default to support dual-lane for DWC_usb32 and single-lane 1433 * for DWC_usb31 for super-speed-plus. 1434 */ 1435 if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) { 1436 switch (dwc->max_ssp_rate) { 1437 case USB_SSP_GEN_2x1: 1438 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1) 1439 dev_warn(dev, "UDC only supports Gen 1\n"); 1440 break; 1441 case USB_SSP_GEN_1x2: 1442 case USB_SSP_GEN_2x2: 1443 if (DWC3_IP_IS(DWC31)) 1444 dev_warn(dev, "UDC only supports single lane\n"); 1445 break; 1446 case USB_SSP_GEN_UNKNOWN: 1447 default: 1448 switch (hwparam_gen) { 1449 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 1450 if (DWC3_IP_IS(DWC32)) 1451 dwc->max_ssp_rate = USB_SSP_GEN_2x2; 1452 else 1453 dwc->max_ssp_rate = USB_SSP_GEN_2x1; 1454 break; 1455 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 1456 if (DWC3_IP_IS(DWC32)) 1457 dwc->max_ssp_rate = USB_SSP_GEN_1x2; 1458 break; 1459 } 1460 break; 1461 } 1462 } 1463 } 1464 1465 static int dwc3_probe(struct platform_device *pdev) 1466 { 1467 struct device *dev = &pdev->dev; 1468 struct resource *res, dwc_res; 1469 struct dwc3 *dwc; 1470 1471 int ret; 1472 1473 void __iomem *regs; 1474 1475 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 1476 if (!dwc) 1477 return -ENOMEM; 1478 1479 dwc->dev = dev; 1480 1481 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1482 if (!res) { 1483 dev_err(dev, "missing memory resource\n"); 1484 return -ENODEV; 1485 } 1486 1487 dwc->xhci_resources[0].start = res->start; 1488 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + 1489 DWC3_XHCI_REGS_END; 1490 dwc->xhci_resources[0].flags = res->flags; 1491 dwc->xhci_resources[0].name = res->name; 1492 1493 /* 1494 * Request memory region but exclude xHCI regs, 1495 * since it will be requested by the xhci-plat driver. 1496 */ 1497 dwc_res = *res; 1498 dwc_res.start += DWC3_GLOBALS_REGS_START; 1499 1500 regs = devm_ioremap_resource(dev, &dwc_res); 1501 if (IS_ERR(regs)) 1502 return PTR_ERR(regs); 1503 1504 dwc->regs = regs; 1505 dwc->regs_size = resource_size(&dwc_res); 1506 1507 dwc3_get_properties(dwc); 1508 1509 dwc->reset = devm_reset_control_array_get_optional_shared(dev); 1510 if (IS_ERR(dwc->reset)) 1511 return PTR_ERR(dwc->reset); 1512 1513 if (dev->of_node) { 1514 ret = devm_clk_bulk_get_all(dev, &dwc->clks); 1515 if (ret == -EPROBE_DEFER) 1516 return ret; 1517 /* 1518 * Clocks are optional, but new DT platforms should support all 1519 * clocks as required by the DT-binding. 1520 */ 1521 if (ret < 0) 1522 dwc->num_clks = 0; 1523 else 1524 dwc->num_clks = ret; 1525 1526 } 1527 1528 ret = reset_control_deassert(dwc->reset); 1529 if (ret) 1530 return ret; 1531 1532 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks); 1533 if (ret) 1534 goto assert_reset; 1535 1536 if (!dwc3_core_is_valid(dwc)) { 1537 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 1538 ret = -ENODEV; 1539 goto disable_clks; 1540 } 1541 1542 platform_set_drvdata(pdev, dwc); 1543 dwc3_cache_hwparams(dwc); 1544 1545 spin_lock_init(&dwc->lock); 1546 1547 pm_runtime_set_active(dev); 1548 pm_runtime_use_autosuspend(dev); 1549 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); 1550 pm_runtime_enable(dev); 1551 ret = pm_runtime_get_sync(dev); 1552 if (ret < 0) 1553 goto err1; 1554 1555 pm_runtime_forbid(dev); 1556 1557 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 1558 if (ret) { 1559 dev_err(dwc->dev, "failed to allocate event buffers\n"); 1560 ret = -ENOMEM; 1561 goto err2; 1562 } 1563 1564 ret = dwc3_get_dr_mode(dwc); 1565 if (ret) 1566 goto err3; 1567 1568 ret = dwc3_alloc_scratch_buffers(dwc); 1569 if (ret) 1570 goto err3; 1571 1572 ret = dwc3_core_init(dwc); 1573 if (ret) { 1574 dev_err_probe(dev, ret, "failed to initialize core\n"); 1575 goto err4; 1576 } 1577 1578 dwc3_check_params(dwc); 1579 1580 ret = dwc3_core_init_mode(dwc); 1581 if (ret) 1582 goto err5; 1583 1584 dwc3_debugfs_init(dwc); 1585 pm_runtime_put(dev); 1586 1587 return 0; 1588 1589 err5: 1590 dwc3_event_buffers_cleanup(dwc); 1591 1592 usb_phy_shutdown(dwc->usb2_phy); 1593 usb_phy_shutdown(dwc->usb3_phy); 1594 phy_exit(dwc->usb2_generic_phy); 1595 phy_exit(dwc->usb3_generic_phy); 1596 1597 usb_phy_set_suspend(dwc->usb2_phy, 1); 1598 usb_phy_set_suspend(dwc->usb3_phy, 1); 1599 phy_power_off(dwc->usb2_generic_phy); 1600 phy_power_off(dwc->usb3_generic_phy); 1601 1602 dwc3_ulpi_exit(dwc); 1603 1604 err4: 1605 dwc3_free_scratch_buffers(dwc); 1606 1607 err3: 1608 dwc3_free_event_buffers(dwc); 1609 1610 err2: 1611 pm_runtime_allow(&pdev->dev); 1612 1613 err1: 1614 pm_runtime_put_sync(&pdev->dev); 1615 pm_runtime_disable(&pdev->dev); 1616 1617 disable_clks: 1618 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks); 1619 assert_reset: 1620 reset_control_assert(dwc->reset); 1621 1622 return ret; 1623 } 1624 1625 static int dwc3_remove(struct platform_device *pdev) 1626 { 1627 struct dwc3 *dwc = platform_get_drvdata(pdev); 1628 1629 pm_runtime_get_sync(&pdev->dev); 1630 1631 dwc3_debugfs_exit(dwc); 1632 dwc3_core_exit_mode(dwc); 1633 1634 dwc3_core_exit(dwc); 1635 dwc3_ulpi_exit(dwc); 1636 1637 pm_runtime_disable(&pdev->dev); 1638 pm_runtime_put_noidle(&pdev->dev); 1639 pm_runtime_set_suspended(&pdev->dev); 1640 1641 dwc3_free_event_buffers(dwc); 1642 dwc3_free_scratch_buffers(dwc); 1643 1644 return 0; 1645 } 1646 1647 #ifdef CONFIG_PM 1648 static int dwc3_core_init_for_resume(struct dwc3 *dwc) 1649 { 1650 int ret; 1651 1652 ret = reset_control_deassert(dwc->reset); 1653 if (ret) 1654 return ret; 1655 1656 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks); 1657 if (ret) 1658 goto assert_reset; 1659 1660 ret = dwc3_core_init(dwc); 1661 if (ret) 1662 goto disable_clks; 1663 1664 return 0; 1665 1666 disable_clks: 1667 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks); 1668 assert_reset: 1669 reset_control_assert(dwc->reset); 1670 1671 return ret; 1672 } 1673 1674 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) 1675 { 1676 unsigned long flags; 1677 u32 reg; 1678 1679 switch (dwc->current_dr_role) { 1680 case DWC3_GCTL_PRTCAP_DEVICE: 1681 if (pm_runtime_suspended(dwc->dev)) 1682 break; 1683 spin_lock_irqsave(&dwc->lock, flags); 1684 dwc3_gadget_suspend(dwc); 1685 spin_unlock_irqrestore(&dwc->lock, flags); 1686 synchronize_irq(dwc->irq_gadget); 1687 dwc3_core_exit(dwc); 1688 break; 1689 case DWC3_GCTL_PRTCAP_HOST: 1690 if (!PMSG_IS_AUTO(msg)) { 1691 dwc3_core_exit(dwc); 1692 break; 1693 } 1694 1695 /* Let controller to suspend HSPHY before PHY driver suspends */ 1696 if (dwc->dis_u2_susphy_quirk || 1697 dwc->dis_enblslpm_quirk) { 1698 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1699 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM | 1700 DWC3_GUSB2PHYCFG_SUSPHY; 1701 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1702 1703 /* Give some time for USB2 PHY to suspend */ 1704 usleep_range(5000, 6000); 1705 } 1706 1707 phy_pm_runtime_put_sync(dwc->usb2_generic_phy); 1708 phy_pm_runtime_put_sync(dwc->usb3_generic_phy); 1709 break; 1710 case DWC3_GCTL_PRTCAP_OTG: 1711 /* do nothing during runtime_suspend */ 1712 if (PMSG_IS_AUTO(msg)) 1713 break; 1714 1715 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 1716 spin_lock_irqsave(&dwc->lock, flags); 1717 dwc3_gadget_suspend(dwc); 1718 spin_unlock_irqrestore(&dwc->lock, flags); 1719 synchronize_irq(dwc->irq_gadget); 1720 } 1721 1722 dwc3_otg_exit(dwc); 1723 dwc3_core_exit(dwc); 1724 break; 1725 default: 1726 /* do nothing */ 1727 break; 1728 } 1729 1730 return 0; 1731 } 1732 1733 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) 1734 { 1735 unsigned long flags; 1736 int ret; 1737 u32 reg; 1738 1739 switch (dwc->current_dr_role) { 1740 case DWC3_GCTL_PRTCAP_DEVICE: 1741 ret = dwc3_core_init_for_resume(dwc); 1742 if (ret) 1743 return ret; 1744 1745 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1746 spin_lock_irqsave(&dwc->lock, flags); 1747 dwc3_gadget_resume(dwc); 1748 spin_unlock_irqrestore(&dwc->lock, flags); 1749 break; 1750 case DWC3_GCTL_PRTCAP_HOST: 1751 if (!PMSG_IS_AUTO(msg)) { 1752 ret = dwc3_core_init_for_resume(dwc); 1753 if (ret) 1754 return ret; 1755 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1756 break; 1757 } 1758 /* Restore GUSB2PHYCFG bits that were modified in suspend */ 1759 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1760 if (dwc->dis_u2_susphy_quirk) 1761 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 1762 1763 if (dwc->dis_enblslpm_quirk) 1764 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 1765 1766 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1767 1768 phy_pm_runtime_get_sync(dwc->usb2_generic_phy); 1769 phy_pm_runtime_get_sync(dwc->usb3_generic_phy); 1770 break; 1771 case DWC3_GCTL_PRTCAP_OTG: 1772 /* nothing to do on runtime_resume */ 1773 if (PMSG_IS_AUTO(msg)) 1774 break; 1775 1776 ret = dwc3_core_init_for_resume(dwc); 1777 if (ret) 1778 return ret; 1779 1780 dwc3_set_prtcap(dwc, dwc->current_dr_role); 1781 1782 dwc3_otg_init(dwc); 1783 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) { 1784 dwc3_otg_host_init(dwc); 1785 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 1786 spin_lock_irqsave(&dwc->lock, flags); 1787 dwc3_gadget_resume(dwc); 1788 spin_unlock_irqrestore(&dwc->lock, flags); 1789 } 1790 1791 break; 1792 default: 1793 /* do nothing */ 1794 break; 1795 } 1796 1797 return 0; 1798 } 1799 1800 static int dwc3_runtime_checks(struct dwc3 *dwc) 1801 { 1802 switch (dwc->current_dr_role) { 1803 case DWC3_GCTL_PRTCAP_DEVICE: 1804 if (dwc->connected) 1805 return -EBUSY; 1806 break; 1807 case DWC3_GCTL_PRTCAP_HOST: 1808 default: 1809 /* do nothing */ 1810 break; 1811 } 1812 1813 return 0; 1814 } 1815 1816 static int dwc3_runtime_suspend(struct device *dev) 1817 { 1818 struct dwc3 *dwc = dev_get_drvdata(dev); 1819 int ret; 1820 1821 if (dwc3_runtime_checks(dwc)) 1822 return -EBUSY; 1823 1824 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND); 1825 if (ret) 1826 return ret; 1827 1828 device_init_wakeup(dev, true); 1829 1830 return 0; 1831 } 1832 1833 static int dwc3_runtime_resume(struct device *dev) 1834 { 1835 struct dwc3 *dwc = dev_get_drvdata(dev); 1836 int ret; 1837 1838 device_init_wakeup(dev, false); 1839 1840 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME); 1841 if (ret) 1842 return ret; 1843 1844 switch (dwc->current_dr_role) { 1845 case DWC3_GCTL_PRTCAP_DEVICE: 1846 dwc3_gadget_process_pending_events(dwc); 1847 break; 1848 case DWC3_GCTL_PRTCAP_HOST: 1849 default: 1850 /* do nothing */ 1851 break; 1852 } 1853 1854 pm_runtime_mark_last_busy(dev); 1855 1856 return 0; 1857 } 1858 1859 static int dwc3_runtime_idle(struct device *dev) 1860 { 1861 struct dwc3 *dwc = dev_get_drvdata(dev); 1862 1863 switch (dwc->current_dr_role) { 1864 case DWC3_GCTL_PRTCAP_DEVICE: 1865 if (dwc3_runtime_checks(dwc)) 1866 return -EBUSY; 1867 break; 1868 case DWC3_GCTL_PRTCAP_HOST: 1869 default: 1870 /* do nothing */ 1871 break; 1872 } 1873 1874 pm_runtime_mark_last_busy(dev); 1875 pm_runtime_autosuspend(dev); 1876 1877 return 0; 1878 } 1879 #endif /* CONFIG_PM */ 1880 1881 #ifdef CONFIG_PM_SLEEP 1882 static int dwc3_suspend(struct device *dev) 1883 { 1884 struct dwc3 *dwc = dev_get_drvdata(dev); 1885 int ret; 1886 1887 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND); 1888 if (ret) 1889 return ret; 1890 1891 pinctrl_pm_select_sleep_state(dev); 1892 1893 return 0; 1894 } 1895 1896 static int dwc3_resume(struct device *dev) 1897 { 1898 struct dwc3 *dwc = dev_get_drvdata(dev); 1899 int ret; 1900 1901 pinctrl_pm_select_default_state(dev); 1902 1903 ret = dwc3_resume_common(dwc, PMSG_RESUME); 1904 if (ret) 1905 return ret; 1906 1907 pm_runtime_disable(dev); 1908 pm_runtime_set_active(dev); 1909 pm_runtime_enable(dev); 1910 1911 return 0; 1912 } 1913 1914 static void dwc3_complete(struct device *dev) 1915 { 1916 struct dwc3 *dwc = dev_get_drvdata(dev); 1917 u32 reg; 1918 1919 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST && 1920 dwc->dis_split_quirk) { 1921 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 1922 reg |= DWC3_GUCTL3_SPLITDISABLE; 1923 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 1924 } 1925 } 1926 #else 1927 #define dwc3_complete NULL 1928 #endif /* CONFIG_PM_SLEEP */ 1929 1930 static const struct dev_pm_ops dwc3_dev_pm_ops = { 1931 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) 1932 .complete = dwc3_complete, 1933 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, 1934 dwc3_runtime_idle) 1935 }; 1936 1937 #ifdef CONFIG_OF 1938 static const struct of_device_id of_dwc3_match[] = { 1939 { 1940 .compatible = "snps,dwc3" 1941 }, 1942 { 1943 .compatible = "synopsys,dwc3" 1944 }, 1945 { }, 1946 }; 1947 MODULE_DEVICE_TABLE(of, of_dwc3_match); 1948 #endif 1949 1950 #ifdef CONFIG_ACPI 1951 1952 #define ACPI_ID_INTEL_BSW "808622B7" 1953 1954 static const struct acpi_device_id dwc3_acpi_match[] = { 1955 { ACPI_ID_INTEL_BSW, 0 }, 1956 { }, 1957 }; 1958 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); 1959 #endif 1960 1961 static struct platform_driver dwc3_driver = { 1962 .probe = dwc3_probe, 1963 .remove = dwc3_remove, 1964 .driver = { 1965 .name = "dwc3", 1966 .of_match_table = of_match_ptr(of_dwc3_match), 1967 .acpi_match_table = ACPI_PTR(dwc3_acpi_match), 1968 .pm = &dwc3_dev_pm_ops, 1969 }, 1970 }; 1971 1972 module_platform_driver(dwc3_driver); 1973 1974 MODULE_ALIAS("platform:dwc3"); 1975 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 1976 MODULE_LICENSE("GPL v2"); 1977 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 1978