1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * core.c - DesignWare USB3 DRD Controller Core file 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/version.h> 13 #include <linux/module.h> 14 #include <linux/kernel.h> 15 #include <linux/slab.h> 16 #include <linux/spinlock.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/interrupt.h> 20 #include <linux/ioport.h> 21 #include <linux/io.h> 22 #include <linux/list.h> 23 #include <linux/delay.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/of.h> 26 #include <linux/of_graph.h> 27 #include <linux/acpi.h> 28 #include <linux/pinctrl/consumer.h> 29 #include <linux/reset.h> 30 #include <linux/bitfield.h> 31 32 #include <linux/usb/ch9.h> 33 #include <linux/usb/gadget.h> 34 #include <linux/usb/of.h> 35 #include <linux/usb/otg.h> 36 37 #include "core.h" 38 #include "gadget.h" 39 #include "io.h" 40 41 #include "debug.h" 42 43 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ 44 45 /** 46 * dwc3_get_dr_mode - Validates and sets dr_mode 47 * @dwc: pointer to our context structure 48 */ 49 static int dwc3_get_dr_mode(struct dwc3 *dwc) 50 { 51 enum usb_dr_mode mode; 52 struct device *dev = dwc->dev; 53 unsigned int hw_mode; 54 55 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 56 dwc->dr_mode = USB_DR_MODE_OTG; 57 58 mode = dwc->dr_mode; 59 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 60 61 switch (hw_mode) { 62 case DWC3_GHWPARAMS0_MODE_GADGET: 63 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) { 64 dev_err(dev, 65 "Controller does not support host mode.\n"); 66 return -EINVAL; 67 } 68 mode = USB_DR_MODE_PERIPHERAL; 69 break; 70 case DWC3_GHWPARAMS0_MODE_HOST: 71 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { 72 dev_err(dev, 73 "Controller does not support device mode.\n"); 74 return -EINVAL; 75 } 76 mode = USB_DR_MODE_HOST; 77 break; 78 default: 79 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 80 mode = USB_DR_MODE_HOST; 81 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 82 mode = USB_DR_MODE_PERIPHERAL; 83 84 /* 85 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG 86 * mode. If the controller supports DRD but the dr_mode is not 87 * specified or set to OTG, then set the mode to peripheral. 88 */ 89 if (mode == USB_DR_MODE_OTG && !dwc->edev && 90 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) || 91 !device_property_read_bool(dwc->dev, "usb-role-switch")) && 92 !DWC3_VER_IS_PRIOR(DWC3, 330A)) 93 mode = USB_DR_MODE_PERIPHERAL; 94 } 95 96 if (mode != dwc->dr_mode) { 97 dev_warn(dev, 98 "Configuration mismatch. dr_mode forced to %s\n", 99 mode == USB_DR_MODE_HOST ? "host" : "gadget"); 100 101 dwc->dr_mode = mode; 102 } 103 104 return 0; 105 } 106 107 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) 108 { 109 u32 reg; 110 111 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 112 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 113 reg |= DWC3_GCTL_PRTCAPDIR(mode); 114 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 115 116 dwc->current_dr_role = mode; 117 } 118 119 static void __dwc3_set_mode(struct work_struct *work) 120 { 121 struct dwc3 *dwc = work_to_dwc(work); 122 unsigned long flags; 123 int ret; 124 u32 reg; 125 u32 desired_dr_role; 126 127 mutex_lock(&dwc->mutex); 128 spin_lock_irqsave(&dwc->lock, flags); 129 desired_dr_role = dwc->desired_dr_role; 130 spin_unlock_irqrestore(&dwc->lock, flags); 131 132 pm_runtime_get_sync(dwc->dev); 133 134 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG) 135 dwc3_otg_update(dwc, 0); 136 137 if (!desired_dr_role) 138 goto out; 139 140 if (desired_dr_role == dwc->current_dr_role) 141 goto out; 142 143 if (desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev) 144 goto out; 145 146 switch (dwc->current_dr_role) { 147 case DWC3_GCTL_PRTCAP_HOST: 148 dwc3_host_exit(dwc); 149 break; 150 case DWC3_GCTL_PRTCAP_DEVICE: 151 dwc3_gadget_exit(dwc); 152 dwc3_event_buffers_cleanup(dwc); 153 break; 154 case DWC3_GCTL_PRTCAP_OTG: 155 dwc3_otg_exit(dwc); 156 spin_lock_irqsave(&dwc->lock, flags); 157 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE; 158 spin_unlock_irqrestore(&dwc->lock, flags); 159 dwc3_otg_update(dwc, 1); 160 break; 161 default: 162 break; 163 } 164 165 /* 166 * When current_dr_role is not set, there's no role switching. 167 * Only perform GCTL.CoreSoftReset when there's DRD role switching. 168 */ 169 if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) || 170 DWC3_VER_IS_PRIOR(DWC31, 190A)) && 171 desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) { 172 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 173 reg |= DWC3_GCTL_CORESOFTRESET; 174 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 175 176 /* 177 * Wait for internal clocks to synchronized. DWC_usb31 and 178 * DWC_usb32 may need at least 50ms (less for DWC_usb3). To 179 * keep it consistent across different IPs, let's wait up to 180 * 100ms before clearing GCTL.CORESOFTRESET. 181 */ 182 msleep(100); 183 184 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 185 reg &= ~DWC3_GCTL_CORESOFTRESET; 186 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 187 } 188 189 spin_lock_irqsave(&dwc->lock, flags); 190 191 dwc3_set_prtcap(dwc, desired_dr_role); 192 193 spin_unlock_irqrestore(&dwc->lock, flags); 194 195 switch (desired_dr_role) { 196 case DWC3_GCTL_PRTCAP_HOST: 197 ret = dwc3_host_init(dwc); 198 if (ret) { 199 dev_err(dwc->dev, "failed to initialize host\n"); 200 } else { 201 if (dwc->usb2_phy) 202 otg_set_vbus(dwc->usb2_phy->otg, true); 203 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 204 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 205 if (dwc->dis_split_quirk) { 206 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 207 reg |= DWC3_GUCTL3_SPLITDISABLE; 208 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 209 } 210 } 211 break; 212 case DWC3_GCTL_PRTCAP_DEVICE: 213 dwc3_core_soft_reset(dwc); 214 215 dwc3_event_buffers_setup(dwc); 216 217 if (dwc->usb2_phy) 218 otg_set_vbus(dwc->usb2_phy->otg, false); 219 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 220 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 221 222 ret = dwc3_gadget_init(dwc); 223 if (ret) 224 dev_err(dwc->dev, "failed to initialize peripheral\n"); 225 break; 226 case DWC3_GCTL_PRTCAP_OTG: 227 dwc3_otg_init(dwc); 228 dwc3_otg_update(dwc, 0); 229 break; 230 default: 231 break; 232 } 233 234 out: 235 pm_runtime_mark_last_busy(dwc->dev); 236 pm_runtime_put_autosuspend(dwc->dev); 237 mutex_unlock(&dwc->mutex); 238 } 239 240 void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 241 { 242 unsigned long flags; 243 244 if (dwc->dr_mode != USB_DR_MODE_OTG) 245 return; 246 247 spin_lock_irqsave(&dwc->lock, flags); 248 dwc->desired_dr_role = mode; 249 spin_unlock_irqrestore(&dwc->lock, flags); 250 251 queue_work(system_freezable_wq, &dwc->drd_work); 252 } 253 254 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) 255 { 256 struct dwc3 *dwc = dep->dwc; 257 u32 reg; 258 259 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, 260 DWC3_GDBGFIFOSPACE_NUM(dep->number) | 261 DWC3_GDBGFIFOSPACE_TYPE(type)); 262 263 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); 264 265 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); 266 } 267 268 /** 269 * dwc3_core_soft_reset - Issues core soft reset and PHY reset 270 * @dwc: pointer to our context structure 271 */ 272 int dwc3_core_soft_reset(struct dwc3 *dwc) 273 { 274 u32 reg; 275 int retries = 1000; 276 277 /* 278 * We're resetting only the device side because, if we're in host mode, 279 * XHCI driver will reset the host block. If dwc3 was configured for 280 * host-only mode or current role is host, then we can return early. 281 */ 282 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) 283 return 0; 284 285 /* 286 * If the dr_mode is host and the dwc->current_dr_role is not the 287 * corresponding DWC3_GCTL_PRTCAP_HOST, then the dwc3_core_init_mode 288 * isn't executed yet. Ensure the phy is ready before the controller 289 * updates the GCTL.PRTCAPDIR or other settings by soft-resetting 290 * the phy. 291 * 292 * Note: GUSB3PIPECTL[n] and GUSB2PHYCFG[n] are port settings where n 293 * is port index. If this is a multiport host, then we need to reset 294 * all active ports. 295 */ 296 if (dwc->dr_mode == USB_DR_MODE_HOST) { 297 u32 usb3_port; 298 u32 usb2_port; 299 300 usb3_port = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 301 usb3_port |= DWC3_GUSB3PIPECTL_PHYSOFTRST; 302 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), usb3_port); 303 304 usb2_port = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 305 usb2_port |= DWC3_GUSB2PHYCFG_PHYSOFTRST; 306 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), usb2_port); 307 308 /* Small delay for phy reset assertion */ 309 usleep_range(1000, 2000); 310 311 usb3_port &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST; 312 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), usb3_port); 313 314 usb2_port &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; 315 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), usb2_port); 316 317 /* Wait for clock synchronization */ 318 msleep(50); 319 return 0; 320 } 321 322 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 323 reg |= DWC3_DCTL_CSFTRST; 324 reg &= ~DWC3_DCTL_RUN_STOP; 325 dwc3_gadget_dctl_write_safe(dwc, reg); 326 327 /* 328 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit 329 * is cleared only after all the clocks are synchronized. This can 330 * take a little more than 50ms. Set the polling rate at 20ms 331 * for 10 times instead. 332 */ 333 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 334 retries = 10; 335 336 do { 337 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 338 if (!(reg & DWC3_DCTL_CSFTRST)) 339 goto done; 340 341 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 342 msleep(20); 343 else 344 udelay(1); 345 } while (--retries); 346 347 dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n"); 348 return -ETIMEDOUT; 349 350 done: 351 /* 352 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit 353 * is cleared, we must wait at least 50ms before accessing the PHY 354 * domain (synchronization delay). 355 */ 356 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A)) 357 msleep(50); 358 359 return 0; 360 } 361 362 /* 363 * dwc3_frame_length_adjustment - Adjusts frame length if required 364 * @dwc3: Pointer to our controller context structure 365 */ 366 static void dwc3_frame_length_adjustment(struct dwc3 *dwc) 367 { 368 u32 reg; 369 u32 dft; 370 371 if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 372 return; 373 374 if (dwc->fladj == 0) 375 return; 376 377 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 378 dft = reg & DWC3_GFLADJ_30MHZ_MASK; 379 if (dft != dwc->fladj) { 380 reg &= ~DWC3_GFLADJ_30MHZ_MASK; 381 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; 382 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 383 } 384 } 385 386 /** 387 * dwc3_ref_clk_period - Reference clock period configuration 388 * Default reference clock period depends on hardware 389 * configuration. For systems with reference clock that differs 390 * from the default, this will set clock period in DWC3_GUCTL 391 * register. 392 * @dwc: Pointer to our controller context structure 393 */ 394 static void dwc3_ref_clk_period(struct dwc3 *dwc) 395 { 396 unsigned long period; 397 unsigned long fladj; 398 unsigned long decr; 399 unsigned long rate; 400 u32 reg; 401 402 if (dwc->ref_clk) { 403 rate = clk_get_rate(dwc->ref_clk); 404 if (!rate) 405 return; 406 period = NSEC_PER_SEC / rate; 407 } else if (dwc->ref_clk_per) { 408 period = dwc->ref_clk_per; 409 rate = NSEC_PER_SEC / period; 410 } else { 411 return; 412 } 413 414 reg = dwc3_readl(dwc->regs, DWC3_GUCTL); 415 reg &= ~DWC3_GUCTL_REFCLKPER_MASK; 416 reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period); 417 dwc3_writel(dwc->regs, DWC3_GUCTL, reg); 418 419 if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 420 return; 421 422 /* 423 * The calculation below is 424 * 425 * 125000 * (NSEC_PER_SEC / (rate * period) - 1) 426 * 427 * but rearranged for fixed-point arithmetic. The division must be 428 * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and 429 * neither does rate * period). 430 * 431 * Note that rate * period ~= NSEC_PER_SECOND, minus the number of 432 * nanoseconds of error caused by the truncation which happened during 433 * the division when calculating rate or period (whichever one was 434 * derived from the other). We first calculate the relative error, then 435 * scale it to units of 8 ppm. 436 */ 437 fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period); 438 fladj -= 125000; 439 440 /* 441 * The documented 240MHz constant is scaled by 2 to get PLS1 as well. 442 */ 443 decr = 480000000 / rate; 444 445 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 446 reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK 447 & ~DWC3_GFLADJ_240MHZDECR 448 & ~DWC3_GFLADJ_240MHZDECR_PLS1; 449 reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj) 450 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1) 451 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1); 452 453 if (dwc->gfladj_refclk_lpm_sel) 454 reg |= DWC3_GFLADJ_REFCLK_LPM_SEL; 455 456 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 457 } 458 459 /** 460 * dwc3_free_one_event_buffer - Frees one event buffer 461 * @dwc: Pointer to our controller context structure 462 * @evt: Pointer to event buffer to be freed 463 */ 464 static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 465 struct dwc3_event_buffer *evt) 466 { 467 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma); 468 } 469 470 /** 471 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 472 * @dwc: Pointer to our controller context structure 473 * @length: size of the event buffer 474 * 475 * Returns a pointer to the allocated event buffer structure on success 476 * otherwise ERR_PTR(errno). 477 */ 478 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 479 unsigned int length) 480 { 481 struct dwc3_event_buffer *evt; 482 483 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 484 if (!evt) 485 return ERR_PTR(-ENOMEM); 486 487 evt->dwc = dwc; 488 evt->length = length; 489 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL); 490 if (!evt->cache) 491 return ERR_PTR(-ENOMEM); 492 493 evt->buf = dma_alloc_coherent(dwc->sysdev, length, 494 &evt->dma, GFP_KERNEL); 495 if (!evt->buf) 496 return ERR_PTR(-ENOMEM); 497 498 return evt; 499 } 500 501 /** 502 * dwc3_free_event_buffers - frees all allocated event buffers 503 * @dwc: Pointer to our controller context structure 504 */ 505 static void dwc3_free_event_buffers(struct dwc3 *dwc) 506 { 507 struct dwc3_event_buffer *evt; 508 509 evt = dwc->ev_buf; 510 if (evt) 511 dwc3_free_one_event_buffer(dwc, evt); 512 } 513 514 /** 515 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 516 * @dwc: pointer to our controller context structure 517 * @length: size of event buffer 518 * 519 * Returns 0 on success otherwise negative errno. In the error case, dwc 520 * may contain some buffers allocated but not all which were requested. 521 */ 522 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length) 523 { 524 struct dwc3_event_buffer *evt; 525 526 evt = dwc3_alloc_one_event_buffer(dwc, length); 527 if (IS_ERR(evt)) { 528 dev_err(dwc->dev, "can't allocate event buffer\n"); 529 return PTR_ERR(evt); 530 } 531 dwc->ev_buf = evt; 532 533 return 0; 534 } 535 536 /** 537 * dwc3_event_buffers_setup - setup our allocated event buffers 538 * @dwc: pointer to our controller context structure 539 * 540 * Returns 0 on success otherwise negative errno. 541 */ 542 int dwc3_event_buffers_setup(struct dwc3 *dwc) 543 { 544 struct dwc3_event_buffer *evt; 545 546 evt = dwc->ev_buf; 547 evt->lpos = 0; 548 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 549 lower_32_bits(evt->dma)); 550 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 551 upper_32_bits(evt->dma)); 552 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), 553 DWC3_GEVNTSIZ_SIZE(evt->length)); 554 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 555 556 return 0; 557 } 558 559 void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 560 { 561 struct dwc3_event_buffer *evt; 562 563 evt = dwc->ev_buf; 564 565 evt->lpos = 0; 566 567 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); 568 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); 569 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK 570 | DWC3_GEVNTSIZ_SIZE(0)); 571 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 572 } 573 574 static void dwc3_core_num_eps(struct dwc3 *dwc) 575 { 576 struct dwc3_hwparams *parms = &dwc->hwparams; 577 578 dwc->num_eps = DWC3_NUM_EPS(parms); 579 } 580 581 static void dwc3_cache_hwparams(struct dwc3 *dwc) 582 { 583 struct dwc3_hwparams *parms = &dwc->hwparams; 584 585 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 586 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 587 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 588 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 589 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 590 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 591 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 592 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 593 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 594 595 if (DWC3_IP_IS(DWC32)) 596 parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9); 597 } 598 599 static int dwc3_core_ulpi_init(struct dwc3 *dwc) 600 { 601 int intf; 602 int ret = 0; 603 604 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3); 605 606 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI || 607 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI && 608 dwc->hsphy_interface && 609 !strncmp(dwc->hsphy_interface, "ulpi", 4))) 610 ret = dwc3_ulpi_init(dwc); 611 612 return ret; 613 } 614 615 /** 616 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 617 * @dwc: Pointer to our controller context structure 618 * 619 * Returns 0 on success. The USB PHY interfaces are configured but not 620 * initialized. The PHY interfaces and the PHYs get initialized together with 621 * the core in dwc3_core_init. 622 */ 623 static int dwc3_phy_setup(struct dwc3 *dwc) 624 { 625 unsigned int hw_mode; 626 u32 reg; 627 628 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 629 630 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 631 632 /* 633 * Make sure UX_EXIT_PX is cleared as that causes issues with some 634 * PHYs. Also, this bit is not supposed to be used in normal operation. 635 */ 636 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; 637 638 /* 639 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 640 * to '0' during coreConsultant configuration. So default value 641 * will be '0' when the core is reset. Application needs to set it 642 * to '1' after the core initialization is completed. 643 */ 644 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) 645 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 646 647 /* 648 * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after 649 * power-on reset, and it can be set after core initialization, which is 650 * after device soft-reset during initialization. 651 */ 652 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 653 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 654 655 if (dwc->u2ss_inp3_quirk) 656 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 657 658 if (dwc->dis_rxdet_inp3_quirk) 659 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; 660 661 if (dwc->req_p1p2p3_quirk) 662 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 663 664 if (dwc->del_p1p2p3_quirk) 665 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 666 667 if (dwc->del_phy_power_chg_quirk) 668 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 669 670 if (dwc->lfps_filter_quirk) 671 reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 672 673 if (dwc->rx_detect_poll_quirk) 674 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 675 676 if (dwc->tx_de_emphasis_quirk) 677 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 678 679 if (dwc->dis_u3_susphy_quirk) 680 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 681 682 if (dwc->dis_del_phy_power_chg_quirk) 683 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; 684 685 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 686 687 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 688 689 /* Select the HS PHY interface */ 690 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { 691 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: 692 if (dwc->hsphy_interface && 693 !strncmp(dwc->hsphy_interface, "utmi", 4)) { 694 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; 695 break; 696 } else if (dwc->hsphy_interface && 697 !strncmp(dwc->hsphy_interface, "ulpi", 4)) { 698 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; 699 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 700 } else { 701 /* Relying on default value. */ 702 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) 703 break; 704 } 705 fallthrough; 706 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: 707 default: 708 break; 709 } 710 711 switch (dwc->hsphy_mode) { 712 case USBPHY_INTERFACE_MODE_UTMI: 713 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 714 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 715 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | 716 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); 717 break; 718 case USBPHY_INTERFACE_MODE_UTMIW: 719 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 720 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 721 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | 722 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 723 break; 724 default: 725 break; 726 } 727 728 /* 729 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 730 * '0' during coreConsultant configuration. So default value will 731 * be '0' when the core is reset. Application needs to set it to 732 * '1' after the core initialization is completed. 733 */ 734 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) 735 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 736 737 /* 738 * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after 739 * power-on reset, and it can be set after core initialization, which is 740 * after device soft-reset during initialization. 741 */ 742 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 743 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 744 745 if (dwc->dis_u2_susphy_quirk) 746 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 747 748 if (dwc->dis_enblslpm_quirk) 749 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 750 else 751 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM; 752 753 if (dwc->dis_u2_freeclk_exists_quirk || dwc->gfladj_refclk_lpm_sel) 754 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 755 756 /* 757 * Some ULPI USB PHY does not support internal VBUS supply, to drive 758 * the CPEN pin requires the configuration of the ULPI DRVVBUSEXTERNAL 759 * bit of OTG_CTRL register. Controller configures the USB2 PHY 760 * ULPIEXTVBUSDRV bit[17] of the GUSB2PHYCFG register to drive vBus 761 * with an external supply. 762 */ 763 if (dwc->ulpi_ext_vbus_drv) 764 reg |= DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV; 765 766 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 767 768 return 0; 769 } 770 771 static int dwc3_phy_init(struct dwc3 *dwc) 772 { 773 int ret; 774 775 usb_phy_init(dwc->usb2_phy); 776 usb_phy_init(dwc->usb3_phy); 777 778 ret = phy_init(dwc->usb2_generic_phy); 779 if (ret < 0) 780 goto err_shutdown_usb3_phy; 781 782 ret = phy_init(dwc->usb3_generic_phy); 783 if (ret < 0) 784 goto err_exit_usb2_phy; 785 786 return 0; 787 788 err_exit_usb2_phy: 789 phy_exit(dwc->usb2_generic_phy); 790 err_shutdown_usb3_phy: 791 usb_phy_shutdown(dwc->usb3_phy); 792 usb_phy_shutdown(dwc->usb2_phy); 793 794 return ret; 795 } 796 797 static void dwc3_phy_exit(struct dwc3 *dwc) 798 { 799 phy_exit(dwc->usb3_generic_phy); 800 phy_exit(dwc->usb2_generic_phy); 801 802 usb_phy_shutdown(dwc->usb3_phy); 803 usb_phy_shutdown(dwc->usb2_phy); 804 } 805 806 static int dwc3_phy_power_on(struct dwc3 *dwc) 807 { 808 int ret; 809 810 usb_phy_set_suspend(dwc->usb2_phy, 0); 811 usb_phy_set_suspend(dwc->usb3_phy, 0); 812 813 ret = phy_power_on(dwc->usb2_generic_phy); 814 if (ret < 0) 815 goto err_suspend_usb3_phy; 816 817 ret = phy_power_on(dwc->usb3_generic_phy); 818 if (ret < 0) 819 goto err_power_off_usb2_phy; 820 821 return 0; 822 823 err_power_off_usb2_phy: 824 phy_power_off(dwc->usb2_generic_phy); 825 err_suspend_usb3_phy: 826 usb_phy_set_suspend(dwc->usb3_phy, 1); 827 usb_phy_set_suspend(dwc->usb2_phy, 1); 828 829 return ret; 830 } 831 832 static void dwc3_phy_power_off(struct dwc3 *dwc) 833 { 834 phy_power_off(dwc->usb3_generic_phy); 835 phy_power_off(dwc->usb2_generic_phy); 836 837 usb_phy_set_suspend(dwc->usb3_phy, 1); 838 usb_phy_set_suspend(dwc->usb2_phy, 1); 839 } 840 841 static int dwc3_clk_enable(struct dwc3 *dwc) 842 { 843 int ret; 844 845 ret = clk_prepare_enable(dwc->bus_clk); 846 if (ret) 847 return ret; 848 849 ret = clk_prepare_enable(dwc->ref_clk); 850 if (ret) 851 goto disable_bus_clk; 852 853 ret = clk_prepare_enable(dwc->susp_clk); 854 if (ret) 855 goto disable_ref_clk; 856 857 ret = clk_prepare_enable(dwc->utmi_clk); 858 if (ret) 859 goto disable_susp_clk; 860 861 ret = clk_prepare_enable(dwc->pipe_clk); 862 if (ret) 863 goto disable_utmi_clk; 864 865 return 0; 866 867 disable_utmi_clk: 868 clk_disable_unprepare(dwc->utmi_clk); 869 disable_susp_clk: 870 clk_disable_unprepare(dwc->susp_clk); 871 disable_ref_clk: 872 clk_disable_unprepare(dwc->ref_clk); 873 disable_bus_clk: 874 clk_disable_unprepare(dwc->bus_clk); 875 return ret; 876 } 877 878 static void dwc3_clk_disable(struct dwc3 *dwc) 879 { 880 clk_disable_unprepare(dwc->pipe_clk); 881 clk_disable_unprepare(dwc->utmi_clk); 882 clk_disable_unprepare(dwc->susp_clk); 883 clk_disable_unprepare(dwc->ref_clk); 884 clk_disable_unprepare(dwc->bus_clk); 885 } 886 887 static void dwc3_core_exit(struct dwc3 *dwc) 888 { 889 dwc3_event_buffers_cleanup(dwc); 890 dwc3_phy_power_off(dwc); 891 dwc3_phy_exit(dwc); 892 dwc3_clk_disable(dwc); 893 reset_control_assert(dwc->reset); 894 } 895 896 static bool dwc3_core_is_valid(struct dwc3 *dwc) 897 { 898 u32 reg; 899 900 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 901 dwc->ip = DWC3_GSNPS_ID(reg); 902 903 /* This should read as U3 followed by revision number */ 904 if (DWC3_IP_IS(DWC3)) { 905 dwc->revision = reg; 906 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) { 907 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); 908 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE); 909 } else { 910 return false; 911 } 912 913 return true; 914 } 915 916 static void dwc3_core_setup_global_control(struct dwc3 *dwc) 917 { 918 u32 reg; 919 920 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 921 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 922 923 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 924 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 925 /** 926 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 927 * issue which would cause xHCI compliance tests to fail. 928 * 929 * Because of that we cannot enable clock gating on such 930 * configurations. 931 * 932 * Refers to: 933 * 934 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 935 * SOF/ITP Mode Used 936 */ 937 if ((dwc->dr_mode == USB_DR_MODE_HOST || 938 dwc->dr_mode == USB_DR_MODE_OTG) && 939 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A)) 940 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 941 else 942 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 943 break; 944 case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 945 /* 946 * REVISIT Enabling this bit so that host-mode hibernation 947 * will work. Device-mode hibernation is not yet implemented. 948 */ 949 reg |= DWC3_GCTL_GBLHIBERNATIONEN; 950 break; 951 default: 952 /* nothing */ 953 break; 954 } 955 956 /* check if current dwc3 is on simulation board */ 957 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 958 dev_info(dwc->dev, "Running with FPGA optimizations\n"); 959 dwc->is_fpga = true; 960 } 961 962 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, 963 "disable_scramble cannot be used on non-FPGA builds\n"); 964 965 if (dwc->disable_scramble_quirk && dwc->is_fpga) 966 reg |= DWC3_GCTL_DISSCRAMBLE; 967 else 968 reg &= ~DWC3_GCTL_DISSCRAMBLE; 969 970 if (dwc->u2exit_lfps_quirk) 971 reg |= DWC3_GCTL_U2EXIT_LFPS; 972 973 /* 974 * WORKAROUND: DWC3 revisions <1.90a have a bug 975 * where the device can fail to connect at SuperSpeed 976 * and falls back to high-speed mode which causes 977 * the device to enter a Connect/Disconnect loop 978 */ 979 if (DWC3_VER_IS_PRIOR(DWC3, 190A)) 980 reg |= DWC3_GCTL_U2RSTECN; 981 982 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 983 } 984 985 static int dwc3_core_get_phy(struct dwc3 *dwc); 986 static int dwc3_core_ulpi_init(struct dwc3 *dwc); 987 988 /* set global incr burst type configuration registers */ 989 static void dwc3_set_incr_burst_type(struct dwc3 *dwc) 990 { 991 struct device *dev = dwc->dev; 992 /* incrx_mode : for INCR burst type. */ 993 bool incrx_mode; 994 /* incrx_size : for size of INCRX burst. */ 995 u32 incrx_size; 996 u32 *vals; 997 u32 cfg; 998 int ntype; 999 int ret; 1000 int i; 1001 1002 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); 1003 1004 /* 1005 * Handle property "snps,incr-burst-type-adjustment". 1006 * Get the number of value from this property: 1007 * result <= 0, means this property is not supported. 1008 * result = 1, means INCRx burst mode supported. 1009 * result > 1, means undefined length burst mode supported. 1010 */ 1011 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment"); 1012 if (ntype <= 0) 1013 return; 1014 1015 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL); 1016 if (!vals) 1017 return; 1018 1019 /* Get INCR burst type, and parse it */ 1020 ret = device_property_read_u32_array(dev, 1021 "snps,incr-burst-type-adjustment", vals, ntype); 1022 if (ret) { 1023 kfree(vals); 1024 dev_err(dev, "Error to get property\n"); 1025 return; 1026 } 1027 1028 incrx_size = *vals; 1029 1030 if (ntype > 1) { 1031 /* INCRX (undefined length) burst mode */ 1032 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE; 1033 for (i = 1; i < ntype; i++) { 1034 if (vals[i] > incrx_size) 1035 incrx_size = vals[i]; 1036 } 1037 } else { 1038 /* INCRX burst mode */ 1039 incrx_mode = INCRX_BURST_MODE; 1040 } 1041 1042 kfree(vals); 1043 1044 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */ 1045 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK; 1046 if (incrx_mode) 1047 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA; 1048 switch (incrx_size) { 1049 case 256: 1050 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA; 1051 break; 1052 case 128: 1053 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA; 1054 break; 1055 case 64: 1056 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA; 1057 break; 1058 case 32: 1059 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA; 1060 break; 1061 case 16: 1062 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA; 1063 break; 1064 case 8: 1065 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA; 1066 break; 1067 case 4: 1068 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA; 1069 break; 1070 case 1: 1071 break; 1072 default: 1073 dev_err(dev, "Invalid property\n"); 1074 break; 1075 } 1076 1077 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg); 1078 } 1079 1080 static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc) 1081 { 1082 u32 scale; 1083 u32 reg; 1084 1085 if (!dwc->susp_clk) 1086 return; 1087 1088 /* 1089 * The power down scale field specifies how many suspend_clk 1090 * periods fit into a 16KHz clock period. When performing 1091 * the division, round up the remainder. 1092 * 1093 * The power down scale value is calculated using the fastest 1094 * frequency of the suspend_clk. If it isn't fixed (but within 1095 * the accuracy requirement), the driver may not know the max 1096 * rate of the suspend_clk, so only update the power down scale 1097 * if the default is less than the calculated value from 1098 * clk_get_rate() or if the default is questionably high 1099 * (3x or more) to be within the requirement. 1100 */ 1101 scale = DIV_ROUND_UP(clk_get_rate(dwc->susp_clk), 16000); 1102 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 1103 if ((reg & DWC3_GCTL_PWRDNSCALE_MASK) < DWC3_GCTL_PWRDNSCALE(scale) || 1104 (reg & DWC3_GCTL_PWRDNSCALE_MASK) > DWC3_GCTL_PWRDNSCALE(scale*3)) { 1105 reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK); 1106 reg |= DWC3_GCTL_PWRDNSCALE(scale); 1107 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 1108 } 1109 } 1110 1111 static void dwc3_config_threshold(struct dwc3 *dwc) 1112 { 1113 u32 reg; 1114 u8 rx_thr_num; 1115 u8 rx_maxburst; 1116 u8 tx_thr_num; 1117 u8 tx_maxburst; 1118 1119 /* 1120 * Must config both number of packets and max burst settings to enable 1121 * RX and/or TX threshold. 1122 */ 1123 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) { 1124 rx_thr_num = dwc->rx_thr_num_pkt_prd; 1125 rx_maxburst = dwc->rx_max_burst_prd; 1126 tx_thr_num = dwc->tx_thr_num_pkt_prd; 1127 tx_maxburst = dwc->tx_max_burst_prd; 1128 1129 if (rx_thr_num && rx_maxburst) { 1130 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1131 reg |= DWC31_RXTHRNUMPKTSEL_PRD; 1132 1133 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0); 1134 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num); 1135 1136 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0); 1137 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst); 1138 1139 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1140 } 1141 1142 if (tx_thr_num && tx_maxburst) { 1143 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1144 reg |= DWC31_TXTHRNUMPKTSEL_PRD; 1145 1146 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0); 1147 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num); 1148 1149 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0); 1150 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst); 1151 1152 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1153 } 1154 } 1155 1156 rx_thr_num = dwc->rx_thr_num_pkt; 1157 rx_maxburst = dwc->rx_max_burst; 1158 tx_thr_num = dwc->tx_thr_num_pkt; 1159 tx_maxburst = dwc->tx_max_burst; 1160 1161 if (DWC3_IP_IS(DWC3)) { 1162 if (rx_thr_num && rx_maxburst) { 1163 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1164 reg |= DWC3_GRXTHRCFG_PKTCNTSEL; 1165 1166 reg &= ~DWC3_GRXTHRCFG_RXPKTCNT(~0); 1167 reg |= DWC3_GRXTHRCFG_RXPKTCNT(rx_thr_num); 1168 1169 reg &= ~DWC3_GRXTHRCFG_MAXRXBURSTSIZE(~0); 1170 reg |= DWC3_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst); 1171 1172 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1173 } 1174 1175 if (tx_thr_num && tx_maxburst) { 1176 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1177 reg |= DWC3_GTXTHRCFG_PKTCNTSEL; 1178 1179 reg &= ~DWC3_GTXTHRCFG_TXPKTCNT(~0); 1180 reg |= DWC3_GTXTHRCFG_TXPKTCNT(tx_thr_num); 1181 1182 reg &= ~DWC3_GTXTHRCFG_MAXTXBURSTSIZE(~0); 1183 reg |= DWC3_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst); 1184 1185 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1186 } 1187 } else { 1188 if (rx_thr_num && rx_maxburst) { 1189 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1190 reg |= DWC31_GRXTHRCFG_PKTCNTSEL; 1191 1192 reg &= ~DWC31_GRXTHRCFG_RXPKTCNT(~0); 1193 reg |= DWC31_GRXTHRCFG_RXPKTCNT(rx_thr_num); 1194 1195 reg &= ~DWC31_GRXTHRCFG_MAXRXBURSTSIZE(~0); 1196 reg |= DWC31_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst); 1197 1198 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1199 } 1200 1201 if (tx_thr_num && tx_maxburst) { 1202 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1203 reg |= DWC31_GTXTHRCFG_PKTCNTSEL; 1204 1205 reg &= ~DWC31_GTXTHRCFG_TXPKTCNT(~0); 1206 reg |= DWC31_GTXTHRCFG_TXPKTCNT(tx_thr_num); 1207 1208 reg &= ~DWC31_GTXTHRCFG_MAXTXBURSTSIZE(~0); 1209 reg |= DWC31_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst); 1210 1211 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1212 } 1213 } 1214 } 1215 1216 /** 1217 * dwc3_core_init - Low-level initialization of DWC3 Core 1218 * @dwc: Pointer to our controller context structure 1219 * 1220 * Returns 0 on success otherwise negative errno. 1221 */ 1222 static int dwc3_core_init(struct dwc3 *dwc) 1223 { 1224 unsigned int hw_mode; 1225 u32 reg; 1226 int ret; 1227 1228 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 1229 1230 /* 1231 * Write Linux Version Code to our GUID register so it's easy to figure 1232 * out which kernel version a bug was found. 1233 */ 1234 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); 1235 1236 ret = dwc3_phy_setup(dwc); 1237 if (ret) 1238 return ret; 1239 1240 if (!dwc->ulpi_ready) { 1241 ret = dwc3_core_ulpi_init(dwc); 1242 if (ret) { 1243 if (ret == -ETIMEDOUT) { 1244 dwc3_core_soft_reset(dwc); 1245 ret = -EPROBE_DEFER; 1246 } 1247 return ret; 1248 } 1249 dwc->ulpi_ready = true; 1250 } 1251 1252 if (!dwc->phys_ready) { 1253 ret = dwc3_core_get_phy(dwc); 1254 if (ret) 1255 goto err_exit_ulpi; 1256 dwc->phys_ready = true; 1257 } 1258 1259 ret = dwc3_phy_init(dwc); 1260 if (ret) 1261 goto err_exit_ulpi; 1262 1263 ret = dwc3_core_soft_reset(dwc); 1264 if (ret) 1265 goto err_exit_phy; 1266 1267 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD && 1268 !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) { 1269 if (!dwc->dis_u3_susphy_quirk) { 1270 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 1271 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 1272 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 1273 } 1274 1275 if (!dwc->dis_u2_susphy_quirk) { 1276 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1277 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 1278 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1279 } 1280 } 1281 1282 dwc3_core_setup_global_control(dwc); 1283 dwc3_core_num_eps(dwc); 1284 1285 /* Set power down scale of suspend_clk */ 1286 dwc3_set_power_down_clk_scale(dwc); 1287 1288 /* Adjust Frame Length */ 1289 dwc3_frame_length_adjustment(dwc); 1290 1291 /* Adjust Reference Clock Period */ 1292 dwc3_ref_clk_period(dwc); 1293 1294 dwc3_set_incr_burst_type(dwc); 1295 1296 ret = dwc3_phy_power_on(dwc); 1297 if (ret) 1298 goto err_exit_phy; 1299 1300 ret = dwc3_event_buffers_setup(dwc); 1301 if (ret) { 1302 dev_err(dwc->dev, "failed to setup event buffers\n"); 1303 goto err_power_off_phy; 1304 } 1305 1306 /* 1307 * ENDXFER polling is available on version 3.10a and later of 1308 * the DWC_usb3 controller. It is NOT available in the 1309 * DWC_usb31 controller. 1310 */ 1311 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) { 1312 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); 1313 reg |= DWC3_GUCTL2_RST_ACTBITLATER; 1314 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); 1315 } 1316 1317 /* 1318 * When configured in HOST mode, after issuing U3/L2 exit controller 1319 * fails to send proper CRC checksum in CRC5 feild. Because of this 1320 * behaviour Transaction Error is generated, resulting in reset and 1321 * re-enumeration of usb device attached. All the termsel, xcvrsel, 1322 * opmode becomes 0 during end of resume. Enabling bit 10 of GUCTL1 1323 * will correct this problem. This option is to support certain 1324 * legacy ULPI PHYs. 1325 */ 1326 if (dwc->resume_hs_terminations) { 1327 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 1328 reg |= DWC3_GUCTL1_RESUME_OPMODE_HS_HOST; 1329 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 1330 } 1331 1332 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) { 1333 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 1334 1335 /* 1336 * Enable hardware control of sending remote wakeup 1337 * in HS when the device is in the L1 state. 1338 */ 1339 if (!DWC3_VER_IS_PRIOR(DWC3, 290A)) 1340 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; 1341 1342 /* 1343 * Decouple USB 2.0 L1 & L2 events which will allow for 1344 * gadget driver to only receive U3/L2 suspend & wakeup 1345 * events and prevent the more frequent L1 LPM transitions 1346 * from interrupting the driver. 1347 */ 1348 if (!DWC3_VER_IS_PRIOR(DWC3, 300A)) 1349 reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT; 1350 1351 if (dwc->dis_tx_ipgap_linecheck_quirk) 1352 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; 1353 1354 if (dwc->parkmode_disable_ss_quirk) 1355 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS; 1356 1357 if (dwc->parkmode_disable_hs_quirk) 1358 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_HS; 1359 1360 if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) && 1361 (dwc->maximum_speed == USB_SPEED_HIGH || 1362 dwc->maximum_speed == USB_SPEED_FULL)) 1363 reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; 1364 1365 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 1366 } 1367 1368 dwc3_config_threshold(dwc); 1369 1370 return 0; 1371 1372 err_power_off_phy: 1373 dwc3_phy_power_off(dwc); 1374 err_exit_phy: 1375 dwc3_phy_exit(dwc); 1376 err_exit_ulpi: 1377 dwc3_ulpi_exit(dwc); 1378 1379 return ret; 1380 } 1381 1382 static int dwc3_core_get_phy(struct dwc3 *dwc) 1383 { 1384 struct device *dev = dwc->dev; 1385 struct device_node *node = dev->of_node; 1386 int ret; 1387 1388 if (node) { 1389 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); 1390 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); 1391 } else { 1392 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 1393 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); 1394 } 1395 1396 if (IS_ERR(dwc->usb2_phy)) { 1397 ret = PTR_ERR(dwc->usb2_phy); 1398 if (ret == -ENXIO || ret == -ENODEV) 1399 dwc->usb2_phy = NULL; 1400 else 1401 return dev_err_probe(dev, ret, "no usb2 phy configured\n"); 1402 } 1403 1404 if (IS_ERR(dwc->usb3_phy)) { 1405 ret = PTR_ERR(dwc->usb3_phy); 1406 if (ret == -ENXIO || ret == -ENODEV) 1407 dwc->usb3_phy = NULL; 1408 else 1409 return dev_err_probe(dev, ret, "no usb3 phy configured\n"); 1410 } 1411 1412 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); 1413 if (IS_ERR(dwc->usb2_generic_phy)) { 1414 ret = PTR_ERR(dwc->usb2_generic_phy); 1415 if (ret == -ENOSYS || ret == -ENODEV) 1416 dwc->usb2_generic_phy = NULL; 1417 else 1418 return dev_err_probe(dev, ret, "no usb2 phy configured\n"); 1419 } 1420 1421 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); 1422 if (IS_ERR(dwc->usb3_generic_phy)) { 1423 ret = PTR_ERR(dwc->usb3_generic_phy); 1424 if (ret == -ENOSYS || ret == -ENODEV) 1425 dwc->usb3_generic_phy = NULL; 1426 else 1427 return dev_err_probe(dev, ret, "no usb3 phy configured\n"); 1428 } 1429 1430 return 0; 1431 } 1432 1433 static int dwc3_core_init_mode(struct dwc3 *dwc) 1434 { 1435 struct device *dev = dwc->dev; 1436 int ret; 1437 1438 switch (dwc->dr_mode) { 1439 case USB_DR_MODE_PERIPHERAL: 1440 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1441 1442 if (dwc->usb2_phy) 1443 otg_set_vbus(dwc->usb2_phy->otg, false); 1444 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 1445 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 1446 1447 ret = dwc3_gadget_init(dwc); 1448 if (ret) 1449 return dev_err_probe(dev, ret, "failed to initialize gadget\n"); 1450 break; 1451 case USB_DR_MODE_HOST: 1452 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1453 1454 if (dwc->usb2_phy) 1455 otg_set_vbus(dwc->usb2_phy->otg, true); 1456 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 1457 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 1458 1459 ret = dwc3_host_init(dwc); 1460 if (ret) 1461 return dev_err_probe(dev, ret, "failed to initialize host\n"); 1462 break; 1463 case USB_DR_MODE_OTG: 1464 INIT_WORK(&dwc->drd_work, __dwc3_set_mode); 1465 ret = dwc3_drd_init(dwc); 1466 if (ret) 1467 return dev_err_probe(dev, ret, "failed to initialize dual-role\n"); 1468 break; 1469 default: 1470 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 1471 return -EINVAL; 1472 } 1473 1474 return 0; 1475 } 1476 1477 static void dwc3_core_exit_mode(struct dwc3 *dwc) 1478 { 1479 switch (dwc->dr_mode) { 1480 case USB_DR_MODE_PERIPHERAL: 1481 dwc3_gadget_exit(dwc); 1482 break; 1483 case USB_DR_MODE_HOST: 1484 dwc3_host_exit(dwc); 1485 break; 1486 case USB_DR_MODE_OTG: 1487 dwc3_drd_exit(dwc); 1488 break; 1489 default: 1490 /* do nothing */ 1491 break; 1492 } 1493 1494 /* de-assert DRVVBUS for HOST and OTG mode */ 1495 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1496 } 1497 1498 static void dwc3_get_properties(struct dwc3 *dwc) 1499 { 1500 struct device *dev = dwc->dev; 1501 u8 lpm_nyet_threshold; 1502 u8 tx_de_emphasis; 1503 u8 hird_threshold; 1504 u8 rx_thr_num_pkt = 0; 1505 u8 rx_max_burst = 0; 1506 u8 tx_thr_num_pkt = 0; 1507 u8 tx_max_burst = 0; 1508 u8 rx_thr_num_pkt_prd = 0; 1509 u8 rx_max_burst_prd = 0; 1510 u8 tx_thr_num_pkt_prd = 0; 1511 u8 tx_max_burst_prd = 0; 1512 u8 tx_fifo_resize_max_num; 1513 const char *usb_psy_name; 1514 int ret; 1515 1516 /* default to highest possible threshold */ 1517 lpm_nyet_threshold = 0xf; 1518 1519 /* default to -3.5dB de-emphasis */ 1520 tx_de_emphasis = 1; 1521 1522 /* 1523 * default to assert utmi_sleep_n and use maximum allowed HIRD 1524 * threshold value of 0b1100 1525 */ 1526 hird_threshold = 12; 1527 1528 /* 1529 * default to a TXFIFO size large enough to fit 6 max packets. This 1530 * allows for systems with larger bus latencies to have some headroom 1531 * for endpoints that have a large bMaxBurst value. 1532 */ 1533 tx_fifo_resize_max_num = 6; 1534 1535 dwc->maximum_speed = usb_get_maximum_speed(dev); 1536 dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev); 1537 dwc->dr_mode = usb_get_dr_mode(dev); 1538 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); 1539 1540 dwc->sysdev_is_parent = device_property_read_bool(dev, 1541 "linux,sysdev_is_parent"); 1542 if (dwc->sysdev_is_parent) 1543 dwc->sysdev = dwc->dev->parent; 1544 else 1545 dwc->sysdev = dwc->dev; 1546 1547 ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name); 1548 if (ret >= 0) { 1549 dwc->usb_psy = power_supply_get_by_name(usb_psy_name); 1550 if (!dwc->usb_psy) 1551 dev_err(dev, "couldn't get usb power supply\n"); 1552 } 1553 1554 dwc->has_lpm_erratum = device_property_read_bool(dev, 1555 "snps,has-lpm-erratum"); 1556 device_property_read_u8(dev, "snps,lpm-nyet-threshold", 1557 &lpm_nyet_threshold); 1558 dwc->is_utmi_l1_suspend = device_property_read_bool(dev, 1559 "snps,is-utmi-l1-suspend"); 1560 device_property_read_u8(dev, "snps,hird-threshold", 1561 &hird_threshold); 1562 dwc->dis_start_transfer_quirk = device_property_read_bool(dev, 1563 "snps,dis-start-transfer-quirk"); 1564 dwc->usb3_lpm_capable = device_property_read_bool(dev, 1565 "snps,usb3_lpm_capable"); 1566 dwc->usb2_lpm_disable = device_property_read_bool(dev, 1567 "snps,usb2-lpm-disable"); 1568 dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev, 1569 "snps,usb2-gadget-lpm-disable"); 1570 device_property_read_u8(dev, "snps,rx-thr-num-pkt", 1571 &rx_thr_num_pkt); 1572 device_property_read_u8(dev, "snps,rx-max-burst", 1573 &rx_max_burst); 1574 device_property_read_u8(dev, "snps,tx-thr-num-pkt", 1575 &tx_thr_num_pkt); 1576 device_property_read_u8(dev, "snps,tx-max-burst", 1577 &tx_max_burst); 1578 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd", 1579 &rx_thr_num_pkt_prd); 1580 device_property_read_u8(dev, "snps,rx-max-burst-prd", 1581 &rx_max_burst_prd); 1582 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd", 1583 &tx_thr_num_pkt_prd); 1584 device_property_read_u8(dev, "snps,tx-max-burst-prd", 1585 &tx_max_burst_prd); 1586 dwc->do_fifo_resize = device_property_read_bool(dev, 1587 "tx-fifo-resize"); 1588 if (dwc->do_fifo_resize) 1589 device_property_read_u8(dev, "tx-fifo-max-num", 1590 &tx_fifo_resize_max_num); 1591 1592 dwc->disable_scramble_quirk = device_property_read_bool(dev, 1593 "snps,disable_scramble_quirk"); 1594 dwc->u2exit_lfps_quirk = device_property_read_bool(dev, 1595 "snps,u2exit_lfps_quirk"); 1596 dwc->u2ss_inp3_quirk = device_property_read_bool(dev, 1597 "snps,u2ss_inp3_quirk"); 1598 dwc->req_p1p2p3_quirk = device_property_read_bool(dev, 1599 "snps,req_p1p2p3_quirk"); 1600 dwc->del_p1p2p3_quirk = device_property_read_bool(dev, 1601 "snps,del_p1p2p3_quirk"); 1602 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, 1603 "snps,del_phy_power_chg_quirk"); 1604 dwc->lfps_filter_quirk = device_property_read_bool(dev, 1605 "snps,lfps_filter_quirk"); 1606 dwc->rx_detect_poll_quirk = device_property_read_bool(dev, 1607 "snps,rx_detect_poll_quirk"); 1608 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, 1609 "snps,dis_u3_susphy_quirk"); 1610 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, 1611 "snps,dis_u2_susphy_quirk"); 1612 dwc->dis_enblslpm_quirk = device_property_read_bool(dev, 1613 "snps,dis_enblslpm_quirk"); 1614 dwc->dis_u1_entry_quirk = device_property_read_bool(dev, 1615 "snps,dis-u1-entry-quirk"); 1616 dwc->dis_u2_entry_quirk = device_property_read_bool(dev, 1617 "snps,dis-u2-entry-quirk"); 1618 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, 1619 "snps,dis_rxdet_inp3_quirk"); 1620 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, 1621 "snps,dis-u2-freeclk-exists-quirk"); 1622 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, 1623 "snps,dis-del-phy-power-chg-quirk"); 1624 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev, 1625 "snps,dis-tx-ipgap-linecheck-quirk"); 1626 dwc->resume_hs_terminations = device_property_read_bool(dev, 1627 "snps,resume-hs-terminations"); 1628 dwc->ulpi_ext_vbus_drv = device_property_read_bool(dev, 1629 "snps,ulpi-ext-vbus-drv"); 1630 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev, 1631 "snps,parkmode-disable-ss-quirk"); 1632 dwc->parkmode_disable_hs_quirk = device_property_read_bool(dev, 1633 "snps,parkmode-disable-hs-quirk"); 1634 dwc->gfladj_refclk_lpm_sel = device_property_read_bool(dev, 1635 "snps,gfladj-refclk-lpm-sel-quirk"); 1636 1637 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, 1638 "snps,tx_de_emphasis_quirk"); 1639 device_property_read_u8(dev, "snps,tx_de_emphasis", 1640 &tx_de_emphasis); 1641 device_property_read_string(dev, "snps,hsphy_interface", 1642 &dwc->hsphy_interface); 1643 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", 1644 &dwc->fladj); 1645 device_property_read_u32(dev, "snps,ref-clock-period-ns", 1646 &dwc->ref_clk_per); 1647 1648 dwc->dis_metastability_quirk = device_property_read_bool(dev, 1649 "snps,dis_metastability_quirk"); 1650 1651 dwc->dis_split_quirk = device_property_read_bool(dev, 1652 "snps,dis-split-quirk"); 1653 1654 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 1655 dwc->tx_de_emphasis = tx_de_emphasis; 1656 1657 dwc->hird_threshold = hird_threshold; 1658 1659 dwc->rx_thr_num_pkt = rx_thr_num_pkt; 1660 dwc->rx_max_burst = rx_max_burst; 1661 1662 dwc->tx_thr_num_pkt = tx_thr_num_pkt; 1663 dwc->tx_max_burst = tx_max_burst; 1664 1665 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd; 1666 dwc->rx_max_burst_prd = rx_max_burst_prd; 1667 1668 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd; 1669 dwc->tx_max_burst_prd = tx_max_burst_prd; 1670 1671 dwc->imod_interval = 0; 1672 1673 dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num; 1674 } 1675 1676 /* check whether the core supports IMOD */ 1677 bool dwc3_has_imod(struct dwc3 *dwc) 1678 { 1679 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) || 1680 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) || 1681 DWC3_IP_IS(DWC32); 1682 } 1683 1684 static void dwc3_check_params(struct dwc3 *dwc) 1685 { 1686 struct device *dev = dwc->dev; 1687 unsigned int hwparam_gen = 1688 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3); 1689 1690 /* Check for proper value of imod_interval */ 1691 if (dwc->imod_interval && !dwc3_has_imod(dwc)) { 1692 dev_warn(dwc->dev, "Interrupt moderation not supported\n"); 1693 dwc->imod_interval = 0; 1694 } 1695 1696 /* 1697 * Workaround for STAR 9000961433 which affects only version 1698 * 3.00a of the DWC_usb3 core. This prevents the controller 1699 * interrupt from being masked while handling events. IMOD 1700 * allows us to work around this issue. Enable it for the 1701 * affected version. 1702 */ 1703 if (!dwc->imod_interval && 1704 DWC3_VER_IS(DWC3, 300A)) 1705 dwc->imod_interval = 1; 1706 1707 /* Check the maximum_speed parameter */ 1708 switch (dwc->maximum_speed) { 1709 case USB_SPEED_FULL: 1710 case USB_SPEED_HIGH: 1711 break; 1712 case USB_SPEED_SUPER: 1713 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) 1714 dev_warn(dev, "UDC doesn't support Gen 1\n"); 1715 break; 1716 case USB_SPEED_SUPER_PLUS: 1717 if ((DWC3_IP_IS(DWC32) && 1718 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) || 1719 (!DWC3_IP_IS(DWC32) && 1720 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) 1721 dev_warn(dev, "UDC doesn't support SSP\n"); 1722 break; 1723 default: 1724 dev_err(dev, "invalid maximum_speed parameter %d\n", 1725 dwc->maximum_speed); 1726 fallthrough; 1727 case USB_SPEED_UNKNOWN: 1728 switch (hwparam_gen) { 1729 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 1730 dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1731 break; 1732 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 1733 if (DWC3_IP_IS(DWC32)) 1734 dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1735 else 1736 dwc->maximum_speed = USB_SPEED_SUPER; 1737 break; 1738 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS: 1739 dwc->maximum_speed = USB_SPEED_HIGH; 1740 break; 1741 default: 1742 dwc->maximum_speed = USB_SPEED_SUPER; 1743 break; 1744 } 1745 break; 1746 } 1747 1748 /* 1749 * Currently the controller does not have visibility into the HW 1750 * parameter to determine the maximum number of lanes the HW supports. 1751 * If the number of lanes is not specified in the device property, then 1752 * set the default to support dual-lane for DWC_usb32 and single-lane 1753 * for DWC_usb31 for super-speed-plus. 1754 */ 1755 if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) { 1756 switch (dwc->max_ssp_rate) { 1757 case USB_SSP_GEN_2x1: 1758 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1) 1759 dev_warn(dev, "UDC only supports Gen 1\n"); 1760 break; 1761 case USB_SSP_GEN_1x2: 1762 case USB_SSP_GEN_2x2: 1763 if (DWC3_IP_IS(DWC31)) 1764 dev_warn(dev, "UDC only supports single lane\n"); 1765 break; 1766 case USB_SSP_GEN_UNKNOWN: 1767 default: 1768 switch (hwparam_gen) { 1769 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 1770 if (DWC3_IP_IS(DWC32)) 1771 dwc->max_ssp_rate = USB_SSP_GEN_2x2; 1772 else 1773 dwc->max_ssp_rate = USB_SSP_GEN_2x1; 1774 break; 1775 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 1776 if (DWC3_IP_IS(DWC32)) 1777 dwc->max_ssp_rate = USB_SSP_GEN_1x2; 1778 break; 1779 } 1780 break; 1781 } 1782 } 1783 } 1784 1785 static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc) 1786 { 1787 struct device *dev = dwc->dev; 1788 struct device_node *np_phy; 1789 struct extcon_dev *edev = NULL; 1790 const char *name; 1791 1792 if (device_property_read_bool(dev, "extcon")) 1793 return extcon_get_edev_by_phandle(dev, 0); 1794 1795 /* 1796 * Device tree platforms should get extcon via phandle. 1797 * On ACPI platforms, we get the name from a device property. 1798 * This device property is for kernel internal use only and 1799 * is expected to be set by the glue code. 1800 */ 1801 if (device_property_read_string(dev, "linux,extcon-name", &name) == 0) 1802 return extcon_get_extcon_dev(name); 1803 1804 /* 1805 * Check explicitly if "usb-role-switch" is used since 1806 * extcon_find_edev_by_node() can not be used to check the absence of 1807 * an extcon device. In the absence of an device it will always return 1808 * EPROBE_DEFER. 1809 */ 1810 if (IS_ENABLED(CONFIG_USB_ROLE_SWITCH) && 1811 device_property_read_bool(dev, "usb-role-switch")) 1812 return NULL; 1813 1814 /* 1815 * Try to get an extcon device from the USB PHY controller's "port" 1816 * node. Check if it has the "port" node first, to avoid printing the 1817 * error message from underlying code, as it's a valid case: extcon 1818 * device (and "port" node) may be missing in case of "usb-role-switch" 1819 * or OTG mode. 1820 */ 1821 np_phy = of_parse_phandle(dev->of_node, "phys", 0); 1822 if (of_graph_is_present(np_phy)) { 1823 struct device_node *np_conn; 1824 1825 np_conn = of_graph_get_remote_node(np_phy, -1, -1); 1826 if (np_conn) 1827 edev = extcon_find_edev_by_node(np_conn); 1828 of_node_put(np_conn); 1829 } 1830 of_node_put(np_phy); 1831 1832 return edev; 1833 } 1834 1835 static int dwc3_get_clocks(struct dwc3 *dwc) 1836 { 1837 struct device *dev = dwc->dev; 1838 1839 if (!dev->of_node) 1840 return 0; 1841 1842 /* 1843 * Clocks are optional, but new DT platforms should support all clocks 1844 * as required by the DT-binding. 1845 * Some devices have different clock names in legacy device trees, 1846 * check for them to retain backwards compatibility. 1847 */ 1848 dwc->bus_clk = devm_clk_get_optional(dev, "bus_early"); 1849 if (IS_ERR(dwc->bus_clk)) { 1850 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk), 1851 "could not get bus clock\n"); 1852 } 1853 1854 if (dwc->bus_clk == NULL) { 1855 dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk"); 1856 if (IS_ERR(dwc->bus_clk)) { 1857 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk), 1858 "could not get bus clock\n"); 1859 } 1860 } 1861 1862 dwc->ref_clk = devm_clk_get_optional(dev, "ref"); 1863 if (IS_ERR(dwc->ref_clk)) { 1864 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk), 1865 "could not get ref clock\n"); 1866 } 1867 1868 if (dwc->ref_clk == NULL) { 1869 dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk"); 1870 if (IS_ERR(dwc->ref_clk)) { 1871 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk), 1872 "could not get ref clock\n"); 1873 } 1874 } 1875 1876 dwc->susp_clk = devm_clk_get_optional(dev, "suspend"); 1877 if (IS_ERR(dwc->susp_clk)) { 1878 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk), 1879 "could not get suspend clock\n"); 1880 } 1881 1882 if (dwc->susp_clk == NULL) { 1883 dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk"); 1884 if (IS_ERR(dwc->susp_clk)) { 1885 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk), 1886 "could not get suspend clock\n"); 1887 } 1888 } 1889 1890 /* specific to Rockchip RK3588 */ 1891 dwc->utmi_clk = devm_clk_get_optional(dev, "utmi"); 1892 if (IS_ERR(dwc->utmi_clk)) { 1893 return dev_err_probe(dev, PTR_ERR(dwc->utmi_clk), 1894 "could not get utmi clock\n"); 1895 } 1896 1897 /* specific to Rockchip RK3588 */ 1898 dwc->pipe_clk = devm_clk_get_optional(dev, "pipe"); 1899 if (IS_ERR(dwc->pipe_clk)) { 1900 return dev_err_probe(dev, PTR_ERR(dwc->pipe_clk), 1901 "could not get pipe clock\n"); 1902 } 1903 1904 return 0; 1905 } 1906 1907 static int dwc3_probe(struct platform_device *pdev) 1908 { 1909 struct device *dev = &pdev->dev; 1910 struct resource *res, dwc_res; 1911 void __iomem *regs; 1912 struct dwc3 *dwc; 1913 int ret; 1914 1915 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 1916 if (!dwc) 1917 return -ENOMEM; 1918 1919 dwc->dev = dev; 1920 1921 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1922 if (!res) { 1923 dev_err(dev, "missing memory resource\n"); 1924 return -ENODEV; 1925 } 1926 1927 dwc->xhci_resources[0].start = res->start; 1928 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + 1929 DWC3_XHCI_REGS_END; 1930 dwc->xhci_resources[0].flags = res->flags; 1931 dwc->xhci_resources[0].name = res->name; 1932 1933 /* 1934 * Request memory region but exclude xHCI regs, 1935 * since it will be requested by the xhci-plat driver. 1936 */ 1937 dwc_res = *res; 1938 dwc_res.start += DWC3_GLOBALS_REGS_START; 1939 1940 if (dev->of_node) { 1941 struct device_node *parent = of_get_parent(dev->of_node); 1942 1943 if (of_device_is_compatible(parent, "realtek,rtd-dwc3")) { 1944 dwc_res.start -= DWC3_GLOBALS_REGS_START; 1945 dwc_res.start += DWC3_RTK_RTD_GLOBALS_REGS_START; 1946 } 1947 1948 of_node_put(parent); 1949 } 1950 1951 regs = devm_ioremap_resource(dev, &dwc_res); 1952 if (IS_ERR(regs)) 1953 return PTR_ERR(regs); 1954 1955 dwc->regs = regs; 1956 dwc->regs_size = resource_size(&dwc_res); 1957 1958 dwc3_get_properties(dwc); 1959 1960 dwc->reset = devm_reset_control_array_get_optional_shared(dev); 1961 if (IS_ERR(dwc->reset)) { 1962 ret = PTR_ERR(dwc->reset); 1963 goto err_put_psy; 1964 } 1965 1966 ret = dwc3_get_clocks(dwc); 1967 if (ret) 1968 goto err_put_psy; 1969 1970 ret = reset_control_deassert(dwc->reset); 1971 if (ret) 1972 goto err_put_psy; 1973 1974 ret = dwc3_clk_enable(dwc); 1975 if (ret) 1976 goto err_assert_reset; 1977 1978 if (!dwc3_core_is_valid(dwc)) { 1979 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 1980 ret = -ENODEV; 1981 goto err_disable_clks; 1982 } 1983 1984 platform_set_drvdata(pdev, dwc); 1985 dwc3_cache_hwparams(dwc); 1986 1987 if (!dwc->sysdev_is_parent && 1988 DWC3_GHWPARAMS0_AWIDTH(dwc->hwparams.hwparams0) == 64) { 1989 ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64)); 1990 if (ret) 1991 goto err_disable_clks; 1992 } 1993 1994 spin_lock_init(&dwc->lock); 1995 mutex_init(&dwc->mutex); 1996 1997 pm_runtime_get_noresume(dev); 1998 pm_runtime_set_active(dev); 1999 pm_runtime_use_autosuspend(dev); 2000 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); 2001 pm_runtime_enable(dev); 2002 2003 pm_runtime_forbid(dev); 2004 2005 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 2006 if (ret) { 2007 dev_err(dwc->dev, "failed to allocate event buffers\n"); 2008 ret = -ENOMEM; 2009 goto err_allow_rpm; 2010 } 2011 2012 dwc->edev = dwc3_get_extcon(dwc); 2013 if (IS_ERR(dwc->edev)) { 2014 ret = dev_err_probe(dwc->dev, PTR_ERR(dwc->edev), "failed to get extcon\n"); 2015 goto err_free_event_buffers; 2016 } 2017 2018 ret = dwc3_get_dr_mode(dwc); 2019 if (ret) 2020 goto err_free_event_buffers; 2021 2022 ret = dwc3_core_init(dwc); 2023 if (ret) { 2024 dev_err_probe(dev, ret, "failed to initialize core\n"); 2025 goto err_free_event_buffers; 2026 } 2027 2028 dwc3_check_params(dwc); 2029 dwc3_debugfs_init(dwc); 2030 2031 ret = dwc3_core_init_mode(dwc); 2032 if (ret) 2033 goto err_exit_debugfs; 2034 2035 pm_runtime_put(dev); 2036 2037 return 0; 2038 2039 err_exit_debugfs: 2040 dwc3_debugfs_exit(dwc); 2041 dwc3_event_buffers_cleanup(dwc); 2042 dwc3_phy_power_off(dwc); 2043 dwc3_phy_exit(dwc); 2044 dwc3_ulpi_exit(dwc); 2045 err_free_event_buffers: 2046 dwc3_free_event_buffers(dwc); 2047 err_allow_rpm: 2048 pm_runtime_allow(dev); 2049 pm_runtime_disable(dev); 2050 pm_runtime_dont_use_autosuspend(dev); 2051 pm_runtime_set_suspended(dev); 2052 pm_runtime_put_noidle(dev); 2053 err_disable_clks: 2054 dwc3_clk_disable(dwc); 2055 err_assert_reset: 2056 reset_control_assert(dwc->reset); 2057 err_put_psy: 2058 if (dwc->usb_psy) 2059 power_supply_put(dwc->usb_psy); 2060 2061 return ret; 2062 } 2063 2064 static void dwc3_remove(struct platform_device *pdev) 2065 { 2066 struct dwc3 *dwc = platform_get_drvdata(pdev); 2067 2068 pm_runtime_get_sync(&pdev->dev); 2069 2070 dwc3_core_exit_mode(dwc); 2071 dwc3_debugfs_exit(dwc); 2072 2073 dwc3_core_exit(dwc); 2074 dwc3_ulpi_exit(dwc); 2075 2076 pm_runtime_allow(&pdev->dev); 2077 pm_runtime_disable(&pdev->dev); 2078 pm_runtime_dont_use_autosuspend(&pdev->dev); 2079 pm_runtime_put_noidle(&pdev->dev); 2080 /* 2081 * HACK: Clear the driver data, which is currently accessed by parent 2082 * glue drivers, before allowing the parent to suspend. 2083 */ 2084 platform_set_drvdata(pdev, NULL); 2085 pm_runtime_set_suspended(&pdev->dev); 2086 2087 dwc3_free_event_buffers(dwc); 2088 2089 if (dwc->usb_psy) 2090 power_supply_put(dwc->usb_psy); 2091 } 2092 2093 #ifdef CONFIG_PM 2094 static int dwc3_core_init_for_resume(struct dwc3 *dwc) 2095 { 2096 int ret; 2097 2098 ret = reset_control_deassert(dwc->reset); 2099 if (ret) 2100 return ret; 2101 2102 ret = dwc3_clk_enable(dwc); 2103 if (ret) 2104 goto assert_reset; 2105 2106 ret = dwc3_core_init(dwc); 2107 if (ret) 2108 goto disable_clks; 2109 2110 return 0; 2111 2112 disable_clks: 2113 dwc3_clk_disable(dwc); 2114 assert_reset: 2115 reset_control_assert(dwc->reset); 2116 2117 return ret; 2118 } 2119 2120 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) 2121 { 2122 unsigned long flags; 2123 u32 reg; 2124 2125 switch (dwc->current_dr_role) { 2126 case DWC3_GCTL_PRTCAP_DEVICE: 2127 if (pm_runtime_suspended(dwc->dev)) 2128 break; 2129 dwc3_gadget_suspend(dwc); 2130 synchronize_irq(dwc->irq_gadget); 2131 dwc3_core_exit(dwc); 2132 break; 2133 case DWC3_GCTL_PRTCAP_HOST: 2134 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) { 2135 dwc3_core_exit(dwc); 2136 break; 2137 } 2138 2139 /* Let controller to suspend HSPHY before PHY driver suspends */ 2140 if (dwc->dis_u2_susphy_quirk || 2141 dwc->dis_enblslpm_quirk) { 2142 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 2143 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM | 2144 DWC3_GUSB2PHYCFG_SUSPHY; 2145 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 2146 2147 /* Give some time for USB2 PHY to suspend */ 2148 usleep_range(5000, 6000); 2149 } 2150 2151 phy_pm_runtime_put_sync(dwc->usb2_generic_phy); 2152 phy_pm_runtime_put_sync(dwc->usb3_generic_phy); 2153 break; 2154 case DWC3_GCTL_PRTCAP_OTG: 2155 /* do nothing during runtime_suspend */ 2156 if (PMSG_IS_AUTO(msg)) 2157 break; 2158 2159 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 2160 spin_lock_irqsave(&dwc->lock, flags); 2161 dwc3_gadget_suspend(dwc); 2162 spin_unlock_irqrestore(&dwc->lock, flags); 2163 synchronize_irq(dwc->irq_gadget); 2164 } 2165 2166 dwc3_otg_exit(dwc); 2167 dwc3_core_exit(dwc); 2168 break; 2169 default: 2170 /* do nothing */ 2171 break; 2172 } 2173 2174 return 0; 2175 } 2176 2177 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) 2178 { 2179 unsigned long flags; 2180 int ret; 2181 u32 reg; 2182 2183 switch (dwc->current_dr_role) { 2184 case DWC3_GCTL_PRTCAP_DEVICE: 2185 ret = dwc3_core_init_for_resume(dwc); 2186 if (ret) 2187 return ret; 2188 2189 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 2190 dwc3_gadget_resume(dwc); 2191 break; 2192 case DWC3_GCTL_PRTCAP_HOST: 2193 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) { 2194 ret = dwc3_core_init_for_resume(dwc); 2195 if (ret) 2196 return ret; 2197 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 2198 break; 2199 } 2200 /* Restore GUSB2PHYCFG bits that were modified in suspend */ 2201 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 2202 if (dwc->dis_u2_susphy_quirk) 2203 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 2204 2205 if (dwc->dis_enblslpm_quirk) 2206 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 2207 2208 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 2209 2210 phy_pm_runtime_get_sync(dwc->usb2_generic_phy); 2211 phy_pm_runtime_get_sync(dwc->usb3_generic_phy); 2212 break; 2213 case DWC3_GCTL_PRTCAP_OTG: 2214 /* nothing to do on runtime_resume */ 2215 if (PMSG_IS_AUTO(msg)) 2216 break; 2217 2218 ret = dwc3_core_init_for_resume(dwc); 2219 if (ret) 2220 return ret; 2221 2222 dwc3_set_prtcap(dwc, dwc->current_dr_role); 2223 2224 dwc3_otg_init(dwc); 2225 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) { 2226 dwc3_otg_host_init(dwc); 2227 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 2228 spin_lock_irqsave(&dwc->lock, flags); 2229 dwc3_gadget_resume(dwc); 2230 spin_unlock_irqrestore(&dwc->lock, flags); 2231 } 2232 2233 break; 2234 default: 2235 /* do nothing */ 2236 break; 2237 } 2238 2239 return 0; 2240 } 2241 2242 static int dwc3_runtime_checks(struct dwc3 *dwc) 2243 { 2244 switch (dwc->current_dr_role) { 2245 case DWC3_GCTL_PRTCAP_DEVICE: 2246 if (dwc->connected) 2247 return -EBUSY; 2248 break; 2249 case DWC3_GCTL_PRTCAP_HOST: 2250 default: 2251 /* do nothing */ 2252 break; 2253 } 2254 2255 return 0; 2256 } 2257 2258 static int dwc3_runtime_suspend(struct device *dev) 2259 { 2260 struct dwc3 *dwc = dev_get_drvdata(dev); 2261 int ret; 2262 2263 if (dwc3_runtime_checks(dwc)) 2264 return -EBUSY; 2265 2266 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND); 2267 if (ret) 2268 return ret; 2269 2270 return 0; 2271 } 2272 2273 static int dwc3_runtime_resume(struct device *dev) 2274 { 2275 struct dwc3 *dwc = dev_get_drvdata(dev); 2276 int ret; 2277 2278 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME); 2279 if (ret) 2280 return ret; 2281 2282 switch (dwc->current_dr_role) { 2283 case DWC3_GCTL_PRTCAP_DEVICE: 2284 dwc3_gadget_process_pending_events(dwc); 2285 break; 2286 case DWC3_GCTL_PRTCAP_HOST: 2287 default: 2288 /* do nothing */ 2289 break; 2290 } 2291 2292 pm_runtime_mark_last_busy(dev); 2293 2294 return 0; 2295 } 2296 2297 static int dwc3_runtime_idle(struct device *dev) 2298 { 2299 struct dwc3 *dwc = dev_get_drvdata(dev); 2300 2301 switch (dwc->current_dr_role) { 2302 case DWC3_GCTL_PRTCAP_DEVICE: 2303 if (dwc3_runtime_checks(dwc)) 2304 return -EBUSY; 2305 break; 2306 case DWC3_GCTL_PRTCAP_HOST: 2307 default: 2308 /* do nothing */ 2309 break; 2310 } 2311 2312 pm_runtime_mark_last_busy(dev); 2313 pm_runtime_autosuspend(dev); 2314 2315 return 0; 2316 } 2317 #endif /* CONFIG_PM */ 2318 2319 #ifdef CONFIG_PM_SLEEP 2320 static int dwc3_suspend(struct device *dev) 2321 { 2322 struct dwc3 *dwc = dev_get_drvdata(dev); 2323 int ret; 2324 2325 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND); 2326 if (ret) 2327 return ret; 2328 2329 pinctrl_pm_select_sleep_state(dev); 2330 2331 return 0; 2332 } 2333 2334 static int dwc3_resume(struct device *dev) 2335 { 2336 struct dwc3 *dwc = dev_get_drvdata(dev); 2337 int ret; 2338 2339 pinctrl_pm_select_default_state(dev); 2340 2341 ret = dwc3_resume_common(dwc, PMSG_RESUME); 2342 if (ret) 2343 return ret; 2344 2345 pm_runtime_disable(dev); 2346 pm_runtime_set_active(dev); 2347 pm_runtime_enable(dev); 2348 2349 return 0; 2350 } 2351 2352 static void dwc3_complete(struct device *dev) 2353 { 2354 struct dwc3 *dwc = dev_get_drvdata(dev); 2355 u32 reg; 2356 2357 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST && 2358 dwc->dis_split_quirk) { 2359 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 2360 reg |= DWC3_GUCTL3_SPLITDISABLE; 2361 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 2362 } 2363 } 2364 #else 2365 #define dwc3_complete NULL 2366 #endif /* CONFIG_PM_SLEEP */ 2367 2368 static const struct dev_pm_ops dwc3_dev_pm_ops = { 2369 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) 2370 .complete = dwc3_complete, 2371 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, 2372 dwc3_runtime_idle) 2373 }; 2374 2375 #ifdef CONFIG_OF 2376 static const struct of_device_id of_dwc3_match[] = { 2377 { 2378 .compatible = "snps,dwc3" 2379 }, 2380 { 2381 .compatible = "synopsys,dwc3" 2382 }, 2383 { }, 2384 }; 2385 MODULE_DEVICE_TABLE(of, of_dwc3_match); 2386 #endif 2387 2388 #ifdef CONFIG_ACPI 2389 2390 #define ACPI_ID_INTEL_BSW "808622B7" 2391 2392 static const struct acpi_device_id dwc3_acpi_match[] = { 2393 { ACPI_ID_INTEL_BSW, 0 }, 2394 { }, 2395 }; 2396 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); 2397 #endif 2398 2399 static struct platform_driver dwc3_driver = { 2400 .probe = dwc3_probe, 2401 .remove_new = dwc3_remove, 2402 .driver = { 2403 .name = "dwc3", 2404 .of_match_table = of_match_ptr(of_dwc3_match), 2405 .acpi_match_table = ACPI_PTR(dwc3_acpi_match), 2406 .pm = &dwc3_dev_pm_ops, 2407 }, 2408 }; 2409 2410 module_platform_driver(dwc3_driver); 2411 2412 MODULE_ALIAS("platform:dwc3"); 2413 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 2414 MODULE_LICENSE("GPL v2"); 2415 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 2416