1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * core.c - DesignWare USB3 DRD Controller Core file 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/version.h> 13 #include <linux/module.h> 14 #include <linux/kernel.h> 15 #include <linux/slab.h> 16 #include <linux/spinlock.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/interrupt.h> 20 #include <linux/ioport.h> 21 #include <linux/io.h> 22 #include <linux/list.h> 23 #include <linux/delay.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/of.h> 26 #include <linux/of_graph.h> 27 #include <linux/acpi.h> 28 #include <linux/pinctrl/consumer.h> 29 #include <linux/reset.h> 30 #include <linux/bitfield.h> 31 32 #include <linux/usb/ch9.h> 33 #include <linux/usb/gadget.h> 34 #include <linux/usb/of.h> 35 #include <linux/usb/otg.h> 36 37 #include "core.h" 38 #include "gadget.h" 39 #include "io.h" 40 41 #include "debug.h" 42 #include "../host/xhci-ext-caps.h" 43 44 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ 45 46 /** 47 * dwc3_get_dr_mode - Validates and sets dr_mode 48 * @dwc: pointer to our context structure 49 */ 50 static int dwc3_get_dr_mode(struct dwc3 *dwc) 51 { 52 enum usb_dr_mode mode; 53 struct device *dev = dwc->dev; 54 unsigned int hw_mode; 55 56 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 57 dwc->dr_mode = USB_DR_MODE_OTG; 58 59 mode = dwc->dr_mode; 60 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 61 62 switch (hw_mode) { 63 case DWC3_GHWPARAMS0_MODE_GADGET: 64 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) { 65 dev_err(dev, 66 "Controller does not support host mode.\n"); 67 return -EINVAL; 68 } 69 mode = USB_DR_MODE_PERIPHERAL; 70 break; 71 case DWC3_GHWPARAMS0_MODE_HOST: 72 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { 73 dev_err(dev, 74 "Controller does not support device mode.\n"); 75 return -EINVAL; 76 } 77 mode = USB_DR_MODE_HOST; 78 break; 79 default: 80 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 81 mode = USB_DR_MODE_HOST; 82 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 83 mode = USB_DR_MODE_PERIPHERAL; 84 85 /* 86 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG 87 * mode. If the controller supports DRD but the dr_mode is not 88 * specified or set to OTG, then set the mode to peripheral. 89 */ 90 if (mode == USB_DR_MODE_OTG && !dwc->edev && 91 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) || 92 !device_property_read_bool(dwc->dev, "usb-role-switch")) && 93 !DWC3_VER_IS_PRIOR(DWC3, 330A)) 94 mode = USB_DR_MODE_PERIPHERAL; 95 } 96 97 if (mode != dwc->dr_mode) { 98 dev_warn(dev, 99 "Configuration mismatch. dr_mode forced to %s\n", 100 mode == USB_DR_MODE_HOST ? "host" : "gadget"); 101 102 dwc->dr_mode = mode; 103 } 104 105 return 0; 106 } 107 108 void dwc3_enable_susphy(struct dwc3 *dwc, bool enable) 109 { 110 u32 reg; 111 int i; 112 113 for (i = 0; i < dwc->num_usb3_ports; i++) { 114 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(i)); 115 if (enable && !dwc->dis_u3_susphy_quirk) 116 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 117 else 118 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 119 120 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(i), reg); 121 } 122 123 for (i = 0; i < dwc->num_usb2_ports; i++) { 124 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i)); 125 if (enable && !dwc->dis_u2_susphy_quirk) 126 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 127 else 128 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 129 130 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg); 131 } 132 } 133 134 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) 135 { 136 u32 reg; 137 138 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 139 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 140 reg |= DWC3_GCTL_PRTCAPDIR(mode); 141 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 142 143 dwc->current_dr_role = mode; 144 } 145 146 static void __dwc3_set_mode(struct work_struct *work) 147 { 148 struct dwc3 *dwc = work_to_dwc(work); 149 unsigned long flags; 150 int ret; 151 u32 reg; 152 u32 desired_dr_role; 153 int i; 154 155 mutex_lock(&dwc->mutex); 156 spin_lock_irqsave(&dwc->lock, flags); 157 desired_dr_role = dwc->desired_dr_role; 158 spin_unlock_irqrestore(&dwc->lock, flags); 159 160 pm_runtime_get_sync(dwc->dev); 161 162 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG) 163 dwc3_otg_update(dwc, 0); 164 165 if (!desired_dr_role) 166 goto out; 167 168 if (desired_dr_role == dwc->current_dr_role) 169 goto out; 170 171 if (desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev) 172 goto out; 173 174 switch (dwc->current_dr_role) { 175 case DWC3_GCTL_PRTCAP_HOST: 176 dwc3_host_exit(dwc); 177 break; 178 case DWC3_GCTL_PRTCAP_DEVICE: 179 dwc3_gadget_exit(dwc); 180 dwc3_event_buffers_cleanup(dwc); 181 break; 182 case DWC3_GCTL_PRTCAP_OTG: 183 dwc3_otg_exit(dwc); 184 spin_lock_irqsave(&dwc->lock, flags); 185 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE; 186 spin_unlock_irqrestore(&dwc->lock, flags); 187 dwc3_otg_update(dwc, 1); 188 break; 189 default: 190 break; 191 } 192 193 /* 194 * When current_dr_role is not set, there's no role switching. 195 * Only perform GCTL.CoreSoftReset when there's DRD role switching. 196 */ 197 if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) || 198 DWC3_VER_IS_PRIOR(DWC31, 190A)) && 199 desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) { 200 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 201 reg |= DWC3_GCTL_CORESOFTRESET; 202 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 203 204 /* 205 * Wait for internal clocks to synchronized. DWC_usb31 and 206 * DWC_usb32 may need at least 50ms (less for DWC_usb3). To 207 * keep it consistent across different IPs, let's wait up to 208 * 100ms before clearing GCTL.CORESOFTRESET. 209 */ 210 msleep(100); 211 212 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 213 reg &= ~DWC3_GCTL_CORESOFTRESET; 214 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 215 } 216 217 spin_lock_irqsave(&dwc->lock, flags); 218 219 dwc3_set_prtcap(dwc, desired_dr_role); 220 221 spin_unlock_irqrestore(&dwc->lock, flags); 222 223 switch (desired_dr_role) { 224 case DWC3_GCTL_PRTCAP_HOST: 225 ret = dwc3_host_init(dwc); 226 if (ret) { 227 dev_err(dwc->dev, "failed to initialize host\n"); 228 } else { 229 if (dwc->usb2_phy) 230 otg_set_vbus(dwc->usb2_phy->otg, true); 231 232 for (i = 0; i < dwc->num_usb2_ports; i++) 233 phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST); 234 for (i = 0; i < dwc->num_usb3_ports; i++) 235 phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST); 236 237 if (dwc->dis_split_quirk) { 238 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 239 reg |= DWC3_GUCTL3_SPLITDISABLE; 240 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 241 } 242 } 243 break; 244 case DWC3_GCTL_PRTCAP_DEVICE: 245 dwc3_core_soft_reset(dwc); 246 247 dwc3_event_buffers_setup(dwc); 248 249 if (dwc->usb2_phy) 250 otg_set_vbus(dwc->usb2_phy->otg, false); 251 phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE); 252 phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE); 253 254 ret = dwc3_gadget_init(dwc); 255 if (ret) 256 dev_err(dwc->dev, "failed to initialize peripheral\n"); 257 break; 258 case DWC3_GCTL_PRTCAP_OTG: 259 dwc3_otg_init(dwc); 260 dwc3_otg_update(dwc, 0); 261 break; 262 default: 263 break; 264 } 265 266 out: 267 pm_runtime_mark_last_busy(dwc->dev); 268 pm_runtime_put_autosuspend(dwc->dev); 269 mutex_unlock(&dwc->mutex); 270 } 271 272 void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 273 { 274 unsigned long flags; 275 276 if (dwc->dr_mode != USB_DR_MODE_OTG) 277 return; 278 279 spin_lock_irqsave(&dwc->lock, flags); 280 dwc->desired_dr_role = mode; 281 spin_unlock_irqrestore(&dwc->lock, flags); 282 283 queue_work(system_freezable_wq, &dwc->drd_work); 284 } 285 286 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) 287 { 288 struct dwc3 *dwc = dep->dwc; 289 u32 reg; 290 291 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, 292 DWC3_GDBGFIFOSPACE_NUM(dep->number) | 293 DWC3_GDBGFIFOSPACE_TYPE(type)); 294 295 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); 296 297 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); 298 } 299 300 /** 301 * dwc3_core_soft_reset - Issues core soft reset and PHY reset 302 * @dwc: pointer to our context structure 303 */ 304 int dwc3_core_soft_reset(struct dwc3 *dwc) 305 { 306 u32 reg; 307 int retries = 1000; 308 309 /* 310 * We're resetting only the device side because, if we're in host mode, 311 * XHCI driver will reset the host block. If dwc3 was configured for 312 * host-only mode, then we can return early. 313 */ 314 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) 315 return 0; 316 317 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 318 reg |= DWC3_DCTL_CSFTRST; 319 reg &= ~DWC3_DCTL_RUN_STOP; 320 dwc3_gadget_dctl_write_safe(dwc, reg); 321 322 /* 323 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit 324 * is cleared only after all the clocks are synchronized. This can 325 * take a little more than 50ms. Set the polling rate at 20ms 326 * for 10 times instead. 327 */ 328 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 329 retries = 10; 330 331 do { 332 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 333 if (!(reg & DWC3_DCTL_CSFTRST)) 334 goto done; 335 336 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 337 msleep(20); 338 else 339 udelay(1); 340 } while (--retries); 341 342 dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n"); 343 return -ETIMEDOUT; 344 345 done: 346 /* 347 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit 348 * is cleared, we must wait at least 50ms before accessing the PHY 349 * domain (synchronization delay). 350 */ 351 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A)) 352 msleep(50); 353 354 return 0; 355 } 356 357 /* 358 * dwc3_frame_length_adjustment - Adjusts frame length if required 359 * @dwc3: Pointer to our controller context structure 360 */ 361 static void dwc3_frame_length_adjustment(struct dwc3 *dwc) 362 { 363 u32 reg; 364 u32 dft; 365 366 if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 367 return; 368 369 if (dwc->fladj == 0) 370 return; 371 372 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 373 dft = reg & DWC3_GFLADJ_30MHZ_MASK; 374 if (dft != dwc->fladj) { 375 reg &= ~DWC3_GFLADJ_30MHZ_MASK; 376 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; 377 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 378 } 379 } 380 381 /** 382 * dwc3_ref_clk_period - Reference clock period configuration 383 * Default reference clock period depends on hardware 384 * configuration. For systems with reference clock that differs 385 * from the default, this will set clock period in DWC3_GUCTL 386 * register. 387 * @dwc: Pointer to our controller context structure 388 */ 389 static void dwc3_ref_clk_period(struct dwc3 *dwc) 390 { 391 unsigned long period; 392 unsigned long fladj; 393 unsigned long decr; 394 unsigned long rate; 395 u32 reg; 396 397 if (dwc->ref_clk) { 398 rate = clk_get_rate(dwc->ref_clk); 399 if (!rate) 400 return; 401 period = NSEC_PER_SEC / rate; 402 } else if (dwc->ref_clk_per) { 403 period = dwc->ref_clk_per; 404 rate = NSEC_PER_SEC / period; 405 } else { 406 return; 407 } 408 409 reg = dwc3_readl(dwc->regs, DWC3_GUCTL); 410 reg &= ~DWC3_GUCTL_REFCLKPER_MASK; 411 reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period); 412 dwc3_writel(dwc->regs, DWC3_GUCTL, reg); 413 414 if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 415 return; 416 417 /* 418 * The calculation below is 419 * 420 * 125000 * (NSEC_PER_SEC / (rate * period) - 1) 421 * 422 * but rearranged for fixed-point arithmetic. The division must be 423 * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and 424 * neither does rate * period). 425 * 426 * Note that rate * period ~= NSEC_PER_SECOND, minus the number of 427 * nanoseconds of error caused by the truncation which happened during 428 * the division when calculating rate or period (whichever one was 429 * derived from the other). We first calculate the relative error, then 430 * scale it to units of 8 ppm. 431 */ 432 fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period); 433 fladj -= 125000; 434 435 /* 436 * The documented 240MHz constant is scaled by 2 to get PLS1 as well. 437 */ 438 decr = 480000000 / rate; 439 440 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 441 reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK 442 & ~DWC3_GFLADJ_240MHZDECR 443 & ~DWC3_GFLADJ_240MHZDECR_PLS1; 444 reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj) 445 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1) 446 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1); 447 448 if (dwc->gfladj_refclk_lpm_sel) 449 reg |= DWC3_GFLADJ_REFCLK_LPM_SEL; 450 451 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 452 } 453 454 /** 455 * dwc3_free_one_event_buffer - Frees one event buffer 456 * @dwc: Pointer to our controller context structure 457 * @evt: Pointer to event buffer to be freed 458 */ 459 static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 460 struct dwc3_event_buffer *evt) 461 { 462 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma); 463 } 464 465 /** 466 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 467 * @dwc: Pointer to our controller context structure 468 * @length: size of the event buffer 469 * 470 * Returns a pointer to the allocated event buffer structure on success 471 * otherwise ERR_PTR(errno). 472 */ 473 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 474 unsigned int length) 475 { 476 struct dwc3_event_buffer *evt; 477 478 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 479 if (!evt) 480 return ERR_PTR(-ENOMEM); 481 482 evt->dwc = dwc; 483 evt->length = length; 484 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL); 485 if (!evt->cache) 486 return ERR_PTR(-ENOMEM); 487 488 evt->buf = dma_alloc_coherent(dwc->sysdev, length, 489 &evt->dma, GFP_KERNEL); 490 if (!evt->buf) 491 return ERR_PTR(-ENOMEM); 492 493 return evt; 494 } 495 496 /** 497 * dwc3_free_event_buffers - frees all allocated event buffers 498 * @dwc: Pointer to our controller context structure 499 */ 500 static void dwc3_free_event_buffers(struct dwc3 *dwc) 501 { 502 struct dwc3_event_buffer *evt; 503 504 evt = dwc->ev_buf; 505 if (evt) 506 dwc3_free_one_event_buffer(dwc, evt); 507 } 508 509 /** 510 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 511 * @dwc: pointer to our controller context structure 512 * @length: size of event buffer 513 * 514 * Returns 0 on success otherwise negative errno. In the error case, dwc 515 * may contain some buffers allocated but not all which were requested. 516 */ 517 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length) 518 { 519 struct dwc3_event_buffer *evt; 520 unsigned int hw_mode; 521 522 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 523 if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) { 524 dwc->ev_buf = NULL; 525 return 0; 526 } 527 528 evt = dwc3_alloc_one_event_buffer(dwc, length); 529 if (IS_ERR(evt)) { 530 dev_err(dwc->dev, "can't allocate event buffer\n"); 531 return PTR_ERR(evt); 532 } 533 dwc->ev_buf = evt; 534 535 return 0; 536 } 537 538 /** 539 * dwc3_event_buffers_setup - setup our allocated event buffers 540 * @dwc: pointer to our controller context structure 541 * 542 * Returns 0 on success otherwise negative errno. 543 */ 544 int dwc3_event_buffers_setup(struct dwc3 *dwc) 545 { 546 struct dwc3_event_buffer *evt; 547 548 if (!dwc->ev_buf) 549 return 0; 550 551 evt = dwc->ev_buf; 552 evt->lpos = 0; 553 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 554 lower_32_bits(evt->dma)); 555 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 556 upper_32_bits(evt->dma)); 557 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), 558 DWC3_GEVNTSIZ_SIZE(evt->length)); 559 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 560 561 return 0; 562 } 563 564 void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 565 { 566 struct dwc3_event_buffer *evt; 567 u32 reg; 568 569 if (!dwc->ev_buf) 570 return; 571 /* 572 * Exynos platforms may not be able to access event buffer if the 573 * controller failed to halt on dwc3_core_exit(). 574 */ 575 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 576 if (!(reg & DWC3_DSTS_DEVCTRLHLT)) 577 return; 578 579 evt = dwc->ev_buf; 580 581 evt->lpos = 0; 582 583 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); 584 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); 585 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK 586 | DWC3_GEVNTSIZ_SIZE(0)); 587 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 588 } 589 590 static void dwc3_core_num_eps(struct dwc3 *dwc) 591 { 592 struct dwc3_hwparams *parms = &dwc->hwparams; 593 594 dwc->num_eps = DWC3_NUM_EPS(parms); 595 } 596 597 static void dwc3_cache_hwparams(struct dwc3 *dwc) 598 { 599 struct dwc3_hwparams *parms = &dwc->hwparams; 600 601 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 602 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 603 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 604 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 605 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 606 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 607 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 608 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 609 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 610 611 if (DWC3_IP_IS(DWC32)) 612 parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9); 613 } 614 615 static void dwc3_config_soc_bus(struct dwc3 *dwc) 616 { 617 if (dwc->gsbuscfg0_reqinfo != DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED) { 618 u32 reg; 619 620 reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); 621 reg &= ~DWC3_GSBUSCFG0_REQINFO(~0); 622 reg |= DWC3_GSBUSCFG0_REQINFO(dwc->gsbuscfg0_reqinfo); 623 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg); 624 } 625 } 626 627 static int dwc3_core_ulpi_init(struct dwc3 *dwc) 628 { 629 int intf; 630 int ret = 0; 631 632 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3); 633 634 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI || 635 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI && 636 dwc->hsphy_interface && 637 !strncmp(dwc->hsphy_interface, "ulpi", 4))) 638 ret = dwc3_ulpi_init(dwc); 639 640 return ret; 641 } 642 643 static int dwc3_ss_phy_setup(struct dwc3 *dwc, int index) 644 { 645 u32 reg; 646 647 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(index)); 648 649 /* 650 * Make sure UX_EXIT_PX is cleared as that causes issues with some 651 * PHYs. Also, this bit is not supposed to be used in normal operation. 652 */ 653 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; 654 655 /* 656 * Above DWC_usb3.0 1.94a, it is recommended to set 657 * DWC3_GUSB3PIPECTL_SUSPHY to '0' during coreConsultant configuration. 658 * So default value will be '0' when the core is reset. Application 659 * needs to set it to '1' after the core initialization is completed. 660 * 661 * Similarly for DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be 662 * cleared after power-on reset, and it can be set after core 663 * initialization. 664 */ 665 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 666 667 if (dwc->u2ss_inp3_quirk) 668 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 669 670 if (dwc->dis_rxdet_inp3_quirk) 671 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; 672 673 if (dwc->req_p1p2p3_quirk) 674 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 675 676 if (dwc->del_p1p2p3_quirk) 677 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 678 679 if (dwc->del_phy_power_chg_quirk) 680 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 681 682 if (dwc->lfps_filter_quirk) 683 reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 684 685 if (dwc->rx_detect_poll_quirk) 686 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 687 688 if (dwc->tx_de_emphasis_quirk) 689 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 690 691 if (dwc->dis_del_phy_power_chg_quirk) 692 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; 693 694 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(index), reg); 695 696 return 0; 697 } 698 699 static int dwc3_hs_phy_setup(struct dwc3 *dwc, int index) 700 { 701 u32 reg; 702 703 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(index)); 704 705 /* Select the HS PHY interface */ 706 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { 707 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: 708 if (dwc->hsphy_interface && 709 !strncmp(dwc->hsphy_interface, "utmi", 4)) { 710 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; 711 break; 712 } else if (dwc->hsphy_interface && 713 !strncmp(dwc->hsphy_interface, "ulpi", 4)) { 714 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; 715 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg); 716 } else { 717 /* Relying on default value. */ 718 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) 719 break; 720 } 721 fallthrough; 722 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: 723 default: 724 break; 725 } 726 727 switch (dwc->hsphy_mode) { 728 case USBPHY_INTERFACE_MODE_UTMI: 729 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 730 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 731 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | 732 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); 733 break; 734 case USBPHY_INTERFACE_MODE_UTMIW: 735 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 736 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 737 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | 738 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 739 break; 740 default: 741 break; 742 } 743 744 /* 745 * Above DWC_usb3.0 1.94a, it is recommended to set 746 * DWC3_GUSB2PHYCFG_SUSPHY to '0' during coreConsultant configuration. 747 * So default value will be '0' when the core is reset. Application 748 * needs to set it to '1' after the core initialization is completed. 749 * 750 * Similarly for DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared 751 * after power-on reset, and it can be set after core initialization. 752 */ 753 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 754 755 if (dwc->dis_enblslpm_quirk) 756 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 757 else 758 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM; 759 760 if (dwc->dis_u2_freeclk_exists_quirk || dwc->gfladj_refclk_lpm_sel) 761 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 762 763 /* 764 * Some ULPI USB PHY does not support internal VBUS supply, to drive 765 * the CPEN pin requires the configuration of the ULPI DRVVBUSEXTERNAL 766 * bit of OTG_CTRL register. Controller configures the USB2 PHY 767 * ULPIEXTVBUSDRV bit[17] of the GUSB2PHYCFG register to drive vBus 768 * with an external supply. 769 */ 770 if (dwc->ulpi_ext_vbus_drv) 771 reg |= DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV; 772 773 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg); 774 775 return 0; 776 } 777 778 /** 779 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 780 * @dwc: Pointer to our controller context structure 781 * 782 * Returns 0 on success. The USB PHY interfaces are configured but not 783 * initialized. The PHY interfaces and the PHYs get initialized together with 784 * the core in dwc3_core_init. 785 */ 786 static int dwc3_phy_setup(struct dwc3 *dwc) 787 { 788 int i; 789 int ret; 790 791 for (i = 0; i < dwc->num_usb3_ports; i++) { 792 ret = dwc3_ss_phy_setup(dwc, i); 793 if (ret) 794 return ret; 795 } 796 797 for (i = 0; i < dwc->num_usb2_ports; i++) { 798 ret = dwc3_hs_phy_setup(dwc, i); 799 if (ret) 800 return ret; 801 } 802 803 return 0; 804 } 805 806 static int dwc3_phy_init(struct dwc3 *dwc) 807 { 808 int ret; 809 int i; 810 int j; 811 812 usb_phy_init(dwc->usb2_phy); 813 usb_phy_init(dwc->usb3_phy); 814 815 for (i = 0; i < dwc->num_usb2_ports; i++) { 816 ret = phy_init(dwc->usb2_generic_phy[i]); 817 if (ret < 0) 818 goto err_exit_usb2_phy; 819 } 820 821 for (j = 0; j < dwc->num_usb3_ports; j++) { 822 ret = phy_init(dwc->usb3_generic_phy[j]); 823 if (ret < 0) 824 goto err_exit_usb3_phy; 825 } 826 827 return 0; 828 829 err_exit_usb3_phy: 830 while (--j >= 0) 831 phy_exit(dwc->usb3_generic_phy[j]); 832 833 err_exit_usb2_phy: 834 while (--i >= 0) 835 phy_exit(dwc->usb2_generic_phy[i]); 836 837 usb_phy_shutdown(dwc->usb3_phy); 838 usb_phy_shutdown(dwc->usb2_phy); 839 840 return ret; 841 } 842 843 static void dwc3_phy_exit(struct dwc3 *dwc) 844 { 845 int i; 846 847 for (i = 0; i < dwc->num_usb3_ports; i++) 848 phy_exit(dwc->usb3_generic_phy[i]); 849 850 for (i = 0; i < dwc->num_usb2_ports; i++) 851 phy_exit(dwc->usb2_generic_phy[i]); 852 853 usb_phy_shutdown(dwc->usb3_phy); 854 usb_phy_shutdown(dwc->usb2_phy); 855 } 856 857 static int dwc3_phy_power_on(struct dwc3 *dwc) 858 { 859 int ret; 860 int i; 861 int j; 862 863 usb_phy_set_suspend(dwc->usb2_phy, 0); 864 usb_phy_set_suspend(dwc->usb3_phy, 0); 865 866 for (i = 0; i < dwc->num_usb2_ports; i++) { 867 ret = phy_power_on(dwc->usb2_generic_phy[i]); 868 if (ret < 0) 869 goto err_power_off_usb2_phy; 870 } 871 872 for (j = 0; j < dwc->num_usb3_ports; j++) { 873 ret = phy_power_on(dwc->usb3_generic_phy[j]); 874 if (ret < 0) 875 goto err_power_off_usb3_phy; 876 } 877 878 return 0; 879 880 err_power_off_usb3_phy: 881 while (--j >= 0) 882 phy_power_off(dwc->usb3_generic_phy[j]); 883 884 err_power_off_usb2_phy: 885 while (--i >= 0) 886 phy_power_off(dwc->usb2_generic_phy[i]); 887 888 usb_phy_set_suspend(dwc->usb3_phy, 1); 889 usb_phy_set_suspend(dwc->usb2_phy, 1); 890 891 return ret; 892 } 893 894 static void dwc3_phy_power_off(struct dwc3 *dwc) 895 { 896 int i; 897 898 for (i = 0; i < dwc->num_usb3_ports; i++) 899 phy_power_off(dwc->usb3_generic_phy[i]); 900 901 for (i = 0; i < dwc->num_usb2_ports; i++) 902 phy_power_off(dwc->usb2_generic_phy[i]); 903 904 usb_phy_set_suspend(dwc->usb3_phy, 1); 905 usb_phy_set_suspend(dwc->usb2_phy, 1); 906 } 907 908 static int dwc3_clk_enable(struct dwc3 *dwc) 909 { 910 int ret; 911 912 ret = clk_prepare_enable(dwc->bus_clk); 913 if (ret) 914 return ret; 915 916 ret = clk_prepare_enable(dwc->ref_clk); 917 if (ret) 918 goto disable_bus_clk; 919 920 ret = clk_prepare_enable(dwc->susp_clk); 921 if (ret) 922 goto disable_ref_clk; 923 924 ret = clk_prepare_enable(dwc->utmi_clk); 925 if (ret) 926 goto disable_susp_clk; 927 928 ret = clk_prepare_enable(dwc->pipe_clk); 929 if (ret) 930 goto disable_utmi_clk; 931 932 return 0; 933 934 disable_utmi_clk: 935 clk_disable_unprepare(dwc->utmi_clk); 936 disable_susp_clk: 937 clk_disable_unprepare(dwc->susp_clk); 938 disable_ref_clk: 939 clk_disable_unprepare(dwc->ref_clk); 940 disable_bus_clk: 941 clk_disable_unprepare(dwc->bus_clk); 942 return ret; 943 } 944 945 static void dwc3_clk_disable(struct dwc3 *dwc) 946 { 947 clk_disable_unprepare(dwc->pipe_clk); 948 clk_disable_unprepare(dwc->utmi_clk); 949 clk_disable_unprepare(dwc->susp_clk); 950 clk_disable_unprepare(dwc->ref_clk); 951 clk_disable_unprepare(dwc->bus_clk); 952 } 953 954 static void dwc3_core_exit(struct dwc3 *dwc) 955 { 956 dwc3_event_buffers_cleanup(dwc); 957 dwc3_phy_power_off(dwc); 958 dwc3_phy_exit(dwc); 959 dwc3_clk_disable(dwc); 960 reset_control_assert(dwc->reset); 961 } 962 963 static bool dwc3_core_is_valid(struct dwc3 *dwc) 964 { 965 u32 reg; 966 967 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 968 dwc->ip = DWC3_GSNPS_ID(reg); 969 970 /* This should read as U3 followed by revision number */ 971 if (DWC3_IP_IS(DWC3)) { 972 dwc->revision = reg; 973 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) { 974 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); 975 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE); 976 } else { 977 return false; 978 } 979 980 return true; 981 } 982 983 static void dwc3_core_setup_global_control(struct dwc3 *dwc) 984 { 985 unsigned int power_opt; 986 unsigned int hw_mode; 987 u32 reg; 988 989 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 990 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 991 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 992 power_opt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1); 993 994 switch (power_opt) { 995 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 996 /** 997 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 998 * issue which would cause xHCI compliance tests to fail. 999 * 1000 * Because of that we cannot enable clock gating on such 1001 * configurations. 1002 * 1003 * Refers to: 1004 * 1005 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 1006 * SOF/ITP Mode Used 1007 */ 1008 if ((dwc->dr_mode == USB_DR_MODE_HOST || 1009 dwc->dr_mode == USB_DR_MODE_OTG) && 1010 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A)) 1011 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 1012 else 1013 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 1014 break; 1015 case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 1016 /* 1017 * REVISIT Enabling this bit so that host-mode hibernation 1018 * will work. Device-mode hibernation is not yet implemented. 1019 */ 1020 reg |= DWC3_GCTL_GBLHIBERNATIONEN; 1021 break; 1022 default: 1023 /* nothing */ 1024 break; 1025 } 1026 1027 /* 1028 * This is a workaround for STAR#4846132, which only affects 1029 * DWC_usb31 version2.00a operating in host mode. 1030 * 1031 * There is a problem in DWC_usb31 version 2.00a operating 1032 * in host mode that would cause a CSR read timeout When CSR 1033 * read coincides with RAM Clock Gating Entry. By disable 1034 * Clock Gating, sacrificing power consumption for normal 1035 * operation. 1036 */ 1037 if (power_opt != DWC3_GHWPARAMS1_EN_PWROPT_NO && 1038 hw_mode != DWC3_GHWPARAMS0_MODE_GADGET && DWC3_VER_IS(DWC31, 200A)) 1039 reg |= DWC3_GCTL_DSBLCLKGTNG; 1040 1041 /* check if current dwc3 is on simulation board */ 1042 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 1043 dev_info(dwc->dev, "Running with FPGA optimizations\n"); 1044 dwc->is_fpga = true; 1045 } 1046 1047 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, 1048 "disable_scramble cannot be used on non-FPGA builds\n"); 1049 1050 if (dwc->disable_scramble_quirk && dwc->is_fpga) 1051 reg |= DWC3_GCTL_DISSCRAMBLE; 1052 else 1053 reg &= ~DWC3_GCTL_DISSCRAMBLE; 1054 1055 if (dwc->u2exit_lfps_quirk) 1056 reg |= DWC3_GCTL_U2EXIT_LFPS; 1057 1058 /* 1059 * WORKAROUND: DWC3 revisions <1.90a have a bug 1060 * where the device can fail to connect at SuperSpeed 1061 * and falls back to high-speed mode which causes 1062 * the device to enter a Connect/Disconnect loop 1063 */ 1064 if (DWC3_VER_IS_PRIOR(DWC3, 190A)) 1065 reg |= DWC3_GCTL_U2RSTECN; 1066 1067 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 1068 } 1069 1070 static int dwc3_core_get_phy(struct dwc3 *dwc); 1071 static int dwc3_core_ulpi_init(struct dwc3 *dwc); 1072 1073 /* set global incr burst type configuration registers */ 1074 static void dwc3_set_incr_burst_type(struct dwc3 *dwc) 1075 { 1076 struct device *dev = dwc->dev; 1077 /* incrx_mode : for INCR burst type. */ 1078 bool incrx_mode; 1079 /* incrx_size : for size of INCRX burst. */ 1080 u32 incrx_size; 1081 u32 *vals; 1082 u32 cfg; 1083 int ntype; 1084 int ret; 1085 int i; 1086 1087 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); 1088 1089 /* 1090 * Handle property "snps,incr-burst-type-adjustment". 1091 * Get the number of value from this property: 1092 * result <= 0, means this property is not supported. 1093 * result = 1, means INCRx burst mode supported. 1094 * result > 1, means undefined length burst mode supported. 1095 */ 1096 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment"); 1097 if (ntype <= 0) 1098 return; 1099 1100 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL); 1101 if (!vals) 1102 return; 1103 1104 /* Get INCR burst type, and parse it */ 1105 ret = device_property_read_u32_array(dev, 1106 "snps,incr-burst-type-adjustment", vals, ntype); 1107 if (ret) { 1108 kfree(vals); 1109 dev_err(dev, "Error to get property\n"); 1110 return; 1111 } 1112 1113 incrx_size = *vals; 1114 1115 if (ntype > 1) { 1116 /* INCRX (undefined length) burst mode */ 1117 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE; 1118 for (i = 1; i < ntype; i++) { 1119 if (vals[i] > incrx_size) 1120 incrx_size = vals[i]; 1121 } 1122 } else { 1123 /* INCRX burst mode */ 1124 incrx_mode = INCRX_BURST_MODE; 1125 } 1126 1127 kfree(vals); 1128 1129 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */ 1130 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK; 1131 if (incrx_mode) 1132 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA; 1133 switch (incrx_size) { 1134 case 256: 1135 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA; 1136 break; 1137 case 128: 1138 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA; 1139 break; 1140 case 64: 1141 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA; 1142 break; 1143 case 32: 1144 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA; 1145 break; 1146 case 16: 1147 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA; 1148 break; 1149 case 8: 1150 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA; 1151 break; 1152 case 4: 1153 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA; 1154 break; 1155 case 1: 1156 break; 1157 default: 1158 dev_err(dev, "Invalid property\n"); 1159 break; 1160 } 1161 1162 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg); 1163 } 1164 1165 static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc) 1166 { 1167 u32 scale; 1168 u32 reg; 1169 1170 if (!dwc->susp_clk) 1171 return; 1172 1173 /* 1174 * The power down scale field specifies how many suspend_clk 1175 * periods fit into a 16KHz clock period. When performing 1176 * the division, round up the remainder. 1177 * 1178 * The power down scale value is calculated using the fastest 1179 * frequency of the suspend_clk. If it isn't fixed (but within 1180 * the accuracy requirement), the driver may not know the max 1181 * rate of the suspend_clk, so only update the power down scale 1182 * if the default is less than the calculated value from 1183 * clk_get_rate() or if the default is questionably high 1184 * (3x or more) to be within the requirement. 1185 */ 1186 scale = DIV_ROUND_UP(clk_get_rate(dwc->susp_clk), 16000); 1187 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 1188 if ((reg & DWC3_GCTL_PWRDNSCALE_MASK) < DWC3_GCTL_PWRDNSCALE(scale) || 1189 (reg & DWC3_GCTL_PWRDNSCALE_MASK) > DWC3_GCTL_PWRDNSCALE(scale*3)) { 1190 reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK); 1191 reg |= DWC3_GCTL_PWRDNSCALE(scale); 1192 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 1193 } 1194 } 1195 1196 static void dwc3_config_threshold(struct dwc3 *dwc) 1197 { 1198 u32 reg; 1199 u8 rx_thr_num; 1200 u8 rx_maxburst; 1201 u8 tx_thr_num; 1202 u8 tx_maxburst; 1203 1204 /* 1205 * Must config both number of packets and max burst settings to enable 1206 * RX and/or TX threshold. 1207 */ 1208 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) { 1209 rx_thr_num = dwc->rx_thr_num_pkt_prd; 1210 rx_maxburst = dwc->rx_max_burst_prd; 1211 tx_thr_num = dwc->tx_thr_num_pkt_prd; 1212 tx_maxburst = dwc->tx_max_burst_prd; 1213 1214 if (rx_thr_num && rx_maxburst) { 1215 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1216 reg |= DWC31_RXTHRNUMPKTSEL_PRD; 1217 1218 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0); 1219 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num); 1220 1221 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0); 1222 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst); 1223 1224 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1225 } 1226 1227 if (tx_thr_num && tx_maxburst) { 1228 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1229 reg |= DWC31_TXTHRNUMPKTSEL_PRD; 1230 1231 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0); 1232 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num); 1233 1234 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0); 1235 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst); 1236 1237 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1238 } 1239 } 1240 1241 rx_thr_num = dwc->rx_thr_num_pkt; 1242 rx_maxburst = dwc->rx_max_burst; 1243 tx_thr_num = dwc->tx_thr_num_pkt; 1244 tx_maxburst = dwc->tx_max_burst; 1245 1246 if (DWC3_IP_IS(DWC3)) { 1247 if (rx_thr_num && rx_maxburst) { 1248 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1249 reg |= DWC3_GRXTHRCFG_PKTCNTSEL; 1250 1251 reg &= ~DWC3_GRXTHRCFG_RXPKTCNT(~0); 1252 reg |= DWC3_GRXTHRCFG_RXPKTCNT(rx_thr_num); 1253 1254 reg &= ~DWC3_GRXTHRCFG_MAXRXBURSTSIZE(~0); 1255 reg |= DWC3_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst); 1256 1257 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1258 } 1259 1260 if (tx_thr_num && tx_maxburst) { 1261 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1262 reg |= DWC3_GTXTHRCFG_PKTCNTSEL; 1263 1264 reg &= ~DWC3_GTXTHRCFG_TXPKTCNT(~0); 1265 reg |= DWC3_GTXTHRCFG_TXPKTCNT(tx_thr_num); 1266 1267 reg &= ~DWC3_GTXTHRCFG_MAXTXBURSTSIZE(~0); 1268 reg |= DWC3_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst); 1269 1270 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1271 } 1272 } else { 1273 if (rx_thr_num && rx_maxburst) { 1274 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1275 reg |= DWC31_GRXTHRCFG_PKTCNTSEL; 1276 1277 reg &= ~DWC31_GRXTHRCFG_RXPKTCNT(~0); 1278 reg |= DWC31_GRXTHRCFG_RXPKTCNT(rx_thr_num); 1279 1280 reg &= ~DWC31_GRXTHRCFG_MAXRXBURSTSIZE(~0); 1281 reg |= DWC31_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst); 1282 1283 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1284 } 1285 1286 if (tx_thr_num && tx_maxburst) { 1287 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1288 reg |= DWC31_GTXTHRCFG_PKTCNTSEL; 1289 1290 reg &= ~DWC31_GTXTHRCFG_TXPKTCNT(~0); 1291 reg |= DWC31_GTXTHRCFG_TXPKTCNT(tx_thr_num); 1292 1293 reg &= ~DWC31_GTXTHRCFG_MAXTXBURSTSIZE(~0); 1294 reg |= DWC31_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst); 1295 1296 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1297 } 1298 } 1299 } 1300 1301 /** 1302 * dwc3_core_init - Low-level initialization of DWC3 Core 1303 * @dwc: Pointer to our controller context structure 1304 * 1305 * Returns 0 on success otherwise negative errno. 1306 */ 1307 static int dwc3_core_init(struct dwc3 *dwc) 1308 { 1309 unsigned int hw_mode; 1310 u32 reg; 1311 int ret; 1312 1313 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 1314 1315 /* 1316 * Write Linux Version Code to our GUID register so it's easy to figure 1317 * out which kernel version a bug was found. 1318 */ 1319 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); 1320 1321 ret = dwc3_phy_setup(dwc); 1322 if (ret) 1323 return ret; 1324 1325 if (!dwc->ulpi_ready) { 1326 ret = dwc3_core_ulpi_init(dwc); 1327 if (ret) { 1328 if (ret == -ETIMEDOUT) { 1329 dwc3_core_soft_reset(dwc); 1330 ret = -EPROBE_DEFER; 1331 } 1332 return ret; 1333 } 1334 dwc->ulpi_ready = true; 1335 } 1336 1337 if (!dwc->phys_ready) { 1338 ret = dwc3_core_get_phy(dwc); 1339 if (ret) 1340 goto err_exit_ulpi; 1341 dwc->phys_ready = true; 1342 } 1343 1344 ret = dwc3_phy_init(dwc); 1345 if (ret) 1346 goto err_exit_ulpi; 1347 1348 ret = dwc3_core_soft_reset(dwc); 1349 if (ret) 1350 goto err_exit_phy; 1351 1352 dwc3_core_setup_global_control(dwc); 1353 dwc3_core_num_eps(dwc); 1354 1355 /* Set power down scale of suspend_clk */ 1356 dwc3_set_power_down_clk_scale(dwc); 1357 1358 /* Adjust Frame Length */ 1359 dwc3_frame_length_adjustment(dwc); 1360 1361 /* Adjust Reference Clock Period */ 1362 dwc3_ref_clk_period(dwc); 1363 1364 dwc3_set_incr_burst_type(dwc); 1365 1366 dwc3_config_soc_bus(dwc); 1367 1368 ret = dwc3_phy_power_on(dwc); 1369 if (ret) 1370 goto err_exit_phy; 1371 1372 ret = dwc3_event_buffers_setup(dwc); 1373 if (ret) { 1374 dev_err(dwc->dev, "failed to setup event buffers\n"); 1375 goto err_power_off_phy; 1376 } 1377 1378 /* 1379 * ENDXFER polling is available on version 3.10a and later of 1380 * the DWC_usb3 controller. It is NOT available in the 1381 * DWC_usb31 controller. 1382 */ 1383 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) { 1384 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); 1385 reg |= DWC3_GUCTL2_RST_ACTBITLATER; 1386 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); 1387 } 1388 1389 /* 1390 * When configured in HOST mode, after issuing U3/L2 exit controller 1391 * fails to send proper CRC checksum in CRC5 feild. Because of this 1392 * behaviour Transaction Error is generated, resulting in reset and 1393 * re-enumeration of usb device attached. All the termsel, xcvrsel, 1394 * opmode becomes 0 during end of resume. Enabling bit 10 of GUCTL1 1395 * will correct this problem. This option is to support certain 1396 * legacy ULPI PHYs. 1397 */ 1398 if (dwc->resume_hs_terminations) { 1399 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 1400 reg |= DWC3_GUCTL1_RESUME_OPMODE_HS_HOST; 1401 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 1402 } 1403 1404 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) { 1405 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 1406 1407 /* 1408 * Enable hardware control of sending remote wakeup 1409 * in HS when the device is in the L1 state. 1410 */ 1411 if (!DWC3_VER_IS_PRIOR(DWC3, 290A)) 1412 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; 1413 1414 /* 1415 * Decouple USB 2.0 L1 & L2 events which will allow for 1416 * gadget driver to only receive U3/L2 suspend & wakeup 1417 * events and prevent the more frequent L1 LPM transitions 1418 * from interrupting the driver. 1419 */ 1420 if (!DWC3_VER_IS_PRIOR(DWC3, 300A)) 1421 reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT; 1422 1423 if (dwc->dis_tx_ipgap_linecheck_quirk) 1424 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; 1425 1426 if (dwc->parkmode_disable_ss_quirk) 1427 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS; 1428 1429 if (dwc->parkmode_disable_hs_quirk) 1430 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_HS; 1431 1432 if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY)) { 1433 if (dwc->maximum_speed == USB_SPEED_FULL || 1434 dwc->maximum_speed == USB_SPEED_HIGH) 1435 reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; 1436 else 1437 reg &= ~DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; 1438 } 1439 1440 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 1441 } 1442 1443 dwc3_config_threshold(dwc); 1444 1445 /* 1446 * Modify this for all supported Super Speed ports when 1447 * multiport support is added. 1448 */ 1449 if (hw_mode != DWC3_GHWPARAMS0_MODE_GADGET && 1450 (DWC3_IP_IS(DWC31)) && 1451 dwc->maximum_speed == USB_SPEED_SUPER) { 1452 reg = dwc3_readl(dwc->regs, DWC3_LLUCTL); 1453 reg |= DWC3_LLUCTL_FORCE_GEN1; 1454 dwc3_writel(dwc->regs, DWC3_LLUCTL, reg); 1455 } 1456 1457 return 0; 1458 1459 err_power_off_phy: 1460 dwc3_phy_power_off(dwc); 1461 err_exit_phy: 1462 dwc3_phy_exit(dwc); 1463 err_exit_ulpi: 1464 dwc3_ulpi_exit(dwc); 1465 1466 return ret; 1467 } 1468 1469 static int dwc3_core_get_phy(struct dwc3 *dwc) 1470 { 1471 struct device *dev = dwc->dev; 1472 struct device_node *node = dev->of_node; 1473 char phy_name[9]; 1474 int ret; 1475 u8 i; 1476 1477 if (node) { 1478 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); 1479 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); 1480 } else { 1481 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 1482 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); 1483 } 1484 1485 if (IS_ERR(dwc->usb2_phy)) { 1486 ret = PTR_ERR(dwc->usb2_phy); 1487 if (ret == -ENXIO || ret == -ENODEV) 1488 dwc->usb2_phy = NULL; 1489 else 1490 return dev_err_probe(dev, ret, "no usb2 phy configured\n"); 1491 } 1492 1493 if (IS_ERR(dwc->usb3_phy)) { 1494 ret = PTR_ERR(dwc->usb3_phy); 1495 if (ret == -ENXIO || ret == -ENODEV) 1496 dwc->usb3_phy = NULL; 1497 else 1498 return dev_err_probe(dev, ret, "no usb3 phy configured\n"); 1499 } 1500 1501 for (i = 0; i < dwc->num_usb2_ports; i++) { 1502 if (dwc->num_usb2_ports == 1) 1503 snprintf(phy_name, sizeof(phy_name), "usb2-phy"); 1504 else 1505 snprintf(phy_name, sizeof(phy_name), "usb2-%u", i); 1506 1507 dwc->usb2_generic_phy[i] = devm_phy_get(dev, phy_name); 1508 if (IS_ERR(dwc->usb2_generic_phy[i])) { 1509 ret = PTR_ERR(dwc->usb2_generic_phy[i]); 1510 if (ret == -ENOSYS || ret == -ENODEV) 1511 dwc->usb2_generic_phy[i] = NULL; 1512 else 1513 return dev_err_probe(dev, ret, "failed to lookup phy %s\n", 1514 phy_name); 1515 } 1516 } 1517 1518 for (i = 0; i < dwc->num_usb3_ports; i++) { 1519 if (dwc->num_usb3_ports == 1) 1520 snprintf(phy_name, sizeof(phy_name), "usb3-phy"); 1521 else 1522 snprintf(phy_name, sizeof(phy_name), "usb3-%u", i); 1523 1524 dwc->usb3_generic_phy[i] = devm_phy_get(dev, phy_name); 1525 if (IS_ERR(dwc->usb3_generic_phy[i])) { 1526 ret = PTR_ERR(dwc->usb3_generic_phy[i]); 1527 if (ret == -ENOSYS || ret == -ENODEV) 1528 dwc->usb3_generic_phy[i] = NULL; 1529 else 1530 return dev_err_probe(dev, ret, "failed to lookup phy %s\n", 1531 phy_name); 1532 } 1533 } 1534 1535 return 0; 1536 } 1537 1538 static int dwc3_core_init_mode(struct dwc3 *dwc) 1539 { 1540 struct device *dev = dwc->dev; 1541 int ret; 1542 int i; 1543 1544 switch (dwc->dr_mode) { 1545 case USB_DR_MODE_PERIPHERAL: 1546 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1547 1548 if (dwc->usb2_phy) 1549 otg_set_vbus(dwc->usb2_phy->otg, false); 1550 phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE); 1551 phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE); 1552 1553 ret = dwc3_gadget_init(dwc); 1554 if (ret) 1555 return dev_err_probe(dev, ret, "failed to initialize gadget\n"); 1556 break; 1557 case USB_DR_MODE_HOST: 1558 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1559 1560 if (dwc->usb2_phy) 1561 otg_set_vbus(dwc->usb2_phy->otg, true); 1562 for (i = 0; i < dwc->num_usb2_ports; i++) 1563 phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST); 1564 for (i = 0; i < dwc->num_usb3_ports; i++) 1565 phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST); 1566 1567 ret = dwc3_host_init(dwc); 1568 if (ret) 1569 return dev_err_probe(dev, ret, "failed to initialize host\n"); 1570 break; 1571 case USB_DR_MODE_OTG: 1572 INIT_WORK(&dwc->drd_work, __dwc3_set_mode); 1573 ret = dwc3_drd_init(dwc); 1574 if (ret) 1575 return dev_err_probe(dev, ret, "failed to initialize dual-role\n"); 1576 break; 1577 default: 1578 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 1579 return -EINVAL; 1580 } 1581 1582 return 0; 1583 } 1584 1585 static void dwc3_core_exit_mode(struct dwc3 *dwc) 1586 { 1587 switch (dwc->dr_mode) { 1588 case USB_DR_MODE_PERIPHERAL: 1589 dwc3_gadget_exit(dwc); 1590 break; 1591 case USB_DR_MODE_HOST: 1592 dwc3_host_exit(dwc); 1593 break; 1594 case USB_DR_MODE_OTG: 1595 dwc3_drd_exit(dwc); 1596 break; 1597 default: 1598 /* do nothing */ 1599 break; 1600 } 1601 1602 /* de-assert DRVVBUS for HOST and OTG mode */ 1603 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1604 } 1605 1606 static void dwc3_get_software_properties(struct dwc3 *dwc) 1607 { 1608 struct device *tmpdev; 1609 u16 gsbuscfg0_reqinfo; 1610 int ret; 1611 1612 dwc->gsbuscfg0_reqinfo = DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED; 1613 1614 /* 1615 * Iterate over all parent nodes for finding swnode properties 1616 * and non-DT (non-ABI) properties. 1617 */ 1618 for (tmpdev = dwc->dev; tmpdev; tmpdev = tmpdev->parent) { 1619 ret = device_property_read_u16(tmpdev, 1620 "snps,gsbuscfg0-reqinfo", 1621 &gsbuscfg0_reqinfo); 1622 if (!ret) 1623 dwc->gsbuscfg0_reqinfo = gsbuscfg0_reqinfo; 1624 } 1625 } 1626 1627 static void dwc3_get_properties(struct dwc3 *dwc) 1628 { 1629 struct device *dev = dwc->dev; 1630 u8 lpm_nyet_threshold; 1631 u8 tx_de_emphasis; 1632 u8 hird_threshold; 1633 u8 rx_thr_num_pkt = 0; 1634 u8 rx_max_burst = 0; 1635 u8 tx_thr_num_pkt = 0; 1636 u8 tx_max_burst = 0; 1637 u8 rx_thr_num_pkt_prd = 0; 1638 u8 rx_max_burst_prd = 0; 1639 u8 tx_thr_num_pkt_prd = 0; 1640 u8 tx_max_burst_prd = 0; 1641 u8 tx_fifo_resize_max_num; 1642 const char *usb_psy_name; 1643 int ret; 1644 1645 /* default to highest possible threshold */ 1646 lpm_nyet_threshold = 0xf; 1647 1648 /* default to -3.5dB de-emphasis */ 1649 tx_de_emphasis = 1; 1650 1651 /* 1652 * default to assert utmi_sleep_n and use maximum allowed HIRD 1653 * threshold value of 0b1100 1654 */ 1655 hird_threshold = 12; 1656 1657 /* 1658 * default to a TXFIFO size large enough to fit 6 max packets. This 1659 * allows for systems with larger bus latencies to have some headroom 1660 * for endpoints that have a large bMaxBurst value. 1661 */ 1662 tx_fifo_resize_max_num = 6; 1663 1664 dwc->maximum_speed = usb_get_maximum_speed(dev); 1665 dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev); 1666 dwc->dr_mode = usb_get_dr_mode(dev); 1667 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); 1668 1669 dwc->sysdev_is_parent = device_property_read_bool(dev, 1670 "linux,sysdev_is_parent"); 1671 if (dwc->sysdev_is_parent) 1672 dwc->sysdev = dwc->dev->parent; 1673 else 1674 dwc->sysdev = dwc->dev; 1675 1676 dwc->sys_wakeup = device_may_wakeup(dwc->sysdev); 1677 1678 ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name); 1679 if (ret >= 0) { 1680 dwc->usb_psy = power_supply_get_by_name(usb_psy_name); 1681 if (!dwc->usb_psy) 1682 dev_err(dev, "couldn't get usb power supply\n"); 1683 } 1684 1685 dwc->has_lpm_erratum = device_property_read_bool(dev, 1686 "snps,has-lpm-erratum"); 1687 device_property_read_u8(dev, "snps,lpm-nyet-threshold", 1688 &lpm_nyet_threshold); 1689 dwc->is_utmi_l1_suspend = device_property_read_bool(dev, 1690 "snps,is-utmi-l1-suspend"); 1691 device_property_read_u8(dev, "snps,hird-threshold", 1692 &hird_threshold); 1693 dwc->dis_start_transfer_quirk = device_property_read_bool(dev, 1694 "snps,dis-start-transfer-quirk"); 1695 dwc->usb3_lpm_capable = device_property_read_bool(dev, 1696 "snps,usb3_lpm_capable"); 1697 dwc->usb2_lpm_disable = device_property_read_bool(dev, 1698 "snps,usb2-lpm-disable"); 1699 dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev, 1700 "snps,usb2-gadget-lpm-disable"); 1701 device_property_read_u8(dev, "snps,rx-thr-num-pkt", 1702 &rx_thr_num_pkt); 1703 device_property_read_u8(dev, "snps,rx-max-burst", 1704 &rx_max_burst); 1705 device_property_read_u8(dev, "snps,tx-thr-num-pkt", 1706 &tx_thr_num_pkt); 1707 device_property_read_u8(dev, "snps,tx-max-burst", 1708 &tx_max_burst); 1709 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd", 1710 &rx_thr_num_pkt_prd); 1711 device_property_read_u8(dev, "snps,rx-max-burst-prd", 1712 &rx_max_burst_prd); 1713 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd", 1714 &tx_thr_num_pkt_prd); 1715 device_property_read_u8(dev, "snps,tx-max-burst-prd", 1716 &tx_max_burst_prd); 1717 dwc->do_fifo_resize = device_property_read_bool(dev, 1718 "tx-fifo-resize"); 1719 if (dwc->do_fifo_resize) 1720 device_property_read_u8(dev, "tx-fifo-max-num", 1721 &tx_fifo_resize_max_num); 1722 1723 dwc->disable_scramble_quirk = device_property_read_bool(dev, 1724 "snps,disable_scramble_quirk"); 1725 dwc->u2exit_lfps_quirk = device_property_read_bool(dev, 1726 "snps,u2exit_lfps_quirk"); 1727 dwc->u2ss_inp3_quirk = device_property_read_bool(dev, 1728 "snps,u2ss_inp3_quirk"); 1729 dwc->req_p1p2p3_quirk = device_property_read_bool(dev, 1730 "snps,req_p1p2p3_quirk"); 1731 dwc->del_p1p2p3_quirk = device_property_read_bool(dev, 1732 "snps,del_p1p2p3_quirk"); 1733 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, 1734 "snps,del_phy_power_chg_quirk"); 1735 dwc->lfps_filter_quirk = device_property_read_bool(dev, 1736 "snps,lfps_filter_quirk"); 1737 dwc->rx_detect_poll_quirk = device_property_read_bool(dev, 1738 "snps,rx_detect_poll_quirk"); 1739 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, 1740 "snps,dis_u3_susphy_quirk"); 1741 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, 1742 "snps,dis_u2_susphy_quirk"); 1743 dwc->dis_enblslpm_quirk = device_property_read_bool(dev, 1744 "snps,dis_enblslpm_quirk"); 1745 dwc->dis_u1_entry_quirk = device_property_read_bool(dev, 1746 "snps,dis-u1-entry-quirk"); 1747 dwc->dis_u2_entry_quirk = device_property_read_bool(dev, 1748 "snps,dis-u2-entry-quirk"); 1749 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, 1750 "snps,dis_rxdet_inp3_quirk"); 1751 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, 1752 "snps,dis-u2-freeclk-exists-quirk"); 1753 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, 1754 "snps,dis-del-phy-power-chg-quirk"); 1755 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev, 1756 "snps,dis-tx-ipgap-linecheck-quirk"); 1757 dwc->resume_hs_terminations = device_property_read_bool(dev, 1758 "snps,resume-hs-terminations"); 1759 dwc->ulpi_ext_vbus_drv = device_property_read_bool(dev, 1760 "snps,ulpi-ext-vbus-drv"); 1761 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev, 1762 "snps,parkmode-disable-ss-quirk"); 1763 dwc->parkmode_disable_hs_quirk = device_property_read_bool(dev, 1764 "snps,parkmode-disable-hs-quirk"); 1765 dwc->gfladj_refclk_lpm_sel = device_property_read_bool(dev, 1766 "snps,gfladj-refclk-lpm-sel-quirk"); 1767 1768 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, 1769 "snps,tx_de_emphasis_quirk"); 1770 device_property_read_u8(dev, "snps,tx_de_emphasis", 1771 &tx_de_emphasis); 1772 device_property_read_string(dev, "snps,hsphy_interface", 1773 &dwc->hsphy_interface); 1774 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", 1775 &dwc->fladj); 1776 device_property_read_u32(dev, "snps,ref-clock-period-ns", 1777 &dwc->ref_clk_per); 1778 1779 dwc->dis_metastability_quirk = device_property_read_bool(dev, 1780 "snps,dis_metastability_quirk"); 1781 1782 dwc->dis_split_quirk = device_property_read_bool(dev, 1783 "snps,dis-split-quirk"); 1784 1785 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 1786 dwc->tx_de_emphasis = tx_de_emphasis; 1787 1788 dwc->hird_threshold = hird_threshold; 1789 1790 dwc->rx_thr_num_pkt = rx_thr_num_pkt; 1791 dwc->rx_max_burst = rx_max_burst; 1792 1793 dwc->tx_thr_num_pkt = tx_thr_num_pkt; 1794 dwc->tx_max_burst = tx_max_burst; 1795 1796 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd; 1797 dwc->rx_max_burst_prd = rx_max_burst_prd; 1798 1799 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd; 1800 dwc->tx_max_burst_prd = tx_max_burst_prd; 1801 1802 dwc->imod_interval = 0; 1803 1804 dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num; 1805 } 1806 1807 /* check whether the core supports IMOD */ 1808 bool dwc3_has_imod(struct dwc3 *dwc) 1809 { 1810 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) || 1811 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) || 1812 DWC3_IP_IS(DWC32); 1813 } 1814 1815 static void dwc3_check_params(struct dwc3 *dwc) 1816 { 1817 struct device *dev = dwc->dev; 1818 unsigned int hwparam_gen = 1819 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3); 1820 1821 /* Check for proper value of imod_interval */ 1822 if (dwc->imod_interval && !dwc3_has_imod(dwc)) { 1823 dev_warn(dwc->dev, "Interrupt moderation not supported\n"); 1824 dwc->imod_interval = 0; 1825 } 1826 1827 /* 1828 * Workaround for STAR 9000961433 which affects only version 1829 * 3.00a of the DWC_usb3 core. This prevents the controller 1830 * interrupt from being masked while handling events. IMOD 1831 * allows us to work around this issue. Enable it for the 1832 * affected version. 1833 */ 1834 if (!dwc->imod_interval && 1835 DWC3_VER_IS(DWC3, 300A)) 1836 dwc->imod_interval = 1; 1837 1838 /* Check the maximum_speed parameter */ 1839 switch (dwc->maximum_speed) { 1840 case USB_SPEED_FULL: 1841 case USB_SPEED_HIGH: 1842 break; 1843 case USB_SPEED_SUPER: 1844 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) 1845 dev_warn(dev, "UDC doesn't support Gen 1\n"); 1846 break; 1847 case USB_SPEED_SUPER_PLUS: 1848 if ((DWC3_IP_IS(DWC32) && 1849 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) || 1850 (!DWC3_IP_IS(DWC32) && 1851 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) 1852 dev_warn(dev, "UDC doesn't support SSP\n"); 1853 break; 1854 default: 1855 dev_err(dev, "invalid maximum_speed parameter %d\n", 1856 dwc->maximum_speed); 1857 fallthrough; 1858 case USB_SPEED_UNKNOWN: 1859 switch (hwparam_gen) { 1860 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 1861 dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1862 break; 1863 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 1864 if (DWC3_IP_IS(DWC32)) 1865 dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1866 else 1867 dwc->maximum_speed = USB_SPEED_SUPER; 1868 break; 1869 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS: 1870 dwc->maximum_speed = USB_SPEED_HIGH; 1871 break; 1872 default: 1873 dwc->maximum_speed = USB_SPEED_SUPER; 1874 break; 1875 } 1876 break; 1877 } 1878 1879 /* 1880 * Currently the controller does not have visibility into the HW 1881 * parameter to determine the maximum number of lanes the HW supports. 1882 * If the number of lanes is not specified in the device property, then 1883 * set the default to support dual-lane for DWC_usb32 and single-lane 1884 * for DWC_usb31 for super-speed-plus. 1885 */ 1886 if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) { 1887 switch (dwc->max_ssp_rate) { 1888 case USB_SSP_GEN_2x1: 1889 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1) 1890 dev_warn(dev, "UDC only supports Gen 1\n"); 1891 break; 1892 case USB_SSP_GEN_1x2: 1893 case USB_SSP_GEN_2x2: 1894 if (DWC3_IP_IS(DWC31)) 1895 dev_warn(dev, "UDC only supports single lane\n"); 1896 break; 1897 case USB_SSP_GEN_UNKNOWN: 1898 default: 1899 switch (hwparam_gen) { 1900 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 1901 if (DWC3_IP_IS(DWC32)) 1902 dwc->max_ssp_rate = USB_SSP_GEN_2x2; 1903 else 1904 dwc->max_ssp_rate = USB_SSP_GEN_2x1; 1905 break; 1906 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 1907 if (DWC3_IP_IS(DWC32)) 1908 dwc->max_ssp_rate = USB_SSP_GEN_1x2; 1909 break; 1910 } 1911 break; 1912 } 1913 } 1914 } 1915 1916 static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc) 1917 { 1918 struct device *dev = dwc->dev; 1919 struct device_node *np_phy; 1920 struct extcon_dev *edev = NULL; 1921 const char *name; 1922 1923 if (device_property_read_bool(dev, "extcon")) 1924 return extcon_get_edev_by_phandle(dev, 0); 1925 1926 /* 1927 * Device tree platforms should get extcon via phandle. 1928 * On ACPI platforms, we get the name from a device property. 1929 * This device property is for kernel internal use only and 1930 * is expected to be set by the glue code. 1931 */ 1932 if (device_property_read_string(dev, "linux,extcon-name", &name) == 0) 1933 return extcon_get_extcon_dev(name); 1934 1935 /* 1936 * Check explicitly if "usb-role-switch" is used since 1937 * extcon_find_edev_by_node() can not be used to check the absence of 1938 * an extcon device. In the absence of an device it will always return 1939 * EPROBE_DEFER. 1940 */ 1941 if (IS_ENABLED(CONFIG_USB_ROLE_SWITCH) && 1942 device_property_read_bool(dev, "usb-role-switch")) 1943 return NULL; 1944 1945 /* 1946 * Try to get an extcon device from the USB PHY controller's "port" 1947 * node. Check if it has the "port" node first, to avoid printing the 1948 * error message from underlying code, as it's a valid case: extcon 1949 * device (and "port" node) may be missing in case of "usb-role-switch" 1950 * or OTG mode. 1951 */ 1952 np_phy = of_parse_phandle(dev->of_node, "phys", 0); 1953 if (of_graph_is_present(np_phy)) { 1954 struct device_node *np_conn; 1955 1956 np_conn = of_graph_get_remote_node(np_phy, -1, -1); 1957 if (np_conn) 1958 edev = extcon_find_edev_by_node(np_conn); 1959 of_node_put(np_conn); 1960 } 1961 of_node_put(np_phy); 1962 1963 return edev; 1964 } 1965 1966 static int dwc3_get_clocks(struct dwc3 *dwc) 1967 { 1968 struct device *dev = dwc->dev; 1969 1970 if (!dev->of_node) 1971 return 0; 1972 1973 /* 1974 * Clocks are optional, but new DT platforms should support all clocks 1975 * as required by the DT-binding. 1976 * Some devices have different clock names in legacy device trees, 1977 * check for them to retain backwards compatibility. 1978 */ 1979 dwc->bus_clk = devm_clk_get_optional(dev, "bus_early"); 1980 if (IS_ERR(dwc->bus_clk)) { 1981 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk), 1982 "could not get bus clock\n"); 1983 } 1984 1985 if (dwc->bus_clk == NULL) { 1986 dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk"); 1987 if (IS_ERR(dwc->bus_clk)) { 1988 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk), 1989 "could not get bus clock\n"); 1990 } 1991 } 1992 1993 dwc->ref_clk = devm_clk_get_optional(dev, "ref"); 1994 if (IS_ERR(dwc->ref_clk)) { 1995 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk), 1996 "could not get ref clock\n"); 1997 } 1998 1999 if (dwc->ref_clk == NULL) { 2000 dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk"); 2001 if (IS_ERR(dwc->ref_clk)) { 2002 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk), 2003 "could not get ref clock\n"); 2004 } 2005 } 2006 2007 dwc->susp_clk = devm_clk_get_optional(dev, "suspend"); 2008 if (IS_ERR(dwc->susp_clk)) { 2009 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk), 2010 "could not get suspend clock\n"); 2011 } 2012 2013 if (dwc->susp_clk == NULL) { 2014 dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk"); 2015 if (IS_ERR(dwc->susp_clk)) { 2016 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk), 2017 "could not get suspend clock\n"); 2018 } 2019 } 2020 2021 /* specific to Rockchip RK3588 */ 2022 dwc->utmi_clk = devm_clk_get_optional(dev, "utmi"); 2023 if (IS_ERR(dwc->utmi_clk)) { 2024 return dev_err_probe(dev, PTR_ERR(dwc->utmi_clk), 2025 "could not get utmi clock\n"); 2026 } 2027 2028 /* specific to Rockchip RK3588 */ 2029 dwc->pipe_clk = devm_clk_get_optional(dev, "pipe"); 2030 if (IS_ERR(dwc->pipe_clk)) { 2031 return dev_err_probe(dev, PTR_ERR(dwc->pipe_clk), 2032 "could not get pipe clock\n"); 2033 } 2034 2035 return 0; 2036 } 2037 2038 static int dwc3_get_num_ports(struct dwc3 *dwc) 2039 { 2040 void __iomem *base; 2041 u8 major_revision; 2042 u32 offset; 2043 u32 val; 2044 2045 /* 2046 * Remap xHCI address space to access XHCI ext cap regs since it is 2047 * needed to get information on number of ports present. 2048 */ 2049 base = ioremap(dwc->xhci_resources[0].start, 2050 resource_size(&dwc->xhci_resources[0])); 2051 if (!base) 2052 return -ENOMEM; 2053 2054 offset = 0; 2055 do { 2056 offset = xhci_find_next_ext_cap(base, offset, 2057 XHCI_EXT_CAPS_PROTOCOL); 2058 if (!offset) 2059 break; 2060 2061 val = readl(base + offset); 2062 major_revision = XHCI_EXT_PORT_MAJOR(val); 2063 2064 val = readl(base + offset + 0x08); 2065 if (major_revision == 0x03) { 2066 dwc->num_usb3_ports += XHCI_EXT_PORT_COUNT(val); 2067 } else if (major_revision <= 0x02) { 2068 dwc->num_usb2_ports += XHCI_EXT_PORT_COUNT(val); 2069 } else { 2070 dev_warn(dwc->dev, "unrecognized port major revision %d\n", 2071 major_revision); 2072 } 2073 } while (1); 2074 2075 dev_dbg(dwc->dev, "hs-ports: %u ss-ports: %u\n", 2076 dwc->num_usb2_ports, dwc->num_usb3_ports); 2077 2078 iounmap(base); 2079 2080 if (dwc->num_usb2_ports > DWC3_USB2_MAX_PORTS || 2081 dwc->num_usb3_ports > DWC3_USB3_MAX_PORTS) 2082 return -EINVAL; 2083 2084 return 0; 2085 } 2086 2087 static int dwc3_probe(struct platform_device *pdev) 2088 { 2089 struct device *dev = &pdev->dev; 2090 struct resource *res, dwc_res; 2091 unsigned int hw_mode; 2092 void __iomem *regs; 2093 struct dwc3 *dwc; 2094 int ret; 2095 2096 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 2097 if (!dwc) 2098 return -ENOMEM; 2099 2100 dwc->dev = dev; 2101 2102 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2103 if (!res) { 2104 dev_err(dev, "missing memory resource\n"); 2105 return -ENODEV; 2106 } 2107 2108 dwc->xhci_resources[0].start = res->start; 2109 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + 2110 DWC3_XHCI_REGS_END; 2111 dwc->xhci_resources[0].flags = res->flags; 2112 dwc->xhci_resources[0].name = res->name; 2113 2114 /* 2115 * Request memory region but exclude xHCI regs, 2116 * since it will be requested by the xhci-plat driver. 2117 */ 2118 dwc_res = *res; 2119 dwc_res.start += DWC3_GLOBALS_REGS_START; 2120 2121 if (dev->of_node) { 2122 struct device_node *parent = of_get_parent(dev->of_node); 2123 2124 if (of_device_is_compatible(parent, "realtek,rtd-dwc3")) { 2125 dwc_res.start -= DWC3_GLOBALS_REGS_START; 2126 dwc_res.start += DWC3_RTK_RTD_GLOBALS_REGS_START; 2127 } 2128 2129 of_node_put(parent); 2130 } 2131 2132 regs = devm_ioremap_resource(dev, &dwc_res); 2133 if (IS_ERR(regs)) 2134 return PTR_ERR(regs); 2135 2136 dwc->regs = regs; 2137 dwc->regs_size = resource_size(&dwc_res); 2138 2139 dwc3_get_properties(dwc); 2140 2141 dwc3_get_software_properties(dwc); 2142 2143 dwc->reset = devm_reset_control_array_get_optional_shared(dev); 2144 if (IS_ERR(dwc->reset)) { 2145 ret = PTR_ERR(dwc->reset); 2146 goto err_put_psy; 2147 } 2148 2149 ret = dwc3_get_clocks(dwc); 2150 if (ret) 2151 goto err_put_psy; 2152 2153 ret = reset_control_deassert(dwc->reset); 2154 if (ret) 2155 goto err_put_psy; 2156 2157 ret = dwc3_clk_enable(dwc); 2158 if (ret) 2159 goto err_assert_reset; 2160 2161 if (!dwc3_core_is_valid(dwc)) { 2162 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 2163 ret = -ENODEV; 2164 goto err_disable_clks; 2165 } 2166 2167 platform_set_drvdata(pdev, dwc); 2168 dwc3_cache_hwparams(dwc); 2169 2170 if (!dwc->sysdev_is_parent && 2171 DWC3_GHWPARAMS0_AWIDTH(dwc->hwparams.hwparams0) == 64) { 2172 ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64)); 2173 if (ret) 2174 goto err_disable_clks; 2175 } 2176 2177 /* 2178 * Currently only DWC3 controllers that are host-only capable 2179 * can have more than one port. 2180 */ 2181 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 2182 if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) { 2183 ret = dwc3_get_num_ports(dwc); 2184 if (ret) 2185 goto err_disable_clks; 2186 } else { 2187 dwc->num_usb2_ports = 1; 2188 dwc->num_usb3_ports = 1; 2189 } 2190 2191 spin_lock_init(&dwc->lock); 2192 mutex_init(&dwc->mutex); 2193 2194 pm_runtime_get_noresume(dev); 2195 pm_runtime_set_active(dev); 2196 pm_runtime_use_autosuspend(dev); 2197 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); 2198 pm_runtime_enable(dev); 2199 2200 pm_runtime_forbid(dev); 2201 2202 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 2203 if (ret) { 2204 dev_err(dwc->dev, "failed to allocate event buffers\n"); 2205 ret = -ENOMEM; 2206 goto err_allow_rpm; 2207 } 2208 2209 dwc->edev = dwc3_get_extcon(dwc); 2210 if (IS_ERR(dwc->edev)) { 2211 ret = dev_err_probe(dwc->dev, PTR_ERR(dwc->edev), "failed to get extcon\n"); 2212 goto err_free_event_buffers; 2213 } 2214 2215 ret = dwc3_get_dr_mode(dwc); 2216 if (ret) 2217 goto err_free_event_buffers; 2218 2219 ret = dwc3_core_init(dwc); 2220 if (ret) { 2221 dev_err_probe(dev, ret, "failed to initialize core\n"); 2222 goto err_free_event_buffers; 2223 } 2224 2225 dwc3_check_params(dwc); 2226 dwc3_debugfs_init(dwc); 2227 2228 ret = dwc3_core_init_mode(dwc); 2229 if (ret) 2230 goto err_exit_debugfs; 2231 2232 pm_runtime_put(dev); 2233 2234 dma_set_max_seg_size(dev, UINT_MAX); 2235 2236 return 0; 2237 2238 err_exit_debugfs: 2239 dwc3_debugfs_exit(dwc); 2240 dwc3_event_buffers_cleanup(dwc); 2241 dwc3_phy_power_off(dwc); 2242 dwc3_phy_exit(dwc); 2243 dwc3_ulpi_exit(dwc); 2244 err_free_event_buffers: 2245 dwc3_free_event_buffers(dwc); 2246 err_allow_rpm: 2247 pm_runtime_allow(dev); 2248 pm_runtime_disable(dev); 2249 pm_runtime_dont_use_autosuspend(dev); 2250 pm_runtime_set_suspended(dev); 2251 pm_runtime_put_noidle(dev); 2252 err_disable_clks: 2253 dwc3_clk_disable(dwc); 2254 err_assert_reset: 2255 reset_control_assert(dwc->reset); 2256 err_put_psy: 2257 if (dwc->usb_psy) 2258 power_supply_put(dwc->usb_psy); 2259 2260 return ret; 2261 } 2262 2263 static void dwc3_remove(struct platform_device *pdev) 2264 { 2265 struct dwc3 *dwc = platform_get_drvdata(pdev); 2266 2267 pm_runtime_get_sync(&pdev->dev); 2268 2269 dwc3_core_exit_mode(dwc); 2270 dwc3_debugfs_exit(dwc); 2271 2272 dwc3_core_exit(dwc); 2273 dwc3_ulpi_exit(dwc); 2274 2275 pm_runtime_allow(&pdev->dev); 2276 pm_runtime_disable(&pdev->dev); 2277 pm_runtime_dont_use_autosuspend(&pdev->dev); 2278 pm_runtime_put_noidle(&pdev->dev); 2279 /* 2280 * HACK: Clear the driver data, which is currently accessed by parent 2281 * glue drivers, before allowing the parent to suspend. 2282 */ 2283 platform_set_drvdata(pdev, NULL); 2284 pm_runtime_set_suspended(&pdev->dev); 2285 2286 dwc3_free_event_buffers(dwc); 2287 2288 if (dwc->usb_psy) 2289 power_supply_put(dwc->usb_psy); 2290 } 2291 2292 #ifdef CONFIG_PM 2293 static int dwc3_core_init_for_resume(struct dwc3 *dwc) 2294 { 2295 int ret; 2296 2297 ret = reset_control_deassert(dwc->reset); 2298 if (ret) 2299 return ret; 2300 2301 ret = dwc3_clk_enable(dwc); 2302 if (ret) 2303 goto assert_reset; 2304 2305 ret = dwc3_core_init(dwc); 2306 if (ret) 2307 goto disable_clks; 2308 2309 return 0; 2310 2311 disable_clks: 2312 dwc3_clk_disable(dwc); 2313 assert_reset: 2314 reset_control_assert(dwc->reset); 2315 2316 return ret; 2317 } 2318 2319 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) 2320 { 2321 u32 reg; 2322 int i; 2323 2324 switch (dwc->current_dr_role) { 2325 case DWC3_GCTL_PRTCAP_DEVICE: 2326 if (pm_runtime_suspended(dwc->dev)) 2327 break; 2328 dwc3_gadget_suspend(dwc); 2329 synchronize_irq(dwc->irq_gadget); 2330 dwc3_core_exit(dwc); 2331 break; 2332 case DWC3_GCTL_PRTCAP_HOST: 2333 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) { 2334 dwc3_core_exit(dwc); 2335 break; 2336 } 2337 2338 /* Let controller to suspend HSPHY before PHY driver suspends */ 2339 if (dwc->dis_u2_susphy_quirk || 2340 dwc->dis_enblslpm_quirk) { 2341 for (i = 0; i < dwc->num_usb2_ports; i++) { 2342 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i)); 2343 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM | 2344 DWC3_GUSB2PHYCFG_SUSPHY; 2345 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg); 2346 } 2347 2348 /* Give some time for USB2 PHY to suspend */ 2349 usleep_range(5000, 6000); 2350 } 2351 2352 for (i = 0; i < dwc->num_usb2_ports; i++) 2353 phy_pm_runtime_put_sync(dwc->usb2_generic_phy[i]); 2354 for (i = 0; i < dwc->num_usb3_ports; i++) 2355 phy_pm_runtime_put_sync(dwc->usb3_generic_phy[i]); 2356 break; 2357 case DWC3_GCTL_PRTCAP_OTG: 2358 /* do nothing during runtime_suspend */ 2359 if (PMSG_IS_AUTO(msg)) 2360 break; 2361 2362 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 2363 dwc3_gadget_suspend(dwc); 2364 synchronize_irq(dwc->irq_gadget); 2365 } 2366 2367 dwc3_otg_exit(dwc); 2368 dwc3_core_exit(dwc); 2369 break; 2370 default: 2371 /* do nothing */ 2372 break; 2373 } 2374 2375 return 0; 2376 } 2377 2378 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) 2379 { 2380 int ret; 2381 u32 reg; 2382 int i; 2383 2384 switch (dwc->current_dr_role) { 2385 case DWC3_GCTL_PRTCAP_DEVICE: 2386 ret = dwc3_core_init_for_resume(dwc); 2387 if (ret) 2388 return ret; 2389 2390 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 2391 dwc3_gadget_resume(dwc); 2392 break; 2393 case DWC3_GCTL_PRTCAP_HOST: 2394 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) { 2395 ret = dwc3_core_init_for_resume(dwc); 2396 if (ret) 2397 return ret; 2398 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 2399 break; 2400 } 2401 /* Restore GUSB2PHYCFG bits that were modified in suspend */ 2402 for (i = 0; i < dwc->num_usb2_ports; i++) { 2403 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i)); 2404 if (dwc->dis_u2_susphy_quirk) 2405 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 2406 2407 if (dwc->dis_enblslpm_quirk) 2408 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 2409 2410 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg); 2411 } 2412 2413 for (i = 0; i < dwc->num_usb2_ports; i++) 2414 phy_pm_runtime_get_sync(dwc->usb2_generic_phy[i]); 2415 for (i = 0; i < dwc->num_usb3_ports; i++) 2416 phy_pm_runtime_get_sync(dwc->usb3_generic_phy[i]); 2417 break; 2418 case DWC3_GCTL_PRTCAP_OTG: 2419 /* nothing to do on runtime_resume */ 2420 if (PMSG_IS_AUTO(msg)) 2421 break; 2422 2423 ret = dwc3_core_init_for_resume(dwc); 2424 if (ret) 2425 return ret; 2426 2427 dwc3_set_prtcap(dwc, dwc->current_dr_role); 2428 2429 dwc3_otg_init(dwc); 2430 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) { 2431 dwc3_otg_host_init(dwc); 2432 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 2433 dwc3_gadget_resume(dwc); 2434 } 2435 2436 break; 2437 default: 2438 /* do nothing */ 2439 break; 2440 } 2441 2442 return 0; 2443 } 2444 2445 static int dwc3_runtime_checks(struct dwc3 *dwc) 2446 { 2447 switch (dwc->current_dr_role) { 2448 case DWC3_GCTL_PRTCAP_DEVICE: 2449 if (dwc->connected) 2450 return -EBUSY; 2451 break; 2452 case DWC3_GCTL_PRTCAP_HOST: 2453 default: 2454 /* do nothing */ 2455 break; 2456 } 2457 2458 return 0; 2459 } 2460 2461 static int dwc3_runtime_suspend(struct device *dev) 2462 { 2463 struct dwc3 *dwc = dev_get_drvdata(dev); 2464 int ret; 2465 2466 if (dwc3_runtime_checks(dwc)) 2467 return -EBUSY; 2468 2469 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND); 2470 if (ret) 2471 return ret; 2472 2473 return 0; 2474 } 2475 2476 static int dwc3_runtime_resume(struct device *dev) 2477 { 2478 struct dwc3 *dwc = dev_get_drvdata(dev); 2479 int ret; 2480 2481 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME); 2482 if (ret) 2483 return ret; 2484 2485 switch (dwc->current_dr_role) { 2486 case DWC3_GCTL_PRTCAP_DEVICE: 2487 dwc3_gadget_process_pending_events(dwc); 2488 break; 2489 case DWC3_GCTL_PRTCAP_HOST: 2490 default: 2491 /* do nothing */ 2492 break; 2493 } 2494 2495 pm_runtime_mark_last_busy(dev); 2496 2497 return 0; 2498 } 2499 2500 static int dwc3_runtime_idle(struct device *dev) 2501 { 2502 struct dwc3 *dwc = dev_get_drvdata(dev); 2503 2504 switch (dwc->current_dr_role) { 2505 case DWC3_GCTL_PRTCAP_DEVICE: 2506 if (dwc3_runtime_checks(dwc)) 2507 return -EBUSY; 2508 break; 2509 case DWC3_GCTL_PRTCAP_HOST: 2510 default: 2511 /* do nothing */ 2512 break; 2513 } 2514 2515 pm_runtime_mark_last_busy(dev); 2516 pm_runtime_autosuspend(dev); 2517 2518 return 0; 2519 } 2520 #endif /* CONFIG_PM */ 2521 2522 #ifdef CONFIG_PM_SLEEP 2523 static int dwc3_suspend(struct device *dev) 2524 { 2525 struct dwc3 *dwc = dev_get_drvdata(dev); 2526 int ret; 2527 2528 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND); 2529 if (ret) 2530 return ret; 2531 2532 pinctrl_pm_select_sleep_state(dev); 2533 2534 return 0; 2535 } 2536 2537 static int dwc3_resume(struct device *dev) 2538 { 2539 struct dwc3 *dwc = dev_get_drvdata(dev); 2540 int ret; 2541 2542 pinctrl_pm_select_default_state(dev); 2543 2544 pm_runtime_disable(dev); 2545 pm_runtime_set_active(dev); 2546 2547 ret = dwc3_resume_common(dwc, PMSG_RESUME); 2548 if (ret) { 2549 pm_runtime_set_suspended(dev); 2550 return ret; 2551 } 2552 2553 pm_runtime_enable(dev); 2554 2555 return 0; 2556 } 2557 2558 static void dwc3_complete(struct device *dev) 2559 { 2560 struct dwc3 *dwc = dev_get_drvdata(dev); 2561 u32 reg; 2562 2563 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST && 2564 dwc->dis_split_quirk) { 2565 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 2566 reg |= DWC3_GUCTL3_SPLITDISABLE; 2567 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 2568 } 2569 } 2570 #else 2571 #define dwc3_complete NULL 2572 #endif /* CONFIG_PM_SLEEP */ 2573 2574 static const struct dev_pm_ops dwc3_dev_pm_ops = { 2575 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) 2576 .complete = dwc3_complete, 2577 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, 2578 dwc3_runtime_idle) 2579 }; 2580 2581 #ifdef CONFIG_OF 2582 static const struct of_device_id of_dwc3_match[] = { 2583 { 2584 .compatible = "snps,dwc3" 2585 }, 2586 { 2587 .compatible = "synopsys,dwc3" 2588 }, 2589 { }, 2590 }; 2591 MODULE_DEVICE_TABLE(of, of_dwc3_match); 2592 #endif 2593 2594 #ifdef CONFIG_ACPI 2595 2596 #define ACPI_ID_INTEL_BSW "808622B7" 2597 2598 static const struct acpi_device_id dwc3_acpi_match[] = { 2599 { ACPI_ID_INTEL_BSW, 0 }, 2600 { }, 2601 }; 2602 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); 2603 #endif 2604 2605 static struct platform_driver dwc3_driver = { 2606 .probe = dwc3_probe, 2607 .remove_new = dwc3_remove, 2608 .driver = { 2609 .name = "dwc3", 2610 .of_match_table = of_match_ptr(of_dwc3_match), 2611 .acpi_match_table = ACPI_PTR(dwc3_acpi_match), 2612 .pm = &dwc3_dev_pm_ops, 2613 }, 2614 }; 2615 2616 module_platform_driver(dwc3_driver); 2617 2618 MODULE_ALIAS("platform:dwc3"); 2619 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 2620 MODULE_LICENSE("GPL v2"); 2621 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 2622