1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * core.c - DesignWare USB3 DRD Controller Core file 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/version.h> 13 #include <linux/module.h> 14 #include <linux/kernel.h> 15 #include <linux/slab.h> 16 #include <linux/spinlock.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/interrupt.h> 20 #include <linux/ioport.h> 21 #include <linux/io.h> 22 #include <linux/list.h> 23 #include <linux/delay.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/of.h> 26 #include <linux/of_graph.h> 27 #include <linux/acpi.h> 28 #include <linux/pci.h> 29 #include <linux/pinctrl/consumer.h> 30 #include <linux/pinctrl/devinfo.h> 31 #include <linux/reset.h> 32 #include <linux/bitfield.h> 33 34 #include <linux/usb/ch9.h> 35 #include <linux/usb/gadget.h> 36 #include <linux/usb/of.h> 37 #include <linux/usb/otg.h> 38 39 #include "core.h" 40 #include "gadget.h" 41 #include "glue.h" 42 #include "io.h" 43 44 #include "debug.h" 45 #include "../host/xhci-ext-caps.h" 46 47 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ 48 49 /** 50 * dwc3_get_dr_mode - Validates and sets dr_mode 51 * @dwc: pointer to our context structure 52 */ 53 static int dwc3_get_dr_mode(struct dwc3 *dwc) 54 { 55 enum usb_dr_mode mode; 56 struct device *dev = dwc->dev; 57 unsigned int hw_mode; 58 59 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 60 dwc->dr_mode = USB_DR_MODE_OTG; 61 62 mode = dwc->dr_mode; 63 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 64 65 switch (hw_mode) { 66 case DWC3_GHWPARAMS0_MODE_GADGET: 67 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) { 68 dev_err(dev, 69 "Controller does not support host mode.\n"); 70 return -EINVAL; 71 } 72 mode = USB_DR_MODE_PERIPHERAL; 73 break; 74 case DWC3_GHWPARAMS0_MODE_HOST: 75 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { 76 dev_err(dev, 77 "Controller does not support device mode.\n"); 78 return -EINVAL; 79 } 80 mode = USB_DR_MODE_HOST; 81 break; 82 default: 83 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 84 mode = USB_DR_MODE_HOST; 85 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 86 mode = USB_DR_MODE_PERIPHERAL; 87 88 /* 89 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG 90 * mode. If the controller supports DRD but the dr_mode is not 91 * specified or set to OTG, then set the mode to peripheral. 92 */ 93 if (mode == USB_DR_MODE_OTG && !dwc->edev && 94 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) || 95 !device_property_read_bool(dwc->dev, "usb-role-switch")) && 96 !DWC3_VER_IS_PRIOR(DWC3, 330A)) 97 mode = USB_DR_MODE_PERIPHERAL; 98 } 99 100 if (mode != dwc->dr_mode) { 101 dev_warn(dev, 102 "Configuration mismatch. dr_mode forced to %s\n", 103 mode == USB_DR_MODE_HOST ? "host" : "gadget"); 104 105 dwc->dr_mode = mode; 106 } 107 108 return 0; 109 } 110 111 void dwc3_enable_susphy(struct dwc3 *dwc, bool enable) 112 { 113 u32 reg; 114 int i; 115 116 for (i = 0; i < dwc->num_usb3_ports; i++) { 117 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(i)); 118 if (enable && !dwc->dis_u3_susphy_quirk) 119 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 120 else 121 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 122 123 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(i), reg); 124 } 125 126 for (i = 0; i < dwc->num_usb2_ports; i++) { 127 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i)); 128 if (enable && !dwc->dis_u2_susphy_quirk) 129 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 130 else 131 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 132 133 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg); 134 } 135 } 136 EXPORT_SYMBOL_GPL(dwc3_enable_susphy); 137 138 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode, bool ignore_susphy) 139 { 140 unsigned int hw_mode; 141 u32 reg; 142 143 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 144 145 /* 146 * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE and 147 * GUSB2PHYCFG.SUSPHY should be cleared during mode switching, 148 * and they can be set after core initialization. 149 */ 150 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 151 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD && !ignore_susphy) { 152 if (DWC3_GCTL_PRTCAP(reg) != mode) 153 dwc3_enable_susphy(dwc, false); 154 } 155 156 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 157 reg |= DWC3_GCTL_PRTCAPDIR(mode); 158 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 159 160 dwc->current_dr_role = mode; 161 trace_dwc3_set_prtcap(mode); 162 } 163 EXPORT_SYMBOL_GPL(dwc3_set_prtcap); 164 165 static void __dwc3_set_mode(struct work_struct *work) 166 { 167 struct dwc3 *dwc = work_to_dwc(work); 168 unsigned long flags; 169 int ret; 170 u32 reg; 171 u32 desired_dr_role; 172 int i; 173 174 mutex_lock(&dwc->mutex); 175 spin_lock_irqsave(&dwc->lock, flags); 176 desired_dr_role = dwc->desired_dr_role; 177 spin_unlock_irqrestore(&dwc->lock, flags); 178 179 pm_runtime_get_sync(dwc->dev); 180 181 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG) 182 dwc3_otg_update(dwc, 0); 183 184 if (!desired_dr_role) 185 goto out; 186 187 if (desired_dr_role == dwc->current_dr_role) 188 goto out; 189 190 if (desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev) 191 goto out; 192 193 switch (dwc->current_dr_role) { 194 case DWC3_GCTL_PRTCAP_HOST: 195 dwc3_host_exit(dwc); 196 break; 197 case DWC3_GCTL_PRTCAP_DEVICE: 198 dwc3_gadget_exit(dwc); 199 dwc3_event_buffers_cleanup(dwc); 200 break; 201 case DWC3_GCTL_PRTCAP_OTG: 202 dwc3_otg_exit(dwc); 203 spin_lock_irqsave(&dwc->lock, flags); 204 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE; 205 spin_unlock_irqrestore(&dwc->lock, flags); 206 dwc3_otg_update(dwc, 1); 207 break; 208 default: 209 break; 210 } 211 212 /* 213 * When current_dr_role is not set, there's no role switching. 214 * Only perform GCTL.CoreSoftReset when there's DRD role switching. 215 */ 216 if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) || 217 DWC3_VER_IS_PRIOR(DWC31, 190A)) && 218 desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) { 219 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 220 reg |= DWC3_GCTL_CORESOFTRESET; 221 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 222 223 /* 224 * Wait for internal clocks to synchronized. DWC_usb31 and 225 * DWC_usb32 may need at least 50ms (less for DWC_usb3). To 226 * keep it consistent across different IPs, let's wait up to 227 * 100ms before clearing GCTL.CORESOFTRESET. 228 */ 229 msleep(100); 230 231 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 232 reg &= ~DWC3_GCTL_CORESOFTRESET; 233 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 234 } 235 236 spin_lock_irqsave(&dwc->lock, flags); 237 238 dwc3_set_prtcap(dwc, desired_dr_role, false); 239 240 spin_unlock_irqrestore(&dwc->lock, flags); 241 242 switch (desired_dr_role) { 243 case DWC3_GCTL_PRTCAP_HOST: 244 ret = dwc3_host_init(dwc); 245 if (ret) { 246 dev_err(dwc->dev, "failed to initialize host\n"); 247 } else { 248 if (dwc->usb2_phy) 249 otg_set_vbus(dwc->usb2_phy->otg, true); 250 251 for (i = 0; i < dwc->num_usb2_ports; i++) 252 phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST); 253 for (i = 0; i < dwc->num_usb3_ports; i++) 254 phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST); 255 256 if (dwc->dis_split_quirk) { 257 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 258 reg |= DWC3_GUCTL3_SPLITDISABLE; 259 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 260 } 261 } 262 break; 263 case DWC3_GCTL_PRTCAP_DEVICE: 264 dwc3_core_soft_reset(dwc); 265 266 dwc3_event_buffers_setup(dwc); 267 268 if (dwc->usb2_phy) 269 otg_set_vbus(dwc->usb2_phy->otg, false); 270 phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE); 271 phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE); 272 273 ret = dwc3_gadget_init(dwc); 274 if (ret) 275 dev_err(dwc->dev, "failed to initialize peripheral\n"); 276 break; 277 case DWC3_GCTL_PRTCAP_OTG: 278 dwc3_otg_init(dwc); 279 dwc3_otg_update(dwc, 0); 280 break; 281 default: 282 break; 283 } 284 285 out: 286 pm_runtime_put_autosuspend(dwc->dev); 287 mutex_unlock(&dwc->mutex); 288 } 289 290 void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 291 { 292 unsigned long flags; 293 294 if (dwc->dr_mode != USB_DR_MODE_OTG) 295 return; 296 297 spin_lock_irqsave(&dwc->lock, flags); 298 dwc->desired_dr_role = mode; 299 spin_unlock_irqrestore(&dwc->lock, flags); 300 301 queue_work(system_freezable_wq, &dwc->drd_work); 302 } 303 304 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) 305 { 306 struct dwc3 *dwc = dep->dwc; 307 u32 reg; 308 309 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, 310 DWC3_GDBGFIFOSPACE_NUM(dep->number) | 311 DWC3_GDBGFIFOSPACE_TYPE(type)); 312 313 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); 314 315 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); 316 } 317 318 /** 319 * dwc3_core_soft_reset - Issues core soft reset and PHY reset 320 * @dwc: pointer to our context structure 321 */ 322 int dwc3_core_soft_reset(struct dwc3 *dwc) 323 { 324 u32 reg; 325 int retries = 1000; 326 327 /* 328 * We're resetting only the device side because, if we're in host mode, 329 * XHCI driver will reset the host block. If dwc3 was configured for 330 * host-only mode, then we can return early. 331 */ 332 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) 333 return 0; 334 335 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 336 reg |= DWC3_DCTL_CSFTRST; 337 reg &= ~DWC3_DCTL_RUN_STOP; 338 dwc3_gadget_dctl_write_safe(dwc, reg); 339 340 /* 341 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit 342 * is cleared only after all the clocks are synchronized. This can 343 * take a little more than 50ms. Set the polling rate at 20ms 344 * for 10 times instead. 345 */ 346 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 347 retries = 10; 348 349 do { 350 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 351 if (!(reg & DWC3_DCTL_CSFTRST)) 352 goto done; 353 354 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 355 msleep(20); 356 else 357 udelay(1); 358 } while (--retries); 359 360 dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n"); 361 return -ETIMEDOUT; 362 363 done: 364 /* 365 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit 366 * is cleared, we must wait at least 50ms before accessing the PHY 367 * domain (synchronization delay). 368 */ 369 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A)) 370 msleep(50); 371 372 return 0; 373 } 374 375 /* 376 * dwc3_frame_length_adjustment - Adjusts frame length if required 377 * @dwc3: Pointer to our controller context structure 378 */ 379 static void dwc3_frame_length_adjustment(struct dwc3 *dwc) 380 { 381 u32 reg; 382 u32 dft; 383 384 if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 385 return; 386 387 if (dwc->fladj == 0) 388 return; 389 390 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 391 dft = reg & DWC3_GFLADJ_30MHZ_MASK; 392 if (dft != dwc->fladj) { 393 reg &= ~DWC3_GFLADJ_30MHZ_MASK; 394 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; 395 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 396 } 397 } 398 399 /** 400 * dwc3_ref_clk_period - Reference clock period configuration 401 * Default reference clock period depends on hardware 402 * configuration. For systems with reference clock that differs 403 * from the default, this will set clock period in DWC3_GUCTL 404 * register. 405 * @dwc: Pointer to our controller context structure 406 */ 407 static void dwc3_ref_clk_period(struct dwc3 *dwc) 408 { 409 unsigned long period; 410 unsigned long fladj; 411 unsigned long decr; 412 unsigned long rate; 413 u32 reg; 414 415 if (dwc->ref_clk) { 416 rate = clk_get_rate(dwc->ref_clk); 417 if (!rate) 418 return; 419 period = NSEC_PER_SEC / rate; 420 } else if (dwc->ref_clk_per) { 421 period = dwc->ref_clk_per; 422 rate = NSEC_PER_SEC / period; 423 } else { 424 return; 425 } 426 427 reg = dwc3_readl(dwc->regs, DWC3_GUCTL); 428 reg &= ~DWC3_GUCTL_REFCLKPER_MASK; 429 reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period); 430 dwc3_writel(dwc->regs, DWC3_GUCTL, reg); 431 432 if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 433 return; 434 435 /* 436 * The calculation below is 437 * 438 * 125000 * (NSEC_PER_SEC / (rate * period) - 1) 439 * 440 * but rearranged for fixed-point arithmetic. The division must be 441 * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and 442 * neither does rate * period). 443 * 444 * Note that rate * period ~= NSEC_PER_SECOND, minus the number of 445 * nanoseconds of error caused by the truncation which happened during 446 * the division when calculating rate or period (whichever one was 447 * derived from the other). We first calculate the relative error, then 448 * scale it to units of 8 ppm. 449 */ 450 fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period); 451 fladj -= 125000; 452 453 /* 454 * The documented 240MHz constant is scaled by 2 to get PLS1 as well. 455 */ 456 decr = 480000000 / rate; 457 458 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 459 reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK 460 & ~DWC3_GFLADJ_240MHZDECR 461 & ~DWC3_GFLADJ_240MHZDECR_PLS1; 462 reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj) 463 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1) 464 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1); 465 466 if (dwc->gfladj_refclk_lpm_sel) 467 reg |= DWC3_GFLADJ_REFCLK_LPM_SEL; 468 469 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 470 } 471 472 /** 473 * dwc3_free_one_event_buffer - Frees one event buffer 474 * @dwc: Pointer to our controller context structure 475 * @evt: Pointer to event buffer to be freed 476 */ 477 static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 478 struct dwc3_event_buffer *evt) 479 { 480 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma); 481 } 482 483 /** 484 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 485 * @dwc: Pointer to our controller context structure 486 * @length: size of the event buffer 487 * 488 * Returns a pointer to the allocated event buffer structure on success 489 * otherwise ERR_PTR(errno). 490 */ 491 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 492 unsigned int length) 493 { 494 struct dwc3_event_buffer *evt; 495 496 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 497 if (!evt) 498 return ERR_PTR(-ENOMEM); 499 500 evt->dwc = dwc; 501 evt->length = length; 502 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL); 503 if (!evt->cache) 504 return ERR_PTR(-ENOMEM); 505 506 evt->buf = dma_alloc_coherent(dwc->sysdev, length, 507 &evt->dma, GFP_KERNEL); 508 if (!evt->buf) 509 return ERR_PTR(-ENOMEM); 510 511 return evt; 512 } 513 514 /** 515 * dwc3_free_event_buffers - frees all allocated event buffers 516 * @dwc: Pointer to our controller context structure 517 */ 518 static void dwc3_free_event_buffers(struct dwc3 *dwc) 519 { 520 struct dwc3_event_buffer *evt; 521 522 evt = dwc->ev_buf; 523 if (evt) 524 dwc3_free_one_event_buffer(dwc, evt); 525 } 526 527 /** 528 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 529 * @dwc: pointer to our controller context structure 530 * @length: size of event buffer 531 * 532 * Returns 0 on success otherwise negative errno. In the error case, dwc 533 * may contain some buffers allocated but not all which were requested. 534 */ 535 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length) 536 { 537 struct dwc3_event_buffer *evt; 538 unsigned int hw_mode; 539 540 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 541 if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) { 542 dwc->ev_buf = NULL; 543 return 0; 544 } 545 546 evt = dwc3_alloc_one_event_buffer(dwc, length); 547 if (IS_ERR(evt)) { 548 dev_err(dwc->dev, "can't allocate event buffer\n"); 549 return PTR_ERR(evt); 550 } 551 dwc->ev_buf = evt; 552 553 return 0; 554 } 555 556 /** 557 * dwc3_event_buffers_setup - setup our allocated event buffers 558 * @dwc: pointer to our controller context structure 559 * 560 * Returns 0 on success otherwise negative errno. 561 */ 562 int dwc3_event_buffers_setup(struct dwc3 *dwc) 563 { 564 struct dwc3_event_buffer *evt; 565 u32 reg; 566 567 if (!dwc->ev_buf) 568 return 0; 569 570 evt = dwc->ev_buf; 571 evt->lpos = 0; 572 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 573 lower_32_bits(evt->dma)); 574 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 575 upper_32_bits(evt->dma)); 576 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), 577 DWC3_GEVNTSIZ_SIZE(evt->length)); 578 579 /* Clear any stale event */ 580 reg = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0)); 581 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), reg); 582 return 0; 583 } 584 585 void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 586 { 587 struct dwc3_event_buffer *evt; 588 u32 reg; 589 590 if (!dwc->ev_buf) 591 return; 592 /* 593 * Exynos platforms may not be able to access event buffer if the 594 * controller failed to halt on dwc3_core_exit(). 595 */ 596 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 597 if (!(reg & DWC3_DSTS_DEVCTRLHLT)) 598 return; 599 600 evt = dwc->ev_buf; 601 602 evt->lpos = 0; 603 604 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); 605 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); 606 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK 607 | DWC3_GEVNTSIZ_SIZE(0)); 608 609 /* Clear any stale event */ 610 reg = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0)); 611 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), reg); 612 } 613 614 static void dwc3_core_num_eps(struct dwc3 *dwc) 615 { 616 struct dwc3_hwparams *parms = &dwc->hwparams; 617 618 dwc->num_eps = DWC3_NUM_EPS(parms); 619 } 620 621 static void dwc3_cache_hwparams(struct dwc3 *dwc) 622 { 623 struct dwc3_hwparams *parms = &dwc->hwparams; 624 625 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 626 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 627 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 628 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 629 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 630 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 631 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 632 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 633 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 634 635 if (DWC3_IP_IS(DWC32)) 636 parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9); 637 } 638 639 static void dwc3_config_soc_bus(struct dwc3 *dwc) 640 { 641 if (dwc->gsbuscfg0_reqinfo != DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED) { 642 u32 reg; 643 644 reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); 645 reg &= ~DWC3_GSBUSCFG0_REQINFO(~0); 646 reg |= DWC3_GSBUSCFG0_REQINFO(dwc->gsbuscfg0_reqinfo); 647 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg); 648 } 649 } 650 651 static int dwc3_core_ulpi_init(struct dwc3 *dwc) 652 { 653 int intf; 654 int ret = 0; 655 656 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3); 657 658 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI || 659 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI && 660 dwc->hsphy_interface && 661 !strncmp(dwc->hsphy_interface, "ulpi", 4))) 662 ret = dwc3_ulpi_init(dwc); 663 664 return ret; 665 } 666 667 static int dwc3_ss_phy_setup(struct dwc3 *dwc, int index) 668 { 669 u32 reg; 670 671 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(index)); 672 673 /* 674 * Make sure UX_EXIT_PX is cleared as that causes issues with some 675 * PHYs. Also, this bit is not supposed to be used in normal operation. 676 */ 677 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; 678 679 /* Ensure the GUSB3PIPECTL.SUSPENDENABLE is cleared prior to phy init. */ 680 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 681 682 if (dwc->u2ss_inp3_quirk) 683 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 684 685 if (dwc->dis_rxdet_inp3_quirk) 686 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; 687 688 if (dwc->req_p1p2p3_quirk) 689 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 690 691 if (dwc->del_p1p2p3_quirk) 692 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 693 694 if (dwc->del_phy_power_chg_quirk) 695 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 696 697 if (dwc->lfps_filter_quirk) 698 reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 699 700 if (dwc->rx_detect_poll_quirk) 701 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 702 703 if (dwc->tx_de_emphasis_quirk) 704 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 705 706 if (dwc->dis_del_phy_power_chg_quirk) 707 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; 708 709 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(index), reg); 710 711 return 0; 712 } 713 714 static int dwc3_hs_phy_setup(struct dwc3 *dwc, int index) 715 { 716 u32 reg; 717 718 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(index)); 719 720 /* Select the HS PHY interface */ 721 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { 722 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: 723 if (dwc->hsphy_interface && 724 !strncmp(dwc->hsphy_interface, "utmi", 4)) { 725 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; 726 break; 727 } else if (dwc->hsphy_interface && 728 !strncmp(dwc->hsphy_interface, "ulpi", 4)) { 729 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; 730 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg); 731 } else { 732 /* Relying on default value. */ 733 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) 734 break; 735 } 736 fallthrough; 737 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: 738 default: 739 break; 740 } 741 742 switch (dwc->hsphy_mode) { 743 case USBPHY_INTERFACE_MODE_UTMI: 744 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 745 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 746 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | 747 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); 748 break; 749 case USBPHY_INTERFACE_MODE_UTMIW: 750 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 751 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 752 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | 753 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 754 break; 755 default: 756 break; 757 } 758 759 /* Ensure the GUSB2PHYCFG.SUSPHY is cleared prior to phy init. */ 760 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 761 762 if (dwc->dis_enblslpm_quirk) 763 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 764 else 765 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM; 766 767 if (dwc->dis_u2_freeclk_exists_quirk || dwc->gfladj_refclk_lpm_sel) 768 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 769 770 /* 771 * Some ULPI USB PHY does not support internal VBUS supply, to drive 772 * the CPEN pin requires the configuration of the ULPI DRVVBUSEXTERNAL 773 * bit of OTG_CTRL register. Controller configures the USB2 PHY 774 * ULPIEXTVBUSDRV bit[17] of the GUSB2PHYCFG register to drive vBus 775 * with an external supply. 776 */ 777 if (dwc->ulpi_ext_vbus_drv) 778 reg |= DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV; 779 780 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg); 781 782 return 0; 783 } 784 785 /** 786 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 787 * @dwc: Pointer to our controller context structure 788 * 789 * Returns 0 on success. The USB PHY interfaces are configured but not 790 * initialized. The PHY interfaces and the PHYs get initialized together with 791 * the core in dwc3_core_init. 792 */ 793 static int dwc3_phy_setup(struct dwc3 *dwc) 794 { 795 int i; 796 int ret; 797 798 for (i = 0; i < dwc->num_usb3_ports; i++) { 799 ret = dwc3_ss_phy_setup(dwc, i); 800 if (ret) 801 return ret; 802 } 803 804 for (i = 0; i < dwc->num_usb2_ports; i++) { 805 ret = dwc3_hs_phy_setup(dwc, i); 806 if (ret) 807 return ret; 808 } 809 810 return 0; 811 } 812 813 static int dwc3_phy_init(struct dwc3 *dwc) 814 { 815 int ret; 816 int i; 817 int j; 818 819 usb_phy_init(dwc->usb2_phy); 820 usb_phy_init(dwc->usb3_phy); 821 822 for (i = 0; i < dwc->num_usb2_ports; i++) { 823 ret = phy_init(dwc->usb2_generic_phy[i]); 824 if (ret < 0) 825 goto err_exit_usb2_phy; 826 } 827 828 for (j = 0; j < dwc->num_usb3_ports; j++) { 829 ret = phy_init(dwc->usb3_generic_phy[j]); 830 if (ret < 0) 831 goto err_exit_usb3_phy; 832 } 833 834 /* 835 * Above DWC_usb3.0 1.94a, it is recommended to set 836 * DWC3_GUSB3PIPECTL_SUSPHY and DWC3_GUSB2PHYCFG_SUSPHY to '0' during 837 * coreConsultant configuration. So default value will be '0' when the 838 * core is reset. Application needs to set it to '1' after the core 839 * initialization is completed. 840 * 841 * Certain phy requires to be in P0 power state during initialization. 842 * Make sure GUSB3PIPECTL.SUSPENDENABLE and GUSB2PHYCFG.SUSPHY are clear 843 * prior to phy init to maintain in the P0 state. 844 * 845 * After phy initialization, some phy operations can only be executed 846 * while in lower P states. Ensure GUSB3PIPECTL.SUSPENDENABLE and 847 * GUSB2PHYCFG.SUSPHY are set soon after initialization to avoid 848 * blocking phy ops. 849 */ 850 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) 851 dwc3_enable_susphy(dwc, true); 852 853 return 0; 854 855 err_exit_usb3_phy: 856 while (--j >= 0) 857 phy_exit(dwc->usb3_generic_phy[j]); 858 859 err_exit_usb2_phy: 860 while (--i >= 0) 861 phy_exit(dwc->usb2_generic_phy[i]); 862 863 usb_phy_shutdown(dwc->usb3_phy); 864 usb_phy_shutdown(dwc->usb2_phy); 865 866 return ret; 867 } 868 869 static void dwc3_phy_exit(struct dwc3 *dwc) 870 { 871 int i; 872 873 for (i = 0; i < dwc->num_usb3_ports; i++) 874 phy_exit(dwc->usb3_generic_phy[i]); 875 876 for (i = 0; i < dwc->num_usb2_ports; i++) 877 phy_exit(dwc->usb2_generic_phy[i]); 878 879 usb_phy_shutdown(dwc->usb3_phy); 880 usb_phy_shutdown(dwc->usb2_phy); 881 } 882 883 static int dwc3_phy_power_on(struct dwc3 *dwc) 884 { 885 int ret; 886 int i; 887 int j; 888 889 usb_phy_set_suspend(dwc->usb2_phy, 0); 890 usb_phy_set_suspend(dwc->usb3_phy, 0); 891 892 for (i = 0; i < dwc->num_usb2_ports; i++) { 893 ret = phy_power_on(dwc->usb2_generic_phy[i]); 894 if (ret < 0) 895 goto err_power_off_usb2_phy; 896 } 897 898 for (j = 0; j < dwc->num_usb3_ports; j++) { 899 ret = phy_power_on(dwc->usb3_generic_phy[j]); 900 if (ret < 0) 901 goto err_power_off_usb3_phy; 902 } 903 904 return 0; 905 906 err_power_off_usb3_phy: 907 while (--j >= 0) 908 phy_power_off(dwc->usb3_generic_phy[j]); 909 910 err_power_off_usb2_phy: 911 while (--i >= 0) 912 phy_power_off(dwc->usb2_generic_phy[i]); 913 914 usb_phy_set_suspend(dwc->usb3_phy, 1); 915 usb_phy_set_suspend(dwc->usb2_phy, 1); 916 917 return ret; 918 } 919 920 static void dwc3_phy_power_off(struct dwc3 *dwc) 921 { 922 int i; 923 924 for (i = 0; i < dwc->num_usb3_ports; i++) 925 phy_power_off(dwc->usb3_generic_phy[i]); 926 927 for (i = 0; i < dwc->num_usb2_ports; i++) 928 phy_power_off(dwc->usb2_generic_phy[i]); 929 930 usb_phy_set_suspend(dwc->usb3_phy, 1); 931 usb_phy_set_suspend(dwc->usb2_phy, 1); 932 } 933 934 static int dwc3_clk_enable(struct dwc3 *dwc) 935 { 936 int ret; 937 938 ret = clk_prepare_enable(dwc->bus_clk); 939 if (ret) 940 return ret; 941 942 ret = clk_prepare_enable(dwc->ref_clk); 943 if (ret) 944 goto disable_bus_clk; 945 946 ret = clk_prepare_enable(dwc->susp_clk); 947 if (ret) 948 goto disable_ref_clk; 949 950 ret = clk_prepare_enable(dwc->utmi_clk); 951 if (ret) 952 goto disable_susp_clk; 953 954 ret = clk_prepare_enable(dwc->pipe_clk); 955 if (ret) 956 goto disable_utmi_clk; 957 958 return 0; 959 960 disable_utmi_clk: 961 clk_disable_unprepare(dwc->utmi_clk); 962 disable_susp_clk: 963 clk_disable_unprepare(dwc->susp_clk); 964 disable_ref_clk: 965 clk_disable_unprepare(dwc->ref_clk); 966 disable_bus_clk: 967 clk_disable_unprepare(dwc->bus_clk); 968 return ret; 969 } 970 971 static void dwc3_clk_disable(struct dwc3 *dwc) 972 { 973 clk_disable_unprepare(dwc->pipe_clk); 974 clk_disable_unprepare(dwc->utmi_clk); 975 clk_disable_unprepare(dwc->susp_clk); 976 clk_disable_unprepare(dwc->ref_clk); 977 clk_disable_unprepare(dwc->bus_clk); 978 } 979 980 void dwc3_core_exit(struct dwc3 *dwc) 981 { 982 dwc3_event_buffers_cleanup(dwc); 983 dwc3_phy_power_off(dwc); 984 dwc3_phy_exit(dwc); 985 dwc3_clk_disable(dwc); 986 reset_control_assert(dwc->reset); 987 } 988 EXPORT_SYMBOL_GPL(dwc3_core_exit); 989 990 static bool dwc3_core_is_valid(struct dwc3 *dwc) 991 { 992 u32 reg; 993 994 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 995 dwc->ip = DWC3_GSNPS_ID(reg); 996 997 /* This should read as U3 followed by revision number */ 998 if (DWC3_IP_IS(DWC3)) { 999 dwc->revision = reg; 1000 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) { 1001 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); 1002 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE); 1003 } else { 1004 return false; 1005 } 1006 1007 return true; 1008 } 1009 1010 static void dwc3_core_setup_global_control(struct dwc3 *dwc) 1011 { 1012 unsigned int power_opt; 1013 unsigned int hw_mode; 1014 u32 reg; 1015 1016 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 1017 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 1018 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 1019 power_opt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1); 1020 1021 switch (power_opt) { 1022 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 1023 /** 1024 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 1025 * issue which would cause xHCI compliance tests to fail. 1026 * 1027 * Because of that we cannot enable clock gating on such 1028 * configurations. 1029 * 1030 * Refers to: 1031 * 1032 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 1033 * SOF/ITP Mode Used 1034 */ 1035 if ((dwc->dr_mode == USB_DR_MODE_HOST || 1036 dwc->dr_mode == USB_DR_MODE_OTG) && 1037 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A)) 1038 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 1039 else 1040 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 1041 break; 1042 case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 1043 /* 1044 * REVISIT Enabling this bit so that host-mode hibernation 1045 * will work. Device-mode hibernation is not yet implemented. 1046 */ 1047 reg |= DWC3_GCTL_GBLHIBERNATIONEN; 1048 break; 1049 default: 1050 /* nothing */ 1051 break; 1052 } 1053 1054 /* 1055 * This is a workaround for STAR#4846132, which only affects 1056 * DWC_usb31 version2.00a operating in host mode. 1057 * 1058 * There is a problem in DWC_usb31 version 2.00a operating 1059 * in host mode that would cause a CSR read timeout When CSR 1060 * read coincides with RAM Clock Gating Entry. By disable 1061 * Clock Gating, sacrificing power consumption for normal 1062 * operation. 1063 */ 1064 if (power_opt != DWC3_GHWPARAMS1_EN_PWROPT_NO && 1065 hw_mode != DWC3_GHWPARAMS0_MODE_GADGET && DWC3_VER_IS(DWC31, 200A)) 1066 reg |= DWC3_GCTL_DSBLCLKGTNG; 1067 1068 /* check if current dwc3 is on simulation board */ 1069 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 1070 dev_info(dwc->dev, "Running with FPGA optimizations\n"); 1071 dwc->is_fpga = true; 1072 } 1073 1074 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, 1075 "disable_scramble cannot be used on non-FPGA builds\n"); 1076 1077 if (dwc->disable_scramble_quirk && dwc->is_fpga) 1078 reg |= DWC3_GCTL_DISSCRAMBLE; 1079 else 1080 reg &= ~DWC3_GCTL_DISSCRAMBLE; 1081 1082 if (dwc->u2exit_lfps_quirk) 1083 reg |= DWC3_GCTL_U2EXIT_LFPS; 1084 1085 /* 1086 * WORKAROUND: DWC3 revisions <1.90a have a bug 1087 * where the device can fail to connect at SuperSpeed 1088 * and falls back to high-speed mode which causes 1089 * the device to enter a Connect/Disconnect loop 1090 */ 1091 if (DWC3_VER_IS_PRIOR(DWC3, 190A)) 1092 reg |= DWC3_GCTL_U2RSTECN; 1093 1094 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 1095 } 1096 1097 static int dwc3_core_get_phy(struct dwc3 *dwc); 1098 static int dwc3_core_ulpi_init(struct dwc3 *dwc); 1099 1100 /* set global incr burst type configuration registers */ 1101 static void dwc3_set_incr_burst_type(struct dwc3 *dwc) 1102 { 1103 struct device *dev = dwc->dev; 1104 /* incrx_mode : for INCR burst type. */ 1105 bool incrx_mode; 1106 /* incrx_size : for size of INCRX burst. */ 1107 u32 incrx_size; 1108 u32 *vals; 1109 u32 cfg; 1110 int ntype; 1111 int ret; 1112 int i; 1113 1114 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); 1115 1116 /* 1117 * Handle property "snps,incr-burst-type-adjustment". 1118 * Get the number of value from this property: 1119 * result <= 0, means this property is not supported. 1120 * result = 1, means INCRx burst mode supported. 1121 * result > 1, means undefined length burst mode supported. 1122 */ 1123 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment"); 1124 if (ntype <= 0) 1125 return; 1126 1127 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL); 1128 if (!vals) 1129 return; 1130 1131 /* Get INCR burst type, and parse it */ 1132 ret = device_property_read_u32_array(dev, 1133 "snps,incr-burst-type-adjustment", vals, ntype); 1134 if (ret) { 1135 kfree(vals); 1136 dev_err(dev, "Error to get property\n"); 1137 return; 1138 } 1139 1140 incrx_size = *vals; 1141 1142 if (ntype > 1) { 1143 /* INCRX (undefined length) burst mode */ 1144 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE; 1145 for (i = 1; i < ntype; i++) { 1146 if (vals[i] > incrx_size) 1147 incrx_size = vals[i]; 1148 } 1149 } else { 1150 /* INCRX burst mode */ 1151 incrx_mode = INCRX_BURST_MODE; 1152 } 1153 1154 kfree(vals); 1155 1156 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */ 1157 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK; 1158 if (incrx_mode) 1159 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA; 1160 switch (incrx_size) { 1161 case 256: 1162 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA; 1163 break; 1164 case 128: 1165 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA; 1166 break; 1167 case 64: 1168 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA; 1169 break; 1170 case 32: 1171 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA; 1172 break; 1173 case 16: 1174 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA; 1175 break; 1176 case 8: 1177 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA; 1178 break; 1179 case 4: 1180 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA; 1181 break; 1182 case 1: 1183 break; 1184 default: 1185 dev_err(dev, "Invalid property\n"); 1186 break; 1187 } 1188 1189 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg); 1190 } 1191 1192 static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc) 1193 { 1194 u32 scale; 1195 u32 reg; 1196 1197 if (!dwc->susp_clk) 1198 return; 1199 1200 /* 1201 * The power down scale field specifies how many suspend_clk 1202 * periods fit into a 16KHz clock period. When performing 1203 * the division, round up the remainder. 1204 * 1205 * The power down scale value is calculated using the fastest 1206 * frequency of the suspend_clk. If it isn't fixed (but within 1207 * the accuracy requirement), the driver may not know the max 1208 * rate of the suspend_clk, so only update the power down scale 1209 * if the default is less than the calculated value from 1210 * clk_get_rate() or if the default is questionably high 1211 * (3x or more) to be within the requirement. 1212 */ 1213 scale = DIV_ROUND_UP(clk_get_rate(dwc->susp_clk), 16000); 1214 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 1215 if ((reg & DWC3_GCTL_PWRDNSCALE_MASK) < DWC3_GCTL_PWRDNSCALE(scale) || 1216 (reg & DWC3_GCTL_PWRDNSCALE_MASK) > DWC3_GCTL_PWRDNSCALE(scale*3)) { 1217 reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK); 1218 reg |= DWC3_GCTL_PWRDNSCALE(scale); 1219 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 1220 } 1221 } 1222 1223 static void dwc3_config_threshold(struct dwc3 *dwc) 1224 { 1225 u32 reg; 1226 u8 rx_thr_num; 1227 u8 rx_maxburst; 1228 u8 tx_thr_num; 1229 u8 tx_maxburst; 1230 1231 /* 1232 * Must config both number of packets and max burst settings to enable 1233 * RX and/or TX threshold. 1234 */ 1235 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) { 1236 rx_thr_num = dwc->rx_thr_num_pkt_prd; 1237 rx_maxburst = dwc->rx_max_burst_prd; 1238 tx_thr_num = dwc->tx_thr_num_pkt_prd; 1239 tx_maxburst = dwc->tx_max_burst_prd; 1240 1241 if (rx_thr_num && rx_maxburst) { 1242 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1243 reg |= DWC31_RXTHRNUMPKTSEL_PRD; 1244 1245 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0); 1246 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num); 1247 1248 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0); 1249 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst); 1250 1251 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1252 } 1253 1254 if (tx_thr_num && tx_maxburst) { 1255 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1256 reg |= DWC31_TXTHRNUMPKTSEL_PRD; 1257 1258 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0); 1259 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num); 1260 1261 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0); 1262 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst); 1263 1264 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1265 } 1266 } 1267 1268 rx_thr_num = dwc->rx_thr_num_pkt; 1269 rx_maxburst = dwc->rx_max_burst; 1270 tx_thr_num = dwc->tx_thr_num_pkt; 1271 tx_maxburst = dwc->tx_max_burst; 1272 1273 if (DWC3_IP_IS(DWC3)) { 1274 if (rx_thr_num && rx_maxburst) { 1275 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1276 reg |= DWC3_GRXTHRCFG_PKTCNTSEL; 1277 1278 reg &= ~DWC3_GRXTHRCFG_RXPKTCNT(~0); 1279 reg |= DWC3_GRXTHRCFG_RXPKTCNT(rx_thr_num); 1280 1281 reg &= ~DWC3_GRXTHRCFG_MAXRXBURSTSIZE(~0); 1282 reg |= DWC3_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst); 1283 1284 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1285 } 1286 1287 if (tx_thr_num && tx_maxburst) { 1288 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1289 reg |= DWC3_GTXTHRCFG_PKTCNTSEL; 1290 1291 reg &= ~DWC3_GTXTHRCFG_TXPKTCNT(~0); 1292 reg |= DWC3_GTXTHRCFG_TXPKTCNT(tx_thr_num); 1293 1294 reg &= ~DWC3_GTXTHRCFG_MAXTXBURSTSIZE(~0); 1295 reg |= DWC3_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst); 1296 1297 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1298 } 1299 } else { 1300 if (rx_thr_num && rx_maxburst) { 1301 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1302 reg |= DWC31_GRXTHRCFG_PKTCNTSEL; 1303 1304 reg &= ~DWC31_GRXTHRCFG_RXPKTCNT(~0); 1305 reg |= DWC31_GRXTHRCFG_RXPKTCNT(rx_thr_num); 1306 1307 reg &= ~DWC31_GRXTHRCFG_MAXRXBURSTSIZE(~0); 1308 reg |= DWC31_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst); 1309 1310 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1311 } 1312 1313 if (tx_thr_num && tx_maxburst) { 1314 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1315 reg |= DWC31_GTXTHRCFG_PKTCNTSEL; 1316 1317 reg &= ~DWC31_GTXTHRCFG_TXPKTCNT(~0); 1318 reg |= DWC31_GTXTHRCFG_TXPKTCNT(tx_thr_num); 1319 1320 reg &= ~DWC31_GTXTHRCFG_MAXTXBURSTSIZE(~0); 1321 reg |= DWC31_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst); 1322 1323 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1324 } 1325 } 1326 } 1327 1328 /** 1329 * dwc3_core_init - Low-level initialization of DWC3 Core 1330 * @dwc: Pointer to our controller context structure 1331 * 1332 * Returns 0 on success otherwise negative errno. 1333 */ 1334 int dwc3_core_init(struct dwc3 *dwc) 1335 { 1336 unsigned int hw_mode; 1337 u32 reg; 1338 int ret; 1339 1340 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 1341 1342 /* 1343 * Write Linux Version Code to our GUID register so it's easy to figure 1344 * out which kernel version a bug was found. 1345 */ 1346 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); 1347 1348 ret = dwc3_phy_setup(dwc); 1349 if (ret) 1350 return ret; 1351 1352 if (!dwc->ulpi_ready) { 1353 ret = dwc3_core_ulpi_init(dwc); 1354 if (ret) { 1355 if (ret == -ETIMEDOUT) { 1356 dwc3_core_soft_reset(dwc); 1357 ret = -EPROBE_DEFER; 1358 } 1359 return ret; 1360 } 1361 dwc->ulpi_ready = true; 1362 } 1363 1364 if (!dwc->phys_ready) { 1365 ret = dwc3_core_get_phy(dwc); 1366 if (ret) 1367 goto err_exit_ulpi; 1368 dwc->phys_ready = true; 1369 } 1370 1371 ret = dwc3_phy_init(dwc); 1372 if (ret) 1373 goto err_exit_ulpi; 1374 1375 ret = dwc3_core_soft_reset(dwc); 1376 if (ret) 1377 goto err_exit_phy; 1378 1379 dwc3_core_setup_global_control(dwc); 1380 dwc3_core_num_eps(dwc); 1381 1382 /* Set power down scale of suspend_clk */ 1383 dwc3_set_power_down_clk_scale(dwc); 1384 1385 /* Adjust Frame Length */ 1386 dwc3_frame_length_adjustment(dwc); 1387 1388 /* Adjust Reference Clock Period */ 1389 dwc3_ref_clk_period(dwc); 1390 1391 dwc3_set_incr_burst_type(dwc); 1392 1393 dwc3_config_soc_bus(dwc); 1394 1395 ret = dwc3_phy_power_on(dwc); 1396 if (ret) 1397 goto err_exit_phy; 1398 1399 ret = dwc3_event_buffers_setup(dwc); 1400 if (ret) { 1401 dev_err(dwc->dev, "failed to setup event buffers\n"); 1402 goto err_power_off_phy; 1403 } 1404 1405 /* 1406 * ENDXFER polling is available on version 3.10a and later of 1407 * the DWC_usb3 controller. It is NOT available in the 1408 * DWC_usb31 controller. 1409 */ 1410 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) { 1411 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); 1412 reg |= DWC3_GUCTL2_RST_ACTBITLATER; 1413 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); 1414 } 1415 1416 /* 1417 * STAR 9001285599: This issue affects DWC_usb3 version 3.20a 1418 * only. If the PM TIMER ECM is enabled through GUCTL2[19], the 1419 * link compliance test (TD7.21) may fail. If the ECN is not 1420 * enabled (GUCTL2[19] = 0), the controller will use the old timer 1421 * value (5us), which is still acceptable for the link compliance 1422 * test. Therefore, do not enable PM TIMER ECM in 3.20a by 1423 * setting GUCTL2[19] by default; instead, use GUCTL2[19] = 0. 1424 */ 1425 if (DWC3_VER_IS(DWC3, 320A)) { 1426 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); 1427 reg &= ~DWC3_GUCTL2_LC_TIMER; 1428 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); 1429 } 1430 1431 /* 1432 * When configured in HOST mode, after issuing U3/L2 exit controller 1433 * fails to send proper CRC checksum in CRC5 field. Because of this 1434 * behaviour Transaction Error is generated, resulting in reset and 1435 * re-enumeration of usb device attached. All the termsel, xcvrsel, 1436 * opmode becomes 0 during end of resume. Enabling bit 10 of GUCTL1 1437 * will correct this problem. This option is to support certain 1438 * legacy ULPI PHYs. 1439 */ 1440 if (dwc->resume_hs_terminations) { 1441 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 1442 reg |= DWC3_GUCTL1_RESUME_OPMODE_HS_HOST; 1443 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 1444 } 1445 1446 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) { 1447 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 1448 1449 /* 1450 * Enable hardware control of sending remote wakeup 1451 * in HS when the device is in the L1 state. 1452 */ 1453 if (!DWC3_VER_IS_PRIOR(DWC3, 290A)) 1454 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; 1455 1456 /* 1457 * Decouple USB 2.0 L1 & L2 events which will allow for 1458 * gadget driver to only receive U3/L2 suspend & wakeup 1459 * events and prevent the more frequent L1 LPM transitions 1460 * from interrupting the driver. 1461 */ 1462 if (!DWC3_VER_IS_PRIOR(DWC3, 300A)) 1463 reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT; 1464 1465 if (dwc->dis_tx_ipgap_linecheck_quirk) 1466 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; 1467 1468 if (dwc->parkmode_disable_ss_quirk) 1469 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS; 1470 1471 if (dwc->parkmode_disable_hs_quirk) 1472 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_HS; 1473 1474 if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY)) { 1475 if (dwc->maximum_speed == USB_SPEED_FULL || 1476 dwc->maximum_speed == USB_SPEED_HIGH) 1477 reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; 1478 else 1479 reg &= ~DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; 1480 } 1481 1482 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 1483 } 1484 1485 dwc3_config_threshold(dwc); 1486 1487 if (hw_mode != DWC3_GHWPARAMS0_MODE_GADGET && 1488 (DWC3_IP_IS(DWC31)) && 1489 dwc->maximum_speed == USB_SPEED_SUPER) { 1490 int i; 1491 1492 for (i = 0; i < dwc->num_usb3_ports; i++) { 1493 reg = dwc3_readl(dwc->regs, DWC3_LLUCTL(i)); 1494 reg |= DWC3_LLUCTL_FORCE_GEN1; 1495 dwc3_writel(dwc->regs, DWC3_LLUCTL(i), reg); 1496 } 1497 } 1498 1499 /* 1500 * STAR 9001346572: This issue affects DWC_usb31 versions 1.80a and 1501 * prior. When an active endpoint not currently cached in the host 1502 * controller is chosen to be cached to the same index as an endpoint 1503 * receiving NAKs, the endpoint receiving NAKs enters continuous 1504 * retry mode. This prevents it from being evicted from the host 1505 * controller cache, blocking the new endpoint from being cached and 1506 * serviced. 1507 * 1508 * To resolve this, for controller versions 1.70a and 1.80a, set the 1509 * GUCTL3 bit[16] (USB2.0 Internal Retry Disable) to 1. This bit 1510 * disables the USB2.0 internal retry feature. The GUCTL3[16] register 1511 * function is available only from version 1.70a. 1512 */ 1513 if (DWC3_VER_IS_WITHIN(DWC31, 170A, 180A)) { 1514 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 1515 reg |= DWC3_GUCTL3_USB20_RETRY_DISABLE; 1516 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 1517 } 1518 1519 return 0; 1520 1521 err_power_off_phy: 1522 dwc3_phy_power_off(dwc); 1523 err_exit_phy: 1524 dwc3_phy_exit(dwc); 1525 err_exit_ulpi: 1526 dwc3_ulpi_exit(dwc); 1527 1528 return ret; 1529 } 1530 EXPORT_SYMBOL_GPL(dwc3_core_init); 1531 1532 static int dwc3_core_get_phy(struct dwc3 *dwc) 1533 { 1534 struct device *dev = dwc->dev; 1535 struct device_node *node = dev->of_node; 1536 char phy_name[9]; 1537 int ret; 1538 u8 i; 1539 1540 if (node) { 1541 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); 1542 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); 1543 } else { 1544 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 1545 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); 1546 } 1547 1548 if (IS_ERR(dwc->usb2_phy)) { 1549 ret = PTR_ERR(dwc->usb2_phy); 1550 if (ret == -ENXIO || ret == -ENODEV) 1551 dwc->usb2_phy = NULL; 1552 else 1553 return dev_err_probe(dev, ret, "no usb2 phy configured\n"); 1554 } 1555 1556 if (IS_ERR(dwc->usb3_phy)) { 1557 ret = PTR_ERR(dwc->usb3_phy); 1558 if (ret == -ENXIO || ret == -ENODEV) 1559 dwc->usb3_phy = NULL; 1560 else 1561 return dev_err_probe(dev, ret, "no usb3 phy configured\n"); 1562 } 1563 1564 for (i = 0; i < dwc->num_usb2_ports; i++) { 1565 if (dwc->num_usb2_ports == 1) 1566 snprintf(phy_name, sizeof(phy_name), "usb2-phy"); 1567 else 1568 snprintf(phy_name, sizeof(phy_name), "usb2-%u", i); 1569 1570 dwc->usb2_generic_phy[i] = devm_phy_get(dev, phy_name); 1571 if (IS_ERR(dwc->usb2_generic_phy[i])) { 1572 ret = PTR_ERR(dwc->usb2_generic_phy[i]); 1573 if (ret == -ENOSYS || ret == -ENODEV) 1574 dwc->usb2_generic_phy[i] = NULL; 1575 else 1576 return dev_err_probe(dev, ret, "failed to lookup phy %s\n", 1577 phy_name); 1578 } 1579 } 1580 1581 for (i = 0; i < dwc->num_usb3_ports; i++) { 1582 if (dwc->num_usb3_ports == 1) 1583 snprintf(phy_name, sizeof(phy_name), "usb3-phy"); 1584 else 1585 snprintf(phy_name, sizeof(phy_name), "usb3-%u", i); 1586 1587 dwc->usb3_generic_phy[i] = devm_phy_get(dev, phy_name); 1588 if (IS_ERR(dwc->usb3_generic_phy[i])) { 1589 ret = PTR_ERR(dwc->usb3_generic_phy[i]); 1590 if (ret == -ENOSYS || ret == -ENODEV) 1591 dwc->usb3_generic_phy[i] = NULL; 1592 else 1593 return dev_err_probe(dev, ret, "failed to lookup phy %s\n", 1594 phy_name); 1595 } 1596 } 1597 1598 return 0; 1599 } 1600 1601 static int dwc3_core_init_mode(struct dwc3 *dwc) 1602 { 1603 struct device *dev = dwc->dev; 1604 int ret; 1605 int i; 1606 1607 switch (dwc->dr_mode) { 1608 case USB_DR_MODE_PERIPHERAL: 1609 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE, false); 1610 1611 if (dwc->usb2_phy) 1612 otg_set_vbus(dwc->usb2_phy->otg, false); 1613 phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE); 1614 phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE); 1615 1616 ret = dwc3_gadget_init(dwc); 1617 if (ret) 1618 return dev_err_probe(dev, ret, "failed to initialize gadget\n"); 1619 break; 1620 case USB_DR_MODE_HOST: 1621 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST, false); 1622 1623 if (dwc->usb2_phy) 1624 otg_set_vbus(dwc->usb2_phy->otg, true); 1625 for (i = 0; i < dwc->num_usb2_ports; i++) 1626 phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST); 1627 for (i = 0; i < dwc->num_usb3_ports; i++) 1628 phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST); 1629 1630 ret = dwc3_host_init(dwc); 1631 if (ret) 1632 return dev_err_probe(dev, ret, "failed to initialize host\n"); 1633 break; 1634 case USB_DR_MODE_OTG: 1635 INIT_WORK(&dwc->drd_work, __dwc3_set_mode); 1636 ret = dwc3_drd_init(dwc); 1637 if (ret) 1638 return dev_err_probe(dev, ret, "failed to initialize dual-role\n"); 1639 break; 1640 default: 1641 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 1642 return -EINVAL; 1643 } 1644 1645 return 0; 1646 } 1647 1648 static void dwc3_core_exit_mode(struct dwc3 *dwc) 1649 { 1650 switch (dwc->dr_mode) { 1651 case USB_DR_MODE_PERIPHERAL: 1652 dwc3_gadget_exit(dwc); 1653 break; 1654 case USB_DR_MODE_HOST: 1655 dwc3_host_exit(dwc); 1656 break; 1657 case USB_DR_MODE_OTG: 1658 dwc3_drd_exit(dwc); 1659 break; 1660 default: 1661 /* do nothing */ 1662 break; 1663 } 1664 1665 /* de-assert DRVVBUS for HOST and OTG mode */ 1666 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE, true); 1667 } 1668 1669 static void dwc3_get_software_properties(struct dwc3 *dwc, 1670 const struct dwc3_properties *properties) 1671 { 1672 struct device *tmpdev; 1673 u16 gsbuscfg0_reqinfo; 1674 int ret; 1675 1676 dwc->gsbuscfg0_reqinfo = DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED; 1677 1678 if (properties->gsbuscfg0_reqinfo != 1679 DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED) { 1680 dwc->gsbuscfg0_reqinfo = properties->gsbuscfg0_reqinfo; 1681 return; 1682 } 1683 1684 /* 1685 * Iterate over all parent nodes for finding swnode properties 1686 * and non-DT (non-ABI) properties. 1687 */ 1688 for (tmpdev = dwc->dev; tmpdev; tmpdev = tmpdev->parent) { 1689 ret = device_property_read_u16(tmpdev, 1690 "snps,gsbuscfg0-reqinfo", 1691 &gsbuscfg0_reqinfo); 1692 if (!ret) 1693 dwc->gsbuscfg0_reqinfo = gsbuscfg0_reqinfo; 1694 } 1695 } 1696 1697 static void dwc3_get_properties(struct dwc3 *dwc) 1698 { 1699 struct device *dev = dwc->dev; 1700 u8 lpm_nyet_threshold; 1701 u8 tx_de_emphasis; 1702 u8 hird_threshold; 1703 u8 rx_thr_num_pkt = 0; 1704 u8 rx_max_burst = 0; 1705 u8 tx_thr_num_pkt = 0; 1706 u8 tx_max_burst = 0; 1707 u8 rx_thr_num_pkt_prd = 0; 1708 u8 rx_max_burst_prd = 0; 1709 u8 tx_thr_num_pkt_prd = 0; 1710 u8 tx_max_burst_prd = 0; 1711 u8 tx_fifo_resize_max_num; 1712 u16 num_hc_interrupters; 1713 1714 /* default to highest possible threshold */ 1715 lpm_nyet_threshold = 0xf; 1716 1717 /* default to -3.5dB de-emphasis */ 1718 tx_de_emphasis = 1; 1719 1720 /* 1721 * default to assert utmi_sleep_n and use maximum allowed HIRD 1722 * threshold value of 0b1100 1723 */ 1724 hird_threshold = 12; 1725 1726 /* 1727 * default to a TXFIFO size large enough to fit 6 max packets. This 1728 * allows for systems with larger bus latencies to have some headroom 1729 * for endpoints that have a large bMaxBurst value. 1730 */ 1731 tx_fifo_resize_max_num = 6; 1732 1733 /* default to a single XHCI interrupter */ 1734 num_hc_interrupters = 1; 1735 1736 dwc->maximum_speed = usb_get_maximum_speed(dev); 1737 dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev); 1738 dwc->dr_mode = usb_get_dr_mode(dev); 1739 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); 1740 1741 dwc->sysdev_is_parent = device_property_read_bool(dev, 1742 "linux,sysdev_is_parent"); 1743 if (dwc->sysdev_is_parent) 1744 dwc->sysdev = dwc->dev->parent; 1745 else 1746 dwc->sysdev = dwc->dev; 1747 1748 dwc->sys_wakeup = device_may_wakeup(dwc->sysdev); 1749 1750 dwc->has_lpm_erratum = device_property_read_bool(dev, 1751 "snps,has-lpm-erratum"); 1752 device_property_read_u8(dev, "snps,lpm-nyet-threshold", 1753 &lpm_nyet_threshold); 1754 dwc->is_utmi_l1_suspend = device_property_read_bool(dev, 1755 "snps,is-utmi-l1-suspend"); 1756 device_property_read_u8(dev, "snps,hird-threshold", 1757 &hird_threshold); 1758 dwc->dis_start_transfer_quirk = device_property_read_bool(dev, 1759 "snps,dis-start-transfer-quirk"); 1760 dwc->usb3_lpm_capable = device_property_read_bool(dev, 1761 "snps,usb3_lpm_capable"); 1762 dwc->usb2_lpm_disable = device_property_read_bool(dev, 1763 "snps,usb2-lpm-disable"); 1764 dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev, 1765 "snps,usb2-gadget-lpm-disable"); 1766 device_property_read_u8(dev, "snps,rx-thr-num-pkt", 1767 &rx_thr_num_pkt); 1768 device_property_read_u8(dev, "snps,rx-max-burst", 1769 &rx_max_burst); 1770 device_property_read_u8(dev, "snps,tx-thr-num-pkt", 1771 &tx_thr_num_pkt); 1772 device_property_read_u8(dev, "snps,tx-max-burst", 1773 &tx_max_burst); 1774 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd", 1775 &rx_thr_num_pkt_prd); 1776 device_property_read_u8(dev, "snps,rx-max-burst-prd", 1777 &rx_max_burst_prd); 1778 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd", 1779 &tx_thr_num_pkt_prd); 1780 device_property_read_u8(dev, "snps,tx-max-burst-prd", 1781 &tx_max_burst_prd); 1782 device_property_read_u16(dev, "num-hc-interrupters", 1783 &num_hc_interrupters); 1784 /* DWC3 core allowed to have a max of 8 interrupters */ 1785 if (num_hc_interrupters > 8) 1786 num_hc_interrupters = 8; 1787 1788 dwc->do_fifo_resize = device_property_read_bool(dev, 1789 "tx-fifo-resize"); 1790 if (dwc->do_fifo_resize) 1791 device_property_read_u8(dev, "tx-fifo-max-num", 1792 &tx_fifo_resize_max_num); 1793 1794 dwc->disable_scramble_quirk = device_property_read_bool(dev, 1795 "snps,disable_scramble_quirk"); 1796 dwc->u2exit_lfps_quirk = device_property_read_bool(dev, 1797 "snps,u2exit_lfps_quirk"); 1798 dwc->u2ss_inp3_quirk = device_property_read_bool(dev, 1799 "snps,u2ss_inp3_quirk"); 1800 dwc->req_p1p2p3_quirk = device_property_read_bool(dev, 1801 "snps,req_p1p2p3_quirk"); 1802 dwc->del_p1p2p3_quirk = device_property_read_bool(dev, 1803 "snps,del_p1p2p3_quirk"); 1804 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, 1805 "snps,del_phy_power_chg_quirk"); 1806 dwc->lfps_filter_quirk = device_property_read_bool(dev, 1807 "snps,lfps_filter_quirk"); 1808 dwc->rx_detect_poll_quirk = device_property_read_bool(dev, 1809 "snps,rx_detect_poll_quirk"); 1810 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, 1811 "snps,dis_u3_susphy_quirk"); 1812 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, 1813 "snps,dis_u2_susphy_quirk"); 1814 dwc->dis_enblslpm_quirk = device_property_read_bool(dev, 1815 "snps,dis_enblslpm_quirk"); 1816 dwc->dis_u1_entry_quirk = device_property_read_bool(dev, 1817 "snps,dis-u1-entry-quirk"); 1818 dwc->dis_u2_entry_quirk = device_property_read_bool(dev, 1819 "snps,dis-u2-entry-quirk"); 1820 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, 1821 "snps,dis_rxdet_inp3_quirk"); 1822 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, 1823 "snps,dis-u2-freeclk-exists-quirk"); 1824 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, 1825 "snps,dis-del-phy-power-chg-quirk"); 1826 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev, 1827 "snps,dis-tx-ipgap-linecheck-quirk"); 1828 dwc->resume_hs_terminations = device_property_read_bool(dev, 1829 "snps,resume-hs-terminations"); 1830 dwc->ulpi_ext_vbus_drv = device_property_read_bool(dev, 1831 "snps,ulpi-ext-vbus-drv"); 1832 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev, 1833 "snps,parkmode-disable-ss-quirk"); 1834 dwc->parkmode_disable_hs_quirk = device_property_read_bool(dev, 1835 "snps,parkmode-disable-hs-quirk"); 1836 dwc->gfladj_refclk_lpm_sel = device_property_read_bool(dev, 1837 "snps,gfladj-refclk-lpm-sel-quirk"); 1838 1839 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, 1840 "snps,tx_de_emphasis_quirk"); 1841 device_property_read_u8(dev, "snps,tx_de_emphasis", 1842 &tx_de_emphasis); 1843 device_property_read_string(dev, "snps,hsphy_interface", 1844 &dwc->hsphy_interface); 1845 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", 1846 &dwc->fladj); 1847 device_property_read_u32(dev, "snps,ref-clock-period-ns", 1848 &dwc->ref_clk_per); 1849 1850 dwc->dis_metastability_quirk = device_property_read_bool(dev, 1851 "snps,dis_metastability_quirk"); 1852 1853 dwc->dis_split_quirk = device_property_read_bool(dev, 1854 "snps,dis-split-quirk"); 1855 1856 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 1857 dwc->tx_de_emphasis = tx_de_emphasis; 1858 1859 dwc->hird_threshold = hird_threshold; 1860 1861 dwc->rx_thr_num_pkt = rx_thr_num_pkt; 1862 dwc->rx_max_burst = rx_max_burst; 1863 1864 dwc->tx_thr_num_pkt = tx_thr_num_pkt; 1865 dwc->tx_max_burst = tx_max_burst; 1866 1867 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd; 1868 dwc->rx_max_burst_prd = rx_max_burst_prd; 1869 1870 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd; 1871 dwc->tx_max_burst_prd = tx_max_burst_prd; 1872 1873 dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num; 1874 1875 dwc->num_hc_interrupters = num_hc_interrupters; 1876 } 1877 1878 /* check whether the core supports IMOD */ 1879 bool dwc3_has_imod(struct dwc3 *dwc) 1880 { 1881 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) || 1882 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) || 1883 DWC3_IP_IS(DWC32); 1884 } 1885 1886 static void dwc3_check_params(struct dwc3 *dwc) 1887 { 1888 struct device *dev = dwc->dev; 1889 unsigned int hwparam_gen = 1890 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3); 1891 1892 /* 1893 * Enable IMOD for all supporting controllers. 1894 * 1895 * Particularly, DWC_usb3 v3.00a must enable this feature for 1896 * the following reason: 1897 * 1898 * Workaround for STAR 9000961433 which affects only version 1899 * 3.00a of the DWC_usb3 core. This prevents the controller 1900 * interrupt from being masked while handling events. IMOD 1901 * allows us to work around this issue. Enable it for the 1902 * affected version. 1903 */ 1904 if (dwc3_has_imod((dwc))) 1905 dwc->imod_interval = 1; 1906 1907 /* Check the maximum_speed parameter */ 1908 switch (dwc->maximum_speed) { 1909 case USB_SPEED_FULL: 1910 case USB_SPEED_HIGH: 1911 break; 1912 case USB_SPEED_SUPER: 1913 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) 1914 dev_warn(dev, "UDC doesn't support Gen 1\n"); 1915 break; 1916 case USB_SPEED_SUPER_PLUS: 1917 if ((DWC3_IP_IS(DWC32) && 1918 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) || 1919 (!DWC3_IP_IS(DWC32) && 1920 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) 1921 dev_warn(dev, "UDC doesn't support SSP\n"); 1922 break; 1923 default: 1924 dev_err(dev, "invalid maximum_speed parameter %d\n", 1925 dwc->maximum_speed); 1926 fallthrough; 1927 case USB_SPEED_UNKNOWN: 1928 switch (hwparam_gen) { 1929 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 1930 dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1931 break; 1932 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 1933 if (DWC3_IP_IS(DWC32)) 1934 dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1935 else 1936 dwc->maximum_speed = USB_SPEED_SUPER; 1937 break; 1938 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS: 1939 dwc->maximum_speed = USB_SPEED_HIGH; 1940 break; 1941 default: 1942 dwc->maximum_speed = USB_SPEED_SUPER; 1943 break; 1944 } 1945 break; 1946 } 1947 1948 /* 1949 * Currently the controller does not have visibility into the HW 1950 * parameter to determine the maximum number of lanes the HW supports. 1951 * If the number of lanes is not specified in the device property, then 1952 * set the default to support dual-lane for DWC_usb32 and single-lane 1953 * for DWC_usb31 for super-speed-plus. 1954 */ 1955 if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) { 1956 switch (dwc->max_ssp_rate) { 1957 case USB_SSP_GEN_2x1: 1958 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1) 1959 dev_warn(dev, "UDC only supports Gen 1\n"); 1960 break; 1961 case USB_SSP_GEN_1x2: 1962 case USB_SSP_GEN_2x2: 1963 if (DWC3_IP_IS(DWC31)) 1964 dev_warn(dev, "UDC only supports single lane\n"); 1965 break; 1966 case USB_SSP_GEN_UNKNOWN: 1967 default: 1968 switch (hwparam_gen) { 1969 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 1970 if (DWC3_IP_IS(DWC32)) 1971 dwc->max_ssp_rate = USB_SSP_GEN_2x2; 1972 else 1973 dwc->max_ssp_rate = USB_SSP_GEN_2x1; 1974 break; 1975 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 1976 if (DWC3_IP_IS(DWC32)) 1977 dwc->max_ssp_rate = USB_SSP_GEN_1x2; 1978 break; 1979 } 1980 break; 1981 } 1982 } 1983 } 1984 1985 static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc) 1986 { 1987 struct device *dev = dwc->dev; 1988 struct device_node *np_phy; 1989 struct extcon_dev *edev = NULL; 1990 const char *name; 1991 1992 if (device_property_present(dev, "extcon")) 1993 return extcon_get_edev_by_phandle(dev, 0); 1994 1995 /* 1996 * Device tree platforms should get extcon via phandle. 1997 * On ACPI platforms, we get the name from a device property. 1998 * This device property is for kernel internal use only and 1999 * is expected to be set by the glue code. 2000 */ 2001 if (device_property_read_string(dev, "linux,extcon-name", &name) == 0) 2002 return extcon_get_extcon_dev(name); 2003 2004 /* 2005 * Check explicitly if "usb-role-switch" is used since 2006 * extcon_find_edev_by_node() can not be used to check the absence of 2007 * an extcon device. In the absence of an device it will always return 2008 * EPROBE_DEFER. 2009 */ 2010 if (IS_ENABLED(CONFIG_USB_ROLE_SWITCH) && 2011 device_property_read_bool(dev, "usb-role-switch")) 2012 return NULL; 2013 2014 /* 2015 * Try to get an extcon device from the USB PHY controller's "port" 2016 * node. Check if it has the "port" node first, to avoid printing the 2017 * error message from underlying code, as it's a valid case: extcon 2018 * device (and "port" node) may be missing in case of "usb-role-switch" 2019 * or OTG mode. 2020 */ 2021 np_phy = of_parse_phandle(dev->of_node, "phys", 0); 2022 if (of_graph_is_present(np_phy)) { 2023 struct device_node *np_conn; 2024 2025 np_conn = of_graph_get_remote_node(np_phy, -1, -1); 2026 if (np_conn) 2027 edev = extcon_find_edev_by_node(np_conn); 2028 of_node_put(np_conn); 2029 } 2030 of_node_put(np_phy); 2031 2032 return edev; 2033 } 2034 2035 static int dwc3_get_clocks(struct dwc3 *dwc) 2036 { 2037 struct device *dev = dwc->dev; 2038 2039 if (!dev->of_node) 2040 return 0; 2041 2042 /* 2043 * Clocks are optional, but new DT platforms should support all clocks 2044 * as required by the DT-binding. 2045 * Some devices have different clock names in legacy device trees, 2046 * check for them to retain backwards compatibility. 2047 */ 2048 dwc->bus_clk = devm_clk_get_optional(dev, "bus_early"); 2049 if (IS_ERR(dwc->bus_clk)) { 2050 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk), 2051 "could not get bus clock\n"); 2052 } 2053 2054 if (dwc->bus_clk == NULL) { 2055 dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk"); 2056 if (IS_ERR(dwc->bus_clk)) { 2057 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk), 2058 "could not get bus clock\n"); 2059 } 2060 } 2061 2062 dwc->ref_clk = devm_clk_get_optional(dev, "ref"); 2063 if (IS_ERR(dwc->ref_clk)) { 2064 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk), 2065 "could not get ref clock\n"); 2066 } 2067 2068 if (dwc->ref_clk == NULL) { 2069 dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk"); 2070 if (IS_ERR(dwc->ref_clk)) { 2071 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk), 2072 "could not get ref clock\n"); 2073 } 2074 } 2075 2076 dwc->susp_clk = devm_clk_get_optional(dev, "suspend"); 2077 if (IS_ERR(dwc->susp_clk)) { 2078 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk), 2079 "could not get suspend clock\n"); 2080 } 2081 2082 if (dwc->susp_clk == NULL) { 2083 dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk"); 2084 if (IS_ERR(dwc->susp_clk)) { 2085 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk), 2086 "could not get suspend clock\n"); 2087 } 2088 } 2089 2090 /* specific to Rockchip RK3588 */ 2091 dwc->utmi_clk = devm_clk_get_optional(dev, "utmi"); 2092 if (IS_ERR(dwc->utmi_clk)) { 2093 return dev_err_probe(dev, PTR_ERR(dwc->utmi_clk), 2094 "could not get utmi clock\n"); 2095 } 2096 2097 /* specific to Rockchip RK3588 */ 2098 dwc->pipe_clk = devm_clk_get_optional(dev, "pipe"); 2099 if (IS_ERR(dwc->pipe_clk)) { 2100 return dev_err_probe(dev, PTR_ERR(dwc->pipe_clk), 2101 "could not get pipe clock\n"); 2102 } 2103 2104 return 0; 2105 } 2106 2107 static int dwc3_get_num_ports(struct dwc3 *dwc) 2108 { 2109 void __iomem *base; 2110 u8 major_revision; 2111 u32 offset; 2112 u32 val; 2113 2114 /* 2115 * Remap xHCI address space to access XHCI ext cap regs since it is 2116 * needed to get information on number of ports present. 2117 */ 2118 base = ioremap(dwc->xhci_resources[0].start, 2119 resource_size(&dwc->xhci_resources[0])); 2120 if (!base) 2121 return -ENOMEM; 2122 2123 offset = 0; 2124 do { 2125 offset = xhci_find_next_ext_cap(base, offset, 2126 XHCI_EXT_CAPS_PROTOCOL); 2127 if (!offset) 2128 break; 2129 2130 val = readl(base + offset); 2131 major_revision = XHCI_EXT_PORT_MAJOR(val); 2132 2133 val = readl(base + offset + 0x08); 2134 if (major_revision == 0x03) { 2135 dwc->num_usb3_ports += XHCI_EXT_PORT_COUNT(val); 2136 } else if (major_revision <= 0x02) { 2137 dwc->num_usb2_ports += XHCI_EXT_PORT_COUNT(val); 2138 } else { 2139 dev_warn(dwc->dev, "unrecognized port major revision %d\n", 2140 major_revision); 2141 } 2142 } while (1); 2143 2144 dev_dbg(dwc->dev, "hs-ports: %u ss-ports: %u\n", 2145 dwc->num_usb2_ports, dwc->num_usb3_ports); 2146 2147 iounmap(base); 2148 2149 if (dwc->num_usb2_ports > DWC3_USB2_MAX_PORTS || 2150 dwc->num_usb3_ports > DWC3_USB3_MAX_PORTS) 2151 return -EINVAL; 2152 2153 return 0; 2154 } 2155 2156 static struct power_supply *dwc3_get_usb_power_supply(struct dwc3 *dwc) 2157 { 2158 struct power_supply *usb_psy; 2159 const char *usb_psy_name; 2160 int ret; 2161 2162 ret = device_property_read_string(dwc->dev, "usb-psy-name", &usb_psy_name); 2163 if (ret < 0) 2164 return NULL; 2165 2166 usb_psy = power_supply_get_by_name(usb_psy_name); 2167 if (!usb_psy) 2168 return ERR_PTR(-EPROBE_DEFER); 2169 2170 return usb_psy; 2171 } 2172 2173 int dwc3_core_probe(const struct dwc3_probe_data *data) 2174 { 2175 struct dwc3 *dwc = data->dwc; 2176 struct device *dev = dwc->dev; 2177 struct resource dwc_res; 2178 unsigned int hw_mode; 2179 void __iomem *regs; 2180 struct resource *res = data->res; 2181 int ret; 2182 2183 dwc->xhci_resources[0].start = res->start; 2184 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + 2185 DWC3_XHCI_REGS_END; 2186 dwc->xhci_resources[0].flags = res->flags; 2187 dwc->xhci_resources[0].name = res->name; 2188 2189 /* 2190 * Request memory region but exclude xHCI regs, 2191 * since it will be requested by the xhci-plat driver. 2192 */ 2193 dwc_res = *res; 2194 dwc_res.start += DWC3_GLOBALS_REGS_START; 2195 2196 if (dev->of_node) { 2197 struct device_node *parent = of_get_parent(dev->of_node); 2198 2199 if (of_device_is_compatible(parent, "realtek,rtd-dwc3")) { 2200 dwc_res.start -= DWC3_GLOBALS_REGS_START; 2201 dwc_res.start += DWC3_RTK_RTD_GLOBALS_REGS_START; 2202 } 2203 2204 of_node_put(parent); 2205 } 2206 2207 regs = devm_ioremap_resource(dev, &dwc_res); 2208 if (IS_ERR(regs)) 2209 return PTR_ERR(regs); 2210 2211 dwc->regs = regs; 2212 dwc->regs_size = resource_size(&dwc_res); 2213 2214 dwc3_get_properties(dwc); 2215 2216 dwc3_get_software_properties(dwc, &data->properties); 2217 2218 dwc->usb_psy = dwc3_get_usb_power_supply(dwc); 2219 if (IS_ERR(dwc->usb_psy)) 2220 return dev_err_probe(dev, PTR_ERR(dwc->usb_psy), "couldn't get usb power supply\n"); 2221 2222 if (!data->ignore_clocks_and_resets) { 2223 dwc->reset = devm_reset_control_array_get_optional_shared(dev); 2224 if (IS_ERR(dwc->reset)) { 2225 ret = PTR_ERR(dwc->reset); 2226 goto err_put_psy; 2227 } 2228 2229 ret = dwc3_get_clocks(dwc); 2230 if (ret) 2231 goto err_put_psy; 2232 } 2233 2234 ret = reset_control_deassert(dwc->reset); 2235 if (ret) 2236 goto err_put_psy; 2237 2238 ret = dwc3_clk_enable(dwc); 2239 if (ret) 2240 goto err_assert_reset; 2241 2242 if (!dwc3_core_is_valid(dwc)) { 2243 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 2244 ret = -ENODEV; 2245 goto err_disable_clks; 2246 } 2247 2248 dev_set_drvdata(dev, dwc); 2249 dwc3_cache_hwparams(dwc); 2250 2251 if (!dev_is_pci(dwc->sysdev) && 2252 DWC3_GHWPARAMS0_AWIDTH(dwc->hwparams.hwparams0) == 64) { 2253 ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64)); 2254 if (ret) 2255 goto err_disable_clks; 2256 } 2257 2258 /* 2259 * Currently only DWC3 controllers that are host-only capable 2260 * can have more than one port. 2261 */ 2262 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 2263 if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) { 2264 ret = dwc3_get_num_ports(dwc); 2265 if (ret) 2266 goto err_disable_clks; 2267 } else { 2268 dwc->num_usb2_ports = 1; 2269 dwc->num_usb3_ports = 1; 2270 } 2271 2272 spin_lock_init(&dwc->lock); 2273 mutex_init(&dwc->mutex); 2274 2275 pm_runtime_get_noresume(dev); 2276 pm_runtime_set_active(dev); 2277 pm_runtime_use_autosuspend(dev); 2278 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); 2279 pm_runtime_enable(dev); 2280 2281 pm_runtime_forbid(dev); 2282 2283 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 2284 if (ret) { 2285 dev_err(dwc->dev, "failed to allocate event buffers\n"); 2286 ret = -ENOMEM; 2287 goto err_allow_rpm; 2288 } 2289 2290 dwc->edev = dwc3_get_extcon(dwc); 2291 if (IS_ERR(dwc->edev)) { 2292 ret = dev_err_probe(dwc->dev, PTR_ERR(dwc->edev), "failed to get extcon\n"); 2293 goto err_free_event_buffers; 2294 } 2295 2296 ret = dwc3_get_dr_mode(dwc); 2297 if (ret) 2298 goto err_free_event_buffers; 2299 2300 ret = dwc3_core_init(dwc); 2301 if (ret) { 2302 dev_err_probe(dev, ret, "failed to initialize core\n"); 2303 goto err_free_event_buffers; 2304 } 2305 2306 dwc3_check_params(dwc); 2307 dwc3_debugfs_init(dwc); 2308 2309 if (!data->skip_core_init_mode) { 2310 ret = dwc3_core_init_mode(dwc); 2311 if (ret) 2312 goto err_exit_debugfs; 2313 } 2314 2315 pm_runtime_put(dev); 2316 2317 dma_set_max_seg_size(dev, UINT_MAX); 2318 2319 return 0; 2320 2321 err_exit_debugfs: 2322 dwc3_debugfs_exit(dwc); 2323 dwc3_event_buffers_cleanup(dwc); 2324 dwc3_phy_power_off(dwc); 2325 dwc3_phy_exit(dwc); 2326 dwc3_ulpi_exit(dwc); 2327 err_free_event_buffers: 2328 dwc3_free_event_buffers(dwc); 2329 err_allow_rpm: 2330 pm_runtime_allow(dev); 2331 pm_runtime_disable(dev); 2332 pm_runtime_dont_use_autosuspend(dev); 2333 pm_runtime_set_suspended(dev); 2334 pm_runtime_put_noidle(dev); 2335 err_disable_clks: 2336 dwc3_clk_disable(dwc); 2337 err_assert_reset: 2338 reset_control_assert(dwc->reset); 2339 err_put_psy: 2340 if (dwc->usb_psy) 2341 power_supply_put(dwc->usb_psy); 2342 2343 return ret; 2344 } 2345 EXPORT_SYMBOL_GPL(dwc3_core_probe); 2346 2347 static int dwc3_probe(struct platform_device *pdev) 2348 { 2349 struct dwc3_probe_data probe_data = {}; 2350 struct resource *res; 2351 struct dwc3 *dwc; 2352 2353 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2354 if (!res) { 2355 dev_err(&pdev->dev, "missing memory resource\n"); 2356 return -ENODEV; 2357 } 2358 2359 dwc = devm_kzalloc(&pdev->dev, sizeof(*dwc), GFP_KERNEL); 2360 if (!dwc) 2361 return -ENOMEM; 2362 2363 dwc->dev = &pdev->dev; 2364 dwc->glue_ops = NULL; 2365 2366 probe_data.dwc = dwc; 2367 probe_data.res = res; 2368 probe_data.properties = DWC3_DEFAULT_PROPERTIES; 2369 2370 return dwc3_core_probe(&probe_data); 2371 } 2372 2373 void dwc3_core_remove(struct dwc3 *dwc) 2374 { 2375 pm_runtime_get_sync(dwc->dev); 2376 2377 dwc3_core_exit_mode(dwc); 2378 dwc3_debugfs_exit(dwc); 2379 2380 dwc3_core_exit(dwc); 2381 dwc3_ulpi_exit(dwc); 2382 2383 pm_runtime_allow(dwc->dev); 2384 pm_runtime_disable(dwc->dev); 2385 pm_runtime_dont_use_autosuspend(dwc->dev); 2386 pm_runtime_put_noidle(dwc->dev); 2387 /* 2388 * HACK: Clear the driver data, which is currently accessed by parent 2389 * glue drivers, before allowing the parent to suspend. 2390 */ 2391 dev_set_drvdata(dwc->dev, NULL); 2392 pm_runtime_set_suspended(dwc->dev); 2393 2394 dwc3_free_event_buffers(dwc); 2395 2396 if (dwc->usb_psy) 2397 power_supply_put(dwc->usb_psy); 2398 } 2399 EXPORT_SYMBOL_GPL(dwc3_core_remove); 2400 2401 static void dwc3_remove(struct platform_device *pdev) 2402 { 2403 dwc3_core_remove(platform_get_drvdata(pdev)); 2404 } 2405 2406 #ifdef CONFIG_PM 2407 static int dwc3_core_init_for_resume(struct dwc3 *dwc) 2408 { 2409 int ret; 2410 2411 ret = reset_control_deassert(dwc->reset); 2412 if (ret) 2413 return ret; 2414 2415 ret = dwc3_clk_enable(dwc); 2416 if (ret) 2417 goto assert_reset; 2418 2419 ret = dwc3_core_init(dwc); 2420 if (ret) 2421 goto disable_clks; 2422 2423 return 0; 2424 2425 disable_clks: 2426 dwc3_clk_disable(dwc); 2427 assert_reset: 2428 reset_control_assert(dwc->reset); 2429 2430 return ret; 2431 } 2432 2433 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) 2434 { 2435 u32 reg; 2436 int i; 2437 int ret; 2438 2439 if (!pm_runtime_suspended(dwc->dev) && !PMSG_IS_AUTO(msg)) { 2440 dwc->susphy_state = (dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)) & 2441 DWC3_GUSB2PHYCFG_SUSPHY) || 2442 (dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)) & 2443 DWC3_GUSB3PIPECTL_SUSPHY); 2444 /* 2445 * TI AM62 platform requires SUSPHY to be 2446 * enabled for system suspend to work. 2447 */ 2448 if (!dwc->susphy_state) 2449 dwc3_enable_susphy(dwc, true); 2450 } 2451 2452 switch (dwc->current_dr_role) { 2453 case DWC3_GCTL_PRTCAP_DEVICE: 2454 if (pm_runtime_suspended(dwc->dev)) 2455 break; 2456 ret = dwc3_gadget_suspend(dwc); 2457 if (ret) 2458 return ret; 2459 synchronize_irq(dwc->irq_gadget); 2460 dwc3_core_exit(dwc); 2461 break; 2462 case DWC3_GCTL_PRTCAP_HOST: 2463 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) { 2464 dwc3_core_exit(dwc); 2465 break; 2466 } 2467 2468 /* Let controller to suspend HSPHY before PHY driver suspends */ 2469 if (dwc->dis_u2_susphy_quirk || 2470 dwc->dis_enblslpm_quirk) { 2471 for (i = 0; i < dwc->num_usb2_ports; i++) { 2472 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i)); 2473 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM | 2474 DWC3_GUSB2PHYCFG_SUSPHY; 2475 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg); 2476 } 2477 2478 /* Give some time for USB2 PHY to suspend */ 2479 usleep_range(5000, 6000); 2480 } 2481 2482 for (i = 0; i < dwc->num_usb2_ports; i++) 2483 phy_pm_runtime_put_sync(dwc->usb2_generic_phy[i]); 2484 for (i = 0; i < dwc->num_usb3_ports; i++) 2485 phy_pm_runtime_put_sync(dwc->usb3_generic_phy[i]); 2486 break; 2487 case DWC3_GCTL_PRTCAP_OTG: 2488 /* do nothing during runtime_suspend */ 2489 if (PMSG_IS_AUTO(msg)) 2490 break; 2491 2492 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 2493 ret = dwc3_gadget_suspend(dwc); 2494 if (ret) 2495 return ret; 2496 synchronize_irq(dwc->irq_gadget); 2497 } 2498 2499 dwc3_otg_exit(dwc); 2500 dwc3_core_exit(dwc); 2501 break; 2502 default: 2503 /* do nothing */ 2504 break; 2505 } 2506 2507 return 0; 2508 } 2509 2510 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) 2511 { 2512 int ret; 2513 u32 reg; 2514 int i; 2515 2516 switch (dwc->current_dr_role) { 2517 case DWC3_GCTL_PRTCAP_DEVICE: 2518 ret = dwc3_core_init_for_resume(dwc); 2519 if (ret) 2520 return ret; 2521 2522 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE, true); 2523 dwc3_gadget_resume(dwc); 2524 break; 2525 case DWC3_GCTL_PRTCAP_HOST: 2526 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) { 2527 ret = dwc3_core_init_for_resume(dwc); 2528 if (ret) 2529 return ret; 2530 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST, true); 2531 break; 2532 } 2533 /* Restore GUSB2PHYCFG bits that were modified in suspend */ 2534 for (i = 0; i < dwc->num_usb2_ports; i++) { 2535 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i)); 2536 if (dwc->dis_u2_susphy_quirk) 2537 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 2538 2539 if (dwc->dis_enblslpm_quirk) 2540 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 2541 2542 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg); 2543 } 2544 2545 for (i = 0; i < dwc->num_usb2_ports; i++) 2546 phy_pm_runtime_get_sync(dwc->usb2_generic_phy[i]); 2547 for (i = 0; i < dwc->num_usb3_ports; i++) 2548 phy_pm_runtime_get_sync(dwc->usb3_generic_phy[i]); 2549 break; 2550 case DWC3_GCTL_PRTCAP_OTG: 2551 /* nothing to do on runtime_resume */ 2552 if (PMSG_IS_AUTO(msg)) 2553 break; 2554 2555 ret = dwc3_core_init_for_resume(dwc); 2556 if (ret) 2557 return ret; 2558 2559 dwc3_set_prtcap(dwc, dwc->current_dr_role, true); 2560 2561 dwc3_otg_init(dwc); 2562 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) { 2563 dwc3_otg_host_init(dwc); 2564 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 2565 dwc3_gadget_resume(dwc); 2566 } 2567 2568 break; 2569 default: 2570 /* do nothing */ 2571 break; 2572 } 2573 2574 if (!PMSG_IS_AUTO(msg)) { 2575 /* restore SUSPHY state to that before system suspend. */ 2576 dwc3_enable_susphy(dwc, dwc->susphy_state); 2577 } 2578 2579 return 0; 2580 } 2581 2582 static int dwc3_runtime_checks(struct dwc3 *dwc) 2583 { 2584 switch (dwc->current_dr_role) { 2585 case DWC3_GCTL_PRTCAP_DEVICE: 2586 if (dwc->connected) 2587 return -EBUSY; 2588 break; 2589 case DWC3_GCTL_PRTCAP_HOST: 2590 default: 2591 /* do nothing */ 2592 break; 2593 } 2594 2595 return 0; 2596 } 2597 2598 int dwc3_runtime_suspend(struct dwc3 *dwc) 2599 { 2600 int ret; 2601 2602 if (dwc3_runtime_checks(dwc)) 2603 return -EBUSY; 2604 2605 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND); 2606 if (ret) 2607 return ret; 2608 2609 return 0; 2610 } 2611 EXPORT_SYMBOL_GPL(dwc3_runtime_suspend); 2612 2613 int dwc3_runtime_resume(struct dwc3 *dwc) 2614 { 2615 struct device *dev = dwc->dev; 2616 int ret; 2617 2618 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME); 2619 if (ret) 2620 return ret; 2621 2622 switch (dwc->current_dr_role) { 2623 case DWC3_GCTL_PRTCAP_DEVICE: 2624 if (dwc->pending_events) { 2625 pm_runtime_put(dev); 2626 dwc->pending_events = false; 2627 enable_irq(dwc->irq_gadget); 2628 } 2629 break; 2630 case DWC3_GCTL_PRTCAP_HOST: 2631 default: 2632 /* do nothing */ 2633 break; 2634 } 2635 2636 pm_runtime_mark_last_busy(dev); 2637 2638 return 0; 2639 } 2640 EXPORT_SYMBOL_GPL(dwc3_runtime_resume); 2641 2642 int dwc3_runtime_idle(struct dwc3 *dwc) 2643 { 2644 struct device *dev = dwc->dev; 2645 2646 switch (dwc->current_dr_role) { 2647 case DWC3_GCTL_PRTCAP_DEVICE: 2648 if (dwc3_runtime_checks(dwc)) 2649 return -EBUSY; 2650 break; 2651 case DWC3_GCTL_PRTCAP_HOST: 2652 default: 2653 /* do nothing */ 2654 break; 2655 } 2656 2657 pm_runtime_autosuspend(dev); 2658 2659 return 0; 2660 } 2661 EXPORT_SYMBOL_GPL(dwc3_runtime_idle); 2662 2663 static int dwc3_plat_runtime_suspend(struct device *dev) 2664 { 2665 return dwc3_runtime_suspend(dev_get_drvdata(dev)); 2666 } 2667 2668 static int dwc3_plat_runtime_resume(struct device *dev) 2669 { 2670 return dwc3_runtime_resume(dev_get_drvdata(dev)); 2671 } 2672 2673 static int dwc3_plat_runtime_idle(struct device *dev) 2674 { 2675 return dwc3_runtime_idle(dev_get_drvdata(dev)); 2676 } 2677 #endif /* CONFIG_PM */ 2678 2679 #ifdef CONFIG_PM_SLEEP 2680 int dwc3_pm_suspend(struct dwc3 *dwc) 2681 { 2682 struct device *dev = dwc->dev; 2683 int ret; 2684 2685 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND); 2686 if (ret) 2687 return ret; 2688 2689 pinctrl_pm_select_sleep_state(dev); 2690 2691 return 0; 2692 } 2693 EXPORT_SYMBOL_GPL(dwc3_pm_suspend); 2694 2695 int dwc3_pm_resume(struct dwc3 *dwc) 2696 { 2697 struct device *dev = dwc->dev; 2698 int ret = 0; 2699 2700 pinctrl_pm_select_default_state(dev); 2701 2702 pm_runtime_disable(dev); 2703 ret = pm_runtime_set_active(dev); 2704 if (ret) 2705 goto out; 2706 2707 ret = dwc3_resume_common(dwc, PMSG_RESUME); 2708 if (ret) 2709 pm_runtime_set_suspended(dev); 2710 2711 out: 2712 pm_runtime_enable(dev); 2713 2714 return ret; 2715 } 2716 EXPORT_SYMBOL_GPL(dwc3_pm_resume); 2717 2718 void dwc3_pm_complete(struct dwc3 *dwc) 2719 { 2720 u32 reg; 2721 2722 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST && 2723 dwc->dis_split_quirk) { 2724 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 2725 reg |= DWC3_GUCTL3_SPLITDISABLE; 2726 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 2727 } 2728 } 2729 EXPORT_SYMBOL_GPL(dwc3_pm_complete); 2730 2731 int dwc3_pm_prepare(struct dwc3 *dwc) 2732 { 2733 struct device *dev = dwc->dev; 2734 2735 /* 2736 * Indicate to the PM core that it may safely leave the device in 2737 * runtime suspend if runtime-suspended already in device mode. 2738 */ 2739 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_DEVICE && 2740 pm_runtime_suspended(dev) && 2741 !dev_pinctrl(dev)) 2742 return 1; 2743 2744 return 0; 2745 } 2746 EXPORT_SYMBOL_GPL(dwc3_pm_prepare); 2747 2748 static int dwc3_plat_suspend(struct device *dev) 2749 { 2750 return dwc3_pm_suspend(dev_get_drvdata(dev)); 2751 } 2752 2753 static int dwc3_plat_resume(struct device *dev) 2754 { 2755 return dwc3_pm_resume(dev_get_drvdata(dev)); 2756 } 2757 2758 static void dwc3_plat_complete(struct device *dev) 2759 { 2760 dwc3_pm_complete(dev_get_drvdata(dev)); 2761 } 2762 2763 static int dwc3_plat_prepare(struct device *dev) 2764 { 2765 return dwc3_pm_prepare(dev_get_drvdata(dev)); 2766 } 2767 #else 2768 #define dwc3_plat_complete NULL 2769 #define dwc3_plat_prepare NULL 2770 #endif /* CONFIG_PM_SLEEP */ 2771 2772 static const struct dev_pm_ops dwc3_dev_pm_ops = { 2773 SET_SYSTEM_SLEEP_PM_OPS(dwc3_plat_suspend, dwc3_plat_resume) 2774 .complete = dwc3_plat_complete, 2775 .prepare = dwc3_plat_prepare, 2776 /* 2777 * Runtime suspend halts the controller on disconnection. It relies on 2778 * platforms with custom connection notification to start the controller 2779 * again. 2780 */ 2781 SET_RUNTIME_PM_OPS(dwc3_plat_runtime_suspend, dwc3_plat_runtime_resume, 2782 dwc3_plat_runtime_idle) 2783 }; 2784 2785 #ifdef CONFIG_OF 2786 static const struct of_device_id of_dwc3_match[] = { 2787 { 2788 .compatible = "snps,dwc3" 2789 }, 2790 { 2791 .compatible = "synopsys,dwc3" 2792 }, 2793 { }, 2794 }; 2795 MODULE_DEVICE_TABLE(of, of_dwc3_match); 2796 #endif 2797 2798 #ifdef CONFIG_ACPI 2799 2800 #define ACPI_ID_INTEL_BSW "808622B7" 2801 2802 static const struct acpi_device_id dwc3_acpi_match[] = { 2803 { ACPI_ID_INTEL_BSW, 0 }, 2804 { }, 2805 }; 2806 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); 2807 #endif 2808 2809 static struct platform_driver dwc3_driver = { 2810 .probe = dwc3_probe, 2811 .remove = dwc3_remove, 2812 .driver = { 2813 .name = "dwc3", 2814 .of_match_table = of_match_ptr(of_dwc3_match), 2815 .acpi_match_table = ACPI_PTR(dwc3_acpi_match), 2816 .pm = &dwc3_dev_pm_ops, 2817 }, 2818 }; 2819 2820 module_platform_driver(dwc3_driver); 2821 2822 MODULE_ALIAS("platform:dwc3"); 2823 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 2824 MODULE_LICENSE("GPL v2"); 2825 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 2826