1 // SPDX-License-Identifier: GPL-2.0 2 /** 3 * core.c - DesignWare USB3 DRD Controller Core file 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 * 10 * This program is free software: you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 of 12 * the License as published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include <linux/version.h> 24 #include <linux/module.h> 25 #include <linux/kernel.h> 26 #include <linux/slab.h> 27 #include <linux/spinlock.h> 28 #include <linux/platform_device.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/interrupt.h> 31 #include <linux/ioport.h> 32 #include <linux/io.h> 33 #include <linux/list.h> 34 #include <linux/delay.h> 35 #include <linux/dma-mapping.h> 36 #include <linux/of.h> 37 #include <linux/acpi.h> 38 #include <linux/pinctrl/consumer.h> 39 40 #include <linux/usb/ch9.h> 41 #include <linux/usb/gadget.h> 42 #include <linux/usb/of.h> 43 #include <linux/usb/otg.h> 44 45 #include "core.h" 46 #include "gadget.h" 47 #include "io.h" 48 49 #include "debug.h" 50 51 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ 52 53 /** 54 * dwc3_get_dr_mode - Validates and sets dr_mode 55 * @dwc: pointer to our context structure 56 */ 57 static int dwc3_get_dr_mode(struct dwc3 *dwc) 58 { 59 enum usb_dr_mode mode; 60 struct device *dev = dwc->dev; 61 unsigned int hw_mode; 62 63 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 64 dwc->dr_mode = USB_DR_MODE_OTG; 65 66 mode = dwc->dr_mode; 67 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 68 69 switch (hw_mode) { 70 case DWC3_GHWPARAMS0_MODE_GADGET: 71 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) { 72 dev_err(dev, 73 "Controller does not support host mode.\n"); 74 return -EINVAL; 75 } 76 mode = USB_DR_MODE_PERIPHERAL; 77 break; 78 case DWC3_GHWPARAMS0_MODE_HOST: 79 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { 80 dev_err(dev, 81 "Controller does not support device mode.\n"); 82 return -EINVAL; 83 } 84 mode = USB_DR_MODE_HOST; 85 break; 86 default: 87 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 88 mode = USB_DR_MODE_HOST; 89 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 90 mode = USB_DR_MODE_PERIPHERAL; 91 } 92 93 if (mode != dwc->dr_mode) { 94 dev_warn(dev, 95 "Configuration mismatch. dr_mode forced to %s\n", 96 mode == USB_DR_MODE_HOST ? "host" : "gadget"); 97 98 dwc->dr_mode = mode; 99 } 100 101 return 0; 102 } 103 104 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc); 105 static int dwc3_event_buffers_setup(struct dwc3 *dwc); 106 107 static void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) 108 { 109 u32 reg; 110 111 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 112 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 113 reg |= DWC3_GCTL_PRTCAPDIR(mode); 114 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 115 } 116 117 static void __dwc3_set_mode(struct work_struct *work) 118 { 119 struct dwc3 *dwc = work_to_dwc(work); 120 unsigned long flags; 121 int ret; 122 123 if (!dwc->desired_dr_role) 124 return; 125 126 if (dwc->desired_dr_role == dwc->current_dr_role) 127 return; 128 129 if (dwc->dr_mode != USB_DR_MODE_OTG) 130 return; 131 132 switch (dwc->current_dr_role) { 133 case DWC3_GCTL_PRTCAP_HOST: 134 dwc3_host_exit(dwc); 135 break; 136 case DWC3_GCTL_PRTCAP_DEVICE: 137 dwc3_gadget_exit(dwc); 138 dwc3_event_buffers_cleanup(dwc); 139 break; 140 default: 141 break; 142 } 143 144 spin_lock_irqsave(&dwc->lock, flags); 145 146 dwc3_set_prtcap(dwc, dwc->desired_dr_role); 147 148 dwc->current_dr_role = dwc->desired_dr_role; 149 150 spin_unlock_irqrestore(&dwc->lock, flags); 151 152 switch (dwc->desired_dr_role) { 153 case DWC3_GCTL_PRTCAP_HOST: 154 ret = dwc3_host_init(dwc); 155 if (ret) { 156 dev_err(dwc->dev, "failed to initialize host\n"); 157 } else { 158 if (dwc->usb2_phy) 159 otg_set_vbus(dwc->usb2_phy->otg, true); 160 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 161 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 162 } 163 break; 164 case DWC3_GCTL_PRTCAP_DEVICE: 165 dwc3_event_buffers_setup(dwc); 166 167 if (dwc->usb2_phy) 168 otg_set_vbus(dwc->usb2_phy->otg, false); 169 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 170 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 171 172 ret = dwc3_gadget_init(dwc); 173 if (ret) 174 dev_err(dwc->dev, "failed to initialize peripheral\n"); 175 break; 176 default: 177 break; 178 } 179 } 180 181 void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 182 { 183 unsigned long flags; 184 185 spin_lock_irqsave(&dwc->lock, flags); 186 dwc->desired_dr_role = mode; 187 spin_unlock_irqrestore(&dwc->lock, flags); 188 189 queue_work(system_power_efficient_wq, &dwc->drd_work); 190 } 191 192 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) 193 { 194 struct dwc3 *dwc = dep->dwc; 195 u32 reg; 196 197 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, 198 DWC3_GDBGFIFOSPACE_NUM(dep->number) | 199 DWC3_GDBGFIFOSPACE_TYPE(type)); 200 201 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); 202 203 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); 204 } 205 206 /** 207 * dwc3_core_soft_reset - Issues core soft reset and PHY reset 208 * @dwc: pointer to our context structure 209 */ 210 static int dwc3_core_soft_reset(struct dwc3 *dwc) 211 { 212 u32 reg; 213 int retries = 1000; 214 int ret; 215 216 usb_phy_init(dwc->usb2_phy); 217 usb_phy_init(dwc->usb3_phy); 218 ret = phy_init(dwc->usb2_generic_phy); 219 if (ret < 0) 220 return ret; 221 222 ret = phy_init(dwc->usb3_generic_phy); 223 if (ret < 0) { 224 phy_exit(dwc->usb2_generic_phy); 225 return ret; 226 } 227 228 /* 229 * We're resetting only the device side because, if we're in host mode, 230 * XHCI driver will reset the host block. If dwc3 was configured for 231 * host-only mode, then we can return early. 232 */ 233 if (dwc->dr_mode == USB_DR_MODE_HOST) 234 return 0; 235 236 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 237 reg |= DWC3_DCTL_CSFTRST; 238 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 239 240 do { 241 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 242 if (!(reg & DWC3_DCTL_CSFTRST)) 243 return 0; 244 245 udelay(1); 246 } while (--retries); 247 248 return -ETIMEDOUT; 249 } 250 251 /* 252 * dwc3_frame_length_adjustment - Adjusts frame length if required 253 * @dwc3: Pointer to our controller context structure 254 */ 255 static void dwc3_frame_length_adjustment(struct dwc3 *dwc) 256 { 257 u32 reg; 258 u32 dft; 259 260 if (dwc->revision < DWC3_REVISION_250A) 261 return; 262 263 if (dwc->fladj == 0) 264 return; 265 266 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 267 dft = reg & DWC3_GFLADJ_30MHZ_MASK; 268 if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj, 269 "request value same as default, ignoring\n")) { 270 reg &= ~DWC3_GFLADJ_30MHZ_MASK; 271 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; 272 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 273 } 274 } 275 276 /** 277 * dwc3_free_one_event_buffer - Frees one event buffer 278 * @dwc: Pointer to our controller context structure 279 * @evt: Pointer to event buffer to be freed 280 */ 281 static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 282 struct dwc3_event_buffer *evt) 283 { 284 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma); 285 } 286 287 /** 288 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 289 * @dwc: Pointer to our controller context structure 290 * @length: size of the event buffer 291 * 292 * Returns a pointer to the allocated event buffer structure on success 293 * otherwise ERR_PTR(errno). 294 */ 295 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 296 unsigned length) 297 { 298 struct dwc3_event_buffer *evt; 299 300 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 301 if (!evt) 302 return ERR_PTR(-ENOMEM); 303 304 evt->dwc = dwc; 305 evt->length = length; 306 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL); 307 if (!evt->cache) 308 return ERR_PTR(-ENOMEM); 309 310 evt->buf = dma_alloc_coherent(dwc->sysdev, length, 311 &evt->dma, GFP_KERNEL); 312 if (!evt->buf) 313 return ERR_PTR(-ENOMEM); 314 315 return evt; 316 } 317 318 /** 319 * dwc3_free_event_buffers - frees all allocated event buffers 320 * @dwc: Pointer to our controller context structure 321 */ 322 static void dwc3_free_event_buffers(struct dwc3 *dwc) 323 { 324 struct dwc3_event_buffer *evt; 325 326 evt = dwc->ev_buf; 327 if (evt) 328 dwc3_free_one_event_buffer(dwc, evt); 329 } 330 331 /** 332 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 333 * @dwc: pointer to our controller context structure 334 * @length: size of event buffer 335 * 336 * Returns 0 on success otherwise negative errno. In the error case, dwc 337 * may contain some buffers allocated but not all which were requested. 338 */ 339 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) 340 { 341 struct dwc3_event_buffer *evt; 342 343 evt = dwc3_alloc_one_event_buffer(dwc, length); 344 if (IS_ERR(evt)) { 345 dev_err(dwc->dev, "can't allocate event buffer\n"); 346 return PTR_ERR(evt); 347 } 348 dwc->ev_buf = evt; 349 350 return 0; 351 } 352 353 /** 354 * dwc3_event_buffers_setup - setup our allocated event buffers 355 * @dwc: pointer to our controller context structure 356 * 357 * Returns 0 on success otherwise negative errno. 358 */ 359 static int dwc3_event_buffers_setup(struct dwc3 *dwc) 360 { 361 struct dwc3_event_buffer *evt; 362 363 evt = dwc->ev_buf; 364 evt->lpos = 0; 365 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 366 lower_32_bits(evt->dma)); 367 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 368 upper_32_bits(evt->dma)); 369 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), 370 DWC3_GEVNTSIZ_SIZE(evt->length)); 371 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 372 373 return 0; 374 } 375 376 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 377 { 378 struct dwc3_event_buffer *evt; 379 380 evt = dwc->ev_buf; 381 382 evt->lpos = 0; 383 384 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); 385 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); 386 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK 387 | DWC3_GEVNTSIZ_SIZE(0)); 388 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 389 } 390 391 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) 392 { 393 if (!dwc->has_hibernation) 394 return 0; 395 396 if (!dwc->nr_scratch) 397 return 0; 398 399 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, 400 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); 401 if (!dwc->scratchbuf) 402 return -ENOMEM; 403 404 return 0; 405 } 406 407 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) 408 { 409 dma_addr_t scratch_addr; 410 u32 param; 411 int ret; 412 413 if (!dwc->has_hibernation) 414 return 0; 415 416 if (!dwc->nr_scratch) 417 return 0; 418 419 /* should never fall here */ 420 if (!WARN_ON(dwc->scratchbuf)) 421 return 0; 422 423 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf, 424 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, 425 DMA_BIDIRECTIONAL); 426 if (dma_mapping_error(dwc->sysdev, scratch_addr)) { 427 dev_err(dwc->sysdev, "failed to map scratch buffer\n"); 428 ret = -EFAULT; 429 goto err0; 430 } 431 432 dwc->scratch_addr = scratch_addr; 433 434 param = lower_32_bits(scratch_addr); 435 436 ret = dwc3_send_gadget_generic_command(dwc, 437 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); 438 if (ret < 0) 439 goto err1; 440 441 param = upper_32_bits(scratch_addr); 442 443 ret = dwc3_send_gadget_generic_command(dwc, 444 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); 445 if (ret < 0) 446 goto err1; 447 448 return 0; 449 450 err1: 451 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 452 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 453 454 err0: 455 return ret; 456 } 457 458 static void dwc3_free_scratch_buffers(struct dwc3 *dwc) 459 { 460 if (!dwc->has_hibernation) 461 return; 462 463 if (!dwc->nr_scratch) 464 return; 465 466 /* should never fall here */ 467 if (!WARN_ON(dwc->scratchbuf)) 468 return; 469 470 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 471 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 472 kfree(dwc->scratchbuf); 473 } 474 475 static void dwc3_core_num_eps(struct dwc3 *dwc) 476 { 477 struct dwc3_hwparams *parms = &dwc->hwparams; 478 479 dwc->num_eps = DWC3_NUM_EPS(parms); 480 } 481 482 static void dwc3_cache_hwparams(struct dwc3 *dwc) 483 { 484 struct dwc3_hwparams *parms = &dwc->hwparams; 485 486 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 487 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 488 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 489 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 490 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 491 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 492 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 493 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 494 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 495 } 496 497 /** 498 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 499 * @dwc: Pointer to our controller context structure 500 * 501 * Returns 0 on success. The USB PHY interfaces are configured but not 502 * initialized. The PHY interfaces and the PHYs get initialized together with 503 * the core in dwc3_core_init. 504 */ 505 static int dwc3_phy_setup(struct dwc3 *dwc) 506 { 507 u32 reg; 508 int ret; 509 510 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 511 512 /* 513 * Make sure UX_EXIT_PX is cleared as that causes issues with some 514 * PHYs. Also, this bit is not supposed to be used in normal operation. 515 */ 516 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; 517 518 /* 519 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 520 * to '0' during coreConsultant configuration. So default value 521 * will be '0' when the core is reset. Application needs to set it 522 * to '1' after the core initialization is completed. 523 */ 524 if (dwc->revision > DWC3_REVISION_194A) 525 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 526 527 if (dwc->u2ss_inp3_quirk) 528 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 529 530 if (dwc->dis_rxdet_inp3_quirk) 531 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; 532 533 if (dwc->req_p1p2p3_quirk) 534 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 535 536 if (dwc->del_p1p2p3_quirk) 537 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 538 539 if (dwc->del_phy_power_chg_quirk) 540 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 541 542 if (dwc->lfps_filter_quirk) 543 reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 544 545 if (dwc->rx_detect_poll_quirk) 546 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 547 548 if (dwc->tx_de_emphasis_quirk) 549 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 550 551 if (dwc->dis_u3_susphy_quirk) 552 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 553 554 if (dwc->dis_del_phy_power_chg_quirk) 555 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; 556 557 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 558 559 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 560 561 /* Select the HS PHY interface */ 562 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { 563 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: 564 if (dwc->hsphy_interface && 565 !strncmp(dwc->hsphy_interface, "utmi", 4)) { 566 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; 567 break; 568 } else if (dwc->hsphy_interface && 569 !strncmp(dwc->hsphy_interface, "ulpi", 4)) { 570 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; 571 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 572 } else { 573 /* Relying on default value. */ 574 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) 575 break; 576 } 577 /* FALLTHROUGH */ 578 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: 579 ret = dwc3_ulpi_init(dwc); 580 if (ret) 581 return ret; 582 /* FALLTHROUGH */ 583 default: 584 break; 585 } 586 587 switch (dwc->hsphy_mode) { 588 case USBPHY_INTERFACE_MODE_UTMI: 589 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 590 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 591 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | 592 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); 593 break; 594 case USBPHY_INTERFACE_MODE_UTMIW: 595 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 596 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 597 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | 598 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 599 break; 600 default: 601 break; 602 } 603 604 /* 605 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 606 * '0' during coreConsultant configuration. So default value will 607 * be '0' when the core is reset. Application needs to set it to 608 * '1' after the core initialization is completed. 609 */ 610 if (dwc->revision > DWC3_REVISION_194A) 611 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 612 613 if (dwc->dis_u2_susphy_quirk) 614 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 615 616 if (dwc->dis_enblslpm_quirk) 617 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 618 619 if (dwc->dis_u2_freeclk_exists_quirk) 620 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 621 622 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 623 624 return 0; 625 } 626 627 static void dwc3_core_exit(struct dwc3 *dwc) 628 { 629 dwc3_event_buffers_cleanup(dwc); 630 631 usb_phy_shutdown(dwc->usb2_phy); 632 usb_phy_shutdown(dwc->usb3_phy); 633 phy_exit(dwc->usb2_generic_phy); 634 phy_exit(dwc->usb3_generic_phy); 635 636 usb_phy_set_suspend(dwc->usb2_phy, 1); 637 usb_phy_set_suspend(dwc->usb3_phy, 1); 638 phy_power_off(dwc->usb2_generic_phy); 639 phy_power_off(dwc->usb3_generic_phy); 640 } 641 642 static bool dwc3_core_is_valid(struct dwc3 *dwc) 643 { 644 u32 reg; 645 646 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 647 648 /* This should read as U3 followed by revision number */ 649 if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) { 650 /* Detected DWC_usb3 IP */ 651 dwc->revision = reg; 652 } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) { 653 /* Detected DWC_usb31 IP */ 654 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); 655 dwc->revision |= DWC3_REVISION_IS_DWC31; 656 } else { 657 return false; 658 } 659 660 return true; 661 } 662 663 static void dwc3_core_setup_global_control(struct dwc3 *dwc) 664 { 665 u32 hwparams4 = dwc->hwparams.hwparams4; 666 u32 reg; 667 668 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 669 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 670 671 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 672 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 673 /** 674 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 675 * issue which would cause xHCI compliance tests to fail. 676 * 677 * Because of that we cannot enable clock gating on such 678 * configurations. 679 * 680 * Refers to: 681 * 682 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 683 * SOF/ITP Mode Used 684 */ 685 if ((dwc->dr_mode == USB_DR_MODE_HOST || 686 dwc->dr_mode == USB_DR_MODE_OTG) && 687 (dwc->revision >= DWC3_REVISION_210A && 688 dwc->revision <= DWC3_REVISION_250A)) 689 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 690 else 691 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 692 break; 693 case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 694 /* enable hibernation here */ 695 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); 696 697 /* 698 * REVISIT Enabling this bit so that host-mode hibernation 699 * will work. Device-mode hibernation is not yet implemented. 700 */ 701 reg |= DWC3_GCTL_GBLHIBERNATIONEN; 702 break; 703 default: 704 /* nothing */ 705 break; 706 } 707 708 /* check if current dwc3 is on simulation board */ 709 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 710 dev_info(dwc->dev, "Running with FPGA optmizations\n"); 711 dwc->is_fpga = true; 712 } 713 714 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, 715 "disable_scramble cannot be used on non-FPGA builds\n"); 716 717 if (dwc->disable_scramble_quirk && dwc->is_fpga) 718 reg |= DWC3_GCTL_DISSCRAMBLE; 719 else 720 reg &= ~DWC3_GCTL_DISSCRAMBLE; 721 722 if (dwc->u2exit_lfps_quirk) 723 reg |= DWC3_GCTL_U2EXIT_LFPS; 724 725 /* 726 * WORKAROUND: DWC3 revisions <1.90a have a bug 727 * where the device can fail to connect at SuperSpeed 728 * and falls back to high-speed mode which causes 729 * the device to enter a Connect/Disconnect loop 730 */ 731 if (dwc->revision < DWC3_REVISION_190A) 732 reg |= DWC3_GCTL_U2RSTECN; 733 734 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 735 } 736 737 static int dwc3_core_get_phy(struct dwc3 *dwc); 738 739 /** 740 * dwc3_core_init - Low-level initialization of DWC3 Core 741 * @dwc: Pointer to our controller context structure 742 * 743 * Returns 0 on success otherwise negative errno. 744 */ 745 static int dwc3_core_init(struct dwc3 *dwc) 746 { 747 u32 reg; 748 int ret; 749 750 if (!dwc3_core_is_valid(dwc)) { 751 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 752 ret = -ENODEV; 753 goto err0; 754 } 755 756 /* 757 * Write Linux Version Code to our GUID register so it's easy to figure 758 * out which kernel version a bug was found. 759 */ 760 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); 761 762 /* Handle USB2.0-only core configuration */ 763 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == 764 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { 765 if (dwc->maximum_speed == USB_SPEED_SUPER) 766 dwc->maximum_speed = USB_SPEED_HIGH; 767 } 768 769 ret = dwc3_core_get_phy(dwc); 770 if (ret) 771 goto err0; 772 773 ret = dwc3_core_soft_reset(dwc); 774 if (ret) 775 goto err0; 776 777 ret = dwc3_phy_setup(dwc); 778 if (ret) 779 goto err0; 780 781 dwc3_core_setup_global_control(dwc); 782 dwc3_core_num_eps(dwc); 783 784 ret = dwc3_setup_scratch_buffers(dwc); 785 if (ret) 786 goto err1; 787 788 /* Adjust Frame Length */ 789 dwc3_frame_length_adjustment(dwc); 790 791 usb_phy_set_suspend(dwc->usb2_phy, 0); 792 usb_phy_set_suspend(dwc->usb3_phy, 0); 793 ret = phy_power_on(dwc->usb2_generic_phy); 794 if (ret < 0) 795 goto err2; 796 797 ret = phy_power_on(dwc->usb3_generic_phy); 798 if (ret < 0) 799 goto err3; 800 801 ret = dwc3_event_buffers_setup(dwc); 802 if (ret) { 803 dev_err(dwc->dev, "failed to setup event buffers\n"); 804 goto err4; 805 } 806 807 /* 808 * ENDXFER polling is available on version 3.10a and later of 809 * the DWC_usb3 controller. It is NOT available in the 810 * DWC_usb31 controller. 811 */ 812 if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) { 813 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); 814 reg |= DWC3_GUCTL2_RST_ACTBITLATER; 815 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); 816 } 817 818 if (dwc->revision >= DWC3_REVISION_250A) { 819 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 820 821 /* 822 * Enable hardware control of sending remote wakeup 823 * in HS when the device is in the L1 state. 824 */ 825 if (dwc->revision >= DWC3_REVISION_290A) 826 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; 827 828 if (dwc->dis_tx_ipgap_linecheck_quirk) 829 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; 830 831 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 832 } 833 834 return 0; 835 836 err4: 837 phy_power_off(dwc->usb3_generic_phy); 838 839 err3: 840 phy_power_off(dwc->usb2_generic_phy); 841 842 err2: 843 usb_phy_set_suspend(dwc->usb2_phy, 1); 844 usb_phy_set_suspend(dwc->usb3_phy, 1); 845 846 err1: 847 usb_phy_shutdown(dwc->usb2_phy); 848 usb_phy_shutdown(dwc->usb3_phy); 849 phy_exit(dwc->usb2_generic_phy); 850 phy_exit(dwc->usb3_generic_phy); 851 852 err0: 853 return ret; 854 } 855 856 static int dwc3_core_get_phy(struct dwc3 *dwc) 857 { 858 struct device *dev = dwc->dev; 859 struct device_node *node = dev->of_node; 860 int ret; 861 862 if (node) { 863 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); 864 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); 865 } else { 866 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 867 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); 868 } 869 870 if (IS_ERR(dwc->usb2_phy)) { 871 ret = PTR_ERR(dwc->usb2_phy); 872 if (ret == -ENXIO || ret == -ENODEV) { 873 dwc->usb2_phy = NULL; 874 } else if (ret == -EPROBE_DEFER) { 875 return ret; 876 } else { 877 dev_err(dev, "no usb2 phy configured\n"); 878 return ret; 879 } 880 } 881 882 if (IS_ERR(dwc->usb3_phy)) { 883 ret = PTR_ERR(dwc->usb3_phy); 884 if (ret == -ENXIO || ret == -ENODEV) { 885 dwc->usb3_phy = NULL; 886 } else if (ret == -EPROBE_DEFER) { 887 return ret; 888 } else { 889 dev_err(dev, "no usb3 phy configured\n"); 890 return ret; 891 } 892 } 893 894 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); 895 if (IS_ERR(dwc->usb2_generic_phy)) { 896 ret = PTR_ERR(dwc->usb2_generic_phy); 897 if (ret == -ENOSYS || ret == -ENODEV) { 898 dwc->usb2_generic_phy = NULL; 899 } else if (ret == -EPROBE_DEFER) { 900 return ret; 901 } else { 902 dev_err(dev, "no usb2 phy configured\n"); 903 return ret; 904 } 905 } 906 907 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); 908 if (IS_ERR(dwc->usb3_generic_phy)) { 909 ret = PTR_ERR(dwc->usb3_generic_phy); 910 if (ret == -ENOSYS || ret == -ENODEV) { 911 dwc->usb3_generic_phy = NULL; 912 } else if (ret == -EPROBE_DEFER) { 913 return ret; 914 } else { 915 dev_err(dev, "no usb3 phy configured\n"); 916 return ret; 917 } 918 } 919 920 return 0; 921 } 922 923 static int dwc3_core_init_mode(struct dwc3 *dwc) 924 { 925 struct device *dev = dwc->dev; 926 int ret; 927 928 switch (dwc->dr_mode) { 929 case USB_DR_MODE_PERIPHERAL: 930 dwc->current_dr_role = DWC3_GCTL_PRTCAP_DEVICE; 931 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 932 933 if (dwc->usb2_phy) 934 otg_set_vbus(dwc->usb2_phy->otg, false); 935 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 936 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 937 938 ret = dwc3_gadget_init(dwc); 939 if (ret) { 940 if (ret != -EPROBE_DEFER) 941 dev_err(dev, "failed to initialize gadget\n"); 942 return ret; 943 } 944 break; 945 case USB_DR_MODE_HOST: 946 dwc->current_dr_role = DWC3_GCTL_PRTCAP_HOST; 947 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 948 949 if (dwc->usb2_phy) 950 otg_set_vbus(dwc->usb2_phy->otg, true); 951 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 952 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 953 954 ret = dwc3_host_init(dwc); 955 if (ret) { 956 if (ret != -EPROBE_DEFER) 957 dev_err(dev, "failed to initialize host\n"); 958 return ret; 959 } 960 break; 961 case USB_DR_MODE_OTG: 962 INIT_WORK(&dwc->drd_work, __dwc3_set_mode); 963 ret = dwc3_drd_init(dwc); 964 if (ret) { 965 if (ret != -EPROBE_DEFER) 966 dev_err(dev, "failed to initialize dual-role\n"); 967 return ret; 968 } 969 break; 970 default: 971 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 972 return -EINVAL; 973 } 974 975 return 0; 976 } 977 978 static void dwc3_core_exit_mode(struct dwc3 *dwc) 979 { 980 switch (dwc->dr_mode) { 981 case USB_DR_MODE_PERIPHERAL: 982 dwc3_gadget_exit(dwc); 983 break; 984 case USB_DR_MODE_HOST: 985 dwc3_host_exit(dwc); 986 break; 987 case USB_DR_MODE_OTG: 988 dwc3_drd_exit(dwc); 989 break; 990 default: 991 /* do nothing */ 992 break; 993 } 994 } 995 996 static void dwc3_get_properties(struct dwc3 *dwc) 997 { 998 struct device *dev = dwc->dev; 999 u8 lpm_nyet_threshold; 1000 u8 tx_de_emphasis; 1001 u8 hird_threshold; 1002 1003 /* default to highest possible threshold */ 1004 lpm_nyet_threshold = 0xff; 1005 1006 /* default to -3.5dB de-emphasis */ 1007 tx_de_emphasis = 1; 1008 1009 /* 1010 * default to assert utmi_sleep_n and use maximum allowed HIRD 1011 * threshold value of 0b1100 1012 */ 1013 hird_threshold = 12; 1014 1015 dwc->maximum_speed = usb_get_maximum_speed(dev); 1016 dwc->dr_mode = usb_get_dr_mode(dev); 1017 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); 1018 1019 dwc->sysdev_is_parent = device_property_read_bool(dev, 1020 "linux,sysdev_is_parent"); 1021 if (dwc->sysdev_is_parent) 1022 dwc->sysdev = dwc->dev->parent; 1023 else 1024 dwc->sysdev = dwc->dev; 1025 1026 dwc->has_lpm_erratum = device_property_read_bool(dev, 1027 "snps,has-lpm-erratum"); 1028 device_property_read_u8(dev, "snps,lpm-nyet-threshold", 1029 &lpm_nyet_threshold); 1030 dwc->is_utmi_l1_suspend = device_property_read_bool(dev, 1031 "snps,is-utmi-l1-suspend"); 1032 device_property_read_u8(dev, "snps,hird-threshold", 1033 &hird_threshold); 1034 dwc->usb3_lpm_capable = device_property_read_bool(dev, 1035 "snps,usb3_lpm_capable"); 1036 1037 dwc->disable_scramble_quirk = device_property_read_bool(dev, 1038 "snps,disable_scramble_quirk"); 1039 dwc->u2exit_lfps_quirk = device_property_read_bool(dev, 1040 "snps,u2exit_lfps_quirk"); 1041 dwc->u2ss_inp3_quirk = device_property_read_bool(dev, 1042 "snps,u2ss_inp3_quirk"); 1043 dwc->req_p1p2p3_quirk = device_property_read_bool(dev, 1044 "snps,req_p1p2p3_quirk"); 1045 dwc->del_p1p2p3_quirk = device_property_read_bool(dev, 1046 "snps,del_p1p2p3_quirk"); 1047 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, 1048 "snps,del_phy_power_chg_quirk"); 1049 dwc->lfps_filter_quirk = device_property_read_bool(dev, 1050 "snps,lfps_filter_quirk"); 1051 dwc->rx_detect_poll_quirk = device_property_read_bool(dev, 1052 "snps,rx_detect_poll_quirk"); 1053 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, 1054 "snps,dis_u3_susphy_quirk"); 1055 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, 1056 "snps,dis_u2_susphy_quirk"); 1057 dwc->dis_enblslpm_quirk = device_property_read_bool(dev, 1058 "snps,dis_enblslpm_quirk"); 1059 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, 1060 "snps,dis_rxdet_inp3_quirk"); 1061 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, 1062 "snps,dis-u2-freeclk-exists-quirk"); 1063 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, 1064 "snps,dis-del-phy-power-chg-quirk"); 1065 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev, 1066 "snps,dis-tx-ipgap-linecheck-quirk"); 1067 1068 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, 1069 "snps,tx_de_emphasis_quirk"); 1070 device_property_read_u8(dev, "snps,tx_de_emphasis", 1071 &tx_de_emphasis); 1072 device_property_read_string(dev, "snps,hsphy_interface", 1073 &dwc->hsphy_interface); 1074 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", 1075 &dwc->fladj); 1076 1077 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 1078 dwc->tx_de_emphasis = tx_de_emphasis; 1079 1080 dwc->hird_threshold = hird_threshold 1081 | (dwc->is_utmi_l1_suspend << 4); 1082 1083 dwc->imod_interval = 0; 1084 } 1085 1086 /* check whether the core supports IMOD */ 1087 bool dwc3_has_imod(struct dwc3 *dwc) 1088 { 1089 return ((dwc3_is_usb3(dwc) && 1090 dwc->revision >= DWC3_REVISION_300A) || 1091 (dwc3_is_usb31(dwc) && 1092 dwc->revision >= DWC3_USB31_REVISION_120A)); 1093 } 1094 1095 static void dwc3_check_params(struct dwc3 *dwc) 1096 { 1097 struct device *dev = dwc->dev; 1098 1099 /* Check for proper value of imod_interval */ 1100 if (dwc->imod_interval && !dwc3_has_imod(dwc)) { 1101 dev_warn(dwc->dev, "Interrupt moderation not supported\n"); 1102 dwc->imod_interval = 0; 1103 } 1104 1105 /* 1106 * Workaround for STAR 9000961433 which affects only version 1107 * 3.00a of the DWC_usb3 core. This prevents the controller 1108 * interrupt from being masked while handling events. IMOD 1109 * allows us to work around this issue. Enable it for the 1110 * affected version. 1111 */ 1112 if (!dwc->imod_interval && 1113 (dwc->revision == DWC3_REVISION_300A)) 1114 dwc->imod_interval = 1; 1115 1116 /* Check the maximum_speed parameter */ 1117 switch (dwc->maximum_speed) { 1118 case USB_SPEED_LOW: 1119 case USB_SPEED_FULL: 1120 case USB_SPEED_HIGH: 1121 case USB_SPEED_SUPER: 1122 case USB_SPEED_SUPER_PLUS: 1123 break; 1124 default: 1125 dev_err(dev, "invalid maximum_speed parameter %d\n", 1126 dwc->maximum_speed); 1127 /* fall through */ 1128 case USB_SPEED_UNKNOWN: 1129 /* default to superspeed */ 1130 dwc->maximum_speed = USB_SPEED_SUPER; 1131 1132 /* 1133 * default to superspeed plus if we are capable. 1134 */ 1135 if (dwc3_is_usb31(dwc) && 1136 (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == 1137 DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) 1138 dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1139 1140 break; 1141 } 1142 } 1143 1144 static int dwc3_probe(struct platform_device *pdev) 1145 { 1146 struct device *dev = &pdev->dev; 1147 struct resource *res; 1148 struct dwc3 *dwc; 1149 1150 int ret; 1151 1152 void __iomem *regs; 1153 1154 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 1155 if (!dwc) 1156 return -ENOMEM; 1157 1158 dwc->dev = dev; 1159 1160 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1161 if (!res) { 1162 dev_err(dev, "missing memory resource\n"); 1163 return -ENODEV; 1164 } 1165 1166 dwc->xhci_resources[0].start = res->start; 1167 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + 1168 DWC3_XHCI_REGS_END; 1169 dwc->xhci_resources[0].flags = res->flags; 1170 dwc->xhci_resources[0].name = res->name; 1171 1172 res->start += DWC3_GLOBALS_REGS_START; 1173 1174 /* 1175 * Request memory region but exclude xHCI regs, 1176 * since it will be requested by the xhci-plat driver. 1177 */ 1178 regs = devm_ioremap_resource(dev, res); 1179 if (IS_ERR(regs)) { 1180 ret = PTR_ERR(regs); 1181 goto err0; 1182 } 1183 1184 dwc->regs = regs; 1185 dwc->regs_size = resource_size(res); 1186 1187 dwc3_get_properties(dwc); 1188 1189 platform_set_drvdata(pdev, dwc); 1190 dwc3_cache_hwparams(dwc); 1191 1192 spin_lock_init(&dwc->lock); 1193 1194 pm_runtime_set_active(dev); 1195 pm_runtime_use_autosuspend(dev); 1196 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); 1197 pm_runtime_enable(dev); 1198 ret = pm_runtime_get_sync(dev); 1199 if (ret < 0) 1200 goto err1; 1201 1202 pm_runtime_forbid(dev); 1203 1204 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 1205 if (ret) { 1206 dev_err(dwc->dev, "failed to allocate event buffers\n"); 1207 ret = -ENOMEM; 1208 goto err2; 1209 } 1210 1211 ret = dwc3_get_dr_mode(dwc); 1212 if (ret) 1213 goto err3; 1214 1215 ret = dwc3_alloc_scratch_buffers(dwc); 1216 if (ret) 1217 goto err3; 1218 1219 ret = dwc3_core_init(dwc); 1220 if (ret) { 1221 dev_err(dev, "failed to initialize core\n"); 1222 goto err4; 1223 } 1224 1225 dwc3_check_params(dwc); 1226 1227 ret = dwc3_core_init_mode(dwc); 1228 if (ret) 1229 goto err5; 1230 1231 dwc3_debugfs_init(dwc); 1232 pm_runtime_put(dev); 1233 1234 return 0; 1235 1236 err5: 1237 dwc3_event_buffers_cleanup(dwc); 1238 1239 err4: 1240 dwc3_free_scratch_buffers(dwc); 1241 1242 err3: 1243 dwc3_free_event_buffers(dwc); 1244 dwc3_ulpi_exit(dwc); 1245 1246 err2: 1247 pm_runtime_allow(&pdev->dev); 1248 1249 err1: 1250 pm_runtime_put_sync(&pdev->dev); 1251 pm_runtime_disable(&pdev->dev); 1252 1253 err0: 1254 /* 1255 * restore res->start back to its original value so that, in case the 1256 * probe is deferred, we don't end up getting error in request the 1257 * memory region the next time probe is called. 1258 */ 1259 res->start -= DWC3_GLOBALS_REGS_START; 1260 1261 return ret; 1262 } 1263 1264 static int dwc3_remove(struct platform_device *pdev) 1265 { 1266 struct dwc3 *dwc = platform_get_drvdata(pdev); 1267 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1268 1269 pm_runtime_get_sync(&pdev->dev); 1270 /* 1271 * restore res->start back to its original value so that, in case the 1272 * probe is deferred, we don't end up getting error in request the 1273 * memory region the next time probe is called. 1274 */ 1275 res->start -= DWC3_GLOBALS_REGS_START; 1276 1277 dwc3_debugfs_exit(dwc); 1278 dwc3_core_exit_mode(dwc); 1279 1280 dwc3_core_exit(dwc); 1281 dwc3_ulpi_exit(dwc); 1282 1283 pm_runtime_put_sync(&pdev->dev); 1284 pm_runtime_allow(&pdev->dev); 1285 pm_runtime_disable(&pdev->dev); 1286 1287 dwc3_free_event_buffers(dwc); 1288 dwc3_free_scratch_buffers(dwc); 1289 1290 return 0; 1291 } 1292 1293 #ifdef CONFIG_PM 1294 static int dwc3_suspend_common(struct dwc3 *dwc) 1295 { 1296 unsigned long flags; 1297 1298 switch (dwc->current_dr_role) { 1299 case DWC3_GCTL_PRTCAP_DEVICE: 1300 spin_lock_irqsave(&dwc->lock, flags); 1301 dwc3_gadget_suspend(dwc); 1302 spin_unlock_irqrestore(&dwc->lock, flags); 1303 dwc3_core_exit(dwc); 1304 break; 1305 case DWC3_GCTL_PRTCAP_HOST: 1306 default: 1307 /* do nothing */ 1308 break; 1309 } 1310 1311 return 0; 1312 } 1313 1314 static int dwc3_resume_common(struct dwc3 *dwc) 1315 { 1316 unsigned long flags; 1317 int ret; 1318 1319 switch (dwc->current_dr_role) { 1320 case DWC3_GCTL_PRTCAP_DEVICE: 1321 ret = dwc3_core_init(dwc); 1322 if (ret) 1323 return ret; 1324 1325 spin_lock_irqsave(&dwc->lock, flags); 1326 dwc3_gadget_resume(dwc); 1327 spin_unlock_irqrestore(&dwc->lock, flags); 1328 break; 1329 case DWC3_GCTL_PRTCAP_HOST: 1330 default: 1331 /* do nothing */ 1332 break; 1333 } 1334 1335 return 0; 1336 } 1337 1338 static int dwc3_runtime_checks(struct dwc3 *dwc) 1339 { 1340 switch (dwc->current_dr_role) { 1341 case USB_DR_MODE_PERIPHERAL: 1342 case USB_DR_MODE_OTG: 1343 if (dwc->connected) 1344 return -EBUSY; 1345 break; 1346 case USB_DR_MODE_HOST: 1347 default: 1348 /* do nothing */ 1349 break; 1350 } 1351 1352 return 0; 1353 } 1354 1355 static int dwc3_runtime_suspend(struct device *dev) 1356 { 1357 struct dwc3 *dwc = dev_get_drvdata(dev); 1358 int ret; 1359 1360 if (dwc3_runtime_checks(dwc)) 1361 return -EBUSY; 1362 1363 ret = dwc3_suspend_common(dwc); 1364 if (ret) 1365 return ret; 1366 1367 device_init_wakeup(dev, true); 1368 1369 return 0; 1370 } 1371 1372 static int dwc3_runtime_resume(struct device *dev) 1373 { 1374 struct dwc3 *dwc = dev_get_drvdata(dev); 1375 int ret; 1376 1377 device_init_wakeup(dev, false); 1378 1379 ret = dwc3_resume_common(dwc); 1380 if (ret) 1381 return ret; 1382 1383 switch (dwc->current_dr_role) { 1384 case DWC3_GCTL_PRTCAP_DEVICE: 1385 dwc3_gadget_process_pending_events(dwc); 1386 break; 1387 case DWC3_GCTL_PRTCAP_HOST: 1388 default: 1389 /* do nothing */ 1390 break; 1391 } 1392 1393 pm_runtime_mark_last_busy(dev); 1394 1395 return 0; 1396 } 1397 1398 static int dwc3_runtime_idle(struct device *dev) 1399 { 1400 struct dwc3 *dwc = dev_get_drvdata(dev); 1401 1402 switch (dwc->current_dr_role) { 1403 case DWC3_GCTL_PRTCAP_DEVICE: 1404 if (dwc3_runtime_checks(dwc)) 1405 return -EBUSY; 1406 break; 1407 case DWC3_GCTL_PRTCAP_HOST: 1408 default: 1409 /* do nothing */ 1410 break; 1411 } 1412 1413 pm_runtime_mark_last_busy(dev); 1414 pm_runtime_autosuspend(dev); 1415 1416 return 0; 1417 } 1418 #endif /* CONFIG_PM */ 1419 1420 #ifdef CONFIG_PM_SLEEP 1421 static int dwc3_suspend(struct device *dev) 1422 { 1423 struct dwc3 *dwc = dev_get_drvdata(dev); 1424 int ret; 1425 1426 ret = dwc3_suspend_common(dwc); 1427 if (ret) 1428 return ret; 1429 1430 pinctrl_pm_select_sleep_state(dev); 1431 1432 return 0; 1433 } 1434 1435 static int dwc3_resume(struct device *dev) 1436 { 1437 struct dwc3 *dwc = dev_get_drvdata(dev); 1438 int ret; 1439 1440 pinctrl_pm_select_default_state(dev); 1441 1442 ret = dwc3_resume_common(dwc); 1443 if (ret) 1444 return ret; 1445 1446 pm_runtime_disable(dev); 1447 pm_runtime_set_active(dev); 1448 pm_runtime_enable(dev); 1449 1450 return 0; 1451 } 1452 #endif /* CONFIG_PM_SLEEP */ 1453 1454 static const struct dev_pm_ops dwc3_dev_pm_ops = { 1455 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) 1456 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, 1457 dwc3_runtime_idle) 1458 }; 1459 1460 #ifdef CONFIG_OF 1461 static const struct of_device_id of_dwc3_match[] = { 1462 { 1463 .compatible = "snps,dwc3" 1464 }, 1465 { 1466 .compatible = "synopsys,dwc3" 1467 }, 1468 { }, 1469 }; 1470 MODULE_DEVICE_TABLE(of, of_dwc3_match); 1471 #endif 1472 1473 #ifdef CONFIG_ACPI 1474 1475 #define ACPI_ID_INTEL_BSW "808622B7" 1476 1477 static const struct acpi_device_id dwc3_acpi_match[] = { 1478 { ACPI_ID_INTEL_BSW, 0 }, 1479 { }, 1480 }; 1481 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); 1482 #endif 1483 1484 static struct platform_driver dwc3_driver = { 1485 .probe = dwc3_probe, 1486 .remove = dwc3_remove, 1487 .driver = { 1488 .name = "dwc3", 1489 .of_match_table = of_match_ptr(of_dwc3_match), 1490 .acpi_match_table = ACPI_PTR(dwc3_acpi_match), 1491 .pm = &dwc3_dev_pm_ops, 1492 }, 1493 }; 1494 1495 module_platform_driver(dwc3_driver); 1496 1497 MODULE_ALIAS("platform:dwc3"); 1498 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 1499 MODULE_LICENSE("GPL v2"); 1500 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 1501