1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * core.c - DesignWare USB3 DRD Controller Core file 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/version.h> 13 #include <linux/module.h> 14 #include <linux/kernel.h> 15 #include <linux/slab.h> 16 #include <linux/spinlock.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/interrupt.h> 20 #include <linux/ioport.h> 21 #include <linux/io.h> 22 #include <linux/list.h> 23 #include <linux/delay.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/of.h> 26 #include <linux/acpi.h> 27 #include <linux/pinctrl/consumer.h> 28 #include <linux/reset.h> 29 #include <linux/bitfield.h> 30 31 #include <linux/usb/ch9.h> 32 #include <linux/usb/gadget.h> 33 #include <linux/usb/of.h> 34 #include <linux/usb/otg.h> 35 36 #include "core.h" 37 #include "gadget.h" 38 #include "io.h" 39 40 #include "debug.h" 41 42 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ 43 44 /** 45 * dwc3_get_dr_mode - Validates and sets dr_mode 46 * @dwc: pointer to our context structure 47 */ 48 static int dwc3_get_dr_mode(struct dwc3 *dwc) 49 { 50 enum usb_dr_mode mode; 51 struct device *dev = dwc->dev; 52 unsigned int hw_mode; 53 54 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 55 dwc->dr_mode = USB_DR_MODE_OTG; 56 57 mode = dwc->dr_mode; 58 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 59 60 switch (hw_mode) { 61 case DWC3_GHWPARAMS0_MODE_GADGET: 62 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) { 63 dev_err(dev, 64 "Controller does not support host mode.\n"); 65 return -EINVAL; 66 } 67 mode = USB_DR_MODE_PERIPHERAL; 68 break; 69 case DWC3_GHWPARAMS0_MODE_HOST: 70 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { 71 dev_err(dev, 72 "Controller does not support device mode.\n"); 73 return -EINVAL; 74 } 75 mode = USB_DR_MODE_HOST; 76 break; 77 default: 78 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 79 mode = USB_DR_MODE_HOST; 80 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 81 mode = USB_DR_MODE_PERIPHERAL; 82 83 /* 84 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG 85 * mode. If the controller supports DRD but the dr_mode is not 86 * specified or set to OTG, then set the mode to peripheral. 87 */ 88 if (mode == USB_DR_MODE_OTG && 89 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) || 90 !device_property_read_bool(dwc->dev, "usb-role-switch")) && 91 !DWC3_VER_IS_PRIOR(DWC3, 330A)) 92 mode = USB_DR_MODE_PERIPHERAL; 93 } 94 95 if (mode != dwc->dr_mode) { 96 dev_warn(dev, 97 "Configuration mismatch. dr_mode forced to %s\n", 98 mode == USB_DR_MODE_HOST ? "host" : "gadget"); 99 100 dwc->dr_mode = mode; 101 } 102 103 return 0; 104 } 105 106 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) 107 { 108 u32 reg; 109 110 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 111 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 112 reg |= DWC3_GCTL_PRTCAPDIR(mode); 113 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 114 115 dwc->current_dr_role = mode; 116 } 117 118 static void __dwc3_set_mode(struct work_struct *work) 119 { 120 struct dwc3 *dwc = work_to_dwc(work); 121 unsigned long flags; 122 int ret; 123 u32 reg; 124 125 mutex_lock(&dwc->mutex); 126 127 pm_runtime_get_sync(dwc->dev); 128 129 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG) 130 dwc3_otg_update(dwc, 0); 131 132 if (!dwc->desired_dr_role) 133 goto out; 134 135 if (dwc->desired_dr_role == dwc->current_dr_role) 136 goto out; 137 138 if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev) 139 goto out; 140 141 switch (dwc->current_dr_role) { 142 case DWC3_GCTL_PRTCAP_HOST: 143 dwc3_host_exit(dwc); 144 break; 145 case DWC3_GCTL_PRTCAP_DEVICE: 146 dwc3_gadget_exit(dwc); 147 dwc3_event_buffers_cleanup(dwc); 148 break; 149 case DWC3_GCTL_PRTCAP_OTG: 150 dwc3_otg_exit(dwc); 151 spin_lock_irqsave(&dwc->lock, flags); 152 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE; 153 spin_unlock_irqrestore(&dwc->lock, flags); 154 dwc3_otg_update(dwc, 1); 155 break; 156 default: 157 break; 158 } 159 160 /* For DRD host or device mode only */ 161 if (dwc->desired_dr_role != DWC3_GCTL_PRTCAP_OTG) { 162 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 163 reg |= DWC3_GCTL_CORESOFTRESET; 164 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 165 166 /* 167 * Wait for internal clocks to synchronized. DWC_usb31 and 168 * DWC_usb32 may need at least 50ms (less for DWC_usb3). To 169 * keep it consistent across different IPs, let's wait up to 170 * 100ms before clearing GCTL.CORESOFTRESET. 171 */ 172 msleep(100); 173 174 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 175 reg &= ~DWC3_GCTL_CORESOFTRESET; 176 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 177 } 178 179 spin_lock_irqsave(&dwc->lock, flags); 180 181 dwc3_set_prtcap(dwc, dwc->desired_dr_role); 182 183 spin_unlock_irqrestore(&dwc->lock, flags); 184 185 switch (dwc->desired_dr_role) { 186 case DWC3_GCTL_PRTCAP_HOST: 187 ret = dwc3_host_init(dwc); 188 if (ret) { 189 dev_err(dwc->dev, "failed to initialize host\n"); 190 } else { 191 if (dwc->usb2_phy) 192 otg_set_vbus(dwc->usb2_phy->otg, true); 193 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 194 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 195 if (dwc->dis_split_quirk) { 196 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 197 reg |= DWC3_GUCTL3_SPLITDISABLE; 198 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 199 } 200 } 201 break; 202 case DWC3_GCTL_PRTCAP_DEVICE: 203 dwc3_core_soft_reset(dwc); 204 205 dwc3_event_buffers_setup(dwc); 206 207 if (dwc->usb2_phy) 208 otg_set_vbus(dwc->usb2_phy->otg, false); 209 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 210 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 211 212 ret = dwc3_gadget_init(dwc); 213 if (ret) 214 dev_err(dwc->dev, "failed to initialize peripheral\n"); 215 break; 216 case DWC3_GCTL_PRTCAP_OTG: 217 dwc3_otg_init(dwc); 218 dwc3_otg_update(dwc, 0); 219 break; 220 default: 221 break; 222 } 223 224 out: 225 pm_runtime_mark_last_busy(dwc->dev); 226 pm_runtime_put_autosuspend(dwc->dev); 227 mutex_unlock(&dwc->mutex); 228 } 229 230 void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 231 { 232 unsigned long flags; 233 234 if (dwc->dr_mode != USB_DR_MODE_OTG) 235 return; 236 237 spin_lock_irqsave(&dwc->lock, flags); 238 dwc->desired_dr_role = mode; 239 spin_unlock_irqrestore(&dwc->lock, flags); 240 241 queue_work(system_freezable_wq, &dwc->drd_work); 242 } 243 244 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) 245 { 246 struct dwc3 *dwc = dep->dwc; 247 u32 reg; 248 249 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, 250 DWC3_GDBGFIFOSPACE_NUM(dep->number) | 251 DWC3_GDBGFIFOSPACE_TYPE(type)); 252 253 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); 254 255 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); 256 } 257 258 /** 259 * dwc3_core_soft_reset - Issues core soft reset and PHY reset 260 * @dwc: pointer to our context structure 261 */ 262 int dwc3_core_soft_reset(struct dwc3 *dwc) 263 { 264 u32 reg; 265 int retries = 1000; 266 267 /* 268 * We're resetting only the device side because, if we're in host mode, 269 * XHCI driver will reset the host block. If dwc3 was configured for 270 * host-only mode, then we can return early. 271 */ 272 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) 273 return 0; 274 275 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 276 reg |= DWC3_DCTL_CSFTRST; 277 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 278 279 /* 280 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit 281 * is cleared only after all the clocks are synchronized. This can 282 * take a little more than 50ms. Set the polling rate at 20ms 283 * for 10 times instead. 284 */ 285 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 286 retries = 10; 287 288 do { 289 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 290 if (!(reg & DWC3_DCTL_CSFTRST)) 291 goto done; 292 293 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 294 msleep(20); 295 else 296 udelay(1); 297 } while (--retries); 298 299 return -ETIMEDOUT; 300 301 done: 302 /* 303 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit 304 * is cleared, we must wait at least 50ms before accessing the PHY 305 * domain (synchronization delay). 306 */ 307 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A)) 308 msleep(50); 309 310 return 0; 311 } 312 313 /* 314 * dwc3_frame_length_adjustment - Adjusts frame length if required 315 * @dwc3: Pointer to our controller context structure 316 */ 317 static void dwc3_frame_length_adjustment(struct dwc3 *dwc) 318 { 319 u32 reg; 320 u32 dft; 321 322 if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 323 return; 324 325 if (dwc->fladj == 0) 326 return; 327 328 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 329 dft = reg & DWC3_GFLADJ_30MHZ_MASK; 330 if (dft != dwc->fladj) { 331 reg &= ~DWC3_GFLADJ_30MHZ_MASK; 332 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; 333 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 334 } 335 } 336 337 /** 338 * dwc3_ref_clk_period - Reference clock period configuration 339 * Default reference clock period depends on hardware 340 * configuration. For systems with reference clock that differs 341 * from the default, this will set clock period in DWC3_GUCTL 342 * register. 343 * @dwc: Pointer to our controller context structure 344 * @ref_clk_per: reference clock period in ns 345 */ 346 static void dwc3_ref_clk_period(struct dwc3 *dwc) 347 { 348 unsigned long period; 349 unsigned long fladj; 350 unsigned long decr; 351 unsigned long rate; 352 u32 reg; 353 354 if (dwc->ref_clk) { 355 rate = clk_get_rate(dwc->ref_clk); 356 if (!rate) 357 return; 358 period = NSEC_PER_SEC / rate; 359 } else if (dwc->ref_clk_per) { 360 period = dwc->ref_clk_per; 361 rate = NSEC_PER_SEC / period; 362 } else { 363 return; 364 } 365 366 reg = dwc3_readl(dwc->regs, DWC3_GUCTL); 367 reg &= ~DWC3_GUCTL_REFCLKPER_MASK; 368 reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period); 369 dwc3_writel(dwc->regs, DWC3_GUCTL, reg); 370 371 if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 372 return; 373 374 /* 375 * The calculation below is 376 * 377 * 125000 * (NSEC_PER_SEC / (rate * period) - 1) 378 * 379 * but rearranged for fixed-point arithmetic. The division must be 380 * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and 381 * neither does rate * period). 382 * 383 * Note that rate * period ~= NSEC_PER_SECOND, minus the number of 384 * nanoseconds of error caused by the truncation which happened during 385 * the division when calculating rate or period (whichever one was 386 * derived from the other). We first calculate the relative error, then 387 * scale it to units of 8 ppm. 388 */ 389 fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period); 390 fladj -= 125000; 391 392 /* 393 * The documented 240MHz constant is scaled by 2 to get PLS1 as well. 394 */ 395 decr = 480000000 / rate; 396 397 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 398 reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK 399 & ~DWC3_GFLADJ_240MHZDECR 400 & ~DWC3_GFLADJ_240MHZDECR_PLS1; 401 reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj) 402 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1) 403 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1); 404 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 405 } 406 407 /** 408 * dwc3_free_one_event_buffer - Frees one event buffer 409 * @dwc: Pointer to our controller context structure 410 * @evt: Pointer to event buffer to be freed 411 */ 412 static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 413 struct dwc3_event_buffer *evt) 414 { 415 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma); 416 } 417 418 /** 419 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 420 * @dwc: Pointer to our controller context structure 421 * @length: size of the event buffer 422 * 423 * Returns a pointer to the allocated event buffer structure on success 424 * otherwise ERR_PTR(errno). 425 */ 426 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 427 unsigned length) 428 { 429 struct dwc3_event_buffer *evt; 430 431 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 432 if (!evt) 433 return ERR_PTR(-ENOMEM); 434 435 evt->dwc = dwc; 436 evt->length = length; 437 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL); 438 if (!evt->cache) 439 return ERR_PTR(-ENOMEM); 440 441 evt->buf = dma_alloc_coherent(dwc->sysdev, length, 442 &evt->dma, GFP_KERNEL); 443 if (!evt->buf) 444 return ERR_PTR(-ENOMEM); 445 446 return evt; 447 } 448 449 /** 450 * dwc3_free_event_buffers - frees all allocated event buffers 451 * @dwc: Pointer to our controller context structure 452 */ 453 static void dwc3_free_event_buffers(struct dwc3 *dwc) 454 { 455 struct dwc3_event_buffer *evt; 456 457 evt = dwc->ev_buf; 458 if (evt) 459 dwc3_free_one_event_buffer(dwc, evt); 460 } 461 462 /** 463 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 464 * @dwc: pointer to our controller context structure 465 * @length: size of event buffer 466 * 467 * Returns 0 on success otherwise negative errno. In the error case, dwc 468 * may contain some buffers allocated but not all which were requested. 469 */ 470 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) 471 { 472 struct dwc3_event_buffer *evt; 473 474 evt = dwc3_alloc_one_event_buffer(dwc, length); 475 if (IS_ERR(evt)) { 476 dev_err(dwc->dev, "can't allocate event buffer\n"); 477 return PTR_ERR(evt); 478 } 479 dwc->ev_buf = evt; 480 481 return 0; 482 } 483 484 /** 485 * dwc3_event_buffers_setup - setup our allocated event buffers 486 * @dwc: pointer to our controller context structure 487 * 488 * Returns 0 on success otherwise negative errno. 489 */ 490 int dwc3_event_buffers_setup(struct dwc3 *dwc) 491 { 492 struct dwc3_event_buffer *evt; 493 494 evt = dwc->ev_buf; 495 evt->lpos = 0; 496 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 497 lower_32_bits(evt->dma)); 498 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 499 upper_32_bits(evt->dma)); 500 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), 501 DWC3_GEVNTSIZ_SIZE(evt->length)); 502 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 503 504 return 0; 505 } 506 507 void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 508 { 509 struct dwc3_event_buffer *evt; 510 511 evt = dwc->ev_buf; 512 513 evt->lpos = 0; 514 515 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); 516 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); 517 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK 518 | DWC3_GEVNTSIZ_SIZE(0)); 519 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 520 } 521 522 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) 523 { 524 if (!dwc->has_hibernation) 525 return 0; 526 527 if (!dwc->nr_scratch) 528 return 0; 529 530 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, 531 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); 532 if (!dwc->scratchbuf) 533 return -ENOMEM; 534 535 return 0; 536 } 537 538 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) 539 { 540 dma_addr_t scratch_addr; 541 u32 param; 542 int ret; 543 544 if (!dwc->has_hibernation) 545 return 0; 546 547 if (!dwc->nr_scratch) 548 return 0; 549 550 /* should never fall here */ 551 if (!WARN_ON(dwc->scratchbuf)) 552 return 0; 553 554 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf, 555 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, 556 DMA_BIDIRECTIONAL); 557 if (dma_mapping_error(dwc->sysdev, scratch_addr)) { 558 dev_err(dwc->sysdev, "failed to map scratch buffer\n"); 559 ret = -EFAULT; 560 goto err0; 561 } 562 563 dwc->scratch_addr = scratch_addr; 564 565 param = lower_32_bits(scratch_addr); 566 567 ret = dwc3_send_gadget_generic_command(dwc, 568 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); 569 if (ret < 0) 570 goto err1; 571 572 param = upper_32_bits(scratch_addr); 573 574 ret = dwc3_send_gadget_generic_command(dwc, 575 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); 576 if (ret < 0) 577 goto err1; 578 579 return 0; 580 581 err1: 582 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 583 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 584 585 err0: 586 return ret; 587 } 588 589 static void dwc3_free_scratch_buffers(struct dwc3 *dwc) 590 { 591 if (!dwc->has_hibernation) 592 return; 593 594 if (!dwc->nr_scratch) 595 return; 596 597 /* should never fall here */ 598 if (!WARN_ON(dwc->scratchbuf)) 599 return; 600 601 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 602 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 603 kfree(dwc->scratchbuf); 604 } 605 606 static void dwc3_core_num_eps(struct dwc3 *dwc) 607 { 608 struct dwc3_hwparams *parms = &dwc->hwparams; 609 610 dwc->num_eps = DWC3_NUM_EPS(parms); 611 } 612 613 static void dwc3_cache_hwparams(struct dwc3 *dwc) 614 { 615 struct dwc3_hwparams *parms = &dwc->hwparams; 616 617 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 618 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 619 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 620 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 621 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 622 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 623 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 624 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 625 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 626 627 if (DWC3_IP_IS(DWC32)) 628 parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9); 629 } 630 631 static int dwc3_core_ulpi_init(struct dwc3 *dwc) 632 { 633 int intf; 634 int ret = 0; 635 636 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3); 637 638 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI || 639 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI && 640 dwc->hsphy_interface && 641 !strncmp(dwc->hsphy_interface, "ulpi", 4))) 642 ret = dwc3_ulpi_init(dwc); 643 644 return ret; 645 } 646 647 /** 648 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 649 * @dwc: Pointer to our controller context structure 650 * 651 * Returns 0 on success. The USB PHY interfaces are configured but not 652 * initialized. The PHY interfaces and the PHYs get initialized together with 653 * the core in dwc3_core_init. 654 */ 655 static int dwc3_phy_setup(struct dwc3 *dwc) 656 { 657 unsigned int hw_mode; 658 u32 reg; 659 660 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 661 662 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 663 664 /* 665 * Make sure UX_EXIT_PX is cleared as that causes issues with some 666 * PHYs. Also, this bit is not supposed to be used in normal operation. 667 */ 668 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; 669 670 /* 671 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 672 * to '0' during coreConsultant configuration. So default value 673 * will be '0' when the core is reset. Application needs to set it 674 * to '1' after the core initialization is completed. 675 */ 676 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) 677 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 678 679 /* 680 * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after 681 * power-on reset, and it can be set after core initialization, which is 682 * after device soft-reset during initialization. 683 */ 684 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 685 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 686 687 if (dwc->u2ss_inp3_quirk) 688 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 689 690 if (dwc->dis_rxdet_inp3_quirk) 691 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; 692 693 if (dwc->req_p1p2p3_quirk) 694 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 695 696 if (dwc->del_p1p2p3_quirk) 697 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 698 699 if (dwc->del_phy_power_chg_quirk) 700 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 701 702 if (dwc->lfps_filter_quirk) 703 reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 704 705 if (dwc->rx_detect_poll_quirk) 706 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 707 708 if (dwc->tx_de_emphasis_quirk) 709 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 710 711 if (dwc->dis_u3_susphy_quirk) 712 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 713 714 if (dwc->dis_del_phy_power_chg_quirk) 715 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; 716 717 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 718 719 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 720 721 /* Select the HS PHY interface */ 722 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { 723 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: 724 if (dwc->hsphy_interface && 725 !strncmp(dwc->hsphy_interface, "utmi", 4)) { 726 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; 727 break; 728 } else if (dwc->hsphy_interface && 729 !strncmp(dwc->hsphy_interface, "ulpi", 4)) { 730 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; 731 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 732 } else { 733 /* Relying on default value. */ 734 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) 735 break; 736 } 737 fallthrough; 738 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: 739 default: 740 break; 741 } 742 743 switch (dwc->hsphy_mode) { 744 case USBPHY_INTERFACE_MODE_UTMI: 745 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 746 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 747 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | 748 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); 749 break; 750 case USBPHY_INTERFACE_MODE_UTMIW: 751 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 752 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 753 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | 754 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 755 break; 756 default: 757 break; 758 } 759 760 /* 761 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 762 * '0' during coreConsultant configuration. So default value will 763 * be '0' when the core is reset. Application needs to set it to 764 * '1' after the core initialization is completed. 765 */ 766 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) 767 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 768 769 /* 770 * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after 771 * power-on reset, and it can be set after core initialization, which is 772 * after device soft-reset during initialization. 773 */ 774 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 775 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 776 777 if (dwc->dis_u2_susphy_quirk) 778 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 779 780 if (dwc->dis_enblslpm_quirk) 781 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 782 else 783 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM; 784 785 if (dwc->dis_u2_freeclk_exists_quirk) 786 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 787 788 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 789 790 return 0; 791 } 792 793 static int dwc3_clk_enable(struct dwc3 *dwc) 794 { 795 int ret; 796 797 ret = clk_prepare_enable(dwc->bus_clk); 798 if (ret) 799 return ret; 800 801 ret = clk_prepare_enable(dwc->ref_clk); 802 if (ret) 803 goto disable_bus_clk; 804 805 ret = clk_prepare_enable(dwc->susp_clk); 806 if (ret) 807 goto disable_ref_clk; 808 809 return 0; 810 811 disable_ref_clk: 812 clk_disable_unprepare(dwc->ref_clk); 813 disable_bus_clk: 814 clk_disable_unprepare(dwc->bus_clk); 815 return ret; 816 } 817 818 static void dwc3_clk_disable(struct dwc3 *dwc) 819 { 820 clk_disable_unprepare(dwc->susp_clk); 821 clk_disable_unprepare(dwc->ref_clk); 822 clk_disable_unprepare(dwc->bus_clk); 823 } 824 825 static void dwc3_core_exit(struct dwc3 *dwc) 826 { 827 dwc3_event_buffers_cleanup(dwc); 828 829 usb_phy_shutdown(dwc->usb2_phy); 830 usb_phy_shutdown(dwc->usb3_phy); 831 phy_exit(dwc->usb2_generic_phy); 832 phy_exit(dwc->usb3_generic_phy); 833 834 usb_phy_set_suspend(dwc->usb2_phy, 1); 835 usb_phy_set_suspend(dwc->usb3_phy, 1); 836 phy_power_off(dwc->usb2_generic_phy); 837 phy_power_off(dwc->usb3_generic_phy); 838 dwc3_clk_disable(dwc); 839 reset_control_assert(dwc->reset); 840 } 841 842 static bool dwc3_core_is_valid(struct dwc3 *dwc) 843 { 844 u32 reg; 845 846 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 847 dwc->ip = DWC3_GSNPS_ID(reg); 848 849 /* This should read as U3 followed by revision number */ 850 if (DWC3_IP_IS(DWC3)) { 851 dwc->revision = reg; 852 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) { 853 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); 854 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE); 855 } else { 856 return false; 857 } 858 859 return true; 860 } 861 862 static void dwc3_core_setup_global_control(struct dwc3 *dwc) 863 { 864 u32 hwparams4 = dwc->hwparams.hwparams4; 865 u32 reg; 866 867 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 868 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 869 870 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 871 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 872 /** 873 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 874 * issue which would cause xHCI compliance tests to fail. 875 * 876 * Because of that we cannot enable clock gating on such 877 * configurations. 878 * 879 * Refers to: 880 * 881 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 882 * SOF/ITP Mode Used 883 */ 884 if ((dwc->dr_mode == USB_DR_MODE_HOST || 885 dwc->dr_mode == USB_DR_MODE_OTG) && 886 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A)) 887 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 888 else 889 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 890 break; 891 case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 892 /* enable hibernation here */ 893 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); 894 895 /* 896 * REVISIT Enabling this bit so that host-mode hibernation 897 * will work. Device-mode hibernation is not yet implemented. 898 */ 899 reg |= DWC3_GCTL_GBLHIBERNATIONEN; 900 break; 901 default: 902 /* nothing */ 903 break; 904 } 905 906 /* check if current dwc3 is on simulation board */ 907 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 908 dev_info(dwc->dev, "Running with FPGA optimizations\n"); 909 dwc->is_fpga = true; 910 } 911 912 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, 913 "disable_scramble cannot be used on non-FPGA builds\n"); 914 915 if (dwc->disable_scramble_quirk && dwc->is_fpga) 916 reg |= DWC3_GCTL_DISSCRAMBLE; 917 else 918 reg &= ~DWC3_GCTL_DISSCRAMBLE; 919 920 if (dwc->u2exit_lfps_quirk) 921 reg |= DWC3_GCTL_U2EXIT_LFPS; 922 923 /* 924 * WORKAROUND: DWC3 revisions <1.90a have a bug 925 * where the device can fail to connect at SuperSpeed 926 * and falls back to high-speed mode which causes 927 * the device to enter a Connect/Disconnect loop 928 */ 929 if (DWC3_VER_IS_PRIOR(DWC3, 190A)) 930 reg |= DWC3_GCTL_U2RSTECN; 931 932 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 933 } 934 935 static int dwc3_core_get_phy(struct dwc3 *dwc); 936 static int dwc3_core_ulpi_init(struct dwc3 *dwc); 937 938 /* set global incr burst type configuration registers */ 939 static void dwc3_set_incr_burst_type(struct dwc3 *dwc) 940 { 941 struct device *dev = dwc->dev; 942 /* incrx_mode : for INCR burst type. */ 943 bool incrx_mode; 944 /* incrx_size : for size of INCRX burst. */ 945 u32 incrx_size; 946 u32 *vals; 947 u32 cfg; 948 int ntype; 949 int ret; 950 int i; 951 952 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); 953 954 /* 955 * Handle property "snps,incr-burst-type-adjustment". 956 * Get the number of value from this property: 957 * result <= 0, means this property is not supported. 958 * result = 1, means INCRx burst mode supported. 959 * result > 1, means undefined length burst mode supported. 960 */ 961 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment"); 962 if (ntype <= 0) 963 return; 964 965 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL); 966 if (!vals) { 967 dev_err(dev, "Error to get memory\n"); 968 return; 969 } 970 971 /* Get INCR burst type, and parse it */ 972 ret = device_property_read_u32_array(dev, 973 "snps,incr-burst-type-adjustment", vals, ntype); 974 if (ret) { 975 kfree(vals); 976 dev_err(dev, "Error to get property\n"); 977 return; 978 } 979 980 incrx_size = *vals; 981 982 if (ntype > 1) { 983 /* INCRX (undefined length) burst mode */ 984 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE; 985 for (i = 1; i < ntype; i++) { 986 if (vals[i] > incrx_size) 987 incrx_size = vals[i]; 988 } 989 } else { 990 /* INCRX burst mode */ 991 incrx_mode = INCRX_BURST_MODE; 992 } 993 994 kfree(vals); 995 996 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */ 997 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK; 998 if (incrx_mode) 999 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA; 1000 switch (incrx_size) { 1001 case 256: 1002 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA; 1003 break; 1004 case 128: 1005 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA; 1006 break; 1007 case 64: 1008 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA; 1009 break; 1010 case 32: 1011 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA; 1012 break; 1013 case 16: 1014 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA; 1015 break; 1016 case 8: 1017 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA; 1018 break; 1019 case 4: 1020 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA; 1021 break; 1022 case 1: 1023 break; 1024 default: 1025 dev_err(dev, "Invalid property\n"); 1026 break; 1027 } 1028 1029 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg); 1030 } 1031 1032 /** 1033 * dwc3_core_init - Low-level initialization of DWC3 Core 1034 * @dwc: Pointer to our controller context structure 1035 * 1036 * Returns 0 on success otherwise negative errno. 1037 */ 1038 static int dwc3_core_init(struct dwc3 *dwc) 1039 { 1040 unsigned int hw_mode; 1041 u32 reg; 1042 int ret; 1043 1044 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 1045 1046 /* 1047 * Write Linux Version Code to our GUID register so it's easy to figure 1048 * out which kernel version a bug was found. 1049 */ 1050 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); 1051 1052 ret = dwc3_phy_setup(dwc); 1053 if (ret) 1054 goto err0; 1055 1056 if (!dwc->ulpi_ready) { 1057 ret = dwc3_core_ulpi_init(dwc); 1058 if (ret) 1059 goto err0; 1060 dwc->ulpi_ready = true; 1061 } 1062 1063 if (!dwc->phys_ready) { 1064 ret = dwc3_core_get_phy(dwc); 1065 if (ret) 1066 goto err0a; 1067 dwc->phys_ready = true; 1068 } 1069 1070 usb_phy_init(dwc->usb2_phy); 1071 usb_phy_init(dwc->usb3_phy); 1072 ret = phy_init(dwc->usb2_generic_phy); 1073 if (ret < 0) 1074 goto err0a; 1075 1076 ret = phy_init(dwc->usb3_generic_phy); 1077 if (ret < 0) { 1078 phy_exit(dwc->usb2_generic_phy); 1079 goto err0a; 1080 } 1081 1082 ret = dwc3_core_soft_reset(dwc); 1083 if (ret) 1084 goto err1; 1085 1086 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD && 1087 !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) { 1088 if (!dwc->dis_u3_susphy_quirk) { 1089 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 1090 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 1091 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 1092 } 1093 1094 if (!dwc->dis_u2_susphy_quirk) { 1095 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1096 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 1097 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1098 } 1099 } 1100 1101 dwc3_core_setup_global_control(dwc); 1102 dwc3_core_num_eps(dwc); 1103 1104 ret = dwc3_setup_scratch_buffers(dwc); 1105 if (ret) 1106 goto err1; 1107 1108 /* Adjust Frame Length */ 1109 dwc3_frame_length_adjustment(dwc); 1110 1111 /* Adjust Reference Clock Period */ 1112 dwc3_ref_clk_period(dwc); 1113 1114 dwc3_set_incr_burst_type(dwc); 1115 1116 usb_phy_set_suspend(dwc->usb2_phy, 0); 1117 usb_phy_set_suspend(dwc->usb3_phy, 0); 1118 ret = phy_power_on(dwc->usb2_generic_phy); 1119 if (ret < 0) 1120 goto err2; 1121 1122 ret = phy_power_on(dwc->usb3_generic_phy); 1123 if (ret < 0) 1124 goto err3; 1125 1126 ret = dwc3_event_buffers_setup(dwc); 1127 if (ret) { 1128 dev_err(dwc->dev, "failed to setup event buffers\n"); 1129 goto err4; 1130 } 1131 1132 /* 1133 * ENDXFER polling is available on version 3.10a and later of 1134 * the DWC_usb3 controller. It is NOT available in the 1135 * DWC_usb31 controller. 1136 */ 1137 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) { 1138 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); 1139 reg |= DWC3_GUCTL2_RST_ACTBITLATER; 1140 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); 1141 } 1142 1143 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) { 1144 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 1145 1146 /* 1147 * Enable hardware control of sending remote wakeup 1148 * in HS when the device is in the L1 state. 1149 */ 1150 if (!DWC3_VER_IS_PRIOR(DWC3, 290A)) 1151 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; 1152 1153 /* 1154 * Decouple USB 2.0 L1 & L2 events which will allow for 1155 * gadget driver to only receive U3/L2 suspend & wakeup 1156 * events and prevent the more frequent L1 LPM transitions 1157 * from interrupting the driver. 1158 */ 1159 if (!DWC3_VER_IS_PRIOR(DWC3, 300A)) 1160 reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT; 1161 1162 if (dwc->dis_tx_ipgap_linecheck_quirk) 1163 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; 1164 1165 if (dwc->parkmode_disable_ss_quirk) 1166 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS; 1167 1168 if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) && 1169 (dwc->maximum_speed == USB_SPEED_HIGH || 1170 dwc->maximum_speed == USB_SPEED_FULL)) 1171 reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; 1172 1173 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 1174 } 1175 1176 if (dwc->dr_mode == USB_DR_MODE_HOST || 1177 dwc->dr_mode == USB_DR_MODE_OTG) { 1178 reg = dwc3_readl(dwc->regs, DWC3_GUCTL); 1179 1180 /* 1181 * Enable Auto retry Feature to make the controller operating in 1182 * Host mode on seeing transaction errors(CRC errors or internal 1183 * overrun scenerios) on IN transfers to reply to the device 1184 * with a non-terminating retry ACK (i.e, an ACK transcation 1185 * packet with Retry=1 & Nump != 0) 1186 */ 1187 reg |= DWC3_GUCTL_HSTINAUTORETRY; 1188 1189 dwc3_writel(dwc->regs, DWC3_GUCTL, reg); 1190 } 1191 1192 /* 1193 * Must config both number of packets and max burst settings to enable 1194 * RX and/or TX threshold. 1195 */ 1196 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) { 1197 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd; 1198 u8 rx_maxburst = dwc->rx_max_burst_prd; 1199 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd; 1200 u8 tx_maxburst = dwc->tx_max_burst_prd; 1201 1202 if (rx_thr_num && rx_maxburst) { 1203 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1204 reg |= DWC31_RXTHRNUMPKTSEL_PRD; 1205 1206 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0); 1207 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num); 1208 1209 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0); 1210 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst); 1211 1212 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1213 } 1214 1215 if (tx_thr_num && tx_maxburst) { 1216 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1217 reg |= DWC31_TXTHRNUMPKTSEL_PRD; 1218 1219 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0); 1220 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num); 1221 1222 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0); 1223 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst); 1224 1225 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1226 } 1227 } 1228 1229 return 0; 1230 1231 err4: 1232 phy_power_off(dwc->usb3_generic_phy); 1233 1234 err3: 1235 phy_power_off(dwc->usb2_generic_phy); 1236 1237 err2: 1238 usb_phy_set_suspend(dwc->usb2_phy, 1); 1239 usb_phy_set_suspend(dwc->usb3_phy, 1); 1240 1241 err1: 1242 usb_phy_shutdown(dwc->usb2_phy); 1243 usb_phy_shutdown(dwc->usb3_phy); 1244 phy_exit(dwc->usb2_generic_phy); 1245 phy_exit(dwc->usb3_generic_phy); 1246 1247 err0a: 1248 dwc3_ulpi_exit(dwc); 1249 1250 err0: 1251 return ret; 1252 } 1253 1254 static int dwc3_core_get_phy(struct dwc3 *dwc) 1255 { 1256 struct device *dev = dwc->dev; 1257 struct device_node *node = dev->of_node; 1258 int ret; 1259 1260 if (node) { 1261 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); 1262 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); 1263 } else { 1264 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 1265 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); 1266 } 1267 1268 if (IS_ERR(dwc->usb2_phy)) { 1269 ret = PTR_ERR(dwc->usb2_phy); 1270 if (ret == -ENXIO || ret == -ENODEV) { 1271 dwc->usb2_phy = NULL; 1272 } else { 1273 return dev_err_probe(dev, ret, "no usb2 phy configured\n"); 1274 } 1275 } 1276 1277 if (IS_ERR(dwc->usb3_phy)) { 1278 ret = PTR_ERR(dwc->usb3_phy); 1279 if (ret == -ENXIO || ret == -ENODEV) { 1280 dwc->usb3_phy = NULL; 1281 } else { 1282 return dev_err_probe(dev, ret, "no usb3 phy configured\n"); 1283 } 1284 } 1285 1286 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); 1287 if (IS_ERR(dwc->usb2_generic_phy)) { 1288 ret = PTR_ERR(dwc->usb2_generic_phy); 1289 if (ret == -ENOSYS || ret == -ENODEV) { 1290 dwc->usb2_generic_phy = NULL; 1291 } else { 1292 return dev_err_probe(dev, ret, "no usb2 phy configured\n"); 1293 } 1294 } 1295 1296 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); 1297 if (IS_ERR(dwc->usb3_generic_phy)) { 1298 ret = PTR_ERR(dwc->usb3_generic_phy); 1299 if (ret == -ENOSYS || ret == -ENODEV) { 1300 dwc->usb3_generic_phy = NULL; 1301 } else { 1302 return dev_err_probe(dev, ret, "no usb3 phy configured\n"); 1303 } 1304 } 1305 1306 return 0; 1307 } 1308 1309 static int dwc3_core_init_mode(struct dwc3 *dwc) 1310 { 1311 struct device *dev = dwc->dev; 1312 int ret; 1313 1314 switch (dwc->dr_mode) { 1315 case USB_DR_MODE_PERIPHERAL: 1316 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1317 1318 if (dwc->usb2_phy) 1319 otg_set_vbus(dwc->usb2_phy->otg, false); 1320 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 1321 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 1322 1323 ret = dwc3_gadget_init(dwc); 1324 if (ret) 1325 return dev_err_probe(dev, ret, "failed to initialize gadget\n"); 1326 break; 1327 case USB_DR_MODE_HOST: 1328 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1329 1330 if (dwc->usb2_phy) 1331 otg_set_vbus(dwc->usb2_phy->otg, true); 1332 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 1333 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 1334 1335 ret = dwc3_host_init(dwc); 1336 if (ret) 1337 return dev_err_probe(dev, ret, "failed to initialize host\n"); 1338 break; 1339 case USB_DR_MODE_OTG: 1340 INIT_WORK(&dwc->drd_work, __dwc3_set_mode); 1341 ret = dwc3_drd_init(dwc); 1342 if (ret) 1343 return dev_err_probe(dev, ret, "failed to initialize dual-role\n"); 1344 break; 1345 default: 1346 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 1347 return -EINVAL; 1348 } 1349 1350 return 0; 1351 } 1352 1353 static void dwc3_core_exit_mode(struct dwc3 *dwc) 1354 { 1355 switch (dwc->dr_mode) { 1356 case USB_DR_MODE_PERIPHERAL: 1357 dwc3_gadget_exit(dwc); 1358 break; 1359 case USB_DR_MODE_HOST: 1360 dwc3_host_exit(dwc); 1361 break; 1362 case USB_DR_MODE_OTG: 1363 dwc3_drd_exit(dwc); 1364 break; 1365 default: 1366 /* do nothing */ 1367 break; 1368 } 1369 1370 /* de-assert DRVVBUS for HOST and OTG mode */ 1371 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1372 } 1373 1374 static void dwc3_get_properties(struct dwc3 *dwc) 1375 { 1376 struct device *dev = dwc->dev; 1377 u8 lpm_nyet_threshold; 1378 u8 tx_de_emphasis; 1379 u8 hird_threshold; 1380 u8 rx_thr_num_pkt_prd; 1381 u8 rx_max_burst_prd; 1382 u8 tx_thr_num_pkt_prd; 1383 u8 tx_max_burst_prd; 1384 u8 tx_fifo_resize_max_num; 1385 const char *usb_psy_name; 1386 int ret; 1387 1388 /* default to highest possible threshold */ 1389 lpm_nyet_threshold = 0xf; 1390 1391 /* default to -3.5dB de-emphasis */ 1392 tx_de_emphasis = 1; 1393 1394 /* 1395 * default to assert utmi_sleep_n and use maximum allowed HIRD 1396 * threshold value of 0b1100 1397 */ 1398 hird_threshold = 12; 1399 1400 /* 1401 * default to a TXFIFO size large enough to fit 6 max packets. This 1402 * allows for systems with larger bus latencies to have some headroom 1403 * for endpoints that have a large bMaxBurst value. 1404 */ 1405 tx_fifo_resize_max_num = 6; 1406 1407 dwc->maximum_speed = usb_get_maximum_speed(dev); 1408 dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev); 1409 dwc->dr_mode = usb_get_dr_mode(dev); 1410 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); 1411 1412 dwc->sysdev_is_parent = device_property_read_bool(dev, 1413 "linux,sysdev_is_parent"); 1414 if (dwc->sysdev_is_parent) 1415 dwc->sysdev = dwc->dev->parent; 1416 else 1417 dwc->sysdev = dwc->dev; 1418 1419 ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name); 1420 if (ret >= 0) { 1421 dwc->usb_psy = power_supply_get_by_name(usb_psy_name); 1422 if (!dwc->usb_psy) 1423 dev_err(dev, "couldn't get usb power supply\n"); 1424 } 1425 1426 dwc->has_lpm_erratum = device_property_read_bool(dev, 1427 "snps,has-lpm-erratum"); 1428 device_property_read_u8(dev, "snps,lpm-nyet-threshold", 1429 &lpm_nyet_threshold); 1430 dwc->is_utmi_l1_suspend = device_property_read_bool(dev, 1431 "snps,is-utmi-l1-suspend"); 1432 device_property_read_u8(dev, "snps,hird-threshold", 1433 &hird_threshold); 1434 dwc->dis_start_transfer_quirk = device_property_read_bool(dev, 1435 "snps,dis-start-transfer-quirk"); 1436 dwc->usb3_lpm_capable = device_property_read_bool(dev, 1437 "snps,usb3_lpm_capable"); 1438 dwc->usb2_lpm_disable = device_property_read_bool(dev, 1439 "snps,usb2-lpm-disable"); 1440 dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev, 1441 "snps,usb2-gadget-lpm-disable"); 1442 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd", 1443 &rx_thr_num_pkt_prd); 1444 device_property_read_u8(dev, "snps,rx-max-burst-prd", 1445 &rx_max_burst_prd); 1446 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd", 1447 &tx_thr_num_pkt_prd); 1448 device_property_read_u8(dev, "snps,tx-max-burst-prd", 1449 &tx_max_burst_prd); 1450 dwc->do_fifo_resize = device_property_read_bool(dev, 1451 "tx-fifo-resize"); 1452 if (dwc->do_fifo_resize) 1453 device_property_read_u8(dev, "tx-fifo-max-num", 1454 &tx_fifo_resize_max_num); 1455 1456 dwc->disable_scramble_quirk = device_property_read_bool(dev, 1457 "snps,disable_scramble_quirk"); 1458 dwc->u2exit_lfps_quirk = device_property_read_bool(dev, 1459 "snps,u2exit_lfps_quirk"); 1460 dwc->u2ss_inp3_quirk = device_property_read_bool(dev, 1461 "snps,u2ss_inp3_quirk"); 1462 dwc->req_p1p2p3_quirk = device_property_read_bool(dev, 1463 "snps,req_p1p2p3_quirk"); 1464 dwc->del_p1p2p3_quirk = device_property_read_bool(dev, 1465 "snps,del_p1p2p3_quirk"); 1466 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, 1467 "snps,del_phy_power_chg_quirk"); 1468 dwc->lfps_filter_quirk = device_property_read_bool(dev, 1469 "snps,lfps_filter_quirk"); 1470 dwc->rx_detect_poll_quirk = device_property_read_bool(dev, 1471 "snps,rx_detect_poll_quirk"); 1472 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, 1473 "snps,dis_u3_susphy_quirk"); 1474 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, 1475 "snps,dis_u2_susphy_quirk"); 1476 dwc->dis_enblslpm_quirk = device_property_read_bool(dev, 1477 "snps,dis_enblslpm_quirk"); 1478 dwc->dis_u1_entry_quirk = device_property_read_bool(dev, 1479 "snps,dis-u1-entry-quirk"); 1480 dwc->dis_u2_entry_quirk = device_property_read_bool(dev, 1481 "snps,dis-u2-entry-quirk"); 1482 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, 1483 "snps,dis_rxdet_inp3_quirk"); 1484 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, 1485 "snps,dis-u2-freeclk-exists-quirk"); 1486 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, 1487 "snps,dis-del-phy-power-chg-quirk"); 1488 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev, 1489 "snps,dis-tx-ipgap-linecheck-quirk"); 1490 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev, 1491 "snps,parkmode-disable-ss-quirk"); 1492 1493 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, 1494 "snps,tx_de_emphasis_quirk"); 1495 device_property_read_u8(dev, "snps,tx_de_emphasis", 1496 &tx_de_emphasis); 1497 device_property_read_string(dev, "snps,hsphy_interface", 1498 &dwc->hsphy_interface); 1499 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", 1500 &dwc->fladj); 1501 device_property_read_u32(dev, "snps,ref-clock-period-ns", 1502 &dwc->ref_clk_per); 1503 1504 dwc->dis_metastability_quirk = device_property_read_bool(dev, 1505 "snps,dis_metastability_quirk"); 1506 1507 dwc->dis_split_quirk = device_property_read_bool(dev, 1508 "snps,dis-split-quirk"); 1509 1510 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 1511 dwc->tx_de_emphasis = tx_de_emphasis; 1512 1513 dwc->hird_threshold = hird_threshold; 1514 1515 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd; 1516 dwc->rx_max_burst_prd = rx_max_burst_prd; 1517 1518 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd; 1519 dwc->tx_max_burst_prd = tx_max_burst_prd; 1520 1521 dwc->imod_interval = 0; 1522 1523 dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num; 1524 } 1525 1526 /* check whether the core supports IMOD */ 1527 bool dwc3_has_imod(struct dwc3 *dwc) 1528 { 1529 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) || 1530 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) || 1531 DWC3_IP_IS(DWC32); 1532 } 1533 1534 static void dwc3_check_params(struct dwc3 *dwc) 1535 { 1536 struct device *dev = dwc->dev; 1537 unsigned int hwparam_gen = 1538 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3); 1539 1540 /* Check for proper value of imod_interval */ 1541 if (dwc->imod_interval && !dwc3_has_imod(dwc)) { 1542 dev_warn(dwc->dev, "Interrupt moderation not supported\n"); 1543 dwc->imod_interval = 0; 1544 } 1545 1546 /* 1547 * Workaround for STAR 9000961433 which affects only version 1548 * 3.00a of the DWC_usb3 core. This prevents the controller 1549 * interrupt from being masked while handling events. IMOD 1550 * allows us to work around this issue. Enable it for the 1551 * affected version. 1552 */ 1553 if (!dwc->imod_interval && 1554 DWC3_VER_IS(DWC3, 300A)) 1555 dwc->imod_interval = 1; 1556 1557 /* Check the maximum_speed parameter */ 1558 switch (dwc->maximum_speed) { 1559 case USB_SPEED_FULL: 1560 case USB_SPEED_HIGH: 1561 break; 1562 case USB_SPEED_SUPER: 1563 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) 1564 dev_warn(dev, "UDC doesn't support Gen 1\n"); 1565 break; 1566 case USB_SPEED_SUPER_PLUS: 1567 if ((DWC3_IP_IS(DWC32) && 1568 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) || 1569 (!DWC3_IP_IS(DWC32) && 1570 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) 1571 dev_warn(dev, "UDC doesn't support SSP\n"); 1572 break; 1573 default: 1574 dev_err(dev, "invalid maximum_speed parameter %d\n", 1575 dwc->maximum_speed); 1576 fallthrough; 1577 case USB_SPEED_UNKNOWN: 1578 switch (hwparam_gen) { 1579 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 1580 dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1581 break; 1582 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 1583 if (DWC3_IP_IS(DWC32)) 1584 dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1585 else 1586 dwc->maximum_speed = USB_SPEED_SUPER; 1587 break; 1588 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS: 1589 dwc->maximum_speed = USB_SPEED_HIGH; 1590 break; 1591 default: 1592 dwc->maximum_speed = USB_SPEED_SUPER; 1593 break; 1594 } 1595 break; 1596 } 1597 1598 /* 1599 * Currently the controller does not have visibility into the HW 1600 * parameter to determine the maximum number of lanes the HW supports. 1601 * If the number of lanes is not specified in the device property, then 1602 * set the default to support dual-lane for DWC_usb32 and single-lane 1603 * for DWC_usb31 for super-speed-plus. 1604 */ 1605 if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) { 1606 switch (dwc->max_ssp_rate) { 1607 case USB_SSP_GEN_2x1: 1608 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1) 1609 dev_warn(dev, "UDC only supports Gen 1\n"); 1610 break; 1611 case USB_SSP_GEN_1x2: 1612 case USB_SSP_GEN_2x2: 1613 if (DWC3_IP_IS(DWC31)) 1614 dev_warn(dev, "UDC only supports single lane\n"); 1615 break; 1616 case USB_SSP_GEN_UNKNOWN: 1617 default: 1618 switch (hwparam_gen) { 1619 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 1620 if (DWC3_IP_IS(DWC32)) 1621 dwc->max_ssp_rate = USB_SSP_GEN_2x2; 1622 else 1623 dwc->max_ssp_rate = USB_SSP_GEN_2x1; 1624 break; 1625 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 1626 if (DWC3_IP_IS(DWC32)) 1627 dwc->max_ssp_rate = USB_SSP_GEN_1x2; 1628 break; 1629 } 1630 break; 1631 } 1632 } 1633 } 1634 1635 static int dwc3_probe(struct platform_device *pdev) 1636 { 1637 struct device *dev = &pdev->dev; 1638 struct resource *res, dwc_res; 1639 struct dwc3 *dwc; 1640 1641 int ret; 1642 1643 void __iomem *regs; 1644 1645 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 1646 if (!dwc) 1647 return -ENOMEM; 1648 1649 dwc->dev = dev; 1650 1651 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1652 if (!res) { 1653 dev_err(dev, "missing memory resource\n"); 1654 return -ENODEV; 1655 } 1656 1657 dwc->xhci_resources[0].start = res->start; 1658 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + 1659 DWC3_XHCI_REGS_END; 1660 dwc->xhci_resources[0].flags = res->flags; 1661 dwc->xhci_resources[0].name = res->name; 1662 1663 /* 1664 * Request memory region but exclude xHCI regs, 1665 * since it will be requested by the xhci-plat driver. 1666 */ 1667 dwc_res = *res; 1668 dwc_res.start += DWC3_GLOBALS_REGS_START; 1669 1670 regs = devm_ioremap_resource(dev, &dwc_res); 1671 if (IS_ERR(regs)) 1672 return PTR_ERR(regs); 1673 1674 dwc->regs = regs; 1675 dwc->regs_size = resource_size(&dwc_res); 1676 1677 dwc3_get_properties(dwc); 1678 1679 if (!dwc->sysdev_is_parent) { 1680 ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64)); 1681 if (ret) 1682 return ret; 1683 } 1684 1685 dwc->reset = devm_reset_control_array_get_optional_shared(dev); 1686 if (IS_ERR(dwc->reset)) 1687 return PTR_ERR(dwc->reset); 1688 1689 if (dev->of_node) { 1690 /* 1691 * Clocks are optional, but new DT platforms should support all 1692 * clocks as required by the DT-binding. 1693 */ 1694 dwc->bus_clk = devm_clk_get_optional(dev, "bus_early"); 1695 if (IS_ERR(dwc->bus_clk)) 1696 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk), 1697 "could not get bus clock\n"); 1698 1699 dwc->ref_clk = devm_clk_get_optional(dev, "ref"); 1700 if (IS_ERR(dwc->ref_clk)) 1701 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk), 1702 "could not get ref clock\n"); 1703 1704 dwc->susp_clk = devm_clk_get_optional(dev, "suspend"); 1705 if (IS_ERR(dwc->susp_clk)) 1706 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk), 1707 "could not get suspend clock\n"); 1708 } 1709 1710 ret = reset_control_deassert(dwc->reset); 1711 if (ret) 1712 return ret; 1713 1714 ret = dwc3_clk_enable(dwc); 1715 if (ret) 1716 goto assert_reset; 1717 1718 if (!dwc3_core_is_valid(dwc)) { 1719 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 1720 ret = -ENODEV; 1721 goto disable_clks; 1722 } 1723 1724 platform_set_drvdata(pdev, dwc); 1725 dwc3_cache_hwparams(dwc); 1726 1727 spin_lock_init(&dwc->lock); 1728 mutex_init(&dwc->mutex); 1729 1730 pm_runtime_set_active(dev); 1731 pm_runtime_use_autosuspend(dev); 1732 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); 1733 pm_runtime_enable(dev); 1734 ret = pm_runtime_get_sync(dev); 1735 if (ret < 0) 1736 goto err1; 1737 1738 pm_runtime_forbid(dev); 1739 1740 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 1741 if (ret) { 1742 dev_err(dwc->dev, "failed to allocate event buffers\n"); 1743 ret = -ENOMEM; 1744 goto err2; 1745 } 1746 1747 ret = dwc3_get_dr_mode(dwc); 1748 if (ret) 1749 goto err3; 1750 1751 ret = dwc3_alloc_scratch_buffers(dwc); 1752 if (ret) 1753 goto err3; 1754 1755 ret = dwc3_core_init(dwc); 1756 if (ret) { 1757 dev_err_probe(dev, ret, "failed to initialize core\n"); 1758 goto err4; 1759 } 1760 1761 dwc3_check_params(dwc); 1762 dwc3_debugfs_init(dwc); 1763 1764 ret = dwc3_core_init_mode(dwc); 1765 if (ret) 1766 goto err5; 1767 1768 pm_runtime_put(dev); 1769 1770 return 0; 1771 1772 err5: 1773 dwc3_debugfs_exit(dwc); 1774 dwc3_event_buffers_cleanup(dwc); 1775 1776 usb_phy_shutdown(dwc->usb2_phy); 1777 usb_phy_shutdown(dwc->usb3_phy); 1778 phy_exit(dwc->usb2_generic_phy); 1779 phy_exit(dwc->usb3_generic_phy); 1780 1781 usb_phy_set_suspend(dwc->usb2_phy, 1); 1782 usb_phy_set_suspend(dwc->usb3_phy, 1); 1783 phy_power_off(dwc->usb2_generic_phy); 1784 phy_power_off(dwc->usb3_generic_phy); 1785 1786 dwc3_ulpi_exit(dwc); 1787 1788 err4: 1789 dwc3_free_scratch_buffers(dwc); 1790 1791 err3: 1792 dwc3_free_event_buffers(dwc); 1793 1794 err2: 1795 pm_runtime_allow(&pdev->dev); 1796 1797 err1: 1798 pm_runtime_put_sync(&pdev->dev); 1799 pm_runtime_disable(&pdev->dev); 1800 1801 disable_clks: 1802 dwc3_clk_disable(dwc); 1803 assert_reset: 1804 reset_control_assert(dwc->reset); 1805 1806 if (dwc->usb_psy) 1807 power_supply_put(dwc->usb_psy); 1808 1809 return ret; 1810 } 1811 1812 static int dwc3_remove(struct platform_device *pdev) 1813 { 1814 struct dwc3 *dwc = platform_get_drvdata(pdev); 1815 1816 pm_runtime_get_sync(&pdev->dev); 1817 1818 dwc3_core_exit_mode(dwc); 1819 dwc3_debugfs_exit(dwc); 1820 1821 dwc3_core_exit(dwc); 1822 dwc3_ulpi_exit(dwc); 1823 1824 pm_runtime_disable(&pdev->dev); 1825 pm_runtime_put_noidle(&pdev->dev); 1826 pm_runtime_set_suspended(&pdev->dev); 1827 1828 dwc3_free_event_buffers(dwc); 1829 dwc3_free_scratch_buffers(dwc); 1830 1831 if (dwc->usb_psy) 1832 power_supply_put(dwc->usb_psy); 1833 1834 return 0; 1835 } 1836 1837 #ifdef CONFIG_PM 1838 static int dwc3_core_init_for_resume(struct dwc3 *dwc) 1839 { 1840 int ret; 1841 1842 ret = reset_control_deassert(dwc->reset); 1843 if (ret) 1844 return ret; 1845 1846 ret = dwc3_clk_enable(dwc); 1847 if (ret) 1848 goto assert_reset; 1849 1850 ret = dwc3_core_init(dwc); 1851 if (ret) 1852 goto disable_clks; 1853 1854 return 0; 1855 1856 disable_clks: 1857 dwc3_clk_disable(dwc); 1858 assert_reset: 1859 reset_control_assert(dwc->reset); 1860 1861 return ret; 1862 } 1863 1864 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) 1865 { 1866 unsigned long flags; 1867 u32 reg; 1868 1869 switch (dwc->current_dr_role) { 1870 case DWC3_GCTL_PRTCAP_DEVICE: 1871 if (pm_runtime_suspended(dwc->dev)) 1872 break; 1873 spin_lock_irqsave(&dwc->lock, flags); 1874 dwc3_gadget_suspend(dwc); 1875 spin_unlock_irqrestore(&dwc->lock, flags); 1876 synchronize_irq(dwc->irq_gadget); 1877 dwc3_core_exit(dwc); 1878 break; 1879 case DWC3_GCTL_PRTCAP_HOST: 1880 if (!PMSG_IS_AUTO(msg)) { 1881 dwc3_core_exit(dwc); 1882 break; 1883 } 1884 1885 /* Let controller to suspend HSPHY before PHY driver suspends */ 1886 if (dwc->dis_u2_susphy_quirk || 1887 dwc->dis_enblslpm_quirk) { 1888 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1889 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM | 1890 DWC3_GUSB2PHYCFG_SUSPHY; 1891 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1892 1893 /* Give some time for USB2 PHY to suspend */ 1894 usleep_range(5000, 6000); 1895 } 1896 1897 phy_pm_runtime_put_sync(dwc->usb2_generic_phy); 1898 phy_pm_runtime_put_sync(dwc->usb3_generic_phy); 1899 break; 1900 case DWC3_GCTL_PRTCAP_OTG: 1901 /* do nothing during runtime_suspend */ 1902 if (PMSG_IS_AUTO(msg)) 1903 break; 1904 1905 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 1906 spin_lock_irqsave(&dwc->lock, flags); 1907 dwc3_gadget_suspend(dwc); 1908 spin_unlock_irqrestore(&dwc->lock, flags); 1909 synchronize_irq(dwc->irq_gadget); 1910 } 1911 1912 dwc3_otg_exit(dwc); 1913 dwc3_core_exit(dwc); 1914 break; 1915 default: 1916 /* do nothing */ 1917 break; 1918 } 1919 1920 return 0; 1921 } 1922 1923 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) 1924 { 1925 unsigned long flags; 1926 int ret; 1927 u32 reg; 1928 1929 switch (dwc->current_dr_role) { 1930 case DWC3_GCTL_PRTCAP_DEVICE: 1931 ret = dwc3_core_init_for_resume(dwc); 1932 if (ret) 1933 return ret; 1934 1935 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1936 spin_lock_irqsave(&dwc->lock, flags); 1937 dwc3_gadget_resume(dwc); 1938 spin_unlock_irqrestore(&dwc->lock, flags); 1939 break; 1940 case DWC3_GCTL_PRTCAP_HOST: 1941 if (!PMSG_IS_AUTO(msg)) { 1942 ret = dwc3_core_init_for_resume(dwc); 1943 if (ret) 1944 return ret; 1945 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1946 break; 1947 } 1948 /* Restore GUSB2PHYCFG bits that were modified in suspend */ 1949 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1950 if (dwc->dis_u2_susphy_quirk) 1951 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 1952 1953 if (dwc->dis_enblslpm_quirk) 1954 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 1955 1956 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1957 1958 phy_pm_runtime_get_sync(dwc->usb2_generic_phy); 1959 phy_pm_runtime_get_sync(dwc->usb3_generic_phy); 1960 break; 1961 case DWC3_GCTL_PRTCAP_OTG: 1962 /* nothing to do on runtime_resume */ 1963 if (PMSG_IS_AUTO(msg)) 1964 break; 1965 1966 ret = dwc3_core_init_for_resume(dwc); 1967 if (ret) 1968 return ret; 1969 1970 dwc3_set_prtcap(dwc, dwc->current_dr_role); 1971 1972 dwc3_otg_init(dwc); 1973 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) { 1974 dwc3_otg_host_init(dwc); 1975 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 1976 spin_lock_irqsave(&dwc->lock, flags); 1977 dwc3_gadget_resume(dwc); 1978 spin_unlock_irqrestore(&dwc->lock, flags); 1979 } 1980 1981 break; 1982 default: 1983 /* do nothing */ 1984 break; 1985 } 1986 1987 return 0; 1988 } 1989 1990 static int dwc3_runtime_checks(struct dwc3 *dwc) 1991 { 1992 switch (dwc->current_dr_role) { 1993 case DWC3_GCTL_PRTCAP_DEVICE: 1994 if (dwc->connected) 1995 return -EBUSY; 1996 break; 1997 case DWC3_GCTL_PRTCAP_HOST: 1998 default: 1999 /* do nothing */ 2000 break; 2001 } 2002 2003 return 0; 2004 } 2005 2006 static int dwc3_runtime_suspend(struct device *dev) 2007 { 2008 struct dwc3 *dwc = dev_get_drvdata(dev); 2009 int ret; 2010 2011 if (dwc3_runtime_checks(dwc)) 2012 return -EBUSY; 2013 2014 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND); 2015 if (ret) 2016 return ret; 2017 2018 device_init_wakeup(dev, true); 2019 2020 return 0; 2021 } 2022 2023 static int dwc3_runtime_resume(struct device *dev) 2024 { 2025 struct dwc3 *dwc = dev_get_drvdata(dev); 2026 int ret; 2027 2028 device_init_wakeup(dev, false); 2029 2030 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME); 2031 if (ret) 2032 return ret; 2033 2034 switch (dwc->current_dr_role) { 2035 case DWC3_GCTL_PRTCAP_DEVICE: 2036 dwc3_gadget_process_pending_events(dwc); 2037 break; 2038 case DWC3_GCTL_PRTCAP_HOST: 2039 default: 2040 /* do nothing */ 2041 break; 2042 } 2043 2044 pm_runtime_mark_last_busy(dev); 2045 2046 return 0; 2047 } 2048 2049 static int dwc3_runtime_idle(struct device *dev) 2050 { 2051 struct dwc3 *dwc = dev_get_drvdata(dev); 2052 2053 switch (dwc->current_dr_role) { 2054 case DWC3_GCTL_PRTCAP_DEVICE: 2055 if (dwc3_runtime_checks(dwc)) 2056 return -EBUSY; 2057 break; 2058 case DWC3_GCTL_PRTCAP_HOST: 2059 default: 2060 /* do nothing */ 2061 break; 2062 } 2063 2064 pm_runtime_mark_last_busy(dev); 2065 pm_runtime_autosuspend(dev); 2066 2067 return 0; 2068 } 2069 #endif /* CONFIG_PM */ 2070 2071 #ifdef CONFIG_PM_SLEEP 2072 static int dwc3_suspend(struct device *dev) 2073 { 2074 struct dwc3 *dwc = dev_get_drvdata(dev); 2075 int ret; 2076 2077 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND); 2078 if (ret) 2079 return ret; 2080 2081 pinctrl_pm_select_sleep_state(dev); 2082 2083 return 0; 2084 } 2085 2086 static int dwc3_resume(struct device *dev) 2087 { 2088 struct dwc3 *dwc = dev_get_drvdata(dev); 2089 int ret; 2090 2091 pinctrl_pm_select_default_state(dev); 2092 2093 ret = dwc3_resume_common(dwc, PMSG_RESUME); 2094 if (ret) 2095 return ret; 2096 2097 pm_runtime_disable(dev); 2098 pm_runtime_set_active(dev); 2099 pm_runtime_enable(dev); 2100 2101 return 0; 2102 } 2103 2104 static void dwc3_complete(struct device *dev) 2105 { 2106 struct dwc3 *dwc = dev_get_drvdata(dev); 2107 u32 reg; 2108 2109 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST && 2110 dwc->dis_split_quirk) { 2111 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 2112 reg |= DWC3_GUCTL3_SPLITDISABLE; 2113 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 2114 } 2115 } 2116 #else 2117 #define dwc3_complete NULL 2118 #endif /* CONFIG_PM_SLEEP */ 2119 2120 static const struct dev_pm_ops dwc3_dev_pm_ops = { 2121 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) 2122 .complete = dwc3_complete, 2123 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, 2124 dwc3_runtime_idle) 2125 }; 2126 2127 #ifdef CONFIG_OF 2128 static const struct of_device_id of_dwc3_match[] = { 2129 { 2130 .compatible = "snps,dwc3" 2131 }, 2132 { 2133 .compatible = "synopsys,dwc3" 2134 }, 2135 { }, 2136 }; 2137 MODULE_DEVICE_TABLE(of, of_dwc3_match); 2138 #endif 2139 2140 #ifdef CONFIG_ACPI 2141 2142 #define ACPI_ID_INTEL_BSW "808622B7" 2143 2144 static const struct acpi_device_id dwc3_acpi_match[] = { 2145 { ACPI_ID_INTEL_BSW, 0 }, 2146 { }, 2147 }; 2148 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); 2149 #endif 2150 2151 static struct platform_driver dwc3_driver = { 2152 .probe = dwc3_probe, 2153 .remove = dwc3_remove, 2154 .driver = { 2155 .name = "dwc3", 2156 .of_match_table = of_match_ptr(of_dwc3_match), 2157 .acpi_match_table = ACPI_PTR(dwc3_acpi_match), 2158 .pm = &dwc3_dev_pm_ops, 2159 }, 2160 }; 2161 2162 module_platform_driver(dwc3_driver); 2163 2164 MODULE_ALIAS("platform:dwc3"); 2165 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 2166 MODULE_LICENSE("GPL v2"); 2167 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 2168