1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * core.c - DesignWare USB3 DRD Controller Core file 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/version.h> 13 #include <linux/module.h> 14 #include <linux/kernel.h> 15 #include <linux/slab.h> 16 #include <linux/spinlock.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/interrupt.h> 20 #include <linux/ioport.h> 21 #include <linux/io.h> 22 #include <linux/list.h> 23 #include <linux/delay.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/of.h> 26 #include <linux/of_graph.h> 27 #include <linux/acpi.h> 28 #include <linux/pinctrl/consumer.h> 29 #include <linux/reset.h> 30 #include <linux/bitfield.h> 31 32 #include <linux/usb/ch9.h> 33 #include <linux/usb/gadget.h> 34 #include <linux/usb/of.h> 35 #include <linux/usb/otg.h> 36 37 #include "core.h" 38 #include "gadget.h" 39 #include "io.h" 40 41 #include "debug.h" 42 #include "../host/xhci-ext-caps.h" 43 44 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ 45 46 /** 47 * dwc3_get_dr_mode - Validates and sets dr_mode 48 * @dwc: pointer to our context structure 49 */ 50 static int dwc3_get_dr_mode(struct dwc3 *dwc) 51 { 52 enum usb_dr_mode mode; 53 struct device *dev = dwc->dev; 54 unsigned int hw_mode; 55 56 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 57 dwc->dr_mode = USB_DR_MODE_OTG; 58 59 mode = dwc->dr_mode; 60 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 61 62 switch (hw_mode) { 63 case DWC3_GHWPARAMS0_MODE_GADGET: 64 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) { 65 dev_err(dev, 66 "Controller does not support host mode.\n"); 67 return -EINVAL; 68 } 69 mode = USB_DR_MODE_PERIPHERAL; 70 break; 71 case DWC3_GHWPARAMS0_MODE_HOST: 72 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { 73 dev_err(dev, 74 "Controller does not support device mode.\n"); 75 return -EINVAL; 76 } 77 mode = USB_DR_MODE_HOST; 78 break; 79 default: 80 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 81 mode = USB_DR_MODE_HOST; 82 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 83 mode = USB_DR_MODE_PERIPHERAL; 84 85 /* 86 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG 87 * mode. If the controller supports DRD but the dr_mode is not 88 * specified or set to OTG, then set the mode to peripheral. 89 */ 90 if (mode == USB_DR_MODE_OTG && !dwc->edev && 91 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) || 92 !device_property_read_bool(dwc->dev, "usb-role-switch")) && 93 !DWC3_VER_IS_PRIOR(DWC3, 330A)) 94 mode = USB_DR_MODE_PERIPHERAL; 95 } 96 97 if (mode != dwc->dr_mode) { 98 dev_warn(dev, 99 "Configuration mismatch. dr_mode forced to %s\n", 100 mode == USB_DR_MODE_HOST ? "host" : "gadget"); 101 102 dwc->dr_mode = mode; 103 } 104 105 return 0; 106 } 107 108 void dwc3_enable_susphy(struct dwc3 *dwc, bool enable) 109 { 110 u32 reg; 111 int i; 112 113 for (i = 0; i < dwc->num_usb3_ports; i++) { 114 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(i)); 115 if (enable && !dwc->dis_u3_susphy_quirk) 116 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 117 else 118 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 119 120 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(i), reg); 121 } 122 123 for (i = 0; i < dwc->num_usb2_ports; i++) { 124 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i)); 125 if (enable && !dwc->dis_u2_susphy_quirk) 126 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 127 else 128 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 129 130 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg); 131 } 132 } 133 134 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) 135 { 136 u32 reg; 137 138 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 139 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 140 reg |= DWC3_GCTL_PRTCAPDIR(mode); 141 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 142 143 dwc->current_dr_role = mode; 144 } 145 146 static void __dwc3_set_mode(struct work_struct *work) 147 { 148 struct dwc3 *dwc = work_to_dwc(work); 149 unsigned long flags; 150 int ret; 151 u32 reg; 152 u32 desired_dr_role; 153 int i; 154 155 mutex_lock(&dwc->mutex); 156 spin_lock_irqsave(&dwc->lock, flags); 157 desired_dr_role = dwc->desired_dr_role; 158 spin_unlock_irqrestore(&dwc->lock, flags); 159 160 pm_runtime_get_sync(dwc->dev); 161 162 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG) 163 dwc3_otg_update(dwc, 0); 164 165 if (!desired_dr_role) 166 goto out; 167 168 if (desired_dr_role == dwc->current_dr_role) 169 goto out; 170 171 if (desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev) 172 goto out; 173 174 switch (dwc->current_dr_role) { 175 case DWC3_GCTL_PRTCAP_HOST: 176 dwc3_host_exit(dwc); 177 break; 178 case DWC3_GCTL_PRTCAP_DEVICE: 179 dwc3_gadget_exit(dwc); 180 dwc3_event_buffers_cleanup(dwc); 181 break; 182 case DWC3_GCTL_PRTCAP_OTG: 183 dwc3_otg_exit(dwc); 184 spin_lock_irqsave(&dwc->lock, flags); 185 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE; 186 spin_unlock_irqrestore(&dwc->lock, flags); 187 dwc3_otg_update(dwc, 1); 188 break; 189 default: 190 break; 191 } 192 193 /* 194 * When current_dr_role is not set, there's no role switching. 195 * Only perform GCTL.CoreSoftReset when there's DRD role switching. 196 */ 197 if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) || 198 DWC3_VER_IS_PRIOR(DWC31, 190A)) && 199 desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) { 200 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 201 reg |= DWC3_GCTL_CORESOFTRESET; 202 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 203 204 /* 205 * Wait for internal clocks to synchronized. DWC_usb31 and 206 * DWC_usb32 may need at least 50ms (less for DWC_usb3). To 207 * keep it consistent across different IPs, let's wait up to 208 * 100ms before clearing GCTL.CORESOFTRESET. 209 */ 210 msleep(100); 211 212 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 213 reg &= ~DWC3_GCTL_CORESOFTRESET; 214 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 215 } 216 217 spin_lock_irqsave(&dwc->lock, flags); 218 219 dwc3_set_prtcap(dwc, desired_dr_role); 220 221 spin_unlock_irqrestore(&dwc->lock, flags); 222 223 switch (desired_dr_role) { 224 case DWC3_GCTL_PRTCAP_HOST: 225 ret = dwc3_host_init(dwc); 226 if (ret) { 227 dev_err(dwc->dev, "failed to initialize host\n"); 228 } else { 229 if (dwc->usb2_phy) 230 otg_set_vbus(dwc->usb2_phy->otg, true); 231 232 for (i = 0; i < dwc->num_usb2_ports; i++) 233 phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST); 234 for (i = 0; i < dwc->num_usb3_ports; i++) 235 phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST); 236 237 if (dwc->dis_split_quirk) { 238 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 239 reg |= DWC3_GUCTL3_SPLITDISABLE; 240 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 241 } 242 } 243 break; 244 case DWC3_GCTL_PRTCAP_DEVICE: 245 dwc3_core_soft_reset(dwc); 246 247 dwc3_event_buffers_setup(dwc); 248 249 if (dwc->usb2_phy) 250 otg_set_vbus(dwc->usb2_phy->otg, false); 251 phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE); 252 phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE); 253 254 ret = dwc3_gadget_init(dwc); 255 if (ret) 256 dev_err(dwc->dev, "failed to initialize peripheral\n"); 257 break; 258 case DWC3_GCTL_PRTCAP_OTG: 259 dwc3_otg_init(dwc); 260 dwc3_otg_update(dwc, 0); 261 break; 262 default: 263 break; 264 } 265 266 out: 267 pm_runtime_mark_last_busy(dwc->dev); 268 pm_runtime_put_autosuspend(dwc->dev); 269 mutex_unlock(&dwc->mutex); 270 } 271 272 void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 273 { 274 unsigned long flags; 275 276 if (dwc->dr_mode != USB_DR_MODE_OTG) 277 return; 278 279 spin_lock_irqsave(&dwc->lock, flags); 280 dwc->desired_dr_role = mode; 281 spin_unlock_irqrestore(&dwc->lock, flags); 282 283 queue_work(system_freezable_wq, &dwc->drd_work); 284 } 285 286 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) 287 { 288 struct dwc3 *dwc = dep->dwc; 289 u32 reg; 290 291 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, 292 DWC3_GDBGFIFOSPACE_NUM(dep->number) | 293 DWC3_GDBGFIFOSPACE_TYPE(type)); 294 295 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); 296 297 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); 298 } 299 300 /** 301 * dwc3_core_soft_reset - Issues core soft reset and PHY reset 302 * @dwc: pointer to our context structure 303 */ 304 int dwc3_core_soft_reset(struct dwc3 *dwc) 305 { 306 u32 reg; 307 int retries = 1000; 308 309 /* 310 * We're resetting only the device side because, if we're in host mode, 311 * XHCI driver will reset the host block. If dwc3 was configured for 312 * host-only mode, then we can return early. 313 */ 314 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) 315 return 0; 316 317 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 318 reg |= DWC3_DCTL_CSFTRST; 319 reg &= ~DWC3_DCTL_RUN_STOP; 320 dwc3_gadget_dctl_write_safe(dwc, reg); 321 322 /* 323 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit 324 * is cleared only after all the clocks are synchronized. This can 325 * take a little more than 50ms. Set the polling rate at 20ms 326 * for 10 times instead. 327 */ 328 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 329 retries = 10; 330 331 do { 332 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 333 if (!(reg & DWC3_DCTL_CSFTRST)) 334 goto done; 335 336 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 337 msleep(20); 338 else 339 udelay(1); 340 } while (--retries); 341 342 dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n"); 343 return -ETIMEDOUT; 344 345 done: 346 /* 347 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit 348 * is cleared, we must wait at least 50ms before accessing the PHY 349 * domain (synchronization delay). 350 */ 351 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A)) 352 msleep(50); 353 354 return 0; 355 } 356 357 /* 358 * dwc3_frame_length_adjustment - Adjusts frame length if required 359 * @dwc3: Pointer to our controller context structure 360 */ 361 static void dwc3_frame_length_adjustment(struct dwc3 *dwc) 362 { 363 u32 reg; 364 u32 dft; 365 366 if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 367 return; 368 369 if (dwc->fladj == 0) 370 return; 371 372 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 373 dft = reg & DWC3_GFLADJ_30MHZ_MASK; 374 if (dft != dwc->fladj) { 375 reg &= ~DWC3_GFLADJ_30MHZ_MASK; 376 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; 377 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 378 } 379 } 380 381 /** 382 * dwc3_ref_clk_period - Reference clock period configuration 383 * Default reference clock period depends on hardware 384 * configuration. For systems with reference clock that differs 385 * from the default, this will set clock period in DWC3_GUCTL 386 * register. 387 * @dwc: Pointer to our controller context structure 388 */ 389 static void dwc3_ref_clk_period(struct dwc3 *dwc) 390 { 391 unsigned long period; 392 unsigned long fladj; 393 unsigned long decr; 394 unsigned long rate; 395 u32 reg; 396 397 if (dwc->ref_clk) { 398 rate = clk_get_rate(dwc->ref_clk); 399 if (!rate) 400 return; 401 period = NSEC_PER_SEC / rate; 402 } else if (dwc->ref_clk_per) { 403 period = dwc->ref_clk_per; 404 rate = NSEC_PER_SEC / period; 405 } else { 406 return; 407 } 408 409 reg = dwc3_readl(dwc->regs, DWC3_GUCTL); 410 reg &= ~DWC3_GUCTL_REFCLKPER_MASK; 411 reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period); 412 dwc3_writel(dwc->regs, DWC3_GUCTL, reg); 413 414 if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 415 return; 416 417 /* 418 * The calculation below is 419 * 420 * 125000 * (NSEC_PER_SEC / (rate * period) - 1) 421 * 422 * but rearranged for fixed-point arithmetic. The division must be 423 * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and 424 * neither does rate * period). 425 * 426 * Note that rate * period ~= NSEC_PER_SECOND, minus the number of 427 * nanoseconds of error caused by the truncation which happened during 428 * the division when calculating rate or period (whichever one was 429 * derived from the other). We first calculate the relative error, then 430 * scale it to units of 8 ppm. 431 */ 432 fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period); 433 fladj -= 125000; 434 435 /* 436 * The documented 240MHz constant is scaled by 2 to get PLS1 as well. 437 */ 438 decr = 480000000 / rate; 439 440 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 441 reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK 442 & ~DWC3_GFLADJ_240MHZDECR 443 & ~DWC3_GFLADJ_240MHZDECR_PLS1; 444 reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj) 445 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1) 446 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1); 447 448 if (dwc->gfladj_refclk_lpm_sel) 449 reg |= DWC3_GFLADJ_REFCLK_LPM_SEL; 450 451 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 452 } 453 454 /** 455 * dwc3_free_one_event_buffer - Frees one event buffer 456 * @dwc: Pointer to our controller context structure 457 * @evt: Pointer to event buffer to be freed 458 */ 459 static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 460 struct dwc3_event_buffer *evt) 461 { 462 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma); 463 } 464 465 /** 466 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 467 * @dwc: Pointer to our controller context structure 468 * @length: size of the event buffer 469 * 470 * Returns a pointer to the allocated event buffer structure on success 471 * otherwise ERR_PTR(errno). 472 */ 473 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 474 unsigned int length) 475 { 476 struct dwc3_event_buffer *evt; 477 478 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 479 if (!evt) 480 return ERR_PTR(-ENOMEM); 481 482 evt->dwc = dwc; 483 evt->length = length; 484 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL); 485 if (!evt->cache) 486 return ERR_PTR(-ENOMEM); 487 488 evt->buf = dma_alloc_coherent(dwc->sysdev, length, 489 &evt->dma, GFP_KERNEL); 490 if (!evt->buf) 491 return ERR_PTR(-ENOMEM); 492 493 return evt; 494 } 495 496 /** 497 * dwc3_free_event_buffers - frees all allocated event buffers 498 * @dwc: Pointer to our controller context structure 499 */ 500 static void dwc3_free_event_buffers(struct dwc3 *dwc) 501 { 502 struct dwc3_event_buffer *evt; 503 504 evt = dwc->ev_buf; 505 if (evt) 506 dwc3_free_one_event_buffer(dwc, evt); 507 } 508 509 /** 510 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 511 * @dwc: pointer to our controller context structure 512 * @length: size of event buffer 513 * 514 * Returns 0 on success otherwise negative errno. In the error case, dwc 515 * may contain some buffers allocated but not all which were requested. 516 */ 517 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length) 518 { 519 struct dwc3_event_buffer *evt; 520 unsigned int hw_mode; 521 522 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 523 if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) { 524 dwc->ev_buf = NULL; 525 return 0; 526 } 527 528 evt = dwc3_alloc_one_event_buffer(dwc, length); 529 if (IS_ERR(evt)) { 530 dev_err(dwc->dev, "can't allocate event buffer\n"); 531 return PTR_ERR(evt); 532 } 533 dwc->ev_buf = evt; 534 535 return 0; 536 } 537 538 /** 539 * dwc3_event_buffers_setup - setup our allocated event buffers 540 * @dwc: pointer to our controller context structure 541 * 542 * Returns 0 on success otherwise negative errno. 543 */ 544 int dwc3_event_buffers_setup(struct dwc3 *dwc) 545 { 546 struct dwc3_event_buffer *evt; 547 548 if (!dwc->ev_buf) 549 return 0; 550 551 evt = dwc->ev_buf; 552 evt->lpos = 0; 553 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 554 lower_32_bits(evt->dma)); 555 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 556 upper_32_bits(evt->dma)); 557 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), 558 DWC3_GEVNTSIZ_SIZE(evt->length)); 559 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 560 561 return 0; 562 } 563 564 void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 565 { 566 struct dwc3_event_buffer *evt; 567 u32 reg; 568 569 if (!dwc->ev_buf) 570 return; 571 /* 572 * Exynos platforms may not be able to access event buffer if the 573 * controller failed to halt on dwc3_core_exit(). 574 */ 575 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 576 if (!(reg & DWC3_DSTS_DEVCTRLHLT)) 577 return; 578 579 evt = dwc->ev_buf; 580 581 evt->lpos = 0; 582 583 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); 584 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); 585 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK 586 | DWC3_GEVNTSIZ_SIZE(0)); 587 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 588 } 589 590 static void dwc3_core_num_eps(struct dwc3 *dwc) 591 { 592 struct dwc3_hwparams *parms = &dwc->hwparams; 593 594 dwc->num_eps = DWC3_NUM_EPS(parms); 595 } 596 597 static void dwc3_cache_hwparams(struct dwc3 *dwc) 598 { 599 struct dwc3_hwparams *parms = &dwc->hwparams; 600 601 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 602 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 603 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 604 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 605 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 606 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 607 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 608 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 609 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 610 611 if (DWC3_IP_IS(DWC32)) 612 parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9); 613 } 614 615 static void dwc3_config_soc_bus(struct dwc3 *dwc) 616 { 617 if (dwc->gsbuscfg0_reqinfo != DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED) { 618 u32 reg; 619 620 reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); 621 reg &= ~DWC3_GSBUSCFG0_REQINFO(~0); 622 reg |= DWC3_GSBUSCFG0_REQINFO(dwc->gsbuscfg0_reqinfo); 623 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg); 624 } 625 } 626 627 static int dwc3_core_ulpi_init(struct dwc3 *dwc) 628 { 629 int intf; 630 int ret = 0; 631 632 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3); 633 634 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI || 635 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI && 636 dwc->hsphy_interface && 637 !strncmp(dwc->hsphy_interface, "ulpi", 4))) 638 ret = dwc3_ulpi_init(dwc); 639 640 return ret; 641 } 642 643 static int dwc3_ss_phy_setup(struct dwc3 *dwc, int index) 644 { 645 u32 reg; 646 647 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(index)); 648 649 /* 650 * Make sure UX_EXIT_PX is cleared as that causes issues with some 651 * PHYs. Also, this bit is not supposed to be used in normal operation. 652 */ 653 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; 654 655 /* 656 * Above DWC_usb3.0 1.94a, it is recommended to set 657 * DWC3_GUSB3PIPECTL_SUSPHY to '0' during coreConsultant configuration. 658 * So default value will be '0' when the core is reset. Application 659 * needs to set it to '1' after the core initialization is completed. 660 * 661 * Similarly for DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be 662 * cleared after power-on reset, and it can be set after core 663 * initialization. 664 */ 665 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 666 667 if (dwc->u2ss_inp3_quirk) 668 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 669 670 if (dwc->dis_rxdet_inp3_quirk) 671 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; 672 673 if (dwc->req_p1p2p3_quirk) 674 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 675 676 if (dwc->del_p1p2p3_quirk) 677 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 678 679 if (dwc->del_phy_power_chg_quirk) 680 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 681 682 if (dwc->lfps_filter_quirk) 683 reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 684 685 if (dwc->rx_detect_poll_quirk) 686 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 687 688 if (dwc->tx_de_emphasis_quirk) 689 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 690 691 if (dwc->dis_del_phy_power_chg_quirk) 692 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; 693 694 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(index), reg); 695 696 return 0; 697 } 698 699 static int dwc3_hs_phy_setup(struct dwc3 *dwc, int index) 700 { 701 u32 reg; 702 703 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(index)); 704 705 /* Select the HS PHY interface */ 706 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { 707 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: 708 if (dwc->hsphy_interface && 709 !strncmp(dwc->hsphy_interface, "utmi", 4)) { 710 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; 711 break; 712 } else if (dwc->hsphy_interface && 713 !strncmp(dwc->hsphy_interface, "ulpi", 4)) { 714 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; 715 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg); 716 } else { 717 /* Relying on default value. */ 718 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) 719 break; 720 } 721 fallthrough; 722 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: 723 default: 724 break; 725 } 726 727 switch (dwc->hsphy_mode) { 728 case USBPHY_INTERFACE_MODE_UTMI: 729 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 730 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 731 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | 732 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); 733 break; 734 case USBPHY_INTERFACE_MODE_UTMIW: 735 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 736 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 737 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | 738 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 739 break; 740 default: 741 break; 742 } 743 744 /* 745 * Above DWC_usb3.0 1.94a, it is recommended to set 746 * DWC3_GUSB2PHYCFG_SUSPHY to '0' during coreConsultant configuration. 747 * So default value will be '0' when the core is reset. Application 748 * needs to set it to '1' after the core initialization is completed. 749 * 750 * Similarly for DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared 751 * after power-on reset, and it can be set after core initialization. 752 */ 753 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 754 755 if (dwc->dis_enblslpm_quirk) 756 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 757 else 758 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM; 759 760 if (dwc->dis_u2_freeclk_exists_quirk || dwc->gfladj_refclk_lpm_sel) 761 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 762 763 /* 764 * Some ULPI USB PHY does not support internal VBUS supply, to drive 765 * the CPEN pin requires the configuration of the ULPI DRVVBUSEXTERNAL 766 * bit of OTG_CTRL register. Controller configures the USB2 PHY 767 * ULPIEXTVBUSDRV bit[17] of the GUSB2PHYCFG register to drive vBus 768 * with an external supply. 769 */ 770 if (dwc->ulpi_ext_vbus_drv) 771 reg |= DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV; 772 773 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg); 774 775 return 0; 776 } 777 778 /** 779 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 780 * @dwc: Pointer to our controller context structure 781 * 782 * Returns 0 on success. The USB PHY interfaces are configured but not 783 * initialized. The PHY interfaces and the PHYs get initialized together with 784 * the core in dwc3_core_init. 785 */ 786 static int dwc3_phy_setup(struct dwc3 *dwc) 787 { 788 int i; 789 int ret; 790 791 for (i = 0; i < dwc->num_usb3_ports; i++) { 792 ret = dwc3_ss_phy_setup(dwc, i); 793 if (ret) 794 return ret; 795 } 796 797 for (i = 0; i < dwc->num_usb2_ports; i++) { 798 ret = dwc3_hs_phy_setup(dwc, i); 799 if (ret) 800 return ret; 801 } 802 803 return 0; 804 } 805 806 static int dwc3_phy_init(struct dwc3 *dwc) 807 { 808 int ret; 809 int i; 810 int j; 811 812 usb_phy_init(dwc->usb2_phy); 813 usb_phy_init(dwc->usb3_phy); 814 815 for (i = 0; i < dwc->num_usb2_ports; i++) { 816 ret = phy_init(dwc->usb2_generic_phy[i]); 817 if (ret < 0) 818 goto err_exit_usb2_phy; 819 } 820 821 for (j = 0; j < dwc->num_usb3_ports; j++) { 822 ret = phy_init(dwc->usb3_generic_phy[j]); 823 if (ret < 0) 824 goto err_exit_usb3_phy; 825 } 826 827 return 0; 828 829 err_exit_usb3_phy: 830 while (--j >= 0) 831 phy_exit(dwc->usb3_generic_phy[j]); 832 833 err_exit_usb2_phy: 834 while (--i >= 0) 835 phy_exit(dwc->usb2_generic_phy[i]); 836 837 usb_phy_shutdown(dwc->usb3_phy); 838 usb_phy_shutdown(dwc->usb2_phy); 839 840 return ret; 841 } 842 843 static void dwc3_phy_exit(struct dwc3 *dwc) 844 { 845 int i; 846 847 for (i = 0; i < dwc->num_usb3_ports; i++) 848 phy_exit(dwc->usb3_generic_phy[i]); 849 850 for (i = 0; i < dwc->num_usb2_ports; i++) 851 phy_exit(dwc->usb2_generic_phy[i]); 852 853 usb_phy_shutdown(dwc->usb3_phy); 854 usb_phy_shutdown(dwc->usb2_phy); 855 } 856 857 static int dwc3_phy_power_on(struct dwc3 *dwc) 858 { 859 int ret; 860 int i; 861 int j; 862 863 usb_phy_set_suspend(dwc->usb2_phy, 0); 864 usb_phy_set_suspend(dwc->usb3_phy, 0); 865 866 for (i = 0; i < dwc->num_usb2_ports; i++) { 867 ret = phy_power_on(dwc->usb2_generic_phy[i]); 868 if (ret < 0) 869 goto err_power_off_usb2_phy; 870 } 871 872 for (j = 0; j < dwc->num_usb3_ports; j++) { 873 ret = phy_power_on(dwc->usb3_generic_phy[j]); 874 if (ret < 0) 875 goto err_power_off_usb3_phy; 876 } 877 878 return 0; 879 880 err_power_off_usb3_phy: 881 while (--j >= 0) 882 phy_power_off(dwc->usb3_generic_phy[j]); 883 884 err_power_off_usb2_phy: 885 while (--i >= 0) 886 phy_power_off(dwc->usb2_generic_phy[i]); 887 888 usb_phy_set_suspend(dwc->usb3_phy, 1); 889 usb_phy_set_suspend(dwc->usb2_phy, 1); 890 891 return ret; 892 } 893 894 static void dwc3_phy_power_off(struct dwc3 *dwc) 895 { 896 int i; 897 898 for (i = 0; i < dwc->num_usb3_ports; i++) 899 phy_power_off(dwc->usb3_generic_phy[i]); 900 901 for (i = 0; i < dwc->num_usb2_ports; i++) 902 phy_power_off(dwc->usb2_generic_phy[i]); 903 904 usb_phy_set_suspend(dwc->usb3_phy, 1); 905 usb_phy_set_suspend(dwc->usb2_phy, 1); 906 } 907 908 static int dwc3_clk_enable(struct dwc3 *dwc) 909 { 910 int ret; 911 912 ret = clk_prepare_enable(dwc->bus_clk); 913 if (ret) 914 return ret; 915 916 ret = clk_prepare_enable(dwc->ref_clk); 917 if (ret) 918 goto disable_bus_clk; 919 920 ret = clk_prepare_enable(dwc->susp_clk); 921 if (ret) 922 goto disable_ref_clk; 923 924 ret = clk_prepare_enable(dwc->utmi_clk); 925 if (ret) 926 goto disable_susp_clk; 927 928 ret = clk_prepare_enable(dwc->pipe_clk); 929 if (ret) 930 goto disable_utmi_clk; 931 932 return 0; 933 934 disable_utmi_clk: 935 clk_disable_unprepare(dwc->utmi_clk); 936 disable_susp_clk: 937 clk_disable_unprepare(dwc->susp_clk); 938 disable_ref_clk: 939 clk_disable_unprepare(dwc->ref_clk); 940 disable_bus_clk: 941 clk_disable_unprepare(dwc->bus_clk); 942 return ret; 943 } 944 945 static void dwc3_clk_disable(struct dwc3 *dwc) 946 { 947 clk_disable_unprepare(dwc->pipe_clk); 948 clk_disable_unprepare(dwc->utmi_clk); 949 clk_disable_unprepare(dwc->susp_clk); 950 clk_disable_unprepare(dwc->ref_clk); 951 clk_disable_unprepare(dwc->bus_clk); 952 } 953 954 static void dwc3_core_exit(struct dwc3 *dwc) 955 { 956 dwc3_event_buffers_cleanup(dwc); 957 dwc3_phy_power_off(dwc); 958 dwc3_phy_exit(dwc); 959 dwc3_clk_disable(dwc); 960 reset_control_assert(dwc->reset); 961 } 962 963 static bool dwc3_core_is_valid(struct dwc3 *dwc) 964 { 965 u32 reg; 966 967 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 968 dwc->ip = DWC3_GSNPS_ID(reg); 969 970 /* This should read as U3 followed by revision number */ 971 if (DWC3_IP_IS(DWC3)) { 972 dwc->revision = reg; 973 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) { 974 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); 975 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE); 976 } else { 977 return false; 978 } 979 980 return true; 981 } 982 983 static void dwc3_core_setup_global_control(struct dwc3 *dwc) 984 { 985 unsigned int power_opt; 986 unsigned int hw_mode; 987 u32 reg; 988 989 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 990 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 991 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 992 power_opt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1); 993 994 switch (power_opt) { 995 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 996 /** 997 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 998 * issue which would cause xHCI compliance tests to fail. 999 * 1000 * Because of that we cannot enable clock gating on such 1001 * configurations. 1002 * 1003 * Refers to: 1004 * 1005 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 1006 * SOF/ITP Mode Used 1007 */ 1008 if ((dwc->dr_mode == USB_DR_MODE_HOST || 1009 dwc->dr_mode == USB_DR_MODE_OTG) && 1010 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A)) 1011 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 1012 else 1013 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 1014 break; 1015 case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 1016 /* 1017 * REVISIT Enabling this bit so that host-mode hibernation 1018 * will work. Device-mode hibernation is not yet implemented. 1019 */ 1020 reg |= DWC3_GCTL_GBLHIBERNATIONEN; 1021 break; 1022 default: 1023 /* nothing */ 1024 break; 1025 } 1026 1027 /* 1028 * This is a workaround for STAR#4846132, which only affects 1029 * DWC_usb31 version2.00a operating in host mode. 1030 * 1031 * There is a problem in DWC_usb31 version 2.00a operating 1032 * in host mode that would cause a CSR read timeout When CSR 1033 * read coincides with RAM Clock Gating Entry. By disable 1034 * Clock Gating, sacrificing power consumption for normal 1035 * operation. 1036 */ 1037 if (power_opt != DWC3_GHWPARAMS1_EN_PWROPT_NO && 1038 hw_mode != DWC3_GHWPARAMS0_MODE_GADGET && DWC3_VER_IS(DWC31, 200A)) 1039 reg |= DWC3_GCTL_DSBLCLKGTNG; 1040 1041 /* check if current dwc3 is on simulation board */ 1042 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 1043 dev_info(dwc->dev, "Running with FPGA optimizations\n"); 1044 dwc->is_fpga = true; 1045 } 1046 1047 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, 1048 "disable_scramble cannot be used on non-FPGA builds\n"); 1049 1050 if (dwc->disable_scramble_quirk && dwc->is_fpga) 1051 reg |= DWC3_GCTL_DISSCRAMBLE; 1052 else 1053 reg &= ~DWC3_GCTL_DISSCRAMBLE; 1054 1055 if (dwc->u2exit_lfps_quirk) 1056 reg |= DWC3_GCTL_U2EXIT_LFPS; 1057 1058 /* 1059 * WORKAROUND: DWC3 revisions <1.90a have a bug 1060 * where the device can fail to connect at SuperSpeed 1061 * and falls back to high-speed mode which causes 1062 * the device to enter a Connect/Disconnect loop 1063 */ 1064 if (DWC3_VER_IS_PRIOR(DWC3, 190A)) 1065 reg |= DWC3_GCTL_U2RSTECN; 1066 1067 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 1068 } 1069 1070 static int dwc3_core_get_phy(struct dwc3 *dwc); 1071 static int dwc3_core_ulpi_init(struct dwc3 *dwc); 1072 1073 /* set global incr burst type configuration registers */ 1074 static void dwc3_set_incr_burst_type(struct dwc3 *dwc) 1075 { 1076 struct device *dev = dwc->dev; 1077 /* incrx_mode : for INCR burst type. */ 1078 bool incrx_mode; 1079 /* incrx_size : for size of INCRX burst. */ 1080 u32 incrx_size; 1081 u32 *vals; 1082 u32 cfg; 1083 int ntype; 1084 int ret; 1085 int i; 1086 1087 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); 1088 1089 /* 1090 * Handle property "snps,incr-burst-type-adjustment". 1091 * Get the number of value from this property: 1092 * result <= 0, means this property is not supported. 1093 * result = 1, means INCRx burst mode supported. 1094 * result > 1, means undefined length burst mode supported. 1095 */ 1096 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment"); 1097 if (ntype <= 0) 1098 return; 1099 1100 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL); 1101 if (!vals) 1102 return; 1103 1104 /* Get INCR burst type, and parse it */ 1105 ret = device_property_read_u32_array(dev, 1106 "snps,incr-burst-type-adjustment", vals, ntype); 1107 if (ret) { 1108 kfree(vals); 1109 dev_err(dev, "Error to get property\n"); 1110 return; 1111 } 1112 1113 incrx_size = *vals; 1114 1115 if (ntype > 1) { 1116 /* INCRX (undefined length) burst mode */ 1117 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE; 1118 for (i = 1; i < ntype; i++) { 1119 if (vals[i] > incrx_size) 1120 incrx_size = vals[i]; 1121 } 1122 } else { 1123 /* INCRX burst mode */ 1124 incrx_mode = INCRX_BURST_MODE; 1125 } 1126 1127 kfree(vals); 1128 1129 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */ 1130 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK; 1131 if (incrx_mode) 1132 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA; 1133 switch (incrx_size) { 1134 case 256: 1135 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA; 1136 break; 1137 case 128: 1138 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA; 1139 break; 1140 case 64: 1141 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA; 1142 break; 1143 case 32: 1144 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA; 1145 break; 1146 case 16: 1147 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA; 1148 break; 1149 case 8: 1150 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA; 1151 break; 1152 case 4: 1153 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA; 1154 break; 1155 case 1: 1156 break; 1157 default: 1158 dev_err(dev, "Invalid property\n"); 1159 break; 1160 } 1161 1162 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg); 1163 } 1164 1165 static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc) 1166 { 1167 u32 scale; 1168 u32 reg; 1169 1170 if (!dwc->susp_clk) 1171 return; 1172 1173 /* 1174 * The power down scale field specifies how many suspend_clk 1175 * periods fit into a 16KHz clock period. When performing 1176 * the division, round up the remainder. 1177 * 1178 * The power down scale value is calculated using the fastest 1179 * frequency of the suspend_clk. If it isn't fixed (but within 1180 * the accuracy requirement), the driver may not know the max 1181 * rate of the suspend_clk, so only update the power down scale 1182 * if the default is less than the calculated value from 1183 * clk_get_rate() or if the default is questionably high 1184 * (3x or more) to be within the requirement. 1185 */ 1186 scale = DIV_ROUND_UP(clk_get_rate(dwc->susp_clk), 16000); 1187 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 1188 if ((reg & DWC3_GCTL_PWRDNSCALE_MASK) < DWC3_GCTL_PWRDNSCALE(scale) || 1189 (reg & DWC3_GCTL_PWRDNSCALE_MASK) > DWC3_GCTL_PWRDNSCALE(scale*3)) { 1190 reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK); 1191 reg |= DWC3_GCTL_PWRDNSCALE(scale); 1192 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 1193 } 1194 } 1195 1196 static void dwc3_config_threshold(struct dwc3 *dwc) 1197 { 1198 u32 reg; 1199 u8 rx_thr_num; 1200 u8 rx_maxburst; 1201 u8 tx_thr_num; 1202 u8 tx_maxburst; 1203 1204 /* 1205 * Must config both number of packets and max burst settings to enable 1206 * RX and/or TX threshold. 1207 */ 1208 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) { 1209 rx_thr_num = dwc->rx_thr_num_pkt_prd; 1210 rx_maxburst = dwc->rx_max_burst_prd; 1211 tx_thr_num = dwc->tx_thr_num_pkt_prd; 1212 tx_maxburst = dwc->tx_max_burst_prd; 1213 1214 if (rx_thr_num && rx_maxburst) { 1215 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1216 reg |= DWC31_RXTHRNUMPKTSEL_PRD; 1217 1218 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0); 1219 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num); 1220 1221 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0); 1222 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst); 1223 1224 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1225 } 1226 1227 if (tx_thr_num && tx_maxburst) { 1228 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1229 reg |= DWC31_TXTHRNUMPKTSEL_PRD; 1230 1231 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0); 1232 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num); 1233 1234 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0); 1235 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst); 1236 1237 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1238 } 1239 } 1240 1241 rx_thr_num = dwc->rx_thr_num_pkt; 1242 rx_maxburst = dwc->rx_max_burst; 1243 tx_thr_num = dwc->tx_thr_num_pkt; 1244 tx_maxburst = dwc->tx_max_burst; 1245 1246 if (DWC3_IP_IS(DWC3)) { 1247 if (rx_thr_num && rx_maxburst) { 1248 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1249 reg |= DWC3_GRXTHRCFG_PKTCNTSEL; 1250 1251 reg &= ~DWC3_GRXTHRCFG_RXPKTCNT(~0); 1252 reg |= DWC3_GRXTHRCFG_RXPKTCNT(rx_thr_num); 1253 1254 reg &= ~DWC3_GRXTHRCFG_MAXRXBURSTSIZE(~0); 1255 reg |= DWC3_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst); 1256 1257 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1258 } 1259 1260 if (tx_thr_num && tx_maxburst) { 1261 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1262 reg |= DWC3_GTXTHRCFG_PKTCNTSEL; 1263 1264 reg &= ~DWC3_GTXTHRCFG_TXPKTCNT(~0); 1265 reg |= DWC3_GTXTHRCFG_TXPKTCNT(tx_thr_num); 1266 1267 reg &= ~DWC3_GTXTHRCFG_MAXTXBURSTSIZE(~0); 1268 reg |= DWC3_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst); 1269 1270 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1271 } 1272 } else { 1273 if (rx_thr_num && rx_maxburst) { 1274 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1275 reg |= DWC31_GRXTHRCFG_PKTCNTSEL; 1276 1277 reg &= ~DWC31_GRXTHRCFG_RXPKTCNT(~0); 1278 reg |= DWC31_GRXTHRCFG_RXPKTCNT(rx_thr_num); 1279 1280 reg &= ~DWC31_GRXTHRCFG_MAXRXBURSTSIZE(~0); 1281 reg |= DWC31_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst); 1282 1283 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1284 } 1285 1286 if (tx_thr_num && tx_maxburst) { 1287 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1288 reg |= DWC31_GTXTHRCFG_PKTCNTSEL; 1289 1290 reg &= ~DWC31_GTXTHRCFG_TXPKTCNT(~0); 1291 reg |= DWC31_GTXTHRCFG_TXPKTCNT(tx_thr_num); 1292 1293 reg &= ~DWC31_GTXTHRCFG_MAXTXBURSTSIZE(~0); 1294 reg |= DWC31_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst); 1295 1296 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1297 } 1298 } 1299 } 1300 1301 /** 1302 * dwc3_core_init - Low-level initialization of DWC3 Core 1303 * @dwc: Pointer to our controller context structure 1304 * 1305 * Returns 0 on success otherwise negative errno. 1306 */ 1307 static int dwc3_core_init(struct dwc3 *dwc) 1308 { 1309 unsigned int hw_mode; 1310 u32 reg; 1311 int ret; 1312 1313 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 1314 1315 /* 1316 * Write Linux Version Code to our GUID register so it's easy to figure 1317 * out which kernel version a bug was found. 1318 */ 1319 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); 1320 1321 ret = dwc3_phy_setup(dwc); 1322 if (ret) 1323 return ret; 1324 1325 if (!dwc->ulpi_ready) { 1326 ret = dwc3_core_ulpi_init(dwc); 1327 if (ret) { 1328 if (ret == -ETIMEDOUT) { 1329 dwc3_core_soft_reset(dwc); 1330 ret = -EPROBE_DEFER; 1331 } 1332 return ret; 1333 } 1334 dwc->ulpi_ready = true; 1335 } 1336 1337 if (!dwc->phys_ready) { 1338 ret = dwc3_core_get_phy(dwc); 1339 if (ret) 1340 goto err_exit_ulpi; 1341 dwc->phys_ready = true; 1342 } 1343 1344 ret = dwc3_phy_init(dwc); 1345 if (ret) 1346 goto err_exit_ulpi; 1347 1348 ret = dwc3_core_soft_reset(dwc); 1349 if (ret) 1350 goto err_exit_phy; 1351 1352 dwc3_core_setup_global_control(dwc); 1353 dwc3_core_num_eps(dwc); 1354 1355 /* Set power down scale of suspend_clk */ 1356 dwc3_set_power_down_clk_scale(dwc); 1357 1358 /* Adjust Frame Length */ 1359 dwc3_frame_length_adjustment(dwc); 1360 1361 /* Adjust Reference Clock Period */ 1362 dwc3_ref_clk_period(dwc); 1363 1364 dwc3_set_incr_burst_type(dwc); 1365 1366 dwc3_config_soc_bus(dwc); 1367 1368 ret = dwc3_phy_power_on(dwc); 1369 if (ret) 1370 goto err_exit_phy; 1371 1372 ret = dwc3_event_buffers_setup(dwc); 1373 if (ret) { 1374 dev_err(dwc->dev, "failed to setup event buffers\n"); 1375 goto err_power_off_phy; 1376 } 1377 1378 /* 1379 * ENDXFER polling is available on version 3.10a and later of 1380 * the DWC_usb3 controller. It is NOT available in the 1381 * DWC_usb31 controller. 1382 */ 1383 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) { 1384 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); 1385 reg |= DWC3_GUCTL2_RST_ACTBITLATER; 1386 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); 1387 } 1388 1389 /* 1390 * STAR 9001285599: This issue affects DWC_usb3 version 3.20a 1391 * only. If the PM TIMER ECM is enabled through GUCTL2[19], the 1392 * link compliance test (TD7.21) may fail. If the ECN is not 1393 * enabled (GUCTL2[19] = 0), the controller will use the old timer 1394 * value (5us), which is still acceptable for the link compliance 1395 * test. Therefore, do not enable PM TIMER ECM in 3.20a by 1396 * setting GUCTL2[19] by default; instead, use GUCTL2[19] = 0. 1397 */ 1398 if (DWC3_VER_IS(DWC3, 320A)) { 1399 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); 1400 reg &= ~DWC3_GUCTL2_LC_TIMER; 1401 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); 1402 } 1403 1404 /* 1405 * When configured in HOST mode, after issuing U3/L2 exit controller 1406 * fails to send proper CRC checksum in CRC5 feild. Because of this 1407 * behaviour Transaction Error is generated, resulting in reset and 1408 * re-enumeration of usb device attached. All the termsel, xcvrsel, 1409 * opmode becomes 0 during end of resume. Enabling bit 10 of GUCTL1 1410 * will correct this problem. This option is to support certain 1411 * legacy ULPI PHYs. 1412 */ 1413 if (dwc->resume_hs_terminations) { 1414 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 1415 reg |= DWC3_GUCTL1_RESUME_OPMODE_HS_HOST; 1416 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 1417 } 1418 1419 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) { 1420 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 1421 1422 /* 1423 * Enable hardware control of sending remote wakeup 1424 * in HS when the device is in the L1 state. 1425 */ 1426 if (!DWC3_VER_IS_PRIOR(DWC3, 290A)) 1427 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; 1428 1429 /* 1430 * Decouple USB 2.0 L1 & L2 events which will allow for 1431 * gadget driver to only receive U3/L2 suspend & wakeup 1432 * events and prevent the more frequent L1 LPM transitions 1433 * from interrupting the driver. 1434 */ 1435 if (!DWC3_VER_IS_PRIOR(DWC3, 300A)) 1436 reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT; 1437 1438 if (dwc->dis_tx_ipgap_linecheck_quirk) 1439 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; 1440 1441 if (dwc->parkmode_disable_ss_quirk) 1442 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS; 1443 1444 if (dwc->parkmode_disable_hs_quirk) 1445 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_HS; 1446 1447 if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY)) { 1448 if (dwc->maximum_speed == USB_SPEED_FULL || 1449 dwc->maximum_speed == USB_SPEED_HIGH) 1450 reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; 1451 else 1452 reg &= ~DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; 1453 } 1454 1455 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 1456 } 1457 1458 dwc3_config_threshold(dwc); 1459 1460 /* 1461 * Modify this for all supported Super Speed ports when 1462 * multiport support is added. 1463 */ 1464 if (hw_mode != DWC3_GHWPARAMS0_MODE_GADGET && 1465 (DWC3_IP_IS(DWC31)) && 1466 dwc->maximum_speed == USB_SPEED_SUPER) { 1467 reg = dwc3_readl(dwc->regs, DWC3_LLUCTL); 1468 reg |= DWC3_LLUCTL_FORCE_GEN1; 1469 dwc3_writel(dwc->regs, DWC3_LLUCTL, reg); 1470 } 1471 1472 return 0; 1473 1474 err_power_off_phy: 1475 dwc3_phy_power_off(dwc); 1476 err_exit_phy: 1477 dwc3_phy_exit(dwc); 1478 err_exit_ulpi: 1479 dwc3_ulpi_exit(dwc); 1480 1481 return ret; 1482 } 1483 1484 static int dwc3_core_get_phy(struct dwc3 *dwc) 1485 { 1486 struct device *dev = dwc->dev; 1487 struct device_node *node = dev->of_node; 1488 char phy_name[9]; 1489 int ret; 1490 u8 i; 1491 1492 if (node) { 1493 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); 1494 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); 1495 } else { 1496 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 1497 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); 1498 } 1499 1500 if (IS_ERR(dwc->usb2_phy)) { 1501 ret = PTR_ERR(dwc->usb2_phy); 1502 if (ret == -ENXIO || ret == -ENODEV) 1503 dwc->usb2_phy = NULL; 1504 else 1505 return dev_err_probe(dev, ret, "no usb2 phy configured\n"); 1506 } 1507 1508 if (IS_ERR(dwc->usb3_phy)) { 1509 ret = PTR_ERR(dwc->usb3_phy); 1510 if (ret == -ENXIO || ret == -ENODEV) 1511 dwc->usb3_phy = NULL; 1512 else 1513 return dev_err_probe(dev, ret, "no usb3 phy configured\n"); 1514 } 1515 1516 for (i = 0; i < dwc->num_usb2_ports; i++) { 1517 if (dwc->num_usb2_ports == 1) 1518 snprintf(phy_name, sizeof(phy_name), "usb2-phy"); 1519 else 1520 snprintf(phy_name, sizeof(phy_name), "usb2-%u", i); 1521 1522 dwc->usb2_generic_phy[i] = devm_phy_get(dev, phy_name); 1523 if (IS_ERR(dwc->usb2_generic_phy[i])) { 1524 ret = PTR_ERR(dwc->usb2_generic_phy[i]); 1525 if (ret == -ENOSYS || ret == -ENODEV) 1526 dwc->usb2_generic_phy[i] = NULL; 1527 else 1528 return dev_err_probe(dev, ret, "failed to lookup phy %s\n", 1529 phy_name); 1530 } 1531 } 1532 1533 for (i = 0; i < dwc->num_usb3_ports; i++) { 1534 if (dwc->num_usb3_ports == 1) 1535 snprintf(phy_name, sizeof(phy_name), "usb3-phy"); 1536 else 1537 snprintf(phy_name, sizeof(phy_name), "usb3-%u", i); 1538 1539 dwc->usb3_generic_phy[i] = devm_phy_get(dev, phy_name); 1540 if (IS_ERR(dwc->usb3_generic_phy[i])) { 1541 ret = PTR_ERR(dwc->usb3_generic_phy[i]); 1542 if (ret == -ENOSYS || ret == -ENODEV) 1543 dwc->usb3_generic_phy[i] = NULL; 1544 else 1545 return dev_err_probe(dev, ret, "failed to lookup phy %s\n", 1546 phy_name); 1547 } 1548 } 1549 1550 return 0; 1551 } 1552 1553 static int dwc3_core_init_mode(struct dwc3 *dwc) 1554 { 1555 struct device *dev = dwc->dev; 1556 int ret; 1557 int i; 1558 1559 switch (dwc->dr_mode) { 1560 case USB_DR_MODE_PERIPHERAL: 1561 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1562 1563 if (dwc->usb2_phy) 1564 otg_set_vbus(dwc->usb2_phy->otg, false); 1565 phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE); 1566 phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE); 1567 1568 ret = dwc3_gadget_init(dwc); 1569 if (ret) 1570 return dev_err_probe(dev, ret, "failed to initialize gadget\n"); 1571 break; 1572 case USB_DR_MODE_HOST: 1573 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1574 1575 if (dwc->usb2_phy) 1576 otg_set_vbus(dwc->usb2_phy->otg, true); 1577 for (i = 0; i < dwc->num_usb2_ports; i++) 1578 phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST); 1579 for (i = 0; i < dwc->num_usb3_ports; i++) 1580 phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST); 1581 1582 ret = dwc3_host_init(dwc); 1583 if (ret) 1584 return dev_err_probe(dev, ret, "failed to initialize host\n"); 1585 break; 1586 case USB_DR_MODE_OTG: 1587 INIT_WORK(&dwc->drd_work, __dwc3_set_mode); 1588 ret = dwc3_drd_init(dwc); 1589 if (ret) 1590 return dev_err_probe(dev, ret, "failed to initialize dual-role\n"); 1591 break; 1592 default: 1593 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 1594 return -EINVAL; 1595 } 1596 1597 return 0; 1598 } 1599 1600 static void dwc3_core_exit_mode(struct dwc3 *dwc) 1601 { 1602 switch (dwc->dr_mode) { 1603 case USB_DR_MODE_PERIPHERAL: 1604 dwc3_gadget_exit(dwc); 1605 break; 1606 case USB_DR_MODE_HOST: 1607 dwc3_host_exit(dwc); 1608 break; 1609 case USB_DR_MODE_OTG: 1610 dwc3_drd_exit(dwc); 1611 break; 1612 default: 1613 /* do nothing */ 1614 break; 1615 } 1616 1617 /* de-assert DRVVBUS for HOST and OTG mode */ 1618 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1619 } 1620 1621 static void dwc3_get_software_properties(struct dwc3 *dwc) 1622 { 1623 struct device *tmpdev; 1624 u16 gsbuscfg0_reqinfo; 1625 int ret; 1626 1627 dwc->gsbuscfg0_reqinfo = DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED; 1628 1629 /* 1630 * Iterate over all parent nodes for finding swnode properties 1631 * and non-DT (non-ABI) properties. 1632 */ 1633 for (tmpdev = dwc->dev; tmpdev; tmpdev = tmpdev->parent) { 1634 ret = device_property_read_u16(tmpdev, 1635 "snps,gsbuscfg0-reqinfo", 1636 &gsbuscfg0_reqinfo); 1637 if (!ret) 1638 dwc->gsbuscfg0_reqinfo = gsbuscfg0_reqinfo; 1639 } 1640 } 1641 1642 static void dwc3_get_properties(struct dwc3 *dwc) 1643 { 1644 struct device *dev = dwc->dev; 1645 u8 lpm_nyet_threshold; 1646 u8 tx_de_emphasis; 1647 u8 hird_threshold; 1648 u8 rx_thr_num_pkt = 0; 1649 u8 rx_max_burst = 0; 1650 u8 tx_thr_num_pkt = 0; 1651 u8 tx_max_burst = 0; 1652 u8 rx_thr_num_pkt_prd = 0; 1653 u8 rx_max_burst_prd = 0; 1654 u8 tx_thr_num_pkt_prd = 0; 1655 u8 tx_max_burst_prd = 0; 1656 u8 tx_fifo_resize_max_num; 1657 const char *usb_psy_name; 1658 int ret; 1659 1660 /* default to highest possible threshold */ 1661 lpm_nyet_threshold = 0xf; 1662 1663 /* default to -3.5dB de-emphasis */ 1664 tx_de_emphasis = 1; 1665 1666 /* 1667 * default to assert utmi_sleep_n and use maximum allowed HIRD 1668 * threshold value of 0b1100 1669 */ 1670 hird_threshold = 12; 1671 1672 /* 1673 * default to a TXFIFO size large enough to fit 6 max packets. This 1674 * allows for systems with larger bus latencies to have some headroom 1675 * for endpoints that have a large bMaxBurst value. 1676 */ 1677 tx_fifo_resize_max_num = 6; 1678 1679 dwc->maximum_speed = usb_get_maximum_speed(dev); 1680 dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev); 1681 dwc->dr_mode = usb_get_dr_mode(dev); 1682 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); 1683 1684 dwc->sysdev_is_parent = device_property_read_bool(dev, 1685 "linux,sysdev_is_parent"); 1686 if (dwc->sysdev_is_parent) 1687 dwc->sysdev = dwc->dev->parent; 1688 else 1689 dwc->sysdev = dwc->dev; 1690 1691 dwc->sys_wakeup = device_may_wakeup(dwc->sysdev); 1692 1693 ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name); 1694 if (ret >= 0) { 1695 dwc->usb_psy = power_supply_get_by_name(usb_psy_name); 1696 if (!dwc->usb_psy) 1697 dev_err(dev, "couldn't get usb power supply\n"); 1698 } 1699 1700 dwc->has_lpm_erratum = device_property_read_bool(dev, 1701 "snps,has-lpm-erratum"); 1702 device_property_read_u8(dev, "snps,lpm-nyet-threshold", 1703 &lpm_nyet_threshold); 1704 dwc->is_utmi_l1_suspend = device_property_read_bool(dev, 1705 "snps,is-utmi-l1-suspend"); 1706 device_property_read_u8(dev, "snps,hird-threshold", 1707 &hird_threshold); 1708 dwc->dis_start_transfer_quirk = device_property_read_bool(dev, 1709 "snps,dis-start-transfer-quirk"); 1710 dwc->usb3_lpm_capable = device_property_read_bool(dev, 1711 "snps,usb3_lpm_capable"); 1712 dwc->usb2_lpm_disable = device_property_read_bool(dev, 1713 "snps,usb2-lpm-disable"); 1714 dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev, 1715 "snps,usb2-gadget-lpm-disable"); 1716 device_property_read_u8(dev, "snps,rx-thr-num-pkt", 1717 &rx_thr_num_pkt); 1718 device_property_read_u8(dev, "snps,rx-max-burst", 1719 &rx_max_burst); 1720 device_property_read_u8(dev, "snps,tx-thr-num-pkt", 1721 &tx_thr_num_pkt); 1722 device_property_read_u8(dev, "snps,tx-max-burst", 1723 &tx_max_burst); 1724 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd", 1725 &rx_thr_num_pkt_prd); 1726 device_property_read_u8(dev, "snps,rx-max-burst-prd", 1727 &rx_max_burst_prd); 1728 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd", 1729 &tx_thr_num_pkt_prd); 1730 device_property_read_u8(dev, "snps,tx-max-burst-prd", 1731 &tx_max_burst_prd); 1732 dwc->do_fifo_resize = device_property_read_bool(dev, 1733 "tx-fifo-resize"); 1734 if (dwc->do_fifo_resize) 1735 device_property_read_u8(dev, "tx-fifo-max-num", 1736 &tx_fifo_resize_max_num); 1737 1738 dwc->disable_scramble_quirk = device_property_read_bool(dev, 1739 "snps,disable_scramble_quirk"); 1740 dwc->u2exit_lfps_quirk = device_property_read_bool(dev, 1741 "snps,u2exit_lfps_quirk"); 1742 dwc->u2ss_inp3_quirk = device_property_read_bool(dev, 1743 "snps,u2ss_inp3_quirk"); 1744 dwc->req_p1p2p3_quirk = device_property_read_bool(dev, 1745 "snps,req_p1p2p3_quirk"); 1746 dwc->del_p1p2p3_quirk = device_property_read_bool(dev, 1747 "snps,del_p1p2p3_quirk"); 1748 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, 1749 "snps,del_phy_power_chg_quirk"); 1750 dwc->lfps_filter_quirk = device_property_read_bool(dev, 1751 "snps,lfps_filter_quirk"); 1752 dwc->rx_detect_poll_quirk = device_property_read_bool(dev, 1753 "snps,rx_detect_poll_quirk"); 1754 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, 1755 "snps,dis_u3_susphy_quirk"); 1756 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, 1757 "snps,dis_u2_susphy_quirk"); 1758 dwc->dis_enblslpm_quirk = device_property_read_bool(dev, 1759 "snps,dis_enblslpm_quirk"); 1760 dwc->dis_u1_entry_quirk = device_property_read_bool(dev, 1761 "snps,dis-u1-entry-quirk"); 1762 dwc->dis_u2_entry_quirk = device_property_read_bool(dev, 1763 "snps,dis-u2-entry-quirk"); 1764 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, 1765 "snps,dis_rxdet_inp3_quirk"); 1766 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, 1767 "snps,dis-u2-freeclk-exists-quirk"); 1768 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, 1769 "snps,dis-del-phy-power-chg-quirk"); 1770 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev, 1771 "snps,dis-tx-ipgap-linecheck-quirk"); 1772 dwc->resume_hs_terminations = device_property_read_bool(dev, 1773 "snps,resume-hs-terminations"); 1774 dwc->ulpi_ext_vbus_drv = device_property_read_bool(dev, 1775 "snps,ulpi-ext-vbus-drv"); 1776 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev, 1777 "snps,parkmode-disable-ss-quirk"); 1778 dwc->parkmode_disable_hs_quirk = device_property_read_bool(dev, 1779 "snps,parkmode-disable-hs-quirk"); 1780 dwc->gfladj_refclk_lpm_sel = device_property_read_bool(dev, 1781 "snps,gfladj-refclk-lpm-sel-quirk"); 1782 1783 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, 1784 "snps,tx_de_emphasis_quirk"); 1785 device_property_read_u8(dev, "snps,tx_de_emphasis", 1786 &tx_de_emphasis); 1787 device_property_read_string(dev, "snps,hsphy_interface", 1788 &dwc->hsphy_interface); 1789 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", 1790 &dwc->fladj); 1791 device_property_read_u32(dev, "snps,ref-clock-period-ns", 1792 &dwc->ref_clk_per); 1793 1794 dwc->dis_metastability_quirk = device_property_read_bool(dev, 1795 "snps,dis_metastability_quirk"); 1796 1797 dwc->dis_split_quirk = device_property_read_bool(dev, 1798 "snps,dis-split-quirk"); 1799 1800 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 1801 dwc->tx_de_emphasis = tx_de_emphasis; 1802 1803 dwc->hird_threshold = hird_threshold; 1804 1805 dwc->rx_thr_num_pkt = rx_thr_num_pkt; 1806 dwc->rx_max_burst = rx_max_burst; 1807 1808 dwc->tx_thr_num_pkt = tx_thr_num_pkt; 1809 dwc->tx_max_burst = tx_max_burst; 1810 1811 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd; 1812 dwc->rx_max_burst_prd = rx_max_burst_prd; 1813 1814 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd; 1815 dwc->tx_max_burst_prd = tx_max_burst_prd; 1816 1817 dwc->imod_interval = 0; 1818 1819 dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num; 1820 } 1821 1822 /* check whether the core supports IMOD */ 1823 bool dwc3_has_imod(struct dwc3 *dwc) 1824 { 1825 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) || 1826 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) || 1827 DWC3_IP_IS(DWC32); 1828 } 1829 1830 static void dwc3_check_params(struct dwc3 *dwc) 1831 { 1832 struct device *dev = dwc->dev; 1833 unsigned int hwparam_gen = 1834 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3); 1835 1836 /* Check for proper value of imod_interval */ 1837 if (dwc->imod_interval && !dwc3_has_imod(dwc)) { 1838 dev_warn(dwc->dev, "Interrupt moderation not supported\n"); 1839 dwc->imod_interval = 0; 1840 } 1841 1842 /* 1843 * Workaround for STAR 9000961433 which affects only version 1844 * 3.00a of the DWC_usb3 core. This prevents the controller 1845 * interrupt from being masked while handling events. IMOD 1846 * allows us to work around this issue. Enable it for the 1847 * affected version. 1848 */ 1849 if (!dwc->imod_interval && 1850 DWC3_VER_IS(DWC3, 300A)) 1851 dwc->imod_interval = 1; 1852 1853 /* Check the maximum_speed parameter */ 1854 switch (dwc->maximum_speed) { 1855 case USB_SPEED_FULL: 1856 case USB_SPEED_HIGH: 1857 break; 1858 case USB_SPEED_SUPER: 1859 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) 1860 dev_warn(dev, "UDC doesn't support Gen 1\n"); 1861 break; 1862 case USB_SPEED_SUPER_PLUS: 1863 if ((DWC3_IP_IS(DWC32) && 1864 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) || 1865 (!DWC3_IP_IS(DWC32) && 1866 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) 1867 dev_warn(dev, "UDC doesn't support SSP\n"); 1868 break; 1869 default: 1870 dev_err(dev, "invalid maximum_speed parameter %d\n", 1871 dwc->maximum_speed); 1872 fallthrough; 1873 case USB_SPEED_UNKNOWN: 1874 switch (hwparam_gen) { 1875 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 1876 dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1877 break; 1878 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 1879 if (DWC3_IP_IS(DWC32)) 1880 dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1881 else 1882 dwc->maximum_speed = USB_SPEED_SUPER; 1883 break; 1884 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS: 1885 dwc->maximum_speed = USB_SPEED_HIGH; 1886 break; 1887 default: 1888 dwc->maximum_speed = USB_SPEED_SUPER; 1889 break; 1890 } 1891 break; 1892 } 1893 1894 /* 1895 * Currently the controller does not have visibility into the HW 1896 * parameter to determine the maximum number of lanes the HW supports. 1897 * If the number of lanes is not specified in the device property, then 1898 * set the default to support dual-lane for DWC_usb32 and single-lane 1899 * for DWC_usb31 for super-speed-plus. 1900 */ 1901 if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) { 1902 switch (dwc->max_ssp_rate) { 1903 case USB_SSP_GEN_2x1: 1904 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1) 1905 dev_warn(dev, "UDC only supports Gen 1\n"); 1906 break; 1907 case USB_SSP_GEN_1x2: 1908 case USB_SSP_GEN_2x2: 1909 if (DWC3_IP_IS(DWC31)) 1910 dev_warn(dev, "UDC only supports single lane\n"); 1911 break; 1912 case USB_SSP_GEN_UNKNOWN: 1913 default: 1914 switch (hwparam_gen) { 1915 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 1916 if (DWC3_IP_IS(DWC32)) 1917 dwc->max_ssp_rate = USB_SSP_GEN_2x2; 1918 else 1919 dwc->max_ssp_rate = USB_SSP_GEN_2x1; 1920 break; 1921 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 1922 if (DWC3_IP_IS(DWC32)) 1923 dwc->max_ssp_rate = USB_SSP_GEN_1x2; 1924 break; 1925 } 1926 break; 1927 } 1928 } 1929 } 1930 1931 static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc) 1932 { 1933 struct device *dev = dwc->dev; 1934 struct device_node *np_phy; 1935 struct extcon_dev *edev = NULL; 1936 const char *name; 1937 1938 if (device_property_read_bool(dev, "extcon")) 1939 return extcon_get_edev_by_phandle(dev, 0); 1940 1941 /* 1942 * Device tree platforms should get extcon via phandle. 1943 * On ACPI platforms, we get the name from a device property. 1944 * This device property is for kernel internal use only and 1945 * is expected to be set by the glue code. 1946 */ 1947 if (device_property_read_string(dev, "linux,extcon-name", &name) == 0) 1948 return extcon_get_extcon_dev(name); 1949 1950 /* 1951 * Check explicitly if "usb-role-switch" is used since 1952 * extcon_find_edev_by_node() can not be used to check the absence of 1953 * an extcon device. In the absence of an device it will always return 1954 * EPROBE_DEFER. 1955 */ 1956 if (IS_ENABLED(CONFIG_USB_ROLE_SWITCH) && 1957 device_property_read_bool(dev, "usb-role-switch")) 1958 return NULL; 1959 1960 /* 1961 * Try to get an extcon device from the USB PHY controller's "port" 1962 * node. Check if it has the "port" node first, to avoid printing the 1963 * error message from underlying code, as it's a valid case: extcon 1964 * device (and "port" node) may be missing in case of "usb-role-switch" 1965 * or OTG mode. 1966 */ 1967 np_phy = of_parse_phandle(dev->of_node, "phys", 0); 1968 if (of_graph_is_present(np_phy)) { 1969 struct device_node *np_conn; 1970 1971 np_conn = of_graph_get_remote_node(np_phy, -1, -1); 1972 if (np_conn) 1973 edev = extcon_find_edev_by_node(np_conn); 1974 of_node_put(np_conn); 1975 } 1976 of_node_put(np_phy); 1977 1978 return edev; 1979 } 1980 1981 static int dwc3_get_clocks(struct dwc3 *dwc) 1982 { 1983 struct device *dev = dwc->dev; 1984 1985 if (!dev->of_node) 1986 return 0; 1987 1988 /* 1989 * Clocks are optional, but new DT platforms should support all clocks 1990 * as required by the DT-binding. 1991 * Some devices have different clock names in legacy device trees, 1992 * check for them to retain backwards compatibility. 1993 */ 1994 dwc->bus_clk = devm_clk_get_optional(dev, "bus_early"); 1995 if (IS_ERR(dwc->bus_clk)) { 1996 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk), 1997 "could not get bus clock\n"); 1998 } 1999 2000 if (dwc->bus_clk == NULL) { 2001 dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk"); 2002 if (IS_ERR(dwc->bus_clk)) { 2003 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk), 2004 "could not get bus clock\n"); 2005 } 2006 } 2007 2008 dwc->ref_clk = devm_clk_get_optional(dev, "ref"); 2009 if (IS_ERR(dwc->ref_clk)) { 2010 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk), 2011 "could not get ref clock\n"); 2012 } 2013 2014 if (dwc->ref_clk == NULL) { 2015 dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk"); 2016 if (IS_ERR(dwc->ref_clk)) { 2017 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk), 2018 "could not get ref clock\n"); 2019 } 2020 } 2021 2022 dwc->susp_clk = devm_clk_get_optional(dev, "suspend"); 2023 if (IS_ERR(dwc->susp_clk)) { 2024 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk), 2025 "could not get suspend clock\n"); 2026 } 2027 2028 if (dwc->susp_clk == NULL) { 2029 dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk"); 2030 if (IS_ERR(dwc->susp_clk)) { 2031 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk), 2032 "could not get suspend clock\n"); 2033 } 2034 } 2035 2036 /* specific to Rockchip RK3588 */ 2037 dwc->utmi_clk = devm_clk_get_optional(dev, "utmi"); 2038 if (IS_ERR(dwc->utmi_clk)) { 2039 return dev_err_probe(dev, PTR_ERR(dwc->utmi_clk), 2040 "could not get utmi clock\n"); 2041 } 2042 2043 /* specific to Rockchip RK3588 */ 2044 dwc->pipe_clk = devm_clk_get_optional(dev, "pipe"); 2045 if (IS_ERR(dwc->pipe_clk)) { 2046 return dev_err_probe(dev, PTR_ERR(dwc->pipe_clk), 2047 "could not get pipe clock\n"); 2048 } 2049 2050 return 0; 2051 } 2052 2053 static int dwc3_get_num_ports(struct dwc3 *dwc) 2054 { 2055 void __iomem *base; 2056 u8 major_revision; 2057 u32 offset; 2058 u32 val; 2059 2060 /* 2061 * Remap xHCI address space to access XHCI ext cap regs since it is 2062 * needed to get information on number of ports present. 2063 */ 2064 base = ioremap(dwc->xhci_resources[0].start, 2065 resource_size(&dwc->xhci_resources[0])); 2066 if (!base) 2067 return -ENOMEM; 2068 2069 offset = 0; 2070 do { 2071 offset = xhci_find_next_ext_cap(base, offset, 2072 XHCI_EXT_CAPS_PROTOCOL); 2073 if (!offset) 2074 break; 2075 2076 val = readl(base + offset); 2077 major_revision = XHCI_EXT_PORT_MAJOR(val); 2078 2079 val = readl(base + offset + 0x08); 2080 if (major_revision == 0x03) { 2081 dwc->num_usb3_ports += XHCI_EXT_PORT_COUNT(val); 2082 } else if (major_revision <= 0x02) { 2083 dwc->num_usb2_ports += XHCI_EXT_PORT_COUNT(val); 2084 } else { 2085 dev_warn(dwc->dev, "unrecognized port major revision %d\n", 2086 major_revision); 2087 } 2088 } while (1); 2089 2090 dev_dbg(dwc->dev, "hs-ports: %u ss-ports: %u\n", 2091 dwc->num_usb2_ports, dwc->num_usb3_ports); 2092 2093 iounmap(base); 2094 2095 if (dwc->num_usb2_ports > DWC3_USB2_MAX_PORTS || 2096 dwc->num_usb3_ports > DWC3_USB3_MAX_PORTS) 2097 return -EINVAL; 2098 2099 return 0; 2100 } 2101 2102 static int dwc3_probe(struct platform_device *pdev) 2103 { 2104 struct device *dev = &pdev->dev; 2105 struct resource *res, dwc_res; 2106 unsigned int hw_mode; 2107 void __iomem *regs; 2108 struct dwc3 *dwc; 2109 int ret; 2110 2111 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 2112 if (!dwc) 2113 return -ENOMEM; 2114 2115 dwc->dev = dev; 2116 2117 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2118 if (!res) { 2119 dev_err(dev, "missing memory resource\n"); 2120 return -ENODEV; 2121 } 2122 2123 dwc->xhci_resources[0].start = res->start; 2124 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + 2125 DWC3_XHCI_REGS_END; 2126 dwc->xhci_resources[0].flags = res->flags; 2127 dwc->xhci_resources[0].name = res->name; 2128 2129 /* 2130 * Request memory region but exclude xHCI regs, 2131 * since it will be requested by the xhci-plat driver. 2132 */ 2133 dwc_res = *res; 2134 dwc_res.start += DWC3_GLOBALS_REGS_START; 2135 2136 if (dev->of_node) { 2137 struct device_node *parent = of_get_parent(dev->of_node); 2138 2139 if (of_device_is_compatible(parent, "realtek,rtd-dwc3")) { 2140 dwc_res.start -= DWC3_GLOBALS_REGS_START; 2141 dwc_res.start += DWC3_RTK_RTD_GLOBALS_REGS_START; 2142 } 2143 2144 of_node_put(parent); 2145 } 2146 2147 regs = devm_ioremap_resource(dev, &dwc_res); 2148 if (IS_ERR(regs)) 2149 return PTR_ERR(regs); 2150 2151 dwc->regs = regs; 2152 dwc->regs_size = resource_size(&dwc_res); 2153 2154 dwc3_get_properties(dwc); 2155 2156 dwc3_get_software_properties(dwc); 2157 2158 dwc->reset = devm_reset_control_array_get_optional_shared(dev); 2159 if (IS_ERR(dwc->reset)) { 2160 ret = PTR_ERR(dwc->reset); 2161 goto err_put_psy; 2162 } 2163 2164 ret = dwc3_get_clocks(dwc); 2165 if (ret) 2166 goto err_put_psy; 2167 2168 ret = reset_control_deassert(dwc->reset); 2169 if (ret) 2170 goto err_put_psy; 2171 2172 ret = dwc3_clk_enable(dwc); 2173 if (ret) 2174 goto err_assert_reset; 2175 2176 if (!dwc3_core_is_valid(dwc)) { 2177 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 2178 ret = -ENODEV; 2179 goto err_disable_clks; 2180 } 2181 2182 platform_set_drvdata(pdev, dwc); 2183 dwc3_cache_hwparams(dwc); 2184 2185 if (!dwc->sysdev_is_parent && 2186 DWC3_GHWPARAMS0_AWIDTH(dwc->hwparams.hwparams0) == 64) { 2187 ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64)); 2188 if (ret) 2189 goto err_disable_clks; 2190 } 2191 2192 /* 2193 * Currently only DWC3 controllers that are host-only capable 2194 * can have more than one port. 2195 */ 2196 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 2197 if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) { 2198 ret = dwc3_get_num_ports(dwc); 2199 if (ret) 2200 goto err_disable_clks; 2201 } else { 2202 dwc->num_usb2_ports = 1; 2203 dwc->num_usb3_ports = 1; 2204 } 2205 2206 spin_lock_init(&dwc->lock); 2207 mutex_init(&dwc->mutex); 2208 2209 pm_runtime_get_noresume(dev); 2210 pm_runtime_set_active(dev); 2211 pm_runtime_use_autosuspend(dev); 2212 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); 2213 pm_runtime_enable(dev); 2214 2215 pm_runtime_forbid(dev); 2216 2217 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 2218 if (ret) { 2219 dev_err(dwc->dev, "failed to allocate event buffers\n"); 2220 ret = -ENOMEM; 2221 goto err_allow_rpm; 2222 } 2223 2224 dwc->edev = dwc3_get_extcon(dwc); 2225 if (IS_ERR(dwc->edev)) { 2226 ret = dev_err_probe(dwc->dev, PTR_ERR(dwc->edev), "failed to get extcon\n"); 2227 goto err_free_event_buffers; 2228 } 2229 2230 ret = dwc3_get_dr_mode(dwc); 2231 if (ret) 2232 goto err_free_event_buffers; 2233 2234 ret = dwc3_core_init(dwc); 2235 if (ret) { 2236 dev_err_probe(dev, ret, "failed to initialize core\n"); 2237 goto err_free_event_buffers; 2238 } 2239 2240 dwc3_check_params(dwc); 2241 dwc3_debugfs_init(dwc); 2242 2243 ret = dwc3_core_init_mode(dwc); 2244 if (ret) 2245 goto err_exit_debugfs; 2246 2247 pm_runtime_put(dev); 2248 2249 dma_set_max_seg_size(dev, UINT_MAX); 2250 2251 return 0; 2252 2253 err_exit_debugfs: 2254 dwc3_debugfs_exit(dwc); 2255 dwc3_event_buffers_cleanup(dwc); 2256 dwc3_phy_power_off(dwc); 2257 dwc3_phy_exit(dwc); 2258 dwc3_ulpi_exit(dwc); 2259 err_free_event_buffers: 2260 dwc3_free_event_buffers(dwc); 2261 err_allow_rpm: 2262 pm_runtime_allow(dev); 2263 pm_runtime_disable(dev); 2264 pm_runtime_dont_use_autosuspend(dev); 2265 pm_runtime_set_suspended(dev); 2266 pm_runtime_put_noidle(dev); 2267 err_disable_clks: 2268 dwc3_clk_disable(dwc); 2269 err_assert_reset: 2270 reset_control_assert(dwc->reset); 2271 err_put_psy: 2272 if (dwc->usb_psy) 2273 power_supply_put(dwc->usb_psy); 2274 2275 return ret; 2276 } 2277 2278 static void dwc3_remove(struct platform_device *pdev) 2279 { 2280 struct dwc3 *dwc = platform_get_drvdata(pdev); 2281 2282 pm_runtime_get_sync(&pdev->dev); 2283 2284 dwc3_core_exit_mode(dwc); 2285 dwc3_debugfs_exit(dwc); 2286 2287 dwc3_core_exit(dwc); 2288 dwc3_ulpi_exit(dwc); 2289 2290 pm_runtime_allow(&pdev->dev); 2291 pm_runtime_disable(&pdev->dev); 2292 pm_runtime_dont_use_autosuspend(&pdev->dev); 2293 pm_runtime_put_noidle(&pdev->dev); 2294 /* 2295 * HACK: Clear the driver data, which is currently accessed by parent 2296 * glue drivers, before allowing the parent to suspend. 2297 */ 2298 platform_set_drvdata(pdev, NULL); 2299 pm_runtime_set_suspended(&pdev->dev); 2300 2301 dwc3_free_event_buffers(dwc); 2302 2303 if (dwc->usb_psy) 2304 power_supply_put(dwc->usb_psy); 2305 } 2306 2307 #ifdef CONFIG_PM 2308 static int dwc3_core_init_for_resume(struct dwc3 *dwc) 2309 { 2310 int ret; 2311 2312 ret = reset_control_deassert(dwc->reset); 2313 if (ret) 2314 return ret; 2315 2316 ret = dwc3_clk_enable(dwc); 2317 if (ret) 2318 goto assert_reset; 2319 2320 ret = dwc3_core_init(dwc); 2321 if (ret) 2322 goto disable_clks; 2323 2324 return 0; 2325 2326 disable_clks: 2327 dwc3_clk_disable(dwc); 2328 assert_reset: 2329 reset_control_assert(dwc->reset); 2330 2331 return ret; 2332 } 2333 2334 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) 2335 { 2336 u32 reg; 2337 int i; 2338 2339 switch (dwc->current_dr_role) { 2340 case DWC3_GCTL_PRTCAP_DEVICE: 2341 if (pm_runtime_suspended(dwc->dev)) 2342 break; 2343 dwc3_gadget_suspend(dwc); 2344 synchronize_irq(dwc->irq_gadget); 2345 dwc3_core_exit(dwc); 2346 break; 2347 case DWC3_GCTL_PRTCAP_HOST: 2348 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) { 2349 dwc3_core_exit(dwc); 2350 break; 2351 } 2352 2353 /* Let controller to suspend HSPHY before PHY driver suspends */ 2354 if (dwc->dis_u2_susphy_quirk || 2355 dwc->dis_enblslpm_quirk) { 2356 for (i = 0; i < dwc->num_usb2_ports; i++) { 2357 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i)); 2358 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM | 2359 DWC3_GUSB2PHYCFG_SUSPHY; 2360 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg); 2361 } 2362 2363 /* Give some time for USB2 PHY to suspend */ 2364 usleep_range(5000, 6000); 2365 } 2366 2367 for (i = 0; i < dwc->num_usb2_ports; i++) 2368 phy_pm_runtime_put_sync(dwc->usb2_generic_phy[i]); 2369 for (i = 0; i < dwc->num_usb3_ports; i++) 2370 phy_pm_runtime_put_sync(dwc->usb3_generic_phy[i]); 2371 break; 2372 case DWC3_GCTL_PRTCAP_OTG: 2373 /* do nothing during runtime_suspend */ 2374 if (PMSG_IS_AUTO(msg)) 2375 break; 2376 2377 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 2378 dwc3_gadget_suspend(dwc); 2379 synchronize_irq(dwc->irq_gadget); 2380 } 2381 2382 dwc3_otg_exit(dwc); 2383 dwc3_core_exit(dwc); 2384 break; 2385 default: 2386 /* do nothing */ 2387 break; 2388 } 2389 2390 return 0; 2391 } 2392 2393 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) 2394 { 2395 int ret; 2396 u32 reg; 2397 int i; 2398 2399 switch (dwc->current_dr_role) { 2400 case DWC3_GCTL_PRTCAP_DEVICE: 2401 ret = dwc3_core_init_for_resume(dwc); 2402 if (ret) 2403 return ret; 2404 2405 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 2406 dwc3_gadget_resume(dwc); 2407 break; 2408 case DWC3_GCTL_PRTCAP_HOST: 2409 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) { 2410 ret = dwc3_core_init_for_resume(dwc); 2411 if (ret) 2412 return ret; 2413 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 2414 break; 2415 } 2416 /* Restore GUSB2PHYCFG bits that were modified in suspend */ 2417 for (i = 0; i < dwc->num_usb2_ports; i++) { 2418 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i)); 2419 if (dwc->dis_u2_susphy_quirk) 2420 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 2421 2422 if (dwc->dis_enblslpm_quirk) 2423 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 2424 2425 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg); 2426 } 2427 2428 for (i = 0; i < dwc->num_usb2_ports; i++) 2429 phy_pm_runtime_get_sync(dwc->usb2_generic_phy[i]); 2430 for (i = 0; i < dwc->num_usb3_ports; i++) 2431 phy_pm_runtime_get_sync(dwc->usb3_generic_phy[i]); 2432 break; 2433 case DWC3_GCTL_PRTCAP_OTG: 2434 /* nothing to do on runtime_resume */ 2435 if (PMSG_IS_AUTO(msg)) 2436 break; 2437 2438 ret = dwc3_core_init_for_resume(dwc); 2439 if (ret) 2440 return ret; 2441 2442 dwc3_set_prtcap(dwc, dwc->current_dr_role); 2443 2444 dwc3_otg_init(dwc); 2445 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) { 2446 dwc3_otg_host_init(dwc); 2447 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 2448 dwc3_gadget_resume(dwc); 2449 } 2450 2451 break; 2452 default: 2453 /* do nothing */ 2454 break; 2455 } 2456 2457 return 0; 2458 } 2459 2460 static int dwc3_runtime_checks(struct dwc3 *dwc) 2461 { 2462 switch (dwc->current_dr_role) { 2463 case DWC3_GCTL_PRTCAP_DEVICE: 2464 if (dwc->connected) 2465 return -EBUSY; 2466 break; 2467 case DWC3_GCTL_PRTCAP_HOST: 2468 default: 2469 /* do nothing */ 2470 break; 2471 } 2472 2473 return 0; 2474 } 2475 2476 static int dwc3_runtime_suspend(struct device *dev) 2477 { 2478 struct dwc3 *dwc = dev_get_drvdata(dev); 2479 int ret; 2480 2481 if (dwc3_runtime_checks(dwc)) 2482 return -EBUSY; 2483 2484 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND); 2485 if (ret) 2486 return ret; 2487 2488 return 0; 2489 } 2490 2491 static int dwc3_runtime_resume(struct device *dev) 2492 { 2493 struct dwc3 *dwc = dev_get_drvdata(dev); 2494 int ret; 2495 2496 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME); 2497 if (ret) 2498 return ret; 2499 2500 switch (dwc->current_dr_role) { 2501 case DWC3_GCTL_PRTCAP_DEVICE: 2502 dwc3_gadget_process_pending_events(dwc); 2503 break; 2504 case DWC3_GCTL_PRTCAP_HOST: 2505 default: 2506 /* do nothing */ 2507 break; 2508 } 2509 2510 pm_runtime_mark_last_busy(dev); 2511 2512 return 0; 2513 } 2514 2515 static int dwc3_runtime_idle(struct device *dev) 2516 { 2517 struct dwc3 *dwc = dev_get_drvdata(dev); 2518 2519 switch (dwc->current_dr_role) { 2520 case DWC3_GCTL_PRTCAP_DEVICE: 2521 if (dwc3_runtime_checks(dwc)) 2522 return -EBUSY; 2523 break; 2524 case DWC3_GCTL_PRTCAP_HOST: 2525 default: 2526 /* do nothing */ 2527 break; 2528 } 2529 2530 pm_runtime_mark_last_busy(dev); 2531 pm_runtime_autosuspend(dev); 2532 2533 return 0; 2534 } 2535 #endif /* CONFIG_PM */ 2536 2537 #ifdef CONFIG_PM_SLEEP 2538 static int dwc3_suspend(struct device *dev) 2539 { 2540 struct dwc3 *dwc = dev_get_drvdata(dev); 2541 int ret; 2542 2543 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND); 2544 if (ret) 2545 return ret; 2546 2547 pinctrl_pm_select_sleep_state(dev); 2548 2549 return 0; 2550 } 2551 2552 static int dwc3_resume(struct device *dev) 2553 { 2554 struct dwc3 *dwc = dev_get_drvdata(dev); 2555 int ret; 2556 2557 pinctrl_pm_select_default_state(dev); 2558 2559 pm_runtime_disable(dev); 2560 pm_runtime_set_active(dev); 2561 2562 ret = dwc3_resume_common(dwc, PMSG_RESUME); 2563 if (ret) { 2564 pm_runtime_set_suspended(dev); 2565 return ret; 2566 } 2567 2568 pm_runtime_enable(dev); 2569 2570 return 0; 2571 } 2572 2573 static void dwc3_complete(struct device *dev) 2574 { 2575 struct dwc3 *dwc = dev_get_drvdata(dev); 2576 u32 reg; 2577 2578 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST && 2579 dwc->dis_split_quirk) { 2580 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 2581 reg |= DWC3_GUCTL3_SPLITDISABLE; 2582 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 2583 } 2584 } 2585 #else 2586 #define dwc3_complete NULL 2587 #endif /* CONFIG_PM_SLEEP */ 2588 2589 static const struct dev_pm_ops dwc3_dev_pm_ops = { 2590 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) 2591 .complete = dwc3_complete, 2592 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, 2593 dwc3_runtime_idle) 2594 }; 2595 2596 #ifdef CONFIG_OF 2597 static const struct of_device_id of_dwc3_match[] = { 2598 { 2599 .compatible = "snps,dwc3" 2600 }, 2601 { 2602 .compatible = "synopsys,dwc3" 2603 }, 2604 { }, 2605 }; 2606 MODULE_DEVICE_TABLE(of, of_dwc3_match); 2607 #endif 2608 2609 #ifdef CONFIG_ACPI 2610 2611 #define ACPI_ID_INTEL_BSW "808622B7" 2612 2613 static const struct acpi_device_id dwc3_acpi_match[] = { 2614 { ACPI_ID_INTEL_BSW, 0 }, 2615 { }, 2616 }; 2617 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); 2618 #endif 2619 2620 static struct platform_driver dwc3_driver = { 2621 .probe = dwc3_probe, 2622 .remove_new = dwc3_remove, 2623 .driver = { 2624 .name = "dwc3", 2625 .of_match_table = of_match_ptr(of_dwc3_match), 2626 .acpi_match_table = ACPI_PTR(dwc3_acpi_match), 2627 .pm = &dwc3_dev_pm_ops, 2628 }, 2629 }; 2630 2631 module_platform_driver(dwc3_driver); 2632 2633 MODULE_ALIAS("platform:dwc3"); 2634 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 2635 MODULE_LICENSE("GPL v2"); 2636 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 2637