1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * core.c - DesignWare USB3 DRD Controller Core file 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/version.h> 13 #include <linux/module.h> 14 #include <linux/kernel.h> 15 #include <linux/slab.h> 16 #include <linux/spinlock.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/interrupt.h> 20 #include <linux/ioport.h> 21 #include <linux/io.h> 22 #include <linux/list.h> 23 #include <linux/delay.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/of.h> 26 #include <linux/of_graph.h> 27 #include <linux/acpi.h> 28 #include <linux/pinctrl/consumer.h> 29 #include <linux/reset.h> 30 #include <linux/bitfield.h> 31 32 #include <linux/usb/ch9.h> 33 #include <linux/usb/gadget.h> 34 #include <linux/usb/of.h> 35 #include <linux/usb/otg.h> 36 37 #include "core.h" 38 #include "gadget.h" 39 #include "io.h" 40 41 #include "debug.h" 42 #include "../host/xhci-ext-caps.h" 43 44 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ 45 46 /** 47 * dwc3_get_dr_mode - Validates and sets dr_mode 48 * @dwc: pointer to our context structure 49 */ 50 static int dwc3_get_dr_mode(struct dwc3 *dwc) 51 { 52 enum usb_dr_mode mode; 53 struct device *dev = dwc->dev; 54 unsigned int hw_mode; 55 56 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 57 dwc->dr_mode = USB_DR_MODE_OTG; 58 59 mode = dwc->dr_mode; 60 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 61 62 switch (hw_mode) { 63 case DWC3_GHWPARAMS0_MODE_GADGET: 64 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) { 65 dev_err(dev, 66 "Controller does not support host mode.\n"); 67 return -EINVAL; 68 } 69 mode = USB_DR_MODE_PERIPHERAL; 70 break; 71 case DWC3_GHWPARAMS0_MODE_HOST: 72 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { 73 dev_err(dev, 74 "Controller does not support device mode.\n"); 75 return -EINVAL; 76 } 77 mode = USB_DR_MODE_HOST; 78 break; 79 default: 80 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 81 mode = USB_DR_MODE_HOST; 82 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 83 mode = USB_DR_MODE_PERIPHERAL; 84 85 /* 86 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG 87 * mode. If the controller supports DRD but the dr_mode is not 88 * specified or set to OTG, then set the mode to peripheral. 89 */ 90 if (mode == USB_DR_MODE_OTG && !dwc->edev && 91 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) || 92 !device_property_read_bool(dwc->dev, "usb-role-switch")) && 93 !DWC3_VER_IS_PRIOR(DWC3, 330A)) 94 mode = USB_DR_MODE_PERIPHERAL; 95 } 96 97 if (mode != dwc->dr_mode) { 98 dev_warn(dev, 99 "Configuration mismatch. dr_mode forced to %s\n", 100 mode == USB_DR_MODE_HOST ? "host" : "gadget"); 101 102 dwc->dr_mode = mode; 103 } 104 105 return 0; 106 } 107 108 void dwc3_enable_susphy(struct dwc3 *dwc, bool enable) 109 { 110 u32 reg; 111 112 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 113 if (enable && !dwc->dis_u3_susphy_quirk) 114 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 115 else 116 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 117 118 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 119 120 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 121 if (enable && !dwc->dis_u2_susphy_quirk) 122 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 123 else 124 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 125 126 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 127 } 128 129 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) 130 { 131 u32 reg; 132 133 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 134 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 135 reg |= DWC3_GCTL_PRTCAPDIR(mode); 136 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 137 138 dwc->current_dr_role = mode; 139 } 140 141 static void __dwc3_set_mode(struct work_struct *work) 142 { 143 struct dwc3 *dwc = work_to_dwc(work); 144 unsigned long flags; 145 int ret; 146 u32 reg; 147 u32 desired_dr_role; 148 int i; 149 150 mutex_lock(&dwc->mutex); 151 spin_lock_irqsave(&dwc->lock, flags); 152 desired_dr_role = dwc->desired_dr_role; 153 spin_unlock_irqrestore(&dwc->lock, flags); 154 155 pm_runtime_get_sync(dwc->dev); 156 157 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG) 158 dwc3_otg_update(dwc, 0); 159 160 if (!desired_dr_role) 161 goto out; 162 163 if (desired_dr_role == dwc->current_dr_role) 164 goto out; 165 166 if (desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev) 167 goto out; 168 169 switch (dwc->current_dr_role) { 170 case DWC3_GCTL_PRTCAP_HOST: 171 dwc3_host_exit(dwc); 172 break; 173 case DWC3_GCTL_PRTCAP_DEVICE: 174 dwc3_gadget_exit(dwc); 175 dwc3_event_buffers_cleanup(dwc); 176 break; 177 case DWC3_GCTL_PRTCAP_OTG: 178 dwc3_otg_exit(dwc); 179 spin_lock_irqsave(&dwc->lock, flags); 180 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE; 181 spin_unlock_irqrestore(&dwc->lock, flags); 182 dwc3_otg_update(dwc, 1); 183 break; 184 default: 185 break; 186 } 187 188 /* 189 * When current_dr_role is not set, there's no role switching. 190 * Only perform GCTL.CoreSoftReset when there's DRD role switching. 191 */ 192 if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) || 193 DWC3_VER_IS_PRIOR(DWC31, 190A)) && 194 desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) { 195 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 196 reg |= DWC3_GCTL_CORESOFTRESET; 197 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 198 199 /* 200 * Wait for internal clocks to synchronized. DWC_usb31 and 201 * DWC_usb32 may need at least 50ms (less for DWC_usb3). To 202 * keep it consistent across different IPs, let's wait up to 203 * 100ms before clearing GCTL.CORESOFTRESET. 204 */ 205 msleep(100); 206 207 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 208 reg &= ~DWC3_GCTL_CORESOFTRESET; 209 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 210 } 211 212 spin_lock_irqsave(&dwc->lock, flags); 213 214 dwc3_set_prtcap(dwc, desired_dr_role); 215 216 spin_unlock_irqrestore(&dwc->lock, flags); 217 218 switch (desired_dr_role) { 219 case DWC3_GCTL_PRTCAP_HOST: 220 ret = dwc3_host_init(dwc); 221 if (ret) { 222 dev_err(dwc->dev, "failed to initialize host\n"); 223 } else { 224 if (dwc->usb2_phy) 225 otg_set_vbus(dwc->usb2_phy->otg, true); 226 227 for (i = 0; i < dwc->num_usb2_ports; i++) 228 phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST); 229 for (i = 0; i < dwc->num_usb3_ports; i++) 230 phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST); 231 232 if (dwc->dis_split_quirk) { 233 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 234 reg |= DWC3_GUCTL3_SPLITDISABLE; 235 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 236 } 237 } 238 break; 239 case DWC3_GCTL_PRTCAP_DEVICE: 240 dwc3_core_soft_reset(dwc); 241 242 dwc3_event_buffers_setup(dwc); 243 244 if (dwc->usb2_phy) 245 otg_set_vbus(dwc->usb2_phy->otg, false); 246 phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE); 247 phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE); 248 249 ret = dwc3_gadget_init(dwc); 250 if (ret) 251 dev_err(dwc->dev, "failed to initialize peripheral\n"); 252 break; 253 case DWC3_GCTL_PRTCAP_OTG: 254 dwc3_otg_init(dwc); 255 dwc3_otg_update(dwc, 0); 256 break; 257 default: 258 break; 259 } 260 261 out: 262 pm_runtime_mark_last_busy(dwc->dev); 263 pm_runtime_put_autosuspend(dwc->dev); 264 mutex_unlock(&dwc->mutex); 265 } 266 267 void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 268 { 269 unsigned long flags; 270 271 if (dwc->dr_mode != USB_DR_MODE_OTG) 272 return; 273 274 spin_lock_irqsave(&dwc->lock, flags); 275 dwc->desired_dr_role = mode; 276 spin_unlock_irqrestore(&dwc->lock, flags); 277 278 queue_work(system_freezable_wq, &dwc->drd_work); 279 } 280 281 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) 282 { 283 struct dwc3 *dwc = dep->dwc; 284 u32 reg; 285 286 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, 287 DWC3_GDBGFIFOSPACE_NUM(dep->number) | 288 DWC3_GDBGFIFOSPACE_TYPE(type)); 289 290 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); 291 292 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); 293 } 294 295 /** 296 * dwc3_core_soft_reset - Issues core soft reset and PHY reset 297 * @dwc: pointer to our context structure 298 */ 299 int dwc3_core_soft_reset(struct dwc3 *dwc) 300 { 301 u32 reg; 302 int retries = 1000; 303 304 /* 305 * We're resetting only the device side because, if we're in host mode, 306 * XHCI driver will reset the host block. If dwc3 was configured for 307 * host-only mode, then we can return early. 308 */ 309 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) 310 return 0; 311 312 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 313 reg |= DWC3_DCTL_CSFTRST; 314 reg &= ~DWC3_DCTL_RUN_STOP; 315 dwc3_gadget_dctl_write_safe(dwc, reg); 316 317 /* 318 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit 319 * is cleared only after all the clocks are synchronized. This can 320 * take a little more than 50ms. Set the polling rate at 20ms 321 * for 10 times instead. 322 */ 323 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 324 retries = 10; 325 326 do { 327 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 328 if (!(reg & DWC3_DCTL_CSFTRST)) 329 goto done; 330 331 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 332 msleep(20); 333 else 334 udelay(1); 335 } while (--retries); 336 337 dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n"); 338 return -ETIMEDOUT; 339 340 done: 341 /* 342 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit 343 * is cleared, we must wait at least 50ms before accessing the PHY 344 * domain (synchronization delay). 345 */ 346 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A)) 347 msleep(50); 348 349 return 0; 350 } 351 352 /* 353 * dwc3_frame_length_adjustment - Adjusts frame length if required 354 * @dwc3: Pointer to our controller context structure 355 */ 356 static void dwc3_frame_length_adjustment(struct dwc3 *dwc) 357 { 358 u32 reg; 359 u32 dft; 360 361 if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 362 return; 363 364 if (dwc->fladj == 0) 365 return; 366 367 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 368 dft = reg & DWC3_GFLADJ_30MHZ_MASK; 369 if (dft != dwc->fladj) { 370 reg &= ~DWC3_GFLADJ_30MHZ_MASK; 371 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; 372 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 373 } 374 } 375 376 /** 377 * dwc3_ref_clk_period - Reference clock period configuration 378 * Default reference clock period depends on hardware 379 * configuration. For systems with reference clock that differs 380 * from the default, this will set clock period in DWC3_GUCTL 381 * register. 382 * @dwc: Pointer to our controller context structure 383 */ 384 static void dwc3_ref_clk_period(struct dwc3 *dwc) 385 { 386 unsigned long period; 387 unsigned long fladj; 388 unsigned long decr; 389 unsigned long rate; 390 u32 reg; 391 392 if (dwc->ref_clk) { 393 rate = clk_get_rate(dwc->ref_clk); 394 if (!rate) 395 return; 396 period = NSEC_PER_SEC / rate; 397 } else if (dwc->ref_clk_per) { 398 period = dwc->ref_clk_per; 399 rate = NSEC_PER_SEC / period; 400 } else { 401 return; 402 } 403 404 reg = dwc3_readl(dwc->regs, DWC3_GUCTL); 405 reg &= ~DWC3_GUCTL_REFCLKPER_MASK; 406 reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period); 407 dwc3_writel(dwc->regs, DWC3_GUCTL, reg); 408 409 if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 410 return; 411 412 /* 413 * The calculation below is 414 * 415 * 125000 * (NSEC_PER_SEC / (rate * period) - 1) 416 * 417 * but rearranged for fixed-point arithmetic. The division must be 418 * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and 419 * neither does rate * period). 420 * 421 * Note that rate * period ~= NSEC_PER_SECOND, minus the number of 422 * nanoseconds of error caused by the truncation which happened during 423 * the division when calculating rate or period (whichever one was 424 * derived from the other). We first calculate the relative error, then 425 * scale it to units of 8 ppm. 426 */ 427 fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period); 428 fladj -= 125000; 429 430 /* 431 * The documented 240MHz constant is scaled by 2 to get PLS1 as well. 432 */ 433 decr = 480000000 / rate; 434 435 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 436 reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK 437 & ~DWC3_GFLADJ_240MHZDECR 438 & ~DWC3_GFLADJ_240MHZDECR_PLS1; 439 reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj) 440 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1) 441 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1); 442 443 if (dwc->gfladj_refclk_lpm_sel) 444 reg |= DWC3_GFLADJ_REFCLK_LPM_SEL; 445 446 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 447 } 448 449 /** 450 * dwc3_free_one_event_buffer - Frees one event buffer 451 * @dwc: Pointer to our controller context structure 452 * @evt: Pointer to event buffer to be freed 453 */ 454 static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 455 struct dwc3_event_buffer *evt) 456 { 457 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma); 458 } 459 460 /** 461 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 462 * @dwc: Pointer to our controller context structure 463 * @length: size of the event buffer 464 * 465 * Returns a pointer to the allocated event buffer structure on success 466 * otherwise ERR_PTR(errno). 467 */ 468 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 469 unsigned int length) 470 { 471 struct dwc3_event_buffer *evt; 472 473 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 474 if (!evt) 475 return ERR_PTR(-ENOMEM); 476 477 evt->dwc = dwc; 478 evt->length = length; 479 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL); 480 if (!evt->cache) 481 return ERR_PTR(-ENOMEM); 482 483 evt->buf = dma_alloc_coherent(dwc->sysdev, length, 484 &evt->dma, GFP_KERNEL); 485 if (!evt->buf) 486 return ERR_PTR(-ENOMEM); 487 488 return evt; 489 } 490 491 /** 492 * dwc3_free_event_buffers - frees all allocated event buffers 493 * @dwc: Pointer to our controller context structure 494 */ 495 static void dwc3_free_event_buffers(struct dwc3 *dwc) 496 { 497 struct dwc3_event_buffer *evt; 498 499 evt = dwc->ev_buf; 500 if (evt) 501 dwc3_free_one_event_buffer(dwc, evt); 502 } 503 504 /** 505 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 506 * @dwc: pointer to our controller context structure 507 * @length: size of event buffer 508 * 509 * Returns 0 on success otherwise negative errno. In the error case, dwc 510 * may contain some buffers allocated but not all which were requested. 511 */ 512 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length) 513 { 514 struct dwc3_event_buffer *evt; 515 unsigned int hw_mode; 516 517 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 518 if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) { 519 dwc->ev_buf = NULL; 520 return 0; 521 } 522 523 evt = dwc3_alloc_one_event_buffer(dwc, length); 524 if (IS_ERR(evt)) { 525 dev_err(dwc->dev, "can't allocate event buffer\n"); 526 return PTR_ERR(evt); 527 } 528 dwc->ev_buf = evt; 529 530 return 0; 531 } 532 533 /** 534 * dwc3_event_buffers_setup - setup our allocated event buffers 535 * @dwc: pointer to our controller context structure 536 * 537 * Returns 0 on success otherwise negative errno. 538 */ 539 int dwc3_event_buffers_setup(struct dwc3 *dwc) 540 { 541 struct dwc3_event_buffer *evt; 542 543 if (!dwc->ev_buf) 544 return 0; 545 546 evt = dwc->ev_buf; 547 evt->lpos = 0; 548 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 549 lower_32_bits(evt->dma)); 550 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 551 upper_32_bits(evt->dma)); 552 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), 553 DWC3_GEVNTSIZ_SIZE(evt->length)); 554 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 555 556 return 0; 557 } 558 559 void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 560 { 561 struct dwc3_event_buffer *evt; 562 563 if (!dwc->ev_buf) 564 return; 565 566 evt = dwc->ev_buf; 567 568 evt->lpos = 0; 569 570 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); 571 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); 572 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK 573 | DWC3_GEVNTSIZ_SIZE(0)); 574 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 575 } 576 577 static void dwc3_core_num_eps(struct dwc3 *dwc) 578 { 579 struct dwc3_hwparams *parms = &dwc->hwparams; 580 581 dwc->num_eps = DWC3_NUM_EPS(parms); 582 } 583 584 static void dwc3_cache_hwparams(struct dwc3 *dwc) 585 { 586 struct dwc3_hwparams *parms = &dwc->hwparams; 587 588 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 589 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 590 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 591 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 592 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 593 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 594 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 595 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 596 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 597 598 if (DWC3_IP_IS(DWC32)) 599 parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9); 600 } 601 602 static int dwc3_core_ulpi_init(struct dwc3 *dwc) 603 { 604 int intf; 605 int ret = 0; 606 607 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3); 608 609 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI || 610 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI && 611 dwc->hsphy_interface && 612 !strncmp(dwc->hsphy_interface, "ulpi", 4))) 613 ret = dwc3_ulpi_init(dwc); 614 615 return ret; 616 } 617 618 static int dwc3_ss_phy_setup(struct dwc3 *dwc, int index) 619 { 620 u32 reg; 621 622 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(index)); 623 624 /* 625 * Make sure UX_EXIT_PX is cleared as that causes issues with some 626 * PHYs. Also, this bit is not supposed to be used in normal operation. 627 */ 628 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; 629 630 /* 631 * Above DWC_usb3.0 1.94a, it is recommended to set 632 * DWC3_GUSB3PIPECTL_SUSPHY to '0' during coreConsultant configuration. 633 * So default value will be '0' when the core is reset. Application 634 * needs to set it to '1' after the core initialization is completed. 635 * 636 * Similarly for DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be 637 * cleared after power-on reset, and it can be set after core 638 * initialization. 639 */ 640 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 641 642 if (dwc->u2ss_inp3_quirk) 643 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 644 645 if (dwc->dis_rxdet_inp3_quirk) 646 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; 647 648 if (dwc->req_p1p2p3_quirk) 649 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 650 651 if (dwc->del_p1p2p3_quirk) 652 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 653 654 if (dwc->del_phy_power_chg_quirk) 655 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 656 657 if (dwc->lfps_filter_quirk) 658 reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 659 660 if (dwc->rx_detect_poll_quirk) 661 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 662 663 if (dwc->tx_de_emphasis_quirk) 664 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 665 666 if (dwc->dis_del_phy_power_chg_quirk) 667 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; 668 669 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(index), reg); 670 671 return 0; 672 } 673 674 static int dwc3_hs_phy_setup(struct dwc3 *dwc, int index) 675 { 676 u32 reg; 677 678 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(index)); 679 680 /* Select the HS PHY interface */ 681 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { 682 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: 683 if (dwc->hsphy_interface && 684 !strncmp(dwc->hsphy_interface, "utmi", 4)) { 685 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; 686 break; 687 } else if (dwc->hsphy_interface && 688 !strncmp(dwc->hsphy_interface, "ulpi", 4)) { 689 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; 690 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg); 691 } else { 692 /* Relying on default value. */ 693 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) 694 break; 695 } 696 fallthrough; 697 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: 698 default: 699 break; 700 } 701 702 switch (dwc->hsphy_mode) { 703 case USBPHY_INTERFACE_MODE_UTMI: 704 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 705 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 706 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | 707 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); 708 break; 709 case USBPHY_INTERFACE_MODE_UTMIW: 710 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 711 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 712 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | 713 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 714 break; 715 default: 716 break; 717 } 718 719 /* 720 * Above DWC_usb3.0 1.94a, it is recommended to set 721 * DWC3_GUSB2PHYCFG_SUSPHY to '0' during coreConsultant configuration. 722 * So default value will be '0' when the core is reset. Application 723 * needs to set it to '1' after the core initialization is completed. 724 * 725 * Similarly for DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared 726 * after power-on reset, and it can be set after core initialization. 727 */ 728 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 729 730 if (dwc->dis_enblslpm_quirk) 731 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 732 else 733 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM; 734 735 if (dwc->dis_u2_freeclk_exists_quirk || dwc->gfladj_refclk_lpm_sel) 736 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 737 738 /* 739 * Some ULPI USB PHY does not support internal VBUS supply, to drive 740 * the CPEN pin requires the configuration of the ULPI DRVVBUSEXTERNAL 741 * bit of OTG_CTRL register. Controller configures the USB2 PHY 742 * ULPIEXTVBUSDRV bit[17] of the GUSB2PHYCFG register to drive vBus 743 * with an external supply. 744 */ 745 if (dwc->ulpi_ext_vbus_drv) 746 reg |= DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV; 747 748 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg); 749 750 return 0; 751 } 752 753 /** 754 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 755 * @dwc: Pointer to our controller context structure 756 * 757 * Returns 0 on success. The USB PHY interfaces are configured but not 758 * initialized. The PHY interfaces and the PHYs get initialized together with 759 * the core in dwc3_core_init. 760 */ 761 static int dwc3_phy_setup(struct dwc3 *dwc) 762 { 763 int i; 764 int ret; 765 766 for (i = 0; i < dwc->num_usb3_ports; i++) { 767 ret = dwc3_ss_phy_setup(dwc, i); 768 if (ret) 769 return ret; 770 } 771 772 for (i = 0; i < dwc->num_usb2_ports; i++) { 773 ret = dwc3_hs_phy_setup(dwc, i); 774 if (ret) 775 return ret; 776 } 777 778 return 0; 779 } 780 781 static int dwc3_phy_init(struct dwc3 *dwc) 782 { 783 int ret; 784 int i; 785 int j; 786 787 usb_phy_init(dwc->usb2_phy); 788 usb_phy_init(dwc->usb3_phy); 789 790 for (i = 0; i < dwc->num_usb2_ports; i++) { 791 ret = phy_init(dwc->usb2_generic_phy[i]); 792 if (ret < 0) 793 goto err_exit_usb2_phy; 794 } 795 796 for (j = 0; j < dwc->num_usb3_ports; j++) { 797 ret = phy_init(dwc->usb3_generic_phy[j]); 798 if (ret < 0) 799 goto err_exit_usb3_phy; 800 } 801 802 return 0; 803 804 err_exit_usb3_phy: 805 while (--j >= 0) 806 phy_exit(dwc->usb3_generic_phy[j]); 807 808 err_exit_usb2_phy: 809 while (--i >= 0) 810 phy_exit(dwc->usb2_generic_phy[i]); 811 812 usb_phy_shutdown(dwc->usb3_phy); 813 usb_phy_shutdown(dwc->usb2_phy); 814 815 return ret; 816 } 817 818 static void dwc3_phy_exit(struct dwc3 *dwc) 819 { 820 int i; 821 822 for (i = 0; i < dwc->num_usb3_ports; i++) 823 phy_exit(dwc->usb3_generic_phy[i]); 824 825 for (i = 0; i < dwc->num_usb2_ports; i++) 826 phy_exit(dwc->usb2_generic_phy[i]); 827 828 usb_phy_shutdown(dwc->usb3_phy); 829 usb_phy_shutdown(dwc->usb2_phy); 830 } 831 832 static int dwc3_phy_power_on(struct dwc3 *dwc) 833 { 834 int ret; 835 int i; 836 int j; 837 838 usb_phy_set_suspend(dwc->usb2_phy, 0); 839 usb_phy_set_suspend(dwc->usb3_phy, 0); 840 841 for (i = 0; i < dwc->num_usb2_ports; i++) { 842 ret = phy_power_on(dwc->usb2_generic_phy[i]); 843 if (ret < 0) 844 goto err_power_off_usb2_phy; 845 } 846 847 for (j = 0; j < dwc->num_usb3_ports; j++) { 848 ret = phy_power_on(dwc->usb3_generic_phy[j]); 849 if (ret < 0) 850 goto err_power_off_usb3_phy; 851 } 852 853 return 0; 854 855 err_power_off_usb3_phy: 856 while (--j >= 0) 857 phy_power_off(dwc->usb3_generic_phy[j]); 858 859 err_power_off_usb2_phy: 860 while (--i >= 0) 861 phy_power_off(dwc->usb2_generic_phy[i]); 862 863 usb_phy_set_suspend(dwc->usb3_phy, 1); 864 usb_phy_set_suspend(dwc->usb2_phy, 1); 865 866 return ret; 867 } 868 869 static void dwc3_phy_power_off(struct dwc3 *dwc) 870 { 871 int i; 872 873 for (i = 0; i < dwc->num_usb3_ports; i++) 874 phy_power_off(dwc->usb3_generic_phy[i]); 875 876 for (i = 0; i < dwc->num_usb2_ports; i++) 877 phy_power_off(dwc->usb2_generic_phy[i]); 878 879 usb_phy_set_suspend(dwc->usb3_phy, 1); 880 usb_phy_set_suspend(dwc->usb2_phy, 1); 881 } 882 883 static int dwc3_clk_enable(struct dwc3 *dwc) 884 { 885 int ret; 886 887 ret = clk_prepare_enable(dwc->bus_clk); 888 if (ret) 889 return ret; 890 891 ret = clk_prepare_enable(dwc->ref_clk); 892 if (ret) 893 goto disable_bus_clk; 894 895 ret = clk_prepare_enable(dwc->susp_clk); 896 if (ret) 897 goto disable_ref_clk; 898 899 ret = clk_prepare_enable(dwc->utmi_clk); 900 if (ret) 901 goto disable_susp_clk; 902 903 ret = clk_prepare_enable(dwc->pipe_clk); 904 if (ret) 905 goto disable_utmi_clk; 906 907 return 0; 908 909 disable_utmi_clk: 910 clk_disable_unprepare(dwc->utmi_clk); 911 disable_susp_clk: 912 clk_disable_unprepare(dwc->susp_clk); 913 disable_ref_clk: 914 clk_disable_unprepare(dwc->ref_clk); 915 disable_bus_clk: 916 clk_disable_unprepare(dwc->bus_clk); 917 return ret; 918 } 919 920 static void dwc3_clk_disable(struct dwc3 *dwc) 921 { 922 clk_disable_unprepare(dwc->pipe_clk); 923 clk_disable_unprepare(dwc->utmi_clk); 924 clk_disable_unprepare(dwc->susp_clk); 925 clk_disable_unprepare(dwc->ref_clk); 926 clk_disable_unprepare(dwc->bus_clk); 927 } 928 929 static void dwc3_core_exit(struct dwc3 *dwc) 930 { 931 dwc3_event_buffers_cleanup(dwc); 932 dwc3_phy_power_off(dwc); 933 dwc3_phy_exit(dwc); 934 dwc3_clk_disable(dwc); 935 reset_control_assert(dwc->reset); 936 } 937 938 static bool dwc3_core_is_valid(struct dwc3 *dwc) 939 { 940 u32 reg; 941 942 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 943 dwc->ip = DWC3_GSNPS_ID(reg); 944 945 /* This should read as U3 followed by revision number */ 946 if (DWC3_IP_IS(DWC3)) { 947 dwc->revision = reg; 948 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) { 949 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); 950 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE); 951 } else { 952 return false; 953 } 954 955 return true; 956 } 957 958 static void dwc3_core_setup_global_control(struct dwc3 *dwc) 959 { 960 unsigned int power_opt; 961 unsigned int hw_mode; 962 u32 reg; 963 964 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 965 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 966 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 967 power_opt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1); 968 969 switch (power_opt) { 970 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 971 /** 972 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 973 * issue which would cause xHCI compliance tests to fail. 974 * 975 * Because of that we cannot enable clock gating on such 976 * configurations. 977 * 978 * Refers to: 979 * 980 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 981 * SOF/ITP Mode Used 982 */ 983 if ((dwc->dr_mode == USB_DR_MODE_HOST || 984 dwc->dr_mode == USB_DR_MODE_OTG) && 985 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A)) 986 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 987 else 988 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 989 break; 990 case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 991 /* 992 * REVISIT Enabling this bit so that host-mode hibernation 993 * will work. Device-mode hibernation is not yet implemented. 994 */ 995 reg |= DWC3_GCTL_GBLHIBERNATIONEN; 996 break; 997 default: 998 /* nothing */ 999 break; 1000 } 1001 1002 /* 1003 * This is a workaround for STAR#4846132, which only affects 1004 * DWC_usb31 version2.00a operating in host mode. 1005 * 1006 * There is a problem in DWC_usb31 version 2.00a operating 1007 * in host mode that would cause a CSR read timeout When CSR 1008 * read coincides with RAM Clock Gating Entry. By disable 1009 * Clock Gating, sacrificing power consumption for normal 1010 * operation. 1011 */ 1012 if (power_opt != DWC3_GHWPARAMS1_EN_PWROPT_NO && 1013 hw_mode != DWC3_GHWPARAMS0_MODE_GADGET && DWC3_VER_IS(DWC31, 200A)) 1014 reg |= DWC3_GCTL_DSBLCLKGTNG; 1015 1016 /* check if current dwc3 is on simulation board */ 1017 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 1018 dev_info(dwc->dev, "Running with FPGA optimizations\n"); 1019 dwc->is_fpga = true; 1020 } 1021 1022 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, 1023 "disable_scramble cannot be used on non-FPGA builds\n"); 1024 1025 if (dwc->disable_scramble_quirk && dwc->is_fpga) 1026 reg |= DWC3_GCTL_DISSCRAMBLE; 1027 else 1028 reg &= ~DWC3_GCTL_DISSCRAMBLE; 1029 1030 if (dwc->u2exit_lfps_quirk) 1031 reg |= DWC3_GCTL_U2EXIT_LFPS; 1032 1033 /* 1034 * WORKAROUND: DWC3 revisions <1.90a have a bug 1035 * where the device can fail to connect at SuperSpeed 1036 * and falls back to high-speed mode which causes 1037 * the device to enter a Connect/Disconnect loop 1038 */ 1039 if (DWC3_VER_IS_PRIOR(DWC3, 190A)) 1040 reg |= DWC3_GCTL_U2RSTECN; 1041 1042 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 1043 } 1044 1045 static int dwc3_core_get_phy(struct dwc3 *dwc); 1046 static int dwc3_core_ulpi_init(struct dwc3 *dwc); 1047 1048 /* set global incr burst type configuration registers */ 1049 static void dwc3_set_incr_burst_type(struct dwc3 *dwc) 1050 { 1051 struct device *dev = dwc->dev; 1052 /* incrx_mode : for INCR burst type. */ 1053 bool incrx_mode; 1054 /* incrx_size : for size of INCRX burst. */ 1055 u32 incrx_size; 1056 u32 *vals; 1057 u32 cfg; 1058 int ntype; 1059 int ret; 1060 int i; 1061 1062 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); 1063 1064 /* 1065 * Handle property "snps,incr-burst-type-adjustment". 1066 * Get the number of value from this property: 1067 * result <= 0, means this property is not supported. 1068 * result = 1, means INCRx burst mode supported. 1069 * result > 1, means undefined length burst mode supported. 1070 */ 1071 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment"); 1072 if (ntype <= 0) 1073 return; 1074 1075 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL); 1076 if (!vals) 1077 return; 1078 1079 /* Get INCR burst type, and parse it */ 1080 ret = device_property_read_u32_array(dev, 1081 "snps,incr-burst-type-adjustment", vals, ntype); 1082 if (ret) { 1083 kfree(vals); 1084 dev_err(dev, "Error to get property\n"); 1085 return; 1086 } 1087 1088 incrx_size = *vals; 1089 1090 if (ntype > 1) { 1091 /* INCRX (undefined length) burst mode */ 1092 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE; 1093 for (i = 1; i < ntype; i++) { 1094 if (vals[i] > incrx_size) 1095 incrx_size = vals[i]; 1096 } 1097 } else { 1098 /* INCRX burst mode */ 1099 incrx_mode = INCRX_BURST_MODE; 1100 } 1101 1102 kfree(vals); 1103 1104 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */ 1105 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK; 1106 if (incrx_mode) 1107 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA; 1108 switch (incrx_size) { 1109 case 256: 1110 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA; 1111 break; 1112 case 128: 1113 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA; 1114 break; 1115 case 64: 1116 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA; 1117 break; 1118 case 32: 1119 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA; 1120 break; 1121 case 16: 1122 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA; 1123 break; 1124 case 8: 1125 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA; 1126 break; 1127 case 4: 1128 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA; 1129 break; 1130 case 1: 1131 break; 1132 default: 1133 dev_err(dev, "Invalid property\n"); 1134 break; 1135 } 1136 1137 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg); 1138 } 1139 1140 static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc) 1141 { 1142 u32 scale; 1143 u32 reg; 1144 1145 if (!dwc->susp_clk) 1146 return; 1147 1148 /* 1149 * The power down scale field specifies how many suspend_clk 1150 * periods fit into a 16KHz clock period. When performing 1151 * the division, round up the remainder. 1152 * 1153 * The power down scale value is calculated using the fastest 1154 * frequency of the suspend_clk. If it isn't fixed (but within 1155 * the accuracy requirement), the driver may not know the max 1156 * rate of the suspend_clk, so only update the power down scale 1157 * if the default is less than the calculated value from 1158 * clk_get_rate() or if the default is questionably high 1159 * (3x or more) to be within the requirement. 1160 */ 1161 scale = DIV_ROUND_UP(clk_get_rate(dwc->susp_clk), 16000); 1162 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 1163 if ((reg & DWC3_GCTL_PWRDNSCALE_MASK) < DWC3_GCTL_PWRDNSCALE(scale) || 1164 (reg & DWC3_GCTL_PWRDNSCALE_MASK) > DWC3_GCTL_PWRDNSCALE(scale*3)) { 1165 reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK); 1166 reg |= DWC3_GCTL_PWRDNSCALE(scale); 1167 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 1168 } 1169 } 1170 1171 static void dwc3_config_threshold(struct dwc3 *dwc) 1172 { 1173 u32 reg; 1174 u8 rx_thr_num; 1175 u8 rx_maxburst; 1176 u8 tx_thr_num; 1177 u8 tx_maxburst; 1178 1179 /* 1180 * Must config both number of packets and max burst settings to enable 1181 * RX and/or TX threshold. 1182 */ 1183 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) { 1184 rx_thr_num = dwc->rx_thr_num_pkt_prd; 1185 rx_maxburst = dwc->rx_max_burst_prd; 1186 tx_thr_num = dwc->tx_thr_num_pkt_prd; 1187 tx_maxburst = dwc->tx_max_burst_prd; 1188 1189 if (rx_thr_num && rx_maxburst) { 1190 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1191 reg |= DWC31_RXTHRNUMPKTSEL_PRD; 1192 1193 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0); 1194 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num); 1195 1196 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0); 1197 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst); 1198 1199 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1200 } 1201 1202 if (tx_thr_num && tx_maxburst) { 1203 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1204 reg |= DWC31_TXTHRNUMPKTSEL_PRD; 1205 1206 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0); 1207 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num); 1208 1209 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0); 1210 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst); 1211 1212 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1213 } 1214 } 1215 1216 rx_thr_num = dwc->rx_thr_num_pkt; 1217 rx_maxburst = dwc->rx_max_burst; 1218 tx_thr_num = dwc->tx_thr_num_pkt; 1219 tx_maxburst = dwc->tx_max_burst; 1220 1221 if (DWC3_IP_IS(DWC3)) { 1222 if (rx_thr_num && rx_maxburst) { 1223 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1224 reg |= DWC3_GRXTHRCFG_PKTCNTSEL; 1225 1226 reg &= ~DWC3_GRXTHRCFG_RXPKTCNT(~0); 1227 reg |= DWC3_GRXTHRCFG_RXPKTCNT(rx_thr_num); 1228 1229 reg &= ~DWC3_GRXTHRCFG_MAXRXBURSTSIZE(~0); 1230 reg |= DWC3_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst); 1231 1232 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1233 } 1234 1235 if (tx_thr_num && tx_maxburst) { 1236 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1237 reg |= DWC3_GTXTHRCFG_PKTCNTSEL; 1238 1239 reg &= ~DWC3_GTXTHRCFG_TXPKTCNT(~0); 1240 reg |= DWC3_GTXTHRCFG_TXPKTCNT(tx_thr_num); 1241 1242 reg &= ~DWC3_GTXTHRCFG_MAXTXBURSTSIZE(~0); 1243 reg |= DWC3_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst); 1244 1245 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1246 } 1247 } else { 1248 if (rx_thr_num && rx_maxburst) { 1249 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1250 reg |= DWC31_GRXTHRCFG_PKTCNTSEL; 1251 1252 reg &= ~DWC31_GRXTHRCFG_RXPKTCNT(~0); 1253 reg |= DWC31_GRXTHRCFG_RXPKTCNT(rx_thr_num); 1254 1255 reg &= ~DWC31_GRXTHRCFG_MAXRXBURSTSIZE(~0); 1256 reg |= DWC31_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst); 1257 1258 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1259 } 1260 1261 if (tx_thr_num && tx_maxburst) { 1262 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1263 reg |= DWC31_GTXTHRCFG_PKTCNTSEL; 1264 1265 reg &= ~DWC31_GTXTHRCFG_TXPKTCNT(~0); 1266 reg |= DWC31_GTXTHRCFG_TXPKTCNT(tx_thr_num); 1267 1268 reg &= ~DWC31_GTXTHRCFG_MAXTXBURSTSIZE(~0); 1269 reg |= DWC31_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst); 1270 1271 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1272 } 1273 } 1274 } 1275 1276 /** 1277 * dwc3_core_init - Low-level initialization of DWC3 Core 1278 * @dwc: Pointer to our controller context structure 1279 * 1280 * Returns 0 on success otherwise negative errno. 1281 */ 1282 static int dwc3_core_init(struct dwc3 *dwc) 1283 { 1284 unsigned int hw_mode; 1285 u32 reg; 1286 int ret; 1287 1288 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 1289 1290 /* 1291 * Write Linux Version Code to our GUID register so it's easy to figure 1292 * out which kernel version a bug was found. 1293 */ 1294 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); 1295 1296 ret = dwc3_phy_setup(dwc); 1297 if (ret) 1298 return ret; 1299 1300 if (!dwc->ulpi_ready) { 1301 ret = dwc3_core_ulpi_init(dwc); 1302 if (ret) { 1303 if (ret == -ETIMEDOUT) { 1304 dwc3_core_soft_reset(dwc); 1305 ret = -EPROBE_DEFER; 1306 } 1307 return ret; 1308 } 1309 dwc->ulpi_ready = true; 1310 } 1311 1312 if (!dwc->phys_ready) { 1313 ret = dwc3_core_get_phy(dwc); 1314 if (ret) 1315 goto err_exit_ulpi; 1316 dwc->phys_ready = true; 1317 } 1318 1319 ret = dwc3_phy_init(dwc); 1320 if (ret) 1321 goto err_exit_ulpi; 1322 1323 ret = dwc3_core_soft_reset(dwc); 1324 if (ret) 1325 goto err_exit_phy; 1326 1327 dwc3_core_setup_global_control(dwc); 1328 dwc3_core_num_eps(dwc); 1329 1330 /* Set power down scale of suspend_clk */ 1331 dwc3_set_power_down_clk_scale(dwc); 1332 1333 /* Adjust Frame Length */ 1334 dwc3_frame_length_adjustment(dwc); 1335 1336 /* Adjust Reference Clock Period */ 1337 dwc3_ref_clk_period(dwc); 1338 1339 dwc3_set_incr_burst_type(dwc); 1340 1341 ret = dwc3_phy_power_on(dwc); 1342 if (ret) 1343 goto err_exit_phy; 1344 1345 ret = dwc3_event_buffers_setup(dwc); 1346 if (ret) { 1347 dev_err(dwc->dev, "failed to setup event buffers\n"); 1348 goto err_power_off_phy; 1349 } 1350 1351 /* 1352 * ENDXFER polling is available on version 3.10a and later of 1353 * the DWC_usb3 controller. It is NOT available in the 1354 * DWC_usb31 controller. 1355 */ 1356 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) { 1357 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); 1358 reg |= DWC3_GUCTL2_RST_ACTBITLATER; 1359 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); 1360 } 1361 1362 /* 1363 * When configured in HOST mode, after issuing U3/L2 exit controller 1364 * fails to send proper CRC checksum in CRC5 feild. Because of this 1365 * behaviour Transaction Error is generated, resulting in reset and 1366 * re-enumeration of usb device attached. All the termsel, xcvrsel, 1367 * opmode becomes 0 during end of resume. Enabling bit 10 of GUCTL1 1368 * will correct this problem. This option is to support certain 1369 * legacy ULPI PHYs. 1370 */ 1371 if (dwc->resume_hs_terminations) { 1372 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 1373 reg |= DWC3_GUCTL1_RESUME_OPMODE_HS_HOST; 1374 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 1375 } 1376 1377 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) { 1378 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 1379 1380 /* 1381 * Enable hardware control of sending remote wakeup 1382 * in HS when the device is in the L1 state. 1383 */ 1384 if (!DWC3_VER_IS_PRIOR(DWC3, 290A)) 1385 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; 1386 1387 /* 1388 * Decouple USB 2.0 L1 & L2 events which will allow for 1389 * gadget driver to only receive U3/L2 suspend & wakeup 1390 * events and prevent the more frequent L1 LPM transitions 1391 * from interrupting the driver. 1392 */ 1393 if (!DWC3_VER_IS_PRIOR(DWC3, 300A)) 1394 reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT; 1395 1396 if (dwc->dis_tx_ipgap_linecheck_quirk) 1397 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; 1398 1399 if (dwc->parkmode_disable_ss_quirk) 1400 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS; 1401 1402 if (dwc->parkmode_disable_hs_quirk) 1403 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_HS; 1404 1405 if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY)) { 1406 if (dwc->maximum_speed == USB_SPEED_FULL || 1407 dwc->maximum_speed == USB_SPEED_HIGH) 1408 reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; 1409 else 1410 reg &= ~DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; 1411 } 1412 1413 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 1414 } 1415 1416 dwc3_config_threshold(dwc); 1417 1418 /* 1419 * Modify this for all supported Super Speed ports when 1420 * multiport support is added. 1421 */ 1422 if (hw_mode != DWC3_GHWPARAMS0_MODE_GADGET && 1423 (DWC3_IP_IS(DWC31)) && 1424 dwc->maximum_speed == USB_SPEED_SUPER) { 1425 reg = dwc3_readl(dwc->regs, DWC3_LLUCTL); 1426 reg |= DWC3_LLUCTL_FORCE_GEN1; 1427 dwc3_writel(dwc->regs, DWC3_LLUCTL, reg); 1428 } 1429 1430 return 0; 1431 1432 err_power_off_phy: 1433 dwc3_phy_power_off(dwc); 1434 err_exit_phy: 1435 dwc3_phy_exit(dwc); 1436 err_exit_ulpi: 1437 dwc3_ulpi_exit(dwc); 1438 1439 return ret; 1440 } 1441 1442 static int dwc3_core_get_phy(struct dwc3 *dwc) 1443 { 1444 struct device *dev = dwc->dev; 1445 struct device_node *node = dev->of_node; 1446 char phy_name[9]; 1447 int ret; 1448 u8 i; 1449 1450 if (node) { 1451 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); 1452 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); 1453 } else { 1454 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 1455 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); 1456 } 1457 1458 if (IS_ERR(dwc->usb2_phy)) { 1459 ret = PTR_ERR(dwc->usb2_phy); 1460 if (ret == -ENXIO || ret == -ENODEV) 1461 dwc->usb2_phy = NULL; 1462 else 1463 return dev_err_probe(dev, ret, "no usb2 phy configured\n"); 1464 } 1465 1466 if (IS_ERR(dwc->usb3_phy)) { 1467 ret = PTR_ERR(dwc->usb3_phy); 1468 if (ret == -ENXIO || ret == -ENODEV) 1469 dwc->usb3_phy = NULL; 1470 else 1471 return dev_err_probe(dev, ret, "no usb3 phy configured\n"); 1472 } 1473 1474 for (i = 0; i < dwc->num_usb2_ports; i++) { 1475 if (dwc->num_usb2_ports == 1) 1476 snprintf(phy_name, sizeof(phy_name), "usb2-phy"); 1477 else 1478 snprintf(phy_name, sizeof(phy_name), "usb2-%u", i); 1479 1480 dwc->usb2_generic_phy[i] = devm_phy_get(dev, phy_name); 1481 if (IS_ERR(dwc->usb2_generic_phy[i])) { 1482 ret = PTR_ERR(dwc->usb2_generic_phy[i]); 1483 if (ret == -ENOSYS || ret == -ENODEV) 1484 dwc->usb2_generic_phy[i] = NULL; 1485 else 1486 return dev_err_probe(dev, ret, "failed to lookup phy %s\n", 1487 phy_name); 1488 } 1489 } 1490 1491 for (i = 0; i < dwc->num_usb3_ports; i++) { 1492 if (dwc->num_usb3_ports == 1) 1493 snprintf(phy_name, sizeof(phy_name), "usb3-phy"); 1494 else 1495 snprintf(phy_name, sizeof(phy_name), "usb3-%u", i); 1496 1497 dwc->usb3_generic_phy[i] = devm_phy_get(dev, phy_name); 1498 if (IS_ERR(dwc->usb3_generic_phy[i])) { 1499 ret = PTR_ERR(dwc->usb3_generic_phy[i]); 1500 if (ret == -ENOSYS || ret == -ENODEV) 1501 dwc->usb3_generic_phy[i] = NULL; 1502 else 1503 return dev_err_probe(dev, ret, "failed to lookup phy %s\n", 1504 phy_name); 1505 } 1506 } 1507 1508 return 0; 1509 } 1510 1511 static int dwc3_core_init_mode(struct dwc3 *dwc) 1512 { 1513 struct device *dev = dwc->dev; 1514 int ret; 1515 int i; 1516 1517 switch (dwc->dr_mode) { 1518 case USB_DR_MODE_PERIPHERAL: 1519 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1520 1521 if (dwc->usb2_phy) 1522 otg_set_vbus(dwc->usb2_phy->otg, false); 1523 phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE); 1524 phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE); 1525 1526 ret = dwc3_gadget_init(dwc); 1527 if (ret) 1528 return dev_err_probe(dev, ret, "failed to initialize gadget\n"); 1529 break; 1530 case USB_DR_MODE_HOST: 1531 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1532 1533 if (dwc->usb2_phy) 1534 otg_set_vbus(dwc->usb2_phy->otg, true); 1535 for (i = 0; i < dwc->num_usb2_ports; i++) 1536 phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST); 1537 for (i = 0; i < dwc->num_usb3_ports; i++) 1538 phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST); 1539 1540 ret = dwc3_host_init(dwc); 1541 if (ret) 1542 return dev_err_probe(dev, ret, "failed to initialize host\n"); 1543 break; 1544 case USB_DR_MODE_OTG: 1545 INIT_WORK(&dwc->drd_work, __dwc3_set_mode); 1546 ret = dwc3_drd_init(dwc); 1547 if (ret) 1548 return dev_err_probe(dev, ret, "failed to initialize dual-role\n"); 1549 break; 1550 default: 1551 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 1552 return -EINVAL; 1553 } 1554 1555 return 0; 1556 } 1557 1558 static void dwc3_core_exit_mode(struct dwc3 *dwc) 1559 { 1560 switch (dwc->dr_mode) { 1561 case USB_DR_MODE_PERIPHERAL: 1562 dwc3_gadget_exit(dwc); 1563 break; 1564 case USB_DR_MODE_HOST: 1565 dwc3_host_exit(dwc); 1566 break; 1567 case USB_DR_MODE_OTG: 1568 dwc3_drd_exit(dwc); 1569 break; 1570 default: 1571 /* do nothing */ 1572 break; 1573 } 1574 1575 /* de-assert DRVVBUS for HOST and OTG mode */ 1576 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1577 } 1578 1579 static void dwc3_get_properties(struct dwc3 *dwc) 1580 { 1581 struct device *dev = dwc->dev; 1582 u8 lpm_nyet_threshold; 1583 u8 tx_de_emphasis; 1584 u8 hird_threshold; 1585 u8 rx_thr_num_pkt = 0; 1586 u8 rx_max_burst = 0; 1587 u8 tx_thr_num_pkt = 0; 1588 u8 tx_max_burst = 0; 1589 u8 rx_thr_num_pkt_prd = 0; 1590 u8 rx_max_burst_prd = 0; 1591 u8 tx_thr_num_pkt_prd = 0; 1592 u8 tx_max_burst_prd = 0; 1593 u8 tx_fifo_resize_max_num; 1594 const char *usb_psy_name; 1595 int ret; 1596 1597 /* default to highest possible threshold */ 1598 lpm_nyet_threshold = 0xf; 1599 1600 /* default to -3.5dB de-emphasis */ 1601 tx_de_emphasis = 1; 1602 1603 /* 1604 * default to assert utmi_sleep_n and use maximum allowed HIRD 1605 * threshold value of 0b1100 1606 */ 1607 hird_threshold = 12; 1608 1609 /* 1610 * default to a TXFIFO size large enough to fit 6 max packets. This 1611 * allows for systems with larger bus latencies to have some headroom 1612 * for endpoints that have a large bMaxBurst value. 1613 */ 1614 tx_fifo_resize_max_num = 6; 1615 1616 dwc->maximum_speed = usb_get_maximum_speed(dev); 1617 dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev); 1618 dwc->dr_mode = usb_get_dr_mode(dev); 1619 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); 1620 1621 dwc->sysdev_is_parent = device_property_read_bool(dev, 1622 "linux,sysdev_is_parent"); 1623 if (dwc->sysdev_is_parent) 1624 dwc->sysdev = dwc->dev->parent; 1625 else 1626 dwc->sysdev = dwc->dev; 1627 1628 dwc->sys_wakeup = device_may_wakeup(dwc->sysdev); 1629 1630 ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name); 1631 if (ret >= 0) { 1632 dwc->usb_psy = power_supply_get_by_name(usb_psy_name); 1633 if (!dwc->usb_psy) 1634 dev_err(dev, "couldn't get usb power supply\n"); 1635 } 1636 1637 dwc->has_lpm_erratum = device_property_read_bool(dev, 1638 "snps,has-lpm-erratum"); 1639 device_property_read_u8(dev, "snps,lpm-nyet-threshold", 1640 &lpm_nyet_threshold); 1641 dwc->is_utmi_l1_suspend = device_property_read_bool(dev, 1642 "snps,is-utmi-l1-suspend"); 1643 device_property_read_u8(dev, "snps,hird-threshold", 1644 &hird_threshold); 1645 dwc->dis_start_transfer_quirk = device_property_read_bool(dev, 1646 "snps,dis-start-transfer-quirk"); 1647 dwc->usb3_lpm_capable = device_property_read_bool(dev, 1648 "snps,usb3_lpm_capable"); 1649 dwc->usb2_lpm_disable = device_property_read_bool(dev, 1650 "snps,usb2-lpm-disable"); 1651 dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev, 1652 "snps,usb2-gadget-lpm-disable"); 1653 device_property_read_u8(dev, "snps,rx-thr-num-pkt", 1654 &rx_thr_num_pkt); 1655 device_property_read_u8(dev, "snps,rx-max-burst", 1656 &rx_max_burst); 1657 device_property_read_u8(dev, "snps,tx-thr-num-pkt", 1658 &tx_thr_num_pkt); 1659 device_property_read_u8(dev, "snps,tx-max-burst", 1660 &tx_max_burst); 1661 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd", 1662 &rx_thr_num_pkt_prd); 1663 device_property_read_u8(dev, "snps,rx-max-burst-prd", 1664 &rx_max_burst_prd); 1665 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd", 1666 &tx_thr_num_pkt_prd); 1667 device_property_read_u8(dev, "snps,tx-max-burst-prd", 1668 &tx_max_burst_prd); 1669 dwc->do_fifo_resize = device_property_read_bool(dev, 1670 "tx-fifo-resize"); 1671 if (dwc->do_fifo_resize) 1672 device_property_read_u8(dev, "tx-fifo-max-num", 1673 &tx_fifo_resize_max_num); 1674 1675 dwc->disable_scramble_quirk = device_property_read_bool(dev, 1676 "snps,disable_scramble_quirk"); 1677 dwc->u2exit_lfps_quirk = device_property_read_bool(dev, 1678 "snps,u2exit_lfps_quirk"); 1679 dwc->u2ss_inp3_quirk = device_property_read_bool(dev, 1680 "snps,u2ss_inp3_quirk"); 1681 dwc->req_p1p2p3_quirk = device_property_read_bool(dev, 1682 "snps,req_p1p2p3_quirk"); 1683 dwc->del_p1p2p3_quirk = device_property_read_bool(dev, 1684 "snps,del_p1p2p3_quirk"); 1685 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, 1686 "snps,del_phy_power_chg_quirk"); 1687 dwc->lfps_filter_quirk = device_property_read_bool(dev, 1688 "snps,lfps_filter_quirk"); 1689 dwc->rx_detect_poll_quirk = device_property_read_bool(dev, 1690 "snps,rx_detect_poll_quirk"); 1691 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, 1692 "snps,dis_u3_susphy_quirk"); 1693 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, 1694 "snps,dis_u2_susphy_quirk"); 1695 dwc->dis_enblslpm_quirk = device_property_read_bool(dev, 1696 "snps,dis_enblslpm_quirk"); 1697 dwc->dis_u1_entry_quirk = device_property_read_bool(dev, 1698 "snps,dis-u1-entry-quirk"); 1699 dwc->dis_u2_entry_quirk = device_property_read_bool(dev, 1700 "snps,dis-u2-entry-quirk"); 1701 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, 1702 "snps,dis_rxdet_inp3_quirk"); 1703 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, 1704 "snps,dis-u2-freeclk-exists-quirk"); 1705 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, 1706 "snps,dis-del-phy-power-chg-quirk"); 1707 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev, 1708 "snps,dis-tx-ipgap-linecheck-quirk"); 1709 dwc->resume_hs_terminations = device_property_read_bool(dev, 1710 "snps,resume-hs-terminations"); 1711 dwc->ulpi_ext_vbus_drv = device_property_read_bool(dev, 1712 "snps,ulpi-ext-vbus-drv"); 1713 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev, 1714 "snps,parkmode-disable-ss-quirk"); 1715 dwc->parkmode_disable_hs_quirk = device_property_read_bool(dev, 1716 "snps,parkmode-disable-hs-quirk"); 1717 dwc->gfladj_refclk_lpm_sel = device_property_read_bool(dev, 1718 "snps,gfladj-refclk-lpm-sel-quirk"); 1719 1720 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, 1721 "snps,tx_de_emphasis_quirk"); 1722 device_property_read_u8(dev, "snps,tx_de_emphasis", 1723 &tx_de_emphasis); 1724 device_property_read_string(dev, "snps,hsphy_interface", 1725 &dwc->hsphy_interface); 1726 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", 1727 &dwc->fladj); 1728 device_property_read_u32(dev, "snps,ref-clock-period-ns", 1729 &dwc->ref_clk_per); 1730 1731 dwc->dis_metastability_quirk = device_property_read_bool(dev, 1732 "snps,dis_metastability_quirk"); 1733 1734 dwc->dis_split_quirk = device_property_read_bool(dev, 1735 "snps,dis-split-quirk"); 1736 1737 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 1738 dwc->tx_de_emphasis = tx_de_emphasis; 1739 1740 dwc->hird_threshold = hird_threshold; 1741 1742 dwc->rx_thr_num_pkt = rx_thr_num_pkt; 1743 dwc->rx_max_burst = rx_max_burst; 1744 1745 dwc->tx_thr_num_pkt = tx_thr_num_pkt; 1746 dwc->tx_max_burst = tx_max_burst; 1747 1748 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd; 1749 dwc->rx_max_burst_prd = rx_max_burst_prd; 1750 1751 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd; 1752 dwc->tx_max_burst_prd = tx_max_burst_prd; 1753 1754 dwc->imod_interval = 0; 1755 1756 dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num; 1757 } 1758 1759 /* check whether the core supports IMOD */ 1760 bool dwc3_has_imod(struct dwc3 *dwc) 1761 { 1762 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) || 1763 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) || 1764 DWC3_IP_IS(DWC32); 1765 } 1766 1767 static void dwc3_check_params(struct dwc3 *dwc) 1768 { 1769 struct device *dev = dwc->dev; 1770 unsigned int hwparam_gen = 1771 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3); 1772 1773 /* Check for proper value of imod_interval */ 1774 if (dwc->imod_interval && !dwc3_has_imod(dwc)) { 1775 dev_warn(dwc->dev, "Interrupt moderation not supported\n"); 1776 dwc->imod_interval = 0; 1777 } 1778 1779 /* 1780 * Workaround for STAR 9000961433 which affects only version 1781 * 3.00a of the DWC_usb3 core. This prevents the controller 1782 * interrupt from being masked while handling events. IMOD 1783 * allows us to work around this issue. Enable it for the 1784 * affected version. 1785 */ 1786 if (!dwc->imod_interval && 1787 DWC3_VER_IS(DWC3, 300A)) 1788 dwc->imod_interval = 1; 1789 1790 /* Check the maximum_speed parameter */ 1791 switch (dwc->maximum_speed) { 1792 case USB_SPEED_FULL: 1793 case USB_SPEED_HIGH: 1794 break; 1795 case USB_SPEED_SUPER: 1796 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) 1797 dev_warn(dev, "UDC doesn't support Gen 1\n"); 1798 break; 1799 case USB_SPEED_SUPER_PLUS: 1800 if ((DWC3_IP_IS(DWC32) && 1801 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) || 1802 (!DWC3_IP_IS(DWC32) && 1803 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) 1804 dev_warn(dev, "UDC doesn't support SSP\n"); 1805 break; 1806 default: 1807 dev_err(dev, "invalid maximum_speed parameter %d\n", 1808 dwc->maximum_speed); 1809 fallthrough; 1810 case USB_SPEED_UNKNOWN: 1811 switch (hwparam_gen) { 1812 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 1813 dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1814 break; 1815 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 1816 if (DWC3_IP_IS(DWC32)) 1817 dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1818 else 1819 dwc->maximum_speed = USB_SPEED_SUPER; 1820 break; 1821 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS: 1822 dwc->maximum_speed = USB_SPEED_HIGH; 1823 break; 1824 default: 1825 dwc->maximum_speed = USB_SPEED_SUPER; 1826 break; 1827 } 1828 break; 1829 } 1830 1831 /* 1832 * Currently the controller does not have visibility into the HW 1833 * parameter to determine the maximum number of lanes the HW supports. 1834 * If the number of lanes is not specified in the device property, then 1835 * set the default to support dual-lane for DWC_usb32 and single-lane 1836 * for DWC_usb31 for super-speed-plus. 1837 */ 1838 if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) { 1839 switch (dwc->max_ssp_rate) { 1840 case USB_SSP_GEN_2x1: 1841 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1) 1842 dev_warn(dev, "UDC only supports Gen 1\n"); 1843 break; 1844 case USB_SSP_GEN_1x2: 1845 case USB_SSP_GEN_2x2: 1846 if (DWC3_IP_IS(DWC31)) 1847 dev_warn(dev, "UDC only supports single lane\n"); 1848 break; 1849 case USB_SSP_GEN_UNKNOWN: 1850 default: 1851 switch (hwparam_gen) { 1852 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 1853 if (DWC3_IP_IS(DWC32)) 1854 dwc->max_ssp_rate = USB_SSP_GEN_2x2; 1855 else 1856 dwc->max_ssp_rate = USB_SSP_GEN_2x1; 1857 break; 1858 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 1859 if (DWC3_IP_IS(DWC32)) 1860 dwc->max_ssp_rate = USB_SSP_GEN_1x2; 1861 break; 1862 } 1863 break; 1864 } 1865 } 1866 } 1867 1868 static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc) 1869 { 1870 struct device *dev = dwc->dev; 1871 struct device_node *np_phy; 1872 struct extcon_dev *edev = NULL; 1873 const char *name; 1874 1875 if (device_property_read_bool(dev, "extcon")) 1876 return extcon_get_edev_by_phandle(dev, 0); 1877 1878 /* 1879 * Device tree platforms should get extcon via phandle. 1880 * On ACPI platforms, we get the name from a device property. 1881 * This device property is for kernel internal use only and 1882 * is expected to be set by the glue code. 1883 */ 1884 if (device_property_read_string(dev, "linux,extcon-name", &name) == 0) 1885 return extcon_get_extcon_dev(name); 1886 1887 /* 1888 * Check explicitly if "usb-role-switch" is used since 1889 * extcon_find_edev_by_node() can not be used to check the absence of 1890 * an extcon device. In the absence of an device it will always return 1891 * EPROBE_DEFER. 1892 */ 1893 if (IS_ENABLED(CONFIG_USB_ROLE_SWITCH) && 1894 device_property_read_bool(dev, "usb-role-switch")) 1895 return NULL; 1896 1897 /* 1898 * Try to get an extcon device from the USB PHY controller's "port" 1899 * node. Check if it has the "port" node first, to avoid printing the 1900 * error message from underlying code, as it's a valid case: extcon 1901 * device (and "port" node) may be missing in case of "usb-role-switch" 1902 * or OTG mode. 1903 */ 1904 np_phy = of_parse_phandle(dev->of_node, "phys", 0); 1905 if (of_graph_is_present(np_phy)) { 1906 struct device_node *np_conn; 1907 1908 np_conn = of_graph_get_remote_node(np_phy, -1, -1); 1909 if (np_conn) 1910 edev = extcon_find_edev_by_node(np_conn); 1911 of_node_put(np_conn); 1912 } 1913 of_node_put(np_phy); 1914 1915 return edev; 1916 } 1917 1918 static int dwc3_get_clocks(struct dwc3 *dwc) 1919 { 1920 struct device *dev = dwc->dev; 1921 1922 if (!dev->of_node) 1923 return 0; 1924 1925 /* 1926 * Clocks are optional, but new DT platforms should support all clocks 1927 * as required by the DT-binding. 1928 * Some devices have different clock names in legacy device trees, 1929 * check for them to retain backwards compatibility. 1930 */ 1931 dwc->bus_clk = devm_clk_get_optional(dev, "bus_early"); 1932 if (IS_ERR(dwc->bus_clk)) { 1933 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk), 1934 "could not get bus clock\n"); 1935 } 1936 1937 if (dwc->bus_clk == NULL) { 1938 dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk"); 1939 if (IS_ERR(dwc->bus_clk)) { 1940 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk), 1941 "could not get bus clock\n"); 1942 } 1943 } 1944 1945 dwc->ref_clk = devm_clk_get_optional(dev, "ref"); 1946 if (IS_ERR(dwc->ref_clk)) { 1947 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk), 1948 "could not get ref clock\n"); 1949 } 1950 1951 if (dwc->ref_clk == NULL) { 1952 dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk"); 1953 if (IS_ERR(dwc->ref_clk)) { 1954 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk), 1955 "could not get ref clock\n"); 1956 } 1957 } 1958 1959 dwc->susp_clk = devm_clk_get_optional(dev, "suspend"); 1960 if (IS_ERR(dwc->susp_clk)) { 1961 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk), 1962 "could not get suspend clock\n"); 1963 } 1964 1965 if (dwc->susp_clk == NULL) { 1966 dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk"); 1967 if (IS_ERR(dwc->susp_clk)) { 1968 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk), 1969 "could not get suspend clock\n"); 1970 } 1971 } 1972 1973 /* specific to Rockchip RK3588 */ 1974 dwc->utmi_clk = devm_clk_get_optional(dev, "utmi"); 1975 if (IS_ERR(dwc->utmi_clk)) { 1976 return dev_err_probe(dev, PTR_ERR(dwc->utmi_clk), 1977 "could not get utmi clock\n"); 1978 } 1979 1980 /* specific to Rockchip RK3588 */ 1981 dwc->pipe_clk = devm_clk_get_optional(dev, "pipe"); 1982 if (IS_ERR(dwc->pipe_clk)) { 1983 return dev_err_probe(dev, PTR_ERR(dwc->pipe_clk), 1984 "could not get pipe clock\n"); 1985 } 1986 1987 return 0; 1988 } 1989 1990 static int dwc3_get_num_ports(struct dwc3 *dwc) 1991 { 1992 void __iomem *base; 1993 u8 major_revision; 1994 u32 offset; 1995 u32 val; 1996 1997 /* 1998 * Remap xHCI address space to access XHCI ext cap regs since it is 1999 * needed to get information on number of ports present. 2000 */ 2001 base = ioremap(dwc->xhci_resources[0].start, 2002 resource_size(&dwc->xhci_resources[0])); 2003 if (!base) 2004 return -ENOMEM; 2005 2006 offset = 0; 2007 do { 2008 offset = xhci_find_next_ext_cap(base, offset, 2009 XHCI_EXT_CAPS_PROTOCOL); 2010 if (!offset) 2011 break; 2012 2013 val = readl(base + offset); 2014 major_revision = XHCI_EXT_PORT_MAJOR(val); 2015 2016 val = readl(base + offset + 0x08); 2017 if (major_revision == 0x03) { 2018 dwc->num_usb3_ports += XHCI_EXT_PORT_COUNT(val); 2019 } else if (major_revision <= 0x02) { 2020 dwc->num_usb2_ports += XHCI_EXT_PORT_COUNT(val); 2021 } else { 2022 dev_warn(dwc->dev, "unrecognized port major revision %d\n", 2023 major_revision); 2024 } 2025 } while (1); 2026 2027 dev_dbg(dwc->dev, "hs-ports: %u ss-ports: %u\n", 2028 dwc->num_usb2_ports, dwc->num_usb3_ports); 2029 2030 iounmap(base); 2031 2032 if (dwc->num_usb2_ports > DWC3_USB2_MAX_PORTS || 2033 dwc->num_usb3_ports > DWC3_USB3_MAX_PORTS) 2034 return -EINVAL; 2035 2036 return 0; 2037 } 2038 2039 static int dwc3_probe(struct platform_device *pdev) 2040 { 2041 struct device *dev = &pdev->dev; 2042 struct resource *res, dwc_res; 2043 unsigned int hw_mode; 2044 void __iomem *regs; 2045 struct dwc3 *dwc; 2046 int ret; 2047 2048 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 2049 if (!dwc) 2050 return -ENOMEM; 2051 2052 dwc->dev = dev; 2053 2054 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2055 if (!res) { 2056 dev_err(dev, "missing memory resource\n"); 2057 return -ENODEV; 2058 } 2059 2060 dwc->xhci_resources[0].start = res->start; 2061 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + 2062 DWC3_XHCI_REGS_END; 2063 dwc->xhci_resources[0].flags = res->flags; 2064 dwc->xhci_resources[0].name = res->name; 2065 2066 /* 2067 * Request memory region but exclude xHCI regs, 2068 * since it will be requested by the xhci-plat driver. 2069 */ 2070 dwc_res = *res; 2071 dwc_res.start += DWC3_GLOBALS_REGS_START; 2072 2073 if (dev->of_node) { 2074 struct device_node *parent = of_get_parent(dev->of_node); 2075 2076 if (of_device_is_compatible(parent, "realtek,rtd-dwc3")) { 2077 dwc_res.start -= DWC3_GLOBALS_REGS_START; 2078 dwc_res.start += DWC3_RTK_RTD_GLOBALS_REGS_START; 2079 } 2080 2081 of_node_put(parent); 2082 } 2083 2084 regs = devm_ioremap_resource(dev, &dwc_res); 2085 if (IS_ERR(regs)) 2086 return PTR_ERR(regs); 2087 2088 dwc->regs = regs; 2089 dwc->regs_size = resource_size(&dwc_res); 2090 2091 dwc3_get_properties(dwc); 2092 2093 dwc->reset = devm_reset_control_array_get_optional_shared(dev); 2094 if (IS_ERR(dwc->reset)) { 2095 ret = PTR_ERR(dwc->reset); 2096 goto err_put_psy; 2097 } 2098 2099 ret = dwc3_get_clocks(dwc); 2100 if (ret) 2101 goto err_put_psy; 2102 2103 ret = reset_control_deassert(dwc->reset); 2104 if (ret) 2105 goto err_put_psy; 2106 2107 ret = dwc3_clk_enable(dwc); 2108 if (ret) 2109 goto err_assert_reset; 2110 2111 if (!dwc3_core_is_valid(dwc)) { 2112 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 2113 ret = -ENODEV; 2114 goto err_disable_clks; 2115 } 2116 2117 platform_set_drvdata(pdev, dwc); 2118 dwc3_cache_hwparams(dwc); 2119 2120 if (!dwc->sysdev_is_parent && 2121 DWC3_GHWPARAMS0_AWIDTH(dwc->hwparams.hwparams0) == 64) { 2122 ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64)); 2123 if (ret) 2124 goto err_disable_clks; 2125 } 2126 2127 /* 2128 * Currently only DWC3 controllers that are host-only capable 2129 * can have more than one port. 2130 */ 2131 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 2132 if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) { 2133 ret = dwc3_get_num_ports(dwc); 2134 if (ret) 2135 goto err_disable_clks; 2136 } else { 2137 dwc->num_usb2_ports = 1; 2138 dwc->num_usb3_ports = 1; 2139 } 2140 2141 spin_lock_init(&dwc->lock); 2142 mutex_init(&dwc->mutex); 2143 2144 pm_runtime_get_noresume(dev); 2145 pm_runtime_set_active(dev); 2146 pm_runtime_use_autosuspend(dev); 2147 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); 2148 pm_runtime_enable(dev); 2149 2150 pm_runtime_forbid(dev); 2151 2152 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 2153 if (ret) { 2154 dev_err(dwc->dev, "failed to allocate event buffers\n"); 2155 ret = -ENOMEM; 2156 goto err_allow_rpm; 2157 } 2158 2159 dwc->edev = dwc3_get_extcon(dwc); 2160 if (IS_ERR(dwc->edev)) { 2161 ret = dev_err_probe(dwc->dev, PTR_ERR(dwc->edev), "failed to get extcon\n"); 2162 goto err_free_event_buffers; 2163 } 2164 2165 ret = dwc3_get_dr_mode(dwc); 2166 if (ret) 2167 goto err_free_event_buffers; 2168 2169 ret = dwc3_core_init(dwc); 2170 if (ret) { 2171 dev_err_probe(dev, ret, "failed to initialize core\n"); 2172 goto err_free_event_buffers; 2173 } 2174 2175 dwc3_check_params(dwc); 2176 dwc3_debugfs_init(dwc); 2177 2178 ret = dwc3_core_init_mode(dwc); 2179 if (ret) 2180 goto err_exit_debugfs; 2181 2182 pm_runtime_put(dev); 2183 2184 dma_set_max_seg_size(dev, UINT_MAX); 2185 2186 return 0; 2187 2188 err_exit_debugfs: 2189 dwc3_debugfs_exit(dwc); 2190 dwc3_event_buffers_cleanup(dwc); 2191 dwc3_phy_power_off(dwc); 2192 dwc3_phy_exit(dwc); 2193 dwc3_ulpi_exit(dwc); 2194 err_free_event_buffers: 2195 dwc3_free_event_buffers(dwc); 2196 err_allow_rpm: 2197 pm_runtime_allow(dev); 2198 pm_runtime_disable(dev); 2199 pm_runtime_dont_use_autosuspend(dev); 2200 pm_runtime_set_suspended(dev); 2201 pm_runtime_put_noidle(dev); 2202 err_disable_clks: 2203 dwc3_clk_disable(dwc); 2204 err_assert_reset: 2205 reset_control_assert(dwc->reset); 2206 err_put_psy: 2207 if (dwc->usb_psy) 2208 power_supply_put(dwc->usb_psy); 2209 2210 return ret; 2211 } 2212 2213 static void dwc3_remove(struct platform_device *pdev) 2214 { 2215 struct dwc3 *dwc = platform_get_drvdata(pdev); 2216 2217 pm_runtime_get_sync(&pdev->dev); 2218 2219 dwc3_core_exit_mode(dwc); 2220 dwc3_debugfs_exit(dwc); 2221 2222 dwc3_core_exit(dwc); 2223 dwc3_ulpi_exit(dwc); 2224 2225 pm_runtime_allow(&pdev->dev); 2226 pm_runtime_disable(&pdev->dev); 2227 pm_runtime_dont_use_autosuspend(&pdev->dev); 2228 pm_runtime_put_noidle(&pdev->dev); 2229 /* 2230 * HACK: Clear the driver data, which is currently accessed by parent 2231 * glue drivers, before allowing the parent to suspend. 2232 */ 2233 platform_set_drvdata(pdev, NULL); 2234 pm_runtime_set_suspended(&pdev->dev); 2235 2236 dwc3_free_event_buffers(dwc); 2237 2238 if (dwc->usb_psy) 2239 power_supply_put(dwc->usb_psy); 2240 } 2241 2242 #ifdef CONFIG_PM 2243 static int dwc3_core_init_for_resume(struct dwc3 *dwc) 2244 { 2245 int ret; 2246 2247 ret = reset_control_deassert(dwc->reset); 2248 if (ret) 2249 return ret; 2250 2251 ret = dwc3_clk_enable(dwc); 2252 if (ret) 2253 goto assert_reset; 2254 2255 ret = dwc3_core_init(dwc); 2256 if (ret) 2257 goto disable_clks; 2258 2259 return 0; 2260 2261 disable_clks: 2262 dwc3_clk_disable(dwc); 2263 assert_reset: 2264 reset_control_assert(dwc->reset); 2265 2266 return ret; 2267 } 2268 2269 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) 2270 { 2271 u32 reg; 2272 int i; 2273 2274 switch (dwc->current_dr_role) { 2275 case DWC3_GCTL_PRTCAP_DEVICE: 2276 if (pm_runtime_suspended(dwc->dev)) 2277 break; 2278 dwc3_gadget_suspend(dwc); 2279 synchronize_irq(dwc->irq_gadget); 2280 dwc3_core_exit(dwc); 2281 break; 2282 case DWC3_GCTL_PRTCAP_HOST: 2283 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) { 2284 dwc3_core_exit(dwc); 2285 break; 2286 } 2287 2288 /* Let controller to suspend HSPHY before PHY driver suspends */ 2289 if (dwc->dis_u2_susphy_quirk || 2290 dwc->dis_enblslpm_quirk) { 2291 for (i = 0; i < dwc->num_usb2_ports; i++) { 2292 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i)); 2293 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM | 2294 DWC3_GUSB2PHYCFG_SUSPHY; 2295 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg); 2296 } 2297 2298 /* Give some time for USB2 PHY to suspend */ 2299 usleep_range(5000, 6000); 2300 } 2301 2302 for (i = 0; i < dwc->num_usb2_ports; i++) 2303 phy_pm_runtime_put_sync(dwc->usb2_generic_phy[i]); 2304 for (i = 0; i < dwc->num_usb3_ports; i++) 2305 phy_pm_runtime_put_sync(dwc->usb3_generic_phy[i]); 2306 break; 2307 case DWC3_GCTL_PRTCAP_OTG: 2308 /* do nothing during runtime_suspend */ 2309 if (PMSG_IS_AUTO(msg)) 2310 break; 2311 2312 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 2313 dwc3_gadget_suspend(dwc); 2314 synchronize_irq(dwc->irq_gadget); 2315 } 2316 2317 dwc3_otg_exit(dwc); 2318 dwc3_core_exit(dwc); 2319 break; 2320 default: 2321 /* do nothing */ 2322 break; 2323 } 2324 2325 return 0; 2326 } 2327 2328 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) 2329 { 2330 int ret; 2331 u32 reg; 2332 int i; 2333 2334 switch (dwc->current_dr_role) { 2335 case DWC3_GCTL_PRTCAP_DEVICE: 2336 ret = dwc3_core_init_for_resume(dwc); 2337 if (ret) 2338 return ret; 2339 2340 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 2341 dwc3_gadget_resume(dwc); 2342 break; 2343 case DWC3_GCTL_PRTCAP_HOST: 2344 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) { 2345 ret = dwc3_core_init_for_resume(dwc); 2346 if (ret) 2347 return ret; 2348 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 2349 break; 2350 } 2351 /* Restore GUSB2PHYCFG bits that were modified in suspend */ 2352 for (i = 0; i < dwc->num_usb2_ports; i++) { 2353 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i)); 2354 if (dwc->dis_u2_susphy_quirk) 2355 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 2356 2357 if (dwc->dis_enblslpm_quirk) 2358 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 2359 2360 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg); 2361 } 2362 2363 for (i = 0; i < dwc->num_usb2_ports; i++) 2364 phy_pm_runtime_get_sync(dwc->usb2_generic_phy[i]); 2365 for (i = 0; i < dwc->num_usb3_ports; i++) 2366 phy_pm_runtime_get_sync(dwc->usb3_generic_phy[i]); 2367 break; 2368 case DWC3_GCTL_PRTCAP_OTG: 2369 /* nothing to do on runtime_resume */ 2370 if (PMSG_IS_AUTO(msg)) 2371 break; 2372 2373 ret = dwc3_core_init_for_resume(dwc); 2374 if (ret) 2375 return ret; 2376 2377 dwc3_set_prtcap(dwc, dwc->current_dr_role); 2378 2379 dwc3_otg_init(dwc); 2380 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) { 2381 dwc3_otg_host_init(dwc); 2382 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 2383 dwc3_gadget_resume(dwc); 2384 } 2385 2386 break; 2387 default: 2388 /* do nothing */ 2389 break; 2390 } 2391 2392 return 0; 2393 } 2394 2395 static int dwc3_runtime_checks(struct dwc3 *dwc) 2396 { 2397 switch (dwc->current_dr_role) { 2398 case DWC3_GCTL_PRTCAP_DEVICE: 2399 if (dwc->connected) 2400 return -EBUSY; 2401 break; 2402 case DWC3_GCTL_PRTCAP_HOST: 2403 default: 2404 /* do nothing */ 2405 break; 2406 } 2407 2408 return 0; 2409 } 2410 2411 static int dwc3_runtime_suspend(struct device *dev) 2412 { 2413 struct dwc3 *dwc = dev_get_drvdata(dev); 2414 int ret; 2415 2416 if (dwc3_runtime_checks(dwc)) 2417 return -EBUSY; 2418 2419 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND); 2420 if (ret) 2421 return ret; 2422 2423 return 0; 2424 } 2425 2426 static int dwc3_runtime_resume(struct device *dev) 2427 { 2428 struct dwc3 *dwc = dev_get_drvdata(dev); 2429 int ret; 2430 2431 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME); 2432 if (ret) 2433 return ret; 2434 2435 switch (dwc->current_dr_role) { 2436 case DWC3_GCTL_PRTCAP_DEVICE: 2437 dwc3_gadget_process_pending_events(dwc); 2438 break; 2439 case DWC3_GCTL_PRTCAP_HOST: 2440 default: 2441 /* do nothing */ 2442 break; 2443 } 2444 2445 pm_runtime_mark_last_busy(dev); 2446 2447 return 0; 2448 } 2449 2450 static int dwc3_runtime_idle(struct device *dev) 2451 { 2452 struct dwc3 *dwc = dev_get_drvdata(dev); 2453 2454 switch (dwc->current_dr_role) { 2455 case DWC3_GCTL_PRTCAP_DEVICE: 2456 if (dwc3_runtime_checks(dwc)) 2457 return -EBUSY; 2458 break; 2459 case DWC3_GCTL_PRTCAP_HOST: 2460 default: 2461 /* do nothing */ 2462 break; 2463 } 2464 2465 pm_runtime_mark_last_busy(dev); 2466 pm_runtime_autosuspend(dev); 2467 2468 return 0; 2469 } 2470 #endif /* CONFIG_PM */ 2471 2472 #ifdef CONFIG_PM_SLEEP 2473 static int dwc3_suspend(struct device *dev) 2474 { 2475 struct dwc3 *dwc = dev_get_drvdata(dev); 2476 int ret; 2477 2478 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND); 2479 if (ret) 2480 return ret; 2481 2482 pinctrl_pm_select_sleep_state(dev); 2483 2484 return 0; 2485 } 2486 2487 static int dwc3_resume(struct device *dev) 2488 { 2489 struct dwc3 *dwc = dev_get_drvdata(dev); 2490 int ret; 2491 2492 pinctrl_pm_select_default_state(dev); 2493 2494 pm_runtime_disable(dev); 2495 pm_runtime_set_active(dev); 2496 2497 ret = dwc3_resume_common(dwc, PMSG_RESUME); 2498 if (ret) { 2499 pm_runtime_set_suspended(dev); 2500 return ret; 2501 } 2502 2503 pm_runtime_enable(dev); 2504 2505 return 0; 2506 } 2507 2508 static void dwc3_complete(struct device *dev) 2509 { 2510 struct dwc3 *dwc = dev_get_drvdata(dev); 2511 u32 reg; 2512 2513 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST && 2514 dwc->dis_split_quirk) { 2515 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 2516 reg |= DWC3_GUCTL3_SPLITDISABLE; 2517 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 2518 } 2519 } 2520 #else 2521 #define dwc3_complete NULL 2522 #endif /* CONFIG_PM_SLEEP */ 2523 2524 static const struct dev_pm_ops dwc3_dev_pm_ops = { 2525 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) 2526 .complete = dwc3_complete, 2527 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, 2528 dwc3_runtime_idle) 2529 }; 2530 2531 #ifdef CONFIG_OF 2532 static const struct of_device_id of_dwc3_match[] = { 2533 { 2534 .compatible = "snps,dwc3" 2535 }, 2536 { 2537 .compatible = "synopsys,dwc3" 2538 }, 2539 { }, 2540 }; 2541 MODULE_DEVICE_TABLE(of, of_dwc3_match); 2542 #endif 2543 2544 #ifdef CONFIG_ACPI 2545 2546 #define ACPI_ID_INTEL_BSW "808622B7" 2547 2548 static const struct acpi_device_id dwc3_acpi_match[] = { 2549 { ACPI_ID_INTEL_BSW, 0 }, 2550 { }, 2551 }; 2552 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); 2553 #endif 2554 2555 static struct platform_driver dwc3_driver = { 2556 .probe = dwc3_probe, 2557 .remove_new = dwc3_remove, 2558 .driver = { 2559 .name = "dwc3", 2560 .of_match_table = of_match_ptr(of_dwc3_match), 2561 .acpi_match_table = ACPI_PTR(dwc3_acpi_match), 2562 .pm = &dwc3_dev_pm_ops, 2563 }, 2564 }; 2565 2566 module_platform_driver(dwc3_driver); 2567 2568 MODULE_ALIAS("platform:dwc3"); 2569 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 2570 MODULE_LICENSE("GPL v2"); 2571 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 2572