1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* 3 * platform.c - DesignWare HS OTG Controller platform driver 4 * 5 * Copyright (C) Matthijs Kooijman <matthijs@stdin.nl> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The names of the above-listed copyright holders may not be used 17 * to endorse or promote products derived from this software without 18 * specific prior written permission. 19 * 20 * ALTERNATIVELY, this software may be distributed under the terms of the 21 * GNU General Public License ("GPL") as published by the Free Software 22 * Foundation; either version 2 of the License, or (at your option) any 23 * later version. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <linux/kernel.h> 39 #include <linux/module.h> 40 #include <linux/slab.h> 41 #include <linux/clk.h> 42 #include <linux/device.h> 43 #include <linux/dma-mapping.h> 44 #include <linux/of_device.h> 45 #include <linux/mutex.h> 46 #include <linux/platform_device.h> 47 #include <linux/phy/phy.h> 48 #include <linux/platform_data/s3c-hsotg.h> 49 #include <linux/reset.h> 50 51 #include <linux/usb/of.h> 52 53 #include "core.h" 54 #include "hcd.h" 55 #include "debug.h" 56 57 static const char dwc2_driver_name[] = "dwc2"; 58 59 /* 60 * Check the dr_mode against the module configuration and hardware 61 * capabilities. 62 * 63 * The hardware, module, and dr_mode, can each be set to host, device, 64 * or otg. Check that all these values are compatible and adjust the 65 * value of dr_mode if possible. 66 * 67 * actual 68 * HW MOD dr_mode dr_mode 69 * ------------------------------ 70 * HST HST any : HST 71 * HST DEV any : --- 72 * HST OTG any : HST 73 * 74 * DEV HST any : --- 75 * DEV DEV any : DEV 76 * DEV OTG any : DEV 77 * 78 * OTG HST any : HST 79 * OTG DEV any : DEV 80 * OTG OTG any : dr_mode 81 */ 82 static int dwc2_get_dr_mode(struct dwc2_hsotg *hsotg) 83 { 84 enum usb_dr_mode mode; 85 86 hsotg->dr_mode = usb_get_dr_mode(hsotg->dev); 87 if (hsotg->dr_mode == USB_DR_MODE_UNKNOWN) 88 hsotg->dr_mode = USB_DR_MODE_OTG; 89 90 mode = hsotg->dr_mode; 91 92 if (dwc2_hw_is_device(hsotg)) { 93 if (IS_ENABLED(CONFIG_USB_DWC2_HOST)) { 94 dev_err(hsotg->dev, 95 "Controller does not support host mode.\n"); 96 return -EINVAL; 97 } 98 mode = USB_DR_MODE_PERIPHERAL; 99 } else if (dwc2_hw_is_host(hsotg)) { 100 if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL)) { 101 dev_err(hsotg->dev, 102 "Controller does not support device mode.\n"); 103 return -EINVAL; 104 } 105 mode = USB_DR_MODE_HOST; 106 } else { 107 if (IS_ENABLED(CONFIG_USB_DWC2_HOST)) 108 mode = USB_DR_MODE_HOST; 109 else if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL)) 110 mode = USB_DR_MODE_PERIPHERAL; 111 } 112 113 if (mode != hsotg->dr_mode) { 114 dev_warn(hsotg->dev, 115 "Configuration mismatch. dr_mode forced to %s\n", 116 mode == USB_DR_MODE_HOST ? "host" : "device"); 117 118 hsotg->dr_mode = mode; 119 } 120 121 return 0; 122 } 123 124 static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg) 125 { 126 struct platform_device *pdev = to_platform_device(hsotg->dev); 127 int ret; 128 129 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies), 130 hsotg->supplies); 131 if (ret) 132 return ret; 133 134 if (hsotg->clk) { 135 ret = clk_prepare_enable(hsotg->clk); 136 if (ret) 137 return ret; 138 } 139 140 if (hsotg->uphy) { 141 ret = usb_phy_init(hsotg->uphy); 142 } else if (hsotg->plat && hsotg->plat->phy_init) { 143 ret = hsotg->plat->phy_init(pdev, hsotg->plat->phy_type); 144 } else { 145 ret = phy_power_on(hsotg->phy); 146 if (ret == 0) 147 ret = phy_init(hsotg->phy); 148 } 149 150 return ret; 151 } 152 153 /** 154 * dwc2_lowlevel_hw_enable - enable platform lowlevel hw resources 155 * @hsotg: The driver state 156 * 157 * A wrapper for platform code responsible for controlling 158 * low-level USB platform resources (phy, clock, regulators) 159 */ 160 int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg) 161 { 162 int ret = __dwc2_lowlevel_hw_enable(hsotg); 163 164 if (ret == 0) 165 hsotg->ll_hw_enabled = true; 166 return ret; 167 } 168 169 static int __dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg) 170 { 171 struct platform_device *pdev = to_platform_device(hsotg->dev); 172 int ret = 0; 173 174 if (hsotg->uphy) { 175 usb_phy_shutdown(hsotg->uphy); 176 } else if (hsotg->plat && hsotg->plat->phy_exit) { 177 ret = hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type); 178 } else { 179 ret = phy_exit(hsotg->phy); 180 if (ret == 0) 181 ret = phy_power_off(hsotg->phy); 182 } 183 if (ret) 184 return ret; 185 186 if (hsotg->clk) 187 clk_disable_unprepare(hsotg->clk); 188 189 ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), 190 hsotg->supplies); 191 192 return ret; 193 } 194 195 /** 196 * dwc2_lowlevel_hw_disable - disable platform lowlevel hw resources 197 * @hsotg: The driver state 198 * 199 * A wrapper for platform code responsible for controlling 200 * low-level USB platform resources (phy, clock, regulators) 201 */ 202 int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg) 203 { 204 int ret = __dwc2_lowlevel_hw_disable(hsotg); 205 206 if (ret == 0) 207 hsotg->ll_hw_enabled = false; 208 return ret; 209 } 210 211 static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg) 212 { 213 int i, ret; 214 215 hsotg->reset = devm_reset_control_get_optional(hsotg->dev, "dwc2"); 216 if (IS_ERR(hsotg->reset)) { 217 ret = PTR_ERR(hsotg->reset); 218 dev_err(hsotg->dev, "error getting reset control %d\n", ret); 219 return ret; 220 } 221 222 reset_control_deassert(hsotg->reset); 223 224 hsotg->reset_ecc = devm_reset_control_get_optional(hsotg->dev, "dwc2-ecc"); 225 if (IS_ERR(hsotg->reset_ecc)) { 226 ret = PTR_ERR(hsotg->reset_ecc); 227 dev_err(hsotg->dev, "error getting reset control for ecc %d\n", ret); 228 return ret; 229 } 230 231 reset_control_deassert(hsotg->reset_ecc); 232 233 /* 234 * Attempt to find a generic PHY, then look for an old style 235 * USB PHY and then fall back to pdata 236 */ 237 hsotg->phy = devm_phy_get(hsotg->dev, "usb2-phy"); 238 if (IS_ERR(hsotg->phy)) { 239 ret = PTR_ERR(hsotg->phy); 240 switch (ret) { 241 case -ENODEV: 242 case -ENOSYS: 243 hsotg->phy = NULL; 244 break; 245 case -EPROBE_DEFER: 246 return ret; 247 default: 248 dev_err(hsotg->dev, "error getting phy %d\n", ret); 249 return ret; 250 } 251 } 252 253 if (!hsotg->phy) { 254 hsotg->uphy = devm_usb_get_phy(hsotg->dev, USB_PHY_TYPE_USB2); 255 if (IS_ERR(hsotg->uphy)) { 256 ret = PTR_ERR(hsotg->uphy); 257 switch (ret) { 258 case -ENODEV: 259 case -ENXIO: 260 hsotg->uphy = NULL; 261 break; 262 case -EPROBE_DEFER: 263 return ret; 264 default: 265 dev_err(hsotg->dev, "error getting usb phy %d\n", 266 ret); 267 return ret; 268 } 269 } 270 } 271 272 hsotg->plat = dev_get_platdata(hsotg->dev); 273 274 if (hsotg->phy) { 275 /* 276 * If using the generic PHY framework, check if the PHY bus 277 * width is 8-bit and set the phyif appropriately. 278 */ 279 if (phy_get_bus_width(hsotg->phy) == 8) 280 hsotg->params.phy_utmi_width = 8; 281 } 282 283 /* Clock */ 284 hsotg->clk = devm_clk_get_optional(hsotg->dev, "otg"); 285 if (IS_ERR(hsotg->clk)) { 286 dev_err(hsotg->dev, "cannot get otg clock\n"); 287 return PTR_ERR(hsotg->clk); 288 } 289 290 /* Regulators */ 291 for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++) 292 hsotg->supplies[i].supply = dwc2_hsotg_supply_names[i]; 293 294 ret = devm_regulator_bulk_get(hsotg->dev, ARRAY_SIZE(hsotg->supplies), 295 hsotg->supplies); 296 if (ret) { 297 dev_err(hsotg->dev, "failed to request supplies: %d\n", ret); 298 return ret; 299 } 300 return 0; 301 } 302 303 /** 304 * dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the 305 * DWC_otg driver 306 * 307 * @dev: Platform device 308 * 309 * This routine is called, for example, when the rmmod command is executed. The 310 * device may or may not be electrically present. If it is present, the driver 311 * stops device processing. Any resources used on behalf of this device are 312 * freed. 313 */ 314 static int dwc2_driver_remove(struct platform_device *dev) 315 { 316 struct dwc2_hsotg *hsotg = platform_get_drvdata(dev); 317 318 dwc2_debugfs_exit(hsotg); 319 if (hsotg->hcd_enabled) 320 dwc2_hcd_remove(hsotg); 321 if (hsotg->gadget_enabled) 322 dwc2_hsotg_remove(hsotg); 323 324 if (hsotg->ll_hw_enabled) 325 dwc2_lowlevel_hw_disable(hsotg); 326 327 reset_control_assert(hsotg->reset); 328 reset_control_assert(hsotg->reset_ecc); 329 330 return 0; 331 } 332 333 /** 334 * dwc2_driver_shutdown() - Called on device shutdown 335 * 336 * @dev: Platform device 337 * 338 * In specific conditions (involving usb hubs) dwc2 devices can create a 339 * lot of interrupts, even to the point of overwhelming devices running 340 * at low frequencies. Some devices need to do special clock handling 341 * at shutdown-time which may bring the system clock below the threshold 342 * of being able to handle the dwc2 interrupts. Disabling dwc2-irqs 343 * prevents reboots/poweroffs from getting stuck in such cases. 344 */ 345 static void dwc2_driver_shutdown(struct platform_device *dev) 346 { 347 struct dwc2_hsotg *hsotg = platform_get_drvdata(dev); 348 349 disable_irq(hsotg->irq); 350 } 351 352 /** 353 * dwc2_check_core_endianness() - Returns true if core and AHB have 354 * opposite endianness. 355 * @hsotg: Programming view of the DWC_otg controller. 356 */ 357 static bool dwc2_check_core_endianness(struct dwc2_hsotg *hsotg) 358 { 359 u32 snpsid; 360 361 snpsid = ioread32(hsotg->regs + GSNPSID); 362 if ((snpsid & GSNPSID_ID_MASK) == DWC2_OTG_ID || 363 (snpsid & GSNPSID_ID_MASK) == DWC2_FS_IOT_ID || 364 (snpsid & GSNPSID_ID_MASK) == DWC2_HS_IOT_ID) 365 return false; 366 return true; 367 } 368 369 /** 370 * dwc2_driver_probe() - Called when the DWC_otg core is bound to the DWC_otg 371 * driver 372 * 373 * @dev: Platform device 374 * 375 * This routine creates the driver components required to control the device 376 * (core, HCD, and PCD) and initializes the device. The driver components are 377 * stored in a dwc2_hsotg structure. A reference to the dwc2_hsotg is saved 378 * in the device private data. This allows the driver to access the dwc2_hsotg 379 * structure on subsequent calls to driver methods for this device. 380 */ 381 static int dwc2_driver_probe(struct platform_device *dev) 382 { 383 struct dwc2_hsotg *hsotg; 384 struct resource *res; 385 int retval; 386 387 hsotg = devm_kzalloc(&dev->dev, sizeof(*hsotg), GFP_KERNEL); 388 if (!hsotg) 389 return -ENOMEM; 390 391 hsotg->dev = &dev->dev; 392 393 /* 394 * Use reasonable defaults so platforms don't have to provide these. 395 */ 396 if (!dev->dev.dma_mask) 397 dev->dev.dma_mask = &dev->dev.coherent_dma_mask; 398 retval = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32)); 399 if (retval) { 400 dev_err(&dev->dev, "can't set coherent DMA mask: %d\n", retval); 401 return retval; 402 } 403 404 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 405 hsotg->regs = devm_ioremap_resource(&dev->dev, res); 406 if (IS_ERR(hsotg->regs)) 407 return PTR_ERR(hsotg->regs); 408 409 dev_dbg(&dev->dev, "mapped PA %08lx to VA %p\n", 410 (unsigned long)res->start, hsotg->regs); 411 412 retval = dwc2_lowlevel_hw_init(hsotg); 413 if (retval) 414 return retval; 415 416 spin_lock_init(&hsotg->lock); 417 418 hsotg->irq = platform_get_irq(dev, 0); 419 if (hsotg->irq < 0) { 420 dev_err(&dev->dev, "missing IRQ resource\n"); 421 return hsotg->irq; 422 } 423 424 dev_dbg(hsotg->dev, "registering common handler for irq%d\n", 425 hsotg->irq); 426 retval = devm_request_irq(hsotg->dev, hsotg->irq, 427 dwc2_handle_common_intr, IRQF_SHARED, 428 dev_name(hsotg->dev), hsotg); 429 if (retval) 430 return retval; 431 432 hsotg->vbus_supply = devm_regulator_get_optional(hsotg->dev, "vbus"); 433 if (IS_ERR(hsotg->vbus_supply)) { 434 retval = PTR_ERR(hsotg->vbus_supply); 435 hsotg->vbus_supply = NULL; 436 if (retval != -ENODEV) 437 return retval; 438 } 439 440 retval = dwc2_lowlevel_hw_enable(hsotg); 441 if (retval) 442 return retval; 443 444 hsotg->needs_byte_swap = dwc2_check_core_endianness(hsotg); 445 446 retval = dwc2_get_dr_mode(hsotg); 447 if (retval) 448 goto error; 449 450 /* 451 * Reset before dwc2_get_hwparams() then it could get power-on real 452 * reset value form registers. 453 */ 454 retval = dwc2_core_reset(hsotg, false); 455 if (retval) 456 goto error; 457 458 /* Detect config values from hardware */ 459 retval = dwc2_get_hwparams(hsotg); 460 if (retval) 461 goto error; 462 463 /* 464 * For OTG cores, set the force mode bits to reflect the value 465 * of dr_mode. Force mode bits should not be touched at any 466 * other time after this. 467 */ 468 dwc2_force_dr_mode(hsotg); 469 470 retval = dwc2_init_params(hsotg); 471 if (retval) 472 goto error; 473 474 if (hsotg->dr_mode != USB_DR_MODE_HOST) { 475 retval = dwc2_gadget_init(hsotg); 476 if (retval) 477 goto error; 478 hsotg->gadget_enabled = 1; 479 } 480 481 hsotg->reset_phy_on_wake = 482 of_property_read_bool(dev->dev.of_node, 483 "snps,reset-phy-on-wake"); 484 if (hsotg->reset_phy_on_wake && !hsotg->phy) { 485 dev_warn(hsotg->dev, 486 "Quirk reset-phy-on-wake only supports generic PHYs\n"); 487 hsotg->reset_phy_on_wake = false; 488 } 489 490 if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) { 491 retval = dwc2_hcd_init(hsotg); 492 if (retval) { 493 if (hsotg->gadget_enabled) 494 dwc2_hsotg_remove(hsotg); 495 goto error; 496 } 497 hsotg->hcd_enabled = 1; 498 } 499 500 platform_set_drvdata(dev, hsotg); 501 hsotg->hibernated = 0; 502 503 dwc2_debugfs_init(hsotg); 504 505 /* Gadget code manages lowlevel hw on its own */ 506 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) 507 dwc2_lowlevel_hw_disable(hsotg); 508 509 return 0; 510 511 error: 512 dwc2_lowlevel_hw_disable(hsotg); 513 return retval; 514 } 515 516 static int __maybe_unused dwc2_suspend(struct device *dev) 517 { 518 struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev); 519 int ret = 0; 520 521 if (dwc2_is_device_mode(dwc2)) 522 dwc2_hsotg_suspend(dwc2); 523 524 if (dwc2->ll_hw_enabled) 525 ret = __dwc2_lowlevel_hw_disable(dwc2); 526 527 return ret; 528 } 529 530 static int __maybe_unused dwc2_resume(struct device *dev) 531 { 532 struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev); 533 int ret = 0; 534 535 if (dwc2->ll_hw_enabled) { 536 ret = __dwc2_lowlevel_hw_enable(dwc2); 537 if (ret) 538 return ret; 539 } 540 541 if (dwc2_is_device_mode(dwc2)) 542 ret = dwc2_hsotg_resume(dwc2); 543 544 return ret; 545 } 546 547 static const struct dev_pm_ops dwc2_dev_pm_ops = { 548 SET_SYSTEM_SLEEP_PM_OPS(dwc2_suspend, dwc2_resume) 549 }; 550 551 static struct platform_driver dwc2_platform_driver = { 552 .driver = { 553 .name = dwc2_driver_name, 554 .of_match_table = dwc2_of_match_table, 555 .pm = &dwc2_dev_pm_ops, 556 }, 557 .probe = dwc2_driver_probe, 558 .remove = dwc2_driver_remove, 559 .shutdown = dwc2_driver_shutdown, 560 }; 561 562 module_platform_driver(dwc2_platform_driver); 563 564 MODULE_DESCRIPTION("DESIGNWARE HS OTG Platform Glue"); 565 MODULE_AUTHOR("Matthijs Kooijman <matthijs@stdin.nl>"); 566 MODULE_LICENSE("Dual BSD/GPL"); 567