1 /* 2 * platform.c - DesignWare HS OTG Controller platform driver 3 * 4 * Copyright (C) Matthijs Kooijman <matthijs@stdin.nl> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The names of the above-listed copyright holders may not be used 16 * to endorse or promote products derived from this software without 17 * specific prior written permission. 18 * 19 * ALTERNATIVELY, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") as published by the Free Software 21 * Foundation; either version 2 of the License, or (at your option) any 22 * later version. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <linux/kernel.h> 38 #include <linux/module.h> 39 #include <linux/slab.h> 40 #include <linux/clk.h> 41 #include <linux/device.h> 42 #include <linux/dma-mapping.h> 43 #include <linux/of_device.h> 44 #include <linux/mutex.h> 45 #include <linux/platform_device.h> 46 #include <linux/phy/phy.h> 47 #include <linux/platform_data/s3c-hsotg.h> 48 49 #include <linux/usb/of.h> 50 51 #include "core.h" 52 #include "hcd.h" 53 #include "debug.h" 54 55 static const char dwc2_driver_name[] = "dwc2"; 56 57 static const struct dwc2_core_params params_hi6220 = { 58 .otg_cap = 2, /* No HNP/SRP capable */ 59 .otg_ver = 0, /* 1.3 */ 60 .dma_enable = 1, 61 .dma_desc_enable = 0, 62 .dma_desc_fs_enable = 0, 63 .speed = 0, /* High Speed */ 64 .enable_dynamic_fifo = 1, 65 .en_multiple_tx_fifo = 1, 66 .host_rx_fifo_size = 512, 67 .host_nperio_tx_fifo_size = 512, 68 .host_perio_tx_fifo_size = 512, 69 .max_transfer_size = 65535, 70 .max_packet_count = 511, 71 .host_channels = 16, 72 .phy_type = 1, /* UTMI */ 73 .phy_utmi_width = 8, 74 .phy_ulpi_ddr = 0, /* Single */ 75 .phy_ulpi_ext_vbus = 0, 76 .i2c_enable = 0, 77 .ulpi_fs_ls = 0, 78 .host_support_fs_ls_low_power = 0, 79 .host_ls_low_power_phy_clk = 0, /* 48 MHz */ 80 .ts_dline = 0, 81 .reload_ctl = 0, 82 .ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 83 GAHBCFG_HBSTLEN_SHIFT, 84 .uframe_sched = 0, 85 .external_id_pin_ctl = -1, 86 .hibernation = -1, 87 }; 88 89 static const struct dwc2_core_params params_bcm2835 = { 90 .otg_cap = 0, /* HNP/SRP capable */ 91 .otg_ver = 0, /* 1.3 */ 92 .dma_enable = 1, 93 .dma_desc_enable = 0, 94 .dma_desc_fs_enable = 0, 95 .speed = 0, /* High Speed */ 96 .enable_dynamic_fifo = 1, 97 .en_multiple_tx_fifo = 1, 98 .host_rx_fifo_size = 774, /* 774 DWORDs */ 99 .host_nperio_tx_fifo_size = 256, /* 256 DWORDs */ 100 .host_perio_tx_fifo_size = 512, /* 512 DWORDs */ 101 .max_transfer_size = 65535, 102 .max_packet_count = 511, 103 .host_channels = 8, 104 .phy_type = 1, /* UTMI */ 105 .phy_utmi_width = 8, /* 8 bits */ 106 .phy_ulpi_ddr = 0, /* Single */ 107 .phy_ulpi_ext_vbus = 0, 108 .i2c_enable = 0, 109 .ulpi_fs_ls = 0, 110 .host_support_fs_ls_low_power = 0, 111 .host_ls_low_power_phy_clk = 0, /* 48 MHz */ 112 .ts_dline = 0, 113 .reload_ctl = 0, 114 .ahbcfg = 0x10, 115 .uframe_sched = 0, 116 .external_id_pin_ctl = -1, 117 .hibernation = -1, 118 }; 119 120 static const struct dwc2_core_params params_rk3066 = { 121 .otg_cap = 2, /* non-HNP/non-SRP */ 122 .otg_ver = -1, 123 .dma_enable = -1, 124 .dma_desc_enable = 0, 125 .dma_desc_fs_enable = 0, 126 .speed = -1, 127 .enable_dynamic_fifo = 1, 128 .en_multiple_tx_fifo = -1, 129 .host_rx_fifo_size = 520, /* 520 DWORDs */ 130 .host_nperio_tx_fifo_size = 128, /* 128 DWORDs */ 131 .host_perio_tx_fifo_size = 256, /* 256 DWORDs */ 132 .max_transfer_size = 65535, 133 .max_packet_count = -1, 134 .host_channels = -1, 135 .phy_type = -1, 136 .phy_utmi_width = -1, 137 .phy_ulpi_ddr = -1, 138 .phy_ulpi_ext_vbus = -1, 139 .i2c_enable = -1, 140 .ulpi_fs_ls = -1, 141 .host_support_fs_ls_low_power = -1, 142 .host_ls_low_power_phy_clk = -1, 143 .ts_dline = -1, 144 .reload_ctl = -1, 145 .ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 146 GAHBCFG_HBSTLEN_SHIFT, 147 .uframe_sched = -1, 148 .external_id_pin_ctl = -1, 149 .hibernation = -1, 150 }; 151 152 /* 153 * Check the dr_mode against the module configuration and hardware 154 * capabilities. 155 * 156 * The hardware, module, and dr_mode, can each be set to host, device, 157 * or otg. Check that all these values are compatible and adjust the 158 * value of dr_mode if possible. 159 * 160 * actual 161 * HW MOD dr_mode dr_mode 162 * ------------------------------ 163 * HST HST any : HST 164 * HST DEV any : --- 165 * HST OTG any : HST 166 * 167 * DEV HST any : --- 168 * DEV DEV any : DEV 169 * DEV OTG any : DEV 170 * 171 * OTG HST any : HST 172 * OTG DEV any : DEV 173 * OTG OTG any : dr_mode 174 */ 175 static int dwc2_get_dr_mode(struct dwc2_hsotg *hsotg) 176 { 177 enum usb_dr_mode mode; 178 179 hsotg->dr_mode = usb_get_dr_mode(hsotg->dev); 180 if (hsotg->dr_mode == USB_DR_MODE_UNKNOWN) 181 hsotg->dr_mode = USB_DR_MODE_OTG; 182 183 mode = hsotg->dr_mode; 184 185 if (dwc2_hw_is_device(hsotg)) { 186 if (IS_ENABLED(CONFIG_USB_DWC2_HOST)) { 187 dev_err(hsotg->dev, 188 "Controller does not support host mode.\n"); 189 return -EINVAL; 190 } 191 mode = USB_DR_MODE_PERIPHERAL; 192 } else if (dwc2_hw_is_host(hsotg)) { 193 if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL)) { 194 dev_err(hsotg->dev, 195 "Controller does not support device mode.\n"); 196 return -EINVAL; 197 } 198 mode = USB_DR_MODE_HOST; 199 } else { 200 if (IS_ENABLED(CONFIG_USB_DWC2_HOST)) 201 mode = USB_DR_MODE_HOST; 202 else if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL)) 203 mode = USB_DR_MODE_PERIPHERAL; 204 } 205 206 if (mode != hsotg->dr_mode) { 207 dev_warn(hsotg->dev, 208 "Configuration mismatch. dr_mode forced to %s\n", 209 mode == USB_DR_MODE_HOST ? "host" : "device"); 210 211 hsotg->dr_mode = mode; 212 } 213 214 return 0; 215 } 216 217 static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg) 218 { 219 struct platform_device *pdev = to_platform_device(hsotg->dev); 220 int ret; 221 222 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies), 223 hsotg->supplies); 224 if (ret) 225 return ret; 226 227 if (hsotg->clk) { 228 ret = clk_prepare_enable(hsotg->clk); 229 if (ret) 230 return ret; 231 } 232 233 if (hsotg->uphy) 234 ret = usb_phy_init(hsotg->uphy); 235 else if (hsotg->plat && hsotg->plat->phy_init) 236 ret = hsotg->plat->phy_init(pdev, hsotg->plat->phy_type); 237 else { 238 ret = phy_power_on(hsotg->phy); 239 if (ret == 0) 240 ret = phy_init(hsotg->phy); 241 } 242 243 return ret; 244 } 245 246 /** 247 * dwc2_lowlevel_hw_enable - enable platform lowlevel hw resources 248 * @hsotg: The driver state 249 * 250 * A wrapper for platform code responsible for controlling 251 * low-level USB platform resources (phy, clock, regulators) 252 */ 253 int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg) 254 { 255 int ret = __dwc2_lowlevel_hw_enable(hsotg); 256 257 if (ret == 0) 258 hsotg->ll_hw_enabled = true; 259 return ret; 260 } 261 262 static int __dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg) 263 { 264 struct platform_device *pdev = to_platform_device(hsotg->dev); 265 int ret = 0; 266 267 if (hsotg->uphy) 268 usb_phy_shutdown(hsotg->uphy); 269 else if (hsotg->plat && hsotg->plat->phy_exit) 270 ret = hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type); 271 else { 272 ret = phy_exit(hsotg->phy); 273 if (ret == 0) 274 ret = phy_power_off(hsotg->phy); 275 } 276 if (ret) 277 return ret; 278 279 if (hsotg->clk) 280 clk_disable_unprepare(hsotg->clk); 281 282 ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), 283 hsotg->supplies); 284 285 return ret; 286 } 287 288 /** 289 * dwc2_lowlevel_hw_disable - disable platform lowlevel hw resources 290 * @hsotg: The driver state 291 * 292 * A wrapper for platform code responsible for controlling 293 * low-level USB platform resources (phy, clock, regulators) 294 */ 295 int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg) 296 { 297 int ret = __dwc2_lowlevel_hw_disable(hsotg); 298 299 if (ret == 0) 300 hsotg->ll_hw_enabled = false; 301 return ret; 302 } 303 304 static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg) 305 { 306 int i, ret; 307 308 /* Set default UTMI width */ 309 hsotg->phyif = GUSBCFG_PHYIF16; 310 311 /* 312 * Attempt to find a generic PHY, then look for an old style 313 * USB PHY and then fall back to pdata 314 */ 315 hsotg->phy = devm_phy_get(hsotg->dev, "usb2-phy"); 316 if (IS_ERR(hsotg->phy)) { 317 ret = PTR_ERR(hsotg->phy); 318 switch (ret) { 319 case -ENODEV: 320 case -ENOSYS: 321 hsotg->phy = NULL; 322 break; 323 case -EPROBE_DEFER: 324 return ret; 325 default: 326 dev_err(hsotg->dev, "error getting phy %d\n", ret); 327 return ret; 328 } 329 } 330 331 if (!hsotg->phy) { 332 hsotg->uphy = devm_usb_get_phy(hsotg->dev, USB_PHY_TYPE_USB2); 333 if (IS_ERR(hsotg->uphy)) { 334 ret = PTR_ERR(hsotg->uphy); 335 switch (ret) { 336 case -ENODEV: 337 case -ENXIO: 338 hsotg->uphy = NULL; 339 break; 340 case -EPROBE_DEFER: 341 return ret; 342 default: 343 dev_err(hsotg->dev, "error getting usb phy %d\n", 344 ret); 345 return ret; 346 } 347 } 348 } 349 350 hsotg->plat = dev_get_platdata(hsotg->dev); 351 352 if (hsotg->phy) { 353 /* 354 * If using the generic PHY framework, check if the PHY bus 355 * width is 8-bit and set the phyif appropriately. 356 */ 357 if (phy_get_bus_width(hsotg->phy) == 8) 358 hsotg->phyif = GUSBCFG_PHYIF8; 359 } 360 361 /* Clock */ 362 hsotg->clk = devm_clk_get(hsotg->dev, "otg"); 363 if (IS_ERR(hsotg->clk)) { 364 hsotg->clk = NULL; 365 dev_dbg(hsotg->dev, "cannot get otg clock\n"); 366 } 367 368 /* Regulators */ 369 for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++) 370 hsotg->supplies[i].supply = dwc2_hsotg_supply_names[i]; 371 372 ret = devm_regulator_bulk_get(hsotg->dev, ARRAY_SIZE(hsotg->supplies), 373 hsotg->supplies); 374 if (ret) { 375 dev_err(hsotg->dev, "failed to request supplies: %d\n", ret); 376 return ret; 377 } 378 return 0; 379 } 380 381 /** 382 * dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the 383 * DWC_otg driver 384 * 385 * @dev: Platform device 386 * 387 * This routine is called, for example, when the rmmod command is executed. The 388 * device may or may not be electrically present. If it is present, the driver 389 * stops device processing. Any resources used on behalf of this device are 390 * freed. 391 */ 392 static int dwc2_driver_remove(struct platform_device *dev) 393 { 394 struct dwc2_hsotg *hsotg = platform_get_drvdata(dev); 395 396 dwc2_debugfs_exit(hsotg); 397 if (hsotg->hcd_enabled) 398 dwc2_hcd_remove(hsotg); 399 if (hsotg->gadget_enabled) 400 dwc2_hsotg_remove(hsotg); 401 402 if (hsotg->ll_hw_enabled) 403 dwc2_lowlevel_hw_disable(hsotg); 404 405 return 0; 406 } 407 408 /** 409 * dwc2_driver_shutdown() - Called on device shutdown 410 * 411 * @dev: Platform device 412 * 413 * In specific conditions (involving usb hubs) dwc2 devices can create a 414 * lot of interrupts, even to the point of overwhelming devices running 415 * at low frequencies. Some devices need to do special clock handling 416 * at shutdown-time which may bring the system clock below the threshold 417 * of being able to handle the dwc2 interrupts. Disabling dwc2-irqs 418 * prevents reboots/poweroffs from getting stuck in such cases. 419 */ 420 static void dwc2_driver_shutdown(struct platform_device *dev) 421 { 422 struct dwc2_hsotg *hsotg = platform_get_drvdata(dev); 423 424 disable_irq(hsotg->irq); 425 } 426 427 static const struct of_device_id dwc2_of_match_table[] = { 428 { .compatible = "brcm,bcm2835-usb", .data = ¶ms_bcm2835 }, 429 { .compatible = "hisilicon,hi6220-usb", .data = ¶ms_hi6220 }, 430 { .compatible = "rockchip,rk3066-usb", .data = ¶ms_rk3066 }, 431 { .compatible = "snps,dwc2", .data = NULL }, 432 { .compatible = "samsung,s3c6400-hsotg", .data = NULL}, 433 {}, 434 }; 435 MODULE_DEVICE_TABLE(of, dwc2_of_match_table); 436 437 /** 438 * dwc2_driver_probe() - Called when the DWC_otg core is bound to the DWC_otg 439 * driver 440 * 441 * @dev: Platform device 442 * 443 * This routine creates the driver components required to control the device 444 * (core, HCD, and PCD) and initializes the device. The driver components are 445 * stored in a dwc2_hsotg structure. A reference to the dwc2_hsotg is saved 446 * in the device private data. This allows the driver to access the dwc2_hsotg 447 * structure on subsequent calls to driver methods for this device. 448 */ 449 static int dwc2_driver_probe(struct platform_device *dev) 450 { 451 const struct of_device_id *match; 452 const struct dwc2_core_params *params; 453 struct dwc2_core_params defparams; 454 struct dwc2_hsotg *hsotg; 455 struct resource *res; 456 int retval; 457 458 match = of_match_device(dwc2_of_match_table, &dev->dev); 459 if (match && match->data) { 460 params = match->data; 461 } else { 462 /* Default all params to autodetect */ 463 dwc2_set_all_params(&defparams, -1); 464 params = &defparams; 465 466 /* 467 * Disable descriptor dma mode by default as the HW can support 468 * it, but does not support it for SPLIT transactions. 469 * Disable it for FS devices as well. 470 */ 471 defparams.dma_desc_enable = 0; 472 defparams.dma_desc_fs_enable = 0; 473 } 474 475 hsotg = devm_kzalloc(&dev->dev, sizeof(*hsotg), GFP_KERNEL); 476 if (!hsotg) 477 return -ENOMEM; 478 479 hsotg->dev = &dev->dev; 480 481 /* 482 * Use reasonable defaults so platforms don't have to provide these. 483 */ 484 if (!dev->dev.dma_mask) 485 dev->dev.dma_mask = &dev->dev.coherent_dma_mask; 486 retval = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32)); 487 if (retval) 488 return retval; 489 490 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 491 hsotg->regs = devm_ioremap_resource(&dev->dev, res); 492 if (IS_ERR(hsotg->regs)) 493 return PTR_ERR(hsotg->regs); 494 495 dev_dbg(&dev->dev, "mapped PA %08lx to VA %p\n", 496 (unsigned long)res->start, hsotg->regs); 497 498 retval = dwc2_lowlevel_hw_init(hsotg); 499 if (retval) 500 return retval; 501 502 spin_lock_init(&hsotg->lock); 503 504 hsotg->core_params = devm_kzalloc(&dev->dev, 505 sizeof(*hsotg->core_params), GFP_KERNEL); 506 if (!hsotg->core_params) 507 return -ENOMEM; 508 509 dwc2_set_all_params(hsotg->core_params, -1); 510 511 hsotg->irq = platform_get_irq(dev, 0); 512 if (hsotg->irq < 0) { 513 dev_err(&dev->dev, "missing IRQ resource\n"); 514 return hsotg->irq; 515 } 516 517 dev_dbg(hsotg->dev, "registering common handler for irq%d\n", 518 hsotg->irq); 519 retval = devm_request_irq(hsotg->dev, hsotg->irq, 520 dwc2_handle_common_intr, IRQF_SHARED, 521 dev_name(hsotg->dev), hsotg); 522 if (retval) 523 return retval; 524 525 retval = dwc2_lowlevel_hw_enable(hsotg); 526 if (retval) 527 return retval; 528 529 retval = dwc2_get_dr_mode(hsotg); 530 if (retval) 531 return retval; 532 533 /* 534 * Reset before dwc2_get_hwparams() then it could get power-on real 535 * reset value form registers. 536 */ 537 dwc2_core_reset_and_force_dr_mode(hsotg); 538 539 /* Detect config values from hardware */ 540 retval = dwc2_get_hwparams(hsotg); 541 if (retval) 542 goto error; 543 544 /* Validate parameter values */ 545 dwc2_set_parameters(hsotg, params); 546 547 dwc2_force_dr_mode(hsotg); 548 549 if (hsotg->dr_mode != USB_DR_MODE_HOST) { 550 retval = dwc2_gadget_init(hsotg, hsotg->irq); 551 if (retval) 552 goto error; 553 hsotg->gadget_enabled = 1; 554 } 555 556 if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) { 557 retval = dwc2_hcd_init(hsotg, hsotg->irq); 558 if (retval) { 559 if (hsotg->gadget_enabled) 560 dwc2_hsotg_remove(hsotg); 561 goto error; 562 } 563 hsotg->hcd_enabled = 1; 564 } 565 566 platform_set_drvdata(dev, hsotg); 567 568 dwc2_debugfs_init(hsotg); 569 570 /* Gadget code manages lowlevel hw on its own */ 571 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) 572 dwc2_lowlevel_hw_disable(hsotg); 573 574 return 0; 575 576 error: 577 dwc2_lowlevel_hw_disable(hsotg); 578 return retval; 579 } 580 581 static int __maybe_unused dwc2_suspend(struct device *dev) 582 { 583 struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev); 584 int ret = 0; 585 586 if (dwc2_is_device_mode(dwc2)) 587 dwc2_hsotg_suspend(dwc2); 588 589 if (dwc2->ll_hw_enabled) 590 ret = __dwc2_lowlevel_hw_disable(dwc2); 591 592 return ret; 593 } 594 595 static int __maybe_unused dwc2_resume(struct device *dev) 596 { 597 struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev); 598 int ret = 0; 599 600 if (dwc2->ll_hw_enabled) { 601 ret = __dwc2_lowlevel_hw_enable(dwc2); 602 if (ret) 603 return ret; 604 } 605 606 if (dwc2_is_device_mode(dwc2)) 607 ret = dwc2_hsotg_resume(dwc2); 608 609 return ret; 610 } 611 612 static const struct dev_pm_ops dwc2_dev_pm_ops = { 613 SET_SYSTEM_SLEEP_PM_OPS(dwc2_suspend, dwc2_resume) 614 }; 615 616 static struct platform_driver dwc2_platform_driver = { 617 .driver = { 618 .name = dwc2_driver_name, 619 .of_match_table = dwc2_of_match_table, 620 .pm = &dwc2_dev_pm_ops, 621 }, 622 .probe = dwc2_driver_probe, 623 .remove = dwc2_driver_remove, 624 .shutdown = dwc2_driver_shutdown, 625 }; 626 627 module_platform_driver(dwc2_platform_driver); 628 629 MODULE_DESCRIPTION("DESIGNWARE HS OTG Platform Glue"); 630 MODULE_AUTHOR("Matthijs Kooijman <matthijs@stdin.nl>"); 631 MODULE_LICENSE("Dual BSD/GPL"); 632