1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* 3 * Copyright (C) 2004-2016 Synopsys, Inc. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions, and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The names of the above-listed copyright holders may not be used 15 * to endorse or promote products derived from this software without 16 * specific prior written permission. 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation; either version 2 of the License, or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 24 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 25 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 27 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 28 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 29 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 30 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 31 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 32 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 33 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <linux/kernel.h> 37 #include <linux/module.h> 38 #include <linux/of_device.h> 39 40 #include "core.h" 41 42 static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg) 43 { 44 struct dwc2_core_params *p = &hsotg->params; 45 46 p->host_rx_fifo_size = 774; 47 p->max_transfer_size = 65535; 48 p->max_packet_count = 511; 49 p->ahbcfg = 0x10; 50 } 51 52 static void dwc2_set_his_params(struct dwc2_hsotg *hsotg) 53 { 54 struct dwc2_core_params *p = &hsotg->params; 55 56 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 57 p->speed = DWC2_SPEED_PARAM_HIGH; 58 p->host_rx_fifo_size = 512; 59 p->host_nperio_tx_fifo_size = 512; 60 p->host_perio_tx_fifo_size = 512; 61 p->max_transfer_size = 65535; 62 p->max_packet_count = 511; 63 p->host_channels = 16; 64 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 65 p->phy_utmi_width = 8; 66 p->i2c_enable = false; 67 p->reload_ctl = false; 68 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 69 GAHBCFG_HBSTLEN_SHIFT; 70 p->change_speed_quirk = true; 71 p->power_down = false; 72 } 73 74 static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg) 75 { 76 struct dwc2_core_params *p = &hsotg->params; 77 78 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 79 p->host_rx_fifo_size = 525; 80 p->host_nperio_tx_fifo_size = 128; 81 p->host_perio_tx_fifo_size = 256; 82 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 83 GAHBCFG_HBSTLEN_SHIFT; 84 } 85 86 static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg) 87 { 88 struct dwc2_core_params *p = &hsotg->params; 89 90 p->otg_cap = 2; 91 p->host_rx_fifo_size = 288; 92 p->host_nperio_tx_fifo_size = 128; 93 p->host_perio_tx_fifo_size = 96; 94 p->max_transfer_size = 65535; 95 p->max_packet_count = 511; 96 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 97 GAHBCFG_HBSTLEN_SHIFT; 98 } 99 100 static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg) 101 { 102 struct dwc2_core_params *p = &hsotg->params; 103 104 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 105 p->speed = DWC2_SPEED_PARAM_HIGH; 106 p->host_rx_fifo_size = 512; 107 p->host_nperio_tx_fifo_size = 500; 108 p->host_perio_tx_fifo_size = 500; 109 p->host_channels = 16; 110 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 111 p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 << 112 GAHBCFG_HBSTLEN_SHIFT; 113 } 114 115 static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg) 116 { 117 struct dwc2_core_params *p = &hsotg->params; 118 119 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; 120 } 121 122 static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg) 123 { 124 struct dwc2_core_params *p = &hsotg->params; 125 126 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 127 p->speed = DWC2_SPEED_PARAM_FULL; 128 p->host_rx_fifo_size = 128; 129 p->host_nperio_tx_fifo_size = 96; 130 p->host_perio_tx_fifo_size = 96; 131 p->max_packet_count = 256; 132 p->phy_type = DWC2_PHY_TYPE_PARAM_FS; 133 p->i2c_enable = false; 134 p->activate_stm_fs_transceiver = true; 135 } 136 137 static void dwc2_set_stm32f7_hsotg_params(struct dwc2_hsotg *hsotg) 138 { 139 struct dwc2_core_params *p = &hsotg->params; 140 141 p->host_rx_fifo_size = 622; 142 p->host_nperio_tx_fifo_size = 128; 143 p->host_perio_tx_fifo_size = 256; 144 } 145 146 const struct of_device_id dwc2_of_match_table[] = { 147 { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params }, 148 { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params }, 149 { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params }, 150 { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params }, 151 { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params }, 152 { .compatible = "snps,dwc2" }, 153 { .compatible = "samsung,s3c6400-hsotg" }, 154 { .compatible = "amlogic,meson8-usb", 155 .data = dwc2_set_amlogic_params }, 156 { .compatible = "amlogic,meson8b-usb", 157 .data = dwc2_set_amlogic_params }, 158 { .compatible = "amlogic,meson-gxbb-usb", 159 .data = dwc2_set_amlogic_params }, 160 { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params }, 161 { .compatible = "st,stm32f4x9-fsotg", 162 .data = dwc2_set_stm32f4x9_fsotg_params }, 163 { .compatible = "st,stm32f4x9-hsotg" }, 164 { .compatible = "st,stm32f7-hsotg", 165 .data = dwc2_set_stm32f7_hsotg_params }, 166 {}, 167 }; 168 MODULE_DEVICE_TABLE(of, dwc2_of_match_table); 169 170 static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg) 171 { 172 u8 val; 173 174 switch (hsotg->hw_params.op_mode) { 175 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 176 val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE; 177 break; 178 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 179 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 180 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 181 val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE; 182 break; 183 default: 184 val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 185 break; 186 } 187 188 hsotg->params.otg_cap = val; 189 } 190 191 static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg) 192 { 193 int val; 194 u32 hs_phy_type = hsotg->hw_params.hs_phy_type; 195 196 val = DWC2_PHY_TYPE_PARAM_FS; 197 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) { 198 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI || 199 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI) 200 val = DWC2_PHY_TYPE_PARAM_UTMI; 201 else 202 val = DWC2_PHY_TYPE_PARAM_ULPI; 203 } 204 205 if (dwc2_is_fs_iot(hsotg)) 206 hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS; 207 208 hsotg->params.phy_type = val; 209 } 210 211 static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg) 212 { 213 int val; 214 215 val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ? 216 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH; 217 218 if (dwc2_is_fs_iot(hsotg)) 219 val = DWC2_SPEED_PARAM_FULL; 220 221 if (dwc2_is_hs_iot(hsotg)) 222 val = DWC2_SPEED_PARAM_HIGH; 223 224 hsotg->params.speed = val; 225 } 226 227 static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg) 228 { 229 int val; 230 231 val = (hsotg->hw_params.utmi_phy_data_width == 232 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16; 233 234 hsotg->params.phy_utmi_width = val; 235 } 236 237 static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg) 238 { 239 struct dwc2_core_params *p = &hsotg->params; 240 int depth_average; 241 int fifo_count; 242 int i; 243 244 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 245 246 memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size)); 247 depth_average = dwc2_hsotg_tx_fifo_average_depth(hsotg); 248 for (i = 1; i <= fifo_count; i++) 249 p->g_tx_fifo_size[i] = depth_average; 250 } 251 252 static void dwc2_set_param_power_down(struct dwc2_hsotg *hsotg) 253 { 254 int val; 255 256 if (hsotg->hw_params.hibernation) 257 val = 2; 258 else if (hsotg->hw_params.power_optimized) 259 val = 1; 260 else 261 val = 0; 262 263 hsotg->params.power_down = val; 264 } 265 266 /** 267 * dwc2_set_default_params() - Set all core parameters to their 268 * auto-detected default values. 269 * 270 * @hsotg: Programming view of the DWC_otg controller 271 * 272 */ 273 static void dwc2_set_default_params(struct dwc2_hsotg *hsotg) 274 { 275 struct dwc2_hw_params *hw = &hsotg->hw_params; 276 struct dwc2_core_params *p = &hsotg->params; 277 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); 278 279 dwc2_set_param_otg_cap(hsotg); 280 dwc2_set_param_phy_type(hsotg); 281 dwc2_set_param_speed(hsotg); 282 dwc2_set_param_phy_utmi_width(hsotg); 283 dwc2_set_param_power_down(hsotg); 284 p->phy_ulpi_ddr = false; 285 p->phy_ulpi_ext_vbus = false; 286 287 p->enable_dynamic_fifo = hw->enable_dynamic_fifo; 288 p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo; 289 p->i2c_enable = hw->i2c_enable; 290 p->acg_enable = hw->acg_enable; 291 p->ulpi_fs_ls = false; 292 p->ts_dline = false; 293 p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a); 294 p->uframe_sched = true; 295 p->external_id_pin_ctl = false; 296 p->lpm = true; 297 p->lpm_clock_gating = true; 298 p->besl = true; 299 p->hird_threshold_en = true; 300 p->hird_threshold = 4; 301 p->ipg_isoc_en = false; 302 p->max_packet_count = hw->max_packet_count; 303 p->max_transfer_size = hw->max_transfer_size; 304 p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT; 305 306 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || 307 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 308 p->host_dma = dma_capable; 309 p->dma_desc_enable = false; 310 p->dma_desc_fs_enable = false; 311 p->host_support_fs_ls_low_power = false; 312 p->host_ls_low_power_phy_clk = false; 313 p->host_channels = hw->host_channels; 314 p->host_rx_fifo_size = hw->rx_fifo_size; 315 p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size; 316 p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size; 317 } 318 319 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 320 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 321 p->g_dma = dma_capable; 322 p->g_dma_desc = hw->dma_desc_enable; 323 324 /* 325 * The values for g_rx_fifo_size (2048) and 326 * g_np_tx_fifo_size (1024) come from the legacy s3c 327 * gadget driver. These defaults have been hard-coded 328 * for some time so many platforms depend on these 329 * values. Leave them as defaults for now and only 330 * auto-detect if the hardware does not support the 331 * default. 332 */ 333 p->g_rx_fifo_size = 2048; 334 p->g_np_tx_fifo_size = 1024; 335 dwc2_set_param_tx_fifo_sizes(hsotg); 336 } 337 } 338 339 /** 340 * dwc2_get_device_properties() - Read in device properties. 341 * 342 * @hsotg: Programming view of the DWC_otg controller 343 * 344 * Read in the device properties and adjust core parameters if needed. 345 */ 346 static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg) 347 { 348 struct dwc2_core_params *p = &hsotg->params; 349 int num; 350 351 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 352 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 353 device_property_read_u32(hsotg->dev, "g-rx-fifo-size", 354 &p->g_rx_fifo_size); 355 356 device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size", 357 &p->g_np_tx_fifo_size); 358 359 num = device_property_read_u32_array(hsotg->dev, 360 "g-tx-fifo-size", 361 NULL, 0); 362 363 if (num > 0) { 364 num = min(num, 15); 365 memset(p->g_tx_fifo_size, 0, 366 sizeof(p->g_tx_fifo_size)); 367 device_property_read_u32_array(hsotg->dev, 368 "g-tx-fifo-size", 369 &p->g_tx_fifo_size[1], 370 num); 371 } 372 } 373 374 if (of_find_property(hsotg->dev->of_node, "disable-over-current", NULL)) 375 p->oc_disable = true; 376 } 377 378 static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg) 379 { 380 int valid = 1; 381 382 switch (hsotg->params.otg_cap) { 383 case DWC2_CAP_PARAM_HNP_SRP_CAPABLE: 384 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) 385 valid = 0; 386 break; 387 case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE: 388 switch (hsotg->hw_params.op_mode) { 389 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 390 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 391 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 392 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 393 break; 394 default: 395 valid = 0; 396 break; 397 } 398 break; 399 case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE: 400 /* always valid */ 401 break; 402 default: 403 valid = 0; 404 break; 405 } 406 407 if (!valid) 408 dwc2_set_param_otg_cap(hsotg); 409 } 410 411 static void dwc2_check_param_phy_type(struct dwc2_hsotg *hsotg) 412 { 413 int valid = 0; 414 u32 hs_phy_type; 415 u32 fs_phy_type; 416 417 hs_phy_type = hsotg->hw_params.hs_phy_type; 418 fs_phy_type = hsotg->hw_params.fs_phy_type; 419 420 switch (hsotg->params.phy_type) { 421 case DWC2_PHY_TYPE_PARAM_FS: 422 if (fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) 423 valid = 1; 424 break; 425 case DWC2_PHY_TYPE_PARAM_UTMI: 426 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) || 427 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 428 valid = 1; 429 break; 430 case DWC2_PHY_TYPE_PARAM_ULPI: 431 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) || 432 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 433 valid = 1; 434 break; 435 default: 436 break; 437 } 438 439 if (!valid) 440 dwc2_set_param_phy_type(hsotg); 441 } 442 443 static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg) 444 { 445 int valid = 1; 446 int phy_type = hsotg->params.phy_type; 447 int speed = hsotg->params.speed; 448 449 switch (speed) { 450 case DWC2_SPEED_PARAM_HIGH: 451 if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) && 452 (phy_type == DWC2_PHY_TYPE_PARAM_FS)) 453 valid = 0; 454 break; 455 case DWC2_SPEED_PARAM_FULL: 456 case DWC2_SPEED_PARAM_LOW: 457 break; 458 default: 459 valid = 0; 460 break; 461 } 462 463 if (!valid) 464 dwc2_set_param_speed(hsotg); 465 } 466 467 static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg *hsotg) 468 { 469 int valid = 0; 470 int param = hsotg->params.phy_utmi_width; 471 int width = hsotg->hw_params.utmi_phy_data_width; 472 473 switch (width) { 474 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8: 475 valid = (param == 8); 476 break; 477 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16: 478 valid = (param == 16); 479 break; 480 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16: 481 valid = (param == 8 || param == 16); 482 break; 483 } 484 485 if (!valid) 486 dwc2_set_param_phy_utmi_width(hsotg); 487 } 488 489 static void dwc2_check_param_power_down(struct dwc2_hsotg *hsotg) 490 { 491 int param = hsotg->params.power_down; 492 493 switch (param) { 494 case DWC2_POWER_DOWN_PARAM_NONE: 495 break; 496 case DWC2_POWER_DOWN_PARAM_PARTIAL: 497 if (hsotg->hw_params.power_optimized) 498 break; 499 dev_dbg(hsotg->dev, 500 "Partial power down isn't supported by HW\n"); 501 param = DWC2_POWER_DOWN_PARAM_NONE; 502 break; 503 case DWC2_POWER_DOWN_PARAM_HIBERNATION: 504 if (hsotg->hw_params.hibernation) 505 break; 506 dev_dbg(hsotg->dev, 507 "Hibernation isn't supported by HW\n"); 508 param = DWC2_POWER_DOWN_PARAM_NONE; 509 break; 510 default: 511 dev_err(hsotg->dev, 512 "%s: Invalid parameter power_down=%d\n", 513 __func__, param); 514 param = DWC2_POWER_DOWN_PARAM_NONE; 515 break; 516 } 517 518 hsotg->params.power_down = param; 519 } 520 521 static void dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg) 522 { 523 int fifo_count; 524 int fifo; 525 int min; 526 u32 total = 0; 527 u32 dptxfszn; 528 529 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 530 min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4; 531 532 for (fifo = 1; fifo <= fifo_count; fifo++) 533 total += hsotg->params.g_tx_fifo_size[fifo]; 534 535 if (total > dwc2_hsotg_tx_fifo_total_depth(hsotg) || !total) { 536 dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n", 537 __func__); 538 dwc2_set_param_tx_fifo_sizes(hsotg); 539 } 540 541 for (fifo = 1; fifo <= fifo_count; fifo++) { 542 dptxfszn = hsotg->hw_params.g_tx_fifo_size[fifo]; 543 544 if (hsotg->params.g_tx_fifo_size[fifo] < min || 545 hsotg->params.g_tx_fifo_size[fifo] > dptxfszn) { 546 dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n", 547 __func__, fifo, 548 hsotg->params.g_tx_fifo_size[fifo]); 549 hsotg->params.g_tx_fifo_size[fifo] = dptxfszn; 550 } 551 } 552 } 553 554 #define CHECK_RANGE(_param, _min, _max, _def) do { \ 555 if ((int)(hsotg->params._param) < (_min) || \ 556 (hsotg->params._param) > (_max)) { \ 557 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \ 558 __func__, #_param, hsotg->params._param); \ 559 hsotg->params._param = (_def); \ 560 } \ 561 } while (0) 562 563 #define CHECK_BOOL(_param, _check) do { \ 564 if (hsotg->params._param && !(_check)) { \ 565 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \ 566 __func__, #_param, hsotg->params._param); \ 567 hsotg->params._param = false; \ 568 } \ 569 } while (0) 570 571 static void dwc2_check_params(struct dwc2_hsotg *hsotg) 572 { 573 struct dwc2_hw_params *hw = &hsotg->hw_params; 574 struct dwc2_core_params *p = &hsotg->params; 575 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); 576 577 dwc2_check_param_otg_cap(hsotg); 578 dwc2_check_param_phy_type(hsotg); 579 dwc2_check_param_speed(hsotg); 580 dwc2_check_param_phy_utmi_width(hsotg); 581 dwc2_check_param_power_down(hsotg); 582 CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo); 583 CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo); 584 CHECK_BOOL(i2c_enable, hw->i2c_enable); 585 CHECK_BOOL(ipg_isoc_en, hw->ipg_isoc_en); 586 CHECK_BOOL(acg_enable, hw->acg_enable); 587 CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a)); 588 CHECK_BOOL(lpm, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_80a)); 589 CHECK_BOOL(lpm, hw->lpm_mode); 590 CHECK_BOOL(lpm_clock_gating, hsotg->params.lpm); 591 CHECK_BOOL(besl, hsotg->params.lpm); 592 CHECK_BOOL(besl, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a)); 593 CHECK_BOOL(hird_threshold_en, hsotg->params.lpm); 594 CHECK_RANGE(hird_threshold, 0, hsotg->params.besl ? 12 : 7, 0); 595 CHECK_RANGE(max_packet_count, 596 15, hw->max_packet_count, 597 hw->max_packet_count); 598 CHECK_RANGE(max_transfer_size, 599 2047, hw->max_transfer_size, 600 hw->max_transfer_size); 601 602 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || 603 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 604 CHECK_BOOL(host_dma, dma_capable); 605 CHECK_BOOL(dma_desc_enable, p->host_dma); 606 CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable); 607 CHECK_BOOL(host_ls_low_power_phy_clk, 608 p->phy_type == DWC2_PHY_TYPE_PARAM_FS); 609 CHECK_RANGE(host_channels, 610 1, hw->host_channels, 611 hw->host_channels); 612 CHECK_RANGE(host_rx_fifo_size, 613 16, hw->rx_fifo_size, 614 hw->rx_fifo_size); 615 CHECK_RANGE(host_nperio_tx_fifo_size, 616 16, hw->host_nperio_tx_fifo_size, 617 hw->host_nperio_tx_fifo_size); 618 CHECK_RANGE(host_perio_tx_fifo_size, 619 16, hw->host_perio_tx_fifo_size, 620 hw->host_perio_tx_fifo_size); 621 } 622 623 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 624 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 625 CHECK_BOOL(g_dma, dma_capable); 626 CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable)); 627 CHECK_RANGE(g_rx_fifo_size, 628 16, hw->rx_fifo_size, 629 hw->rx_fifo_size); 630 CHECK_RANGE(g_np_tx_fifo_size, 631 16, hw->dev_nperio_tx_fifo_size, 632 hw->dev_nperio_tx_fifo_size); 633 dwc2_check_param_tx_fifo_sizes(hsotg); 634 } 635 } 636 637 /* 638 * Gets host hardware parameters. Forces host mode if not currently in 639 * host mode. Should be called immediately after a core soft reset in 640 * order to get the reset values. 641 */ 642 static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg) 643 { 644 struct dwc2_hw_params *hw = &hsotg->hw_params; 645 u32 gnptxfsiz; 646 u32 hptxfsiz; 647 648 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) 649 return; 650 651 dwc2_force_mode(hsotg, true); 652 653 gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ); 654 hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ); 655 656 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 657 FIFOSIZE_DEPTH_SHIFT; 658 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >> 659 FIFOSIZE_DEPTH_SHIFT; 660 } 661 662 /* 663 * Gets device hardware parameters. Forces device mode if not 664 * currently in device mode. Should be called immediately after a core 665 * soft reset in order to get the reset values. 666 */ 667 static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg) 668 { 669 struct dwc2_hw_params *hw = &hsotg->hw_params; 670 u32 gnptxfsiz; 671 int fifo, fifo_count; 672 673 if (hsotg->dr_mode == USB_DR_MODE_HOST) 674 return; 675 676 dwc2_force_mode(hsotg, false); 677 678 gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ); 679 680 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 681 682 for (fifo = 1; fifo <= fifo_count; fifo++) { 683 hw->g_tx_fifo_size[fifo] = 684 (dwc2_readl(hsotg, DPTXFSIZN(fifo)) & 685 FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT; 686 } 687 688 hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 689 FIFOSIZE_DEPTH_SHIFT; 690 } 691 692 /** 693 * During device initialization, read various hardware configuration 694 * registers and interpret the contents. 695 * 696 * @hsotg: Programming view of the DWC_otg controller 697 * 698 */ 699 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) 700 { 701 struct dwc2_hw_params *hw = &hsotg->hw_params; 702 unsigned int width; 703 u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4; 704 u32 grxfsiz; 705 706 /* 707 * Attempt to ensure this device is really a DWC_otg Controller. 708 * Read and verify the GSNPSID register contents. The value should be 709 * 0x45f4xxxx, 0x5531xxxx or 0x5532xxxx 710 */ 711 712 hw->snpsid = dwc2_readl(hsotg, GSNPSID); 713 if ((hw->snpsid & GSNPSID_ID_MASK) != DWC2_OTG_ID && 714 (hw->snpsid & GSNPSID_ID_MASK) != DWC2_FS_IOT_ID && 715 (hw->snpsid & GSNPSID_ID_MASK) != DWC2_HS_IOT_ID) { 716 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n", 717 hw->snpsid); 718 return -ENODEV; 719 } 720 721 dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n", 722 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf, 723 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid); 724 725 hwcfg1 = dwc2_readl(hsotg, GHWCFG1); 726 hwcfg2 = dwc2_readl(hsotg, GHWCFG2); 727 hwcfg3 = dwc2_readl(hsotg, GHWCFG3); 728 hwcfg4 = dwc2_readl(hsotg, GHWCFG4); 729 grxfsiz = dwc2_readl(hsotg, GRXFSIZ); 730 731 /* hwcfg1 */ 732 hw->dev_ep_dirs = hwcfg1; 733 734 /* hwcfg2 */ 735 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >> 736 GHWCFG2_OP_MODE_SHIFT; 737 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >> 738 GHWCFG2_ARCHITECTURE_SHIFT; 739 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO); 740 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >> 741 GHWCFG2_NUM_HOST_CHAN_SHIFT); 742 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >> 743 GHWCFG2_HS_PHY_TYPE_SHIFT; 744 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> 745 GHWCFG2_FS_PHY_TYPE_SHIFT; 746 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >> 747 GHWCFG2_NUM_DEV_EP_SHIFT; 748 hw->nperio_tx_q_depth = 749 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >> 750 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1; 751 hw->host_perio_tx_q_depth = 752 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >> 753 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1; 754 hw->dev_token_q_depth = 755 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >> 756 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT; 757 758 /* hwcfg3 */ 759 width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >> 760 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT; 761 hw->max_transfer_size = (1 << (width + 11)) - 1; 762 width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >> 763 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT; 764 hw->max_packet_count = (1 << (width + 4)) - 1; 765 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C); 766 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >> 767 GHWCFG3_DFIFO_DEPTH_SHIFT; 768 hw->lpm_mode = !!(hwcfg3 & GHWCFG3_OTG_LPM_EN); 769 770 /* hwcfg4 */ 771 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN); 772 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >> 773 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT; 774 hw->num_dev_in_eps = (hwcfg4 & GHWCFG4_NUM_IN_EPS_MASK) >> 775 GHWCFG4_NUM_IN_EPS_SHIFT; 776 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA); 777 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ); 778 hw->hibernation = !!(hwcfg4 & GHWCFG4_HIBER); 779 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >> 780 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT; 781 hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED); 782 hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED); 783 784 /* fifo sizes */ 785 hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >> 786 GRXFSIZ_DEPTH_SHIFT; 787 /* 788 * Host specific hardware parameters. Reading these parameters 789 * requires the controller to be in host mode. The mode will 790 * be forced, if necessary, to read these values. 791 */ 792 dwc2_get_host_hwparams(hsotg); 793 dwc2_get_dev_hwparams(hsotg); 794 795 return 0; 796 } 797 798 int dwc2_init_params(struct dwc2_hsotg *hsotg) 799 { 800 const struct of_device_id *match; 801 void (*set_params)(void *data); 802 803 dwc2_set_default_params(hsotg); 804 dwc2_get_device_properties(hsotg); 805 806 match = of_match_device(dwc2_of_match_table, hsotg->dev); 807 if (match && match->data) { 808 set_params = match->data; 809 set_params(hsotg); 810 } 811 812 dwc2_check_params(hsotg); 813 814 return 0; 815 } 816