1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* 3 * Copyright (C) 2004-2016 Synopsys, Inc. 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/module.h> 8 #include <linux/of_device.h> 9 #include <linux/usb/of.h> 10 11 #include "core.h" 12 13 static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg) 14 { 15 struct dwc2_core_params *p = &hsotg->params; 16 17 p->host_rx_fifo_size = 774; 18 p->max_transfer_size = 65535; 19 p->max_packet_count = 511; 20 p->ahbcfg = 0x10; 21 } 22 23 static void dwc2_set_his_params(struct dwc2_hsotg *hsotg) 24 { 25 struct dwc2_core_params *p = &hsotg->params; 26 27 p->otg_caps.hnp_support = false; 28 p->otg_caps.srp_support = false; 29 p->speed = DWC2_SPEED_PARAM_HIGH; 30 p->host_rx_fifo_size = 512; 31 p->host_nperio_tx_fifo_size = 512; 32 p->host_perio_tx_fifo_size = 512; 33 p->max_transfer_size = 65535; 34 p->max_packet_count = 511; 35 p->host_channels = 16; 36 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 37 p->phy_utmi_width = 8; 38 p->i2c_enable = false; 39 p->reload_ctl = false; 40 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 41 GAHBCFG_HBSTLEN_SHIFT; 42 p->change_speed_quirk = true; 43 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 44 } 45 46 static void dwc2_set_jz4775_params(struct dwc2_hsotg *hsotg) 47 { 48 struct dwc2_core_params *p = &hsotg->params; 49 50 p->otg_caps.hnp_support = false; 51 p->speed = DWC2_SPEED_PARAM_HIGH; 52 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 53 p->phy_utmi_width = 16; 54 p->activate_ingenic_overcurrent_detection = 55 !device_property_read_bool(hsotg->dev, "disable-over-current"); 56 } 57 58 static void dwc2_set_x1600_params(struct dwc2_hsotg *hsotg) 59 { 60 struct dwc2_core_params *p = &hsotg->params; 61 62 p->otg_caps.hnp_support = false; 63 p->speed = DWC2_SPEED_PARAM_HIGH; 64 p->host_channels = 16; 65 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 66 p->phy_utmi_width = 16; 67 p->activate_ingenic_overcurrent_detection = 68 !device_property_read_bool(hsotg->dev, "disable-over-current"); 69 } 70 71 static void dwc2_set_x2000_params(struct dwc2_hsotg *hsotg) 72 { 73 struct dwc2_core_params *p = &hsotg->params; 74 75 p->otg_caps.hnp_support = false; 76 p->speed = DWC2_SPEED_PARAM_HIGH; 77 p->host_rx_fifo_size = 1024; 78 p->host_nperio_tx_fifo_size = 1024; 79 p->host_perio_tx_fifo_size = 1024; 80 p->host_channels = 16; 81 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 82 p->phy_utmi_width = 16; 83 p->activate_ingenic_overcurrent_detection = 84 !device_property_read_bool(hsotg->dev, "disable-over-current"); 85 } 86 87 static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg) 88 { 89 struct dwc2_core_params *p = &hsotg->params; 90 91 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 92 p->no_clock_gating = true; 93 p->phy_utmi_width = 8; 94 } 95 96 static void dwc2_set_socfpga_agilex_params(struct dwc2_hsotg *hsotg) 97 { 98 struct dwc2_core_params *p = &hsotg->params; 99 100 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 101 p->no_clock_gating = true; 102 } 103 104 static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg) 105 { 106 struct dwc2_core_params *p = &hsotg->params; 107 108 p->otg_caps.hnp_support = false; 109 p->otg_caps.srp_support = false; 110 p->host_rx_fifo_size = 525; 111 p->host_nperio_tx_fifo_size = 128; 112 p->host_perio_tx_fifo_size = 256; 113 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 114 GAHBCFG_HBSTLEN_SHIFT; 115 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 116 } 117 118 static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg) 119 { 120 struct dwc2_core_params *p = &hsotg->params; 121 122 p->otg_caps.hnp_support = false; 123 p->otg_caps.srp_support = false; 124 p->host_rx_fifo_size = 288; 125 p->host_nperio_tx_fifo_size = 128; 126 p->host_perio_tx_fifo_size = 96; 127 p->max_transfer_size = 65535; 128 p->max_packet_count = 511; 129 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 130 GAHBCFG_HBSTLEN_SHIFT; 131 } 132 133 static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg) 134 { 135 struct dwc2_core_params *p = &hsotg->params; 136 137 p->otg_caps.hnp_support = false; 138 p->otg_caps.srp_support = false; 139 p->speed = DWC2_SPEED_PARAM_HIGH; 140 p->host_rx_fifo_size = 512; 141 p->host_nperio_tx_fifo_size = 500; 142 p->host_perio_tx_fifo_size = 500; 143 p->host_channels = 16; 144 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 145 p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 << 146 GAHBCFG_HBSTLEN_SHIFT; 147 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 148 } 149 150 static void dwc2_set_amlogic_g12a_params(struct dwc2_hsotg *hsotg) 151 { 152 struct dwc2_core_params *p = &hsotg->params; 153 154 p->lpm = false; 155 p->lpm_clock_gating = false; 156 p->besl = false; 157 p->hird_threshold_en = false; 158 } 159 160 static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg) 161 { 162 struct dwc2_core_params *p = &hsotg->params; 163 164 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; 165 } 166 167 static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg) 168 { 169 struct dwc2_core_params *p = &hsotg->params; 170 171 p->otg_caps.hnp_support = false; 172 p->otg_caps.srp_support = false; 173 p->speed = DWC2_SPEED_PARAM_FULL; 174 p->host_rx_fifo_size = 128; 175 p->host_nperio_tx_fifo_size = 96; 176 p->host_perio_tx_fifo_size = 96; 177 p->max_packet_count = 256; 178 p->phy_type = DWC2_PHY_TYPE_PARAM_FS; 179 p->i2c_enable = false; 180 p->activate_stm_fs_transceiver = true; 181 } 182 183 static void dwc2_set_stm32f7_hsotg_params(struct dwc2_hsotg *hsotg) 184 { 185 struct dwc2_core_params *p = &hsotg->params; 186 187 p->host_rx_fifo_size = 622; 188 p->host_nperio_tx_fifo_size = 128; 189 p->host_perio_tx_fifo_size = 256; 190 } 191 192 static void dwc2_set_stm32mp15_fsotg_params(struct dwc2_hsotg *hsotg) 193 { 194 struct dwc2_core_params *p = &hsotg->params; 195 196 p->otg_caps.hnp_support = false; 197 p->otg_caps.srp_support = false; 198 p->otg_caps.otg_rev = 0x200; 199 p->speed = DWC2_SPEED_PARAM_FULL; 200 p->host_rx_fifo_size = 128; 201 p->host_nperio_tx_fifo_size = 96; 202 p->host_perio_tx_fifo_size = 96; 203 p->max_packet_count = 256; 204 p->phy_type = DWC2_PHY_TYPE_PARAM_FS; 205 p->i2c_enable = false; 206 p->activate_stm_fs_transceiver = true; 207 p->activate_stm_id_vb_detection = true; 208 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; 209 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 210 p->host_support_fs_ls_low_power = true; 211 p->host_ls_low_power_phy_clk = true; 212 } 213 214 static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg) 215 { 216 struct dwc2_core_params *p = &hsotg->params; 217 218 p->otg_caps.hnp_support = false; 219 p->otg_caps.srp_support = false; 220 p->otg_caps.otg_rev = 0x200; 221 p->activate_stm_id_vb_detection = !device_property_read_bool(hsotg->dev, "usb-role-switch"); 222 p->host_rx_fifo_size = 440; 223 p->host_nperio_tx_fifo_size = 256; 224 p->host_perio_tx_fifo_size = 256; 225 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; 226 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 227 p->lpm = false; 228 p->lpm_clock_gating = false; 229 p->besl = false; 230 p->hird_threshold_en = false; 231 } 232 233 const struct of_device_id dwc2_of_match_table[] = { 234 { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params }, 235 { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params }, 236 { .compatible = "ingenic,jz4775-otg", .data = dwc2_set_jz4775_params }, 237 { .compatible = "ingenic,jz4780-otg", .data = dwc2_set_jz4775_params }, 238 { .compatible = "ingenic,x1000-otg", .data = dwc2_set_jz4775_params }, 239 { .compatible = "ingenic,x1600-otg", .data = dwc2_set_x1600_params }, 240 { .compatible = "ingenic,x1700-otg", .data = dwc2_set_x1600_params }, 241 { .compatible = "ingenic,x1830-otg", .data = dwc2_set_x1600_params }, 242 { .compatible = "ingenic,x2000-otg", .data = dwc2_set_x2000_params }, 243 { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params }, 244 { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params }, 245 { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params }, 246 { .compatible = "snps,dwc2" }, 247 { .compatible = "samsung,s3c6400-hsotg", 248 .data = dwc2_set_s3c6400_params }, 249 { .compatible = "amlogic,meson8-usb", 250 .data = dwc2_set_amlogic_params }, 251 { .compatible = "amlogic,meson8b-usb", 252 .data = dwc2_set_amlogic_params }, 253 { .compatible = "amlogic,meson-gxbb-usb", 254 .data = dwc2_set_amlogic_params }, 255 { .compatible = "amlogic,meson-g12a-usb", 256 .data = dwc2_set_amlogic_g12a_params }, 257 { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params }, 258 { .compatible = "apm,apm82181-dwc-otg", .data = dwc2_set_amcc_params }, 259 { .compatible = "st,stm32f4x9-fsotg", 260 .data = dwc2_set_stm32f4x9_fsotg_params }, 261 { .compatible = "st,stm32f4x9-hsotg" }, 262 { .compatible = "st,stm32f7-hsotg", 263 .data = dwc2_set_stm32f7_hsotg_params }, 264 { .compatible = "st,stm32mp15-fsotg", 265 .data = dwc2_set_stm32mp15_fsotg_params }, 266 { .compatible = "st,stm32mp15-hsotg", 267 .data = dwc2_set_stm32mp15_hsotg_params }, 268 { .compatible = "intel,socfpga-agilex-hsotg", 269 .data = dwc2_set_socfpga_agilex_params }, 270 {}, 271 }; 272 MODULE_DEVICE_TABLE(of, dwc2_of_match_table); 273 274 const struct acpi_device_id dwc2_acpi_match[] = { 275 { "BCM2848", (kernel_ulong_t)dwc2_set_bcm_params }, 276 { }, 277 }; 278 MODULE_DEVICE_TABLE(acpi, dwc2_acpi_match); 279 280 static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg) 281 { 282 switch (hsotg->hw_params.op_mode) { 283 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 284 hsotg->params.otg_caps.hnp_support = true; 285 hsotg->params.otg_caps.srp_support = true; 286 break; 287 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 288 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 289 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 290 hsotg->params.otg_caps.hnp_support = false; 291 hsotg->params.otg_caps.srp_support = true; 292 break; 293 default: 294 hsotg->params.otg_caps.hnp_support = false; 295 hsotg->params.otg_caps.srp_support = false; 296 break; 297 } 298 } 299 300 static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg) 301 { 302 int val; 303 u32 hs_phy_type = hsotg->hw_params.hs_phy_type; 304 305 val = DWC2_PHY_TYPE_PARAM_FS; 306 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) { 307 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI || 308 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI) 309 val = DWC2_PHY_TYPE_PARAM_UTMI; 310 else 311 val = DWC2_PHY_TYPE_PARAM_ULPI; 312 } 313 314 if (dwc2_is_fs_iot(hsotg)) 315 hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS; 316 317 hsotg->params.phy_type = val; 318 } 319 320 static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg) 321 { 322 int val; 323 324 val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ? 325 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH; 326 327 if (dwc2_is_fs_iot(hsotg)) 328 val = DWC2_SPEED_PARAM_FULL; 329 330 if (dwc2_is_hs_iot(hsotg)) 331 val = DWC2_SPEED_PARAM_HIGH; 332 333 hsotg->params.speed = val; 334 } 335 336 static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg) 337 { 338 int val; 339 340 val = (hsotg->hw_params.utmi_phy_data_width == 341 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16; 342 343 if (hsotg->phy) { 344 /* 345 * If using the generic PHY framework, check if the PHY bus 346 * width is 8-bit and set the phyif appropriately. 347 */ 348 if (phy_get_bus_width(hsotg->phy) == 8) 349 val = 8; 350 } 351 352 hsotg->params.phy_utmi_width = val; 353 } 354 355 static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg) 356 { 357 struct dwc2_core_params *p = &hsotg->params; 358 int depth_average; 359 int fifo_count; 360 int i; 361 362 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 363 364 memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size)); 365 depth_average = dwc2_hsotg_tx_fifo_average_depth(hsotg); 366 for (i = 1; i <= fifo_count; i++) 367 p->g_tx_fifo_size[i] = depth_average; 368 } 369 370 static void dwc2_set_param_power_down(struct dwc2_hsotg *hsotg) 371 { 372 int val; 373 374 if (hsotg->hw_params.hibernation) 375 val = DWC2_POWER_DOWN_PARAM_HIBERNATION; 376 else if (hsotg->hw_params.power_optimized) 377 val = DWC2_POWER_DOWN_PARAM_PARTIAL; 378 else 379 val = DWC2_POWER_DOWN_PARAM_NONE; 380 381 hsotg->params.power_down = val; 382 } 383 384 static void dwc2_set_param_lpm(struct dwc2_hsotg *hsotg) 385 { 386 struct dwc2_core_params *p = &hsotg->params; 387 388 p->lpm = hsotg->hw_params.lpm_mode; 389 if (p->lpm) { 390 p->lpm_clock_gating = true; 391 p->besl = true; 392 p->hird_threshold_en = true; 393 p->hird_threshold = 4; 394 } else { 395 p->lpm_clock_gating = false; 396 p->besl = false; 397 p->hird_threshold_en = false; 398 } 399 } 400 401 /** 402 * dwc2_set_default_params() - Set all core parameters to their 403 * auto-detected default values. 404 * 405 * @hsotg: Programming view of the DWC_otg controller 406 * 407 */ 408 static void dwc2_set_default_params(struct dwc2_hsotg *hsotg) 409 { 410 struct dwc2_hw_params *hw = &hsotg->hw_params; 411 struct dwc2_core_params *p = &hsotg->params; 412 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); 413 414 dwc2_set_param_otg_cap(hsotg); 415 dwc2_set_param_phy_type(hsotg); 416 dwc2_set_param_speed(hsotg); 417 dwc2_set_param_phy_utmi_width(hsotg); 418 dwc2_set_param_power_down(hsotg); 419 dwc2_set_param_lpm(hsotg); 420 p->phy_ulpi_ddr = false; 421 p->phy_ulpi_ext_vbus = false; 422 423 p->enable_dynamic_fifo = hw->enable_dynamic_fifo; 424 p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo; 425 p->i2c_enable = hw->i2c_enable; 426 p->acg_enable = hw->acg_enable; 427 p->ulpi_fs_ls = false; 428 p->ts_dline = false; 429 p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a); 430 p->uframe_sched = true; 431 p->external_id_pin_ctl = false; 432 p->ipg_isoc_en = false; 433 p->service_interval = false; 434 p->max_packet_count = hw->max_packet_count; 435 p->max_transfer_size = hw->max_transfer_size; 436 p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT; 437 p->ref_clk_per = 33333; 438 p->sof_cnt_wkup_alert = 100; 439 440 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || 441 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 442 p->host_dma = dma_capable; 443 p->dma_desc_enable = false; 444 p->dma_desc_fs_enable = false; 445 p->host_support_fs_ls_low_power = false; 446 p->host_ls_low_power_phy_clk = false; 447 p->host_channels = hw->host_channels; 448 p->host_rx_fifo_size = hw->rx_fifo_size; 449 p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size; 450 p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size; 451 } 452 453 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 454 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 455 p->g_dma = dma_capable; 456 p->g_dma_desc = hw->dma_desc_enable; 457 458 /* 459 * The values for g_rx_fifo_size (2048) and 460 * g_np_tx_fifo_size (1024) come from the legacy s3c 461 * gadget driver. These defaults have been hard-coded 462 * for some time so many platforms depend on these 463 * values. Leave them as defaults for now and only 464 * auto-detect if the hardware does not support the 465 * default. 466 */ 467 p->g_rx_fifo_size = 2048; 468 p->g_np_tx_fifo_size = 1024; 469 dwc2_set_param_tx_fifo_sizes(hsotg); 470 } 471 } 472 473 /** 474 * dwc2_get_device_properties() - Read in device properties. 475 * 476 * @hsotg: Programming view of the DWC_otg controller 477 * 478 * Read in the device properties and adjust core parameters if needed. 479 */ 480 static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg) 481 { 482 struct dwc2_core_params *p = &hsotg->params; 483 int num; 484 485 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 486 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 487 device_property_read_u32(hsotg->dev, "g-rx-fifo-size", 488 &p->g_rx_fifo_size); 489 490 device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size", 491 &p->g_np_tx_fifo_size); 492 493 num = device_property_count_u32(hsotg->dev, "g-tx-fifo-size"); 494 if (num > 0) { 495 num = min(num, 15); 496 memset(p->g_tx_fifo_size, 0, 497 sizeof(p->g_tx_fifo_size)); 498 device_property_read_u32_array(hsotg->dev, 499 "g-tx-fifo-size", 500 &p->g_tx_fifo_size[1], 501 num); 502 } 503 504 of_usb_update_otg_caps(hsotg->dev->of_node, &p->otg_caps); 505 } 506 507 if (of_find_property(hsotg->dev->of_node, "disable-over-current", NULL)) 508 p->oc_disable = true; 509 } 510 511 static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg) 512 { 513 int valid = 1; 514 515 if (hsotg->params.otg_caps.hnp_support && hsotg->params.otg_caps.srp_support) { 516 /* check HNP && SRP capable */ 517 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) 518 valid = 0; 519 } else if (!hsotg->params.otg_caps.hnp_support) { 520 /* check SRP only capable */ 521 if (hsotg->params.otg_caps.srp_support) { 522 switch (hsotg->hw_params.op_mode) { 523 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 524 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 525 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 526 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 527 break; 528 default: 529 valid = 0; 530 break; 531 } 532 } 533 /* else: NO HNP && NO SRP capable: always valid */ 534 } else { 535 valid = 0; 536 } 537 538 if (!valid) 539 dwc2_set_param_otg_cap(hsotg); 540 } 541 542 static void dwc2_check_param_phy_type(struct dwc2_hsotg *hsotg) 543 { 544 int valid = 0; 545 u32 hs_phy_type; 546 u32 fs_phy_type; 547 548 hs_phy_type = hsotg->hw_params.hs_phy_type; 549 fs_phy_type = hsotg->hw_params.fs_phy_type; 550 551 switch (hsotg->params.phy_type) { 552 case DWC2_PHY_TYPE_PARAM_FS: 553 if (fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) 554 valid = 1; 555 break; 556 case DWC2_PHY_TYPE_PARAM_UTMI: 557 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) || 558 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 559 valid = 1; 560 break; 561 case DWC2_PHY_TYPE_PARAM_ULPI: 562 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) || 563 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 564 valid = 1; 565 break; 566 default: 567 break; 568 } 569 570 if (!valid) 571 dwc2_set_param_phy_type(hsotg); 572 } 573 574 static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg) 575 { 576 int valid = 1; 577 int phy_type = hsotg->params.phy_type; 578 int speed = hsotg->params.speed; 579 580 switch (speed) { 581 case DWC2_SPEED_PARAM_HIGH: 582 if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) && 583 (phy_type == DWC2_PHY_TYPE_PARAM_FS)) 584 valid = 0; 585 break; 586 case DWC2_SPEED_PARAM_FULL: 587 case DWC2_SPEED_PARAM_LOW: 588 break; 589 default: 590 valid = 0; 591 break; 592 } 593 594 if (!valid) 595 dwc2_set_param_speed(hsotg); 596 } 597 598 static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg *hsotg) 599 { 600 int valid = 0; 601 int param = hsotg->params.phy_utmi_width; 602 int width = hsotg->hw_params.utmi_phy_data_width; 603 604 switch (width) { 605 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8: 606 valid = (param == 8); 607 break; 608 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16: 609 valid = (param == 16); 610 break; 611 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16: 612 valid = (param == 8 || param == 16); 613 break; 614 } 615 616 if (!valid) 617 dwc2_set_param_phy_utmi_width(hsotg); 618 } 619 620 static void dwc2_check_param_power_down(struct dwc2_hsotg *hsotg) 621 { 622 int param = hsotg->params.power_down; 623 624 switch (param) { 625 case DWC2_POWER_DOWN_PARAM_NONE: 626 break; 627 case DWC2_POWER_DOWN_PARAM_PARTIAL: 628 if (hsotg->hw_params.power_optimized) 629 break; 630 dev_dbg(hsotg->dev, 631 "Partial power down isn't supported by HW\n"); 632 param = DWC2_POWER_DOWN_PARAM_NONE; 633 break; 634 case DWC2_POWER_DOWN_PARAM_HIBERNATION: 635 if (hsotg->hw_params.hibernation) 636 break; 637 dev_dbg(hsotg->dev, 638 "Hibernation isn't supported by HW\n"); 639 param = DWC2_POWER_DOWN_PARAM_NONE; 640 break; 641 default: 642 dev_err(hsotg->dev, 643 "%s: Invalid parameter power_down=%d\n", 644 __func__, param); 645 param = DWC2_POWER_DOWN_PARAM_NONE; 646 break; 647 } 648 649 hsotg->params.power_down = param; 650 } 651 652 static void dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg) 653 { 654 int fifo_count; 655 int fifo; 656 int min; 657 u32 total = 0; 658 u32 dptxfszn; 659 660 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 661 min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4; 662 663 for (fifo = 1; fifo <= fifo_count; fifo++) 664 total += hsotg->params.g_tx_fifo_size[fifo]; 665 666 if (total > dwc2_hsotg_tx_fifo_total_depth(hsotg) || !total) { 667 dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n", 668 __func__); 669 dwc2_set_param_tx_fifo_sizes(hsotg); 670 } 671 672 for (fifo = 1; fifo <= fifo_count; fifo++) { 673 dptxfszn = hsotg->hw_params.g_tx_fifo_size[fifo]; 674 675 if (hsotg->params.g_tx_fifo_size[fifo] < min || 676 hsotg->params.g_tx_fifo_size[fifo] > dptxfszn) { 677 dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n", 678 __func__, fifo, 679 hsotg->params.g_tx_fifo_size[fifo]); 680 hsotg->params.g_tx_fifo_size[fifo] = dptxfszn; 681 } 682 } 683 } 684 685 #define CHECK_RANGE(_param, _min, _max, _def) do { \ 686 if ((int)(hsotg->params._param) < (_min) || \ 687 (hsotg->params._param) > (_max)) { \ 688 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \ 689 __func__, #_param, hsotg->params._param); \ 690 hsotg->params._param = (_def); \ 691 } \ 692 } while (0) 693 694 #define CHECK_BOOL(_param, _check) do { \ 695 if (hsotg->params._param && !(_check)) { \ 696 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \ 697 __func__, #_param, hsotg->params._param); \ 698 hsotg->params._param = false; \ 699 } \ 700 } while (0) 701 702 static void dwc2_check_params(struct dwc2_hsotg *hsotg) 703 { 704 struct dwc2_hw_params *hw = &hsotg->hw_params; 705 struct dwc2_core_params *p = &hsotg->params; 706 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); 707 708 dwc2_check_param_otg_cap(hsotg); 709 dwc2_check_param_phy_type(hsotg); 710 dwc2_check_param_speed(hsotg); 711 dwc2_check_param_phy_utmi_width(hsotg); 712 dwc2_check_param_power_down(hsotg); 713 CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo); 714 CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo); 715 CHECK_BOOL(i2c_enable, hw->i2c_enable); 716 CHECK_BOOL(ipg_isoc_en, hw->ipg_isoc_en); 717 CHECK_BOOL(acg_enable, hw->acg_enable); 718 CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a)); 719 CHECK_BOOL(lpm, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_80a)); 720 CHECK_BOOL(lpm, hw->lpm_mode); 721 CHECK_BOOL(lpm_clock_gating, hsotg->params.lpm); 722 CHECK_BOOL(besl, hsotg->params.lpm); 723 CHECK_BOOL(besl, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a)); 724 CHECK_BOOL(hird_threshold_en, hsotg->params.lpm); 725 CHECK_RANGE(hird_threshold, 0, hsotg->params.besl ? 12 : 7, 0); 726 CHECK_BOOL(service_interval, hw->service_interval_mode); 727 CHECK_RANGE(max_packet_count, 728 15, hw->max_packet_count, 729 hw->max_packet_count); 730 CHECK_RANGE(max_transfer_size, 731 2047, hw->max_transfer_size, 732 hw->max_transfer_size); 733 734 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || 735 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 736 CHECK_BOOL(host_dma, dma_capable); 737 CHECK_BOOL(dma_desc_enable, p->host_dma); 738 CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable); 739 CHECK_BOOL(host_ls_low_power_phy_clk, 740 p->phy_type == DWC2_PHY_TYPE_PARAM_FS); 741 CHECK_RANGE(host_channels, 742 1, hw->host_channels, 743 hw->host_channels); 744 CHECK_RANGE(host_rx_fifo_size, 745 16, hw->rx_fifo_size, 746 hw->rx_fifo_size); 747 CHECK_RANGE(host_nperio_tx_fifo_size, 748 16, hw->host_nperio_tx_fifo_size, 749 hw->host_nperio_tx_fifo_size); 750 CHECK_RANGE(host_perio_tx_fifo_size, 751 16, hw->host_perio_tx_fifo_size, 752 hw->host_perio_tx_fifo_size); 753 } 754 755 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 756 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 757 CHECK_BOOL(g_dma, dma_capable); 758 CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable)); 759 CHECK_RANGE(g_rx_fifo_size, 760 16, hw->rx_fifo_size, 761 hw->rx_fifo_size); 762 CHECK_RANGE(g_np_tx_fifo_size, 763 16, hw->dev_nperio_tx_fifo_size, 764 hw->dev_nperio_tx_fifo_size); 765 dwc2_check_param_tx_fifo_sizes(hsotg); 766 } 767 } 768 769 /* 770 * Gets host hardware parameters. Forces host mode if not currently in 771 * host mode. Should be called immediately after a core soft reset in 772 * order to get the reset values. 773 */ 774 static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg) 775 { 776 struct dwc2_hw_params *hw = &hsotg->hw_params; 777 u32 gnptxfsiz; 778 u32 hptxfsiz; 779 780 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) 781 return; 782 783 dwc2_force_mode(hsotg, true); 784 785 gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ); 786 hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ); 787 788 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 789 FIFOSIZE_DEPTH_SHIFT; 790 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >> 791 FIFOSIZE_DEPTH_SHIFT; 792 } 793 794 /* 795 * Gets device hardware parameters. Forces device mode if not 796 * currently in device mode. Should be called immediately after a core 797 * soft reset in order to get the reset values. 798 */ 799 static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg) 800 { 801 struct dwc2_hw_params *hw = &hsotg->hw_params; 802 u32 gnptxfsiz; 803 int fifo, fifo_count; 804 805 if (hsotg->dr_mode == USB_DR_MODE_HOST) 806 return; 807 808 dwc2_force_mode(hsotg, false); 809 810 gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ); 811 812 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 813 814 for (fifo = 1; fifo <= fifo_count; fifo++) { 815 hw->g_tx_fifo_size[fifo] = 816 (dwc2_readl(hsotg, DPTXFSIZN(fifo)) & 817 FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT; 818 } 819 820 hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 821 FIFOSIZE_DEPTH_SHIFT; 822 } 823 824 /** 825 * dwc2_get_hwparams() - During device initialization, read various hardware 826 * configuration registers and interpret the contents. 827 * 828 * @hsotg: Programming view of the DWC_otg controller 829 * 830 */ 831 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) 832 { 833 struct dwc2_hw_params *hw = &hsotg->hw_params; 834 unsigned int width; 835 u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4; 836 u32 grxfsiz; 837 838 hwcfg1 = dwc2_readl(hsotg, GHWCFG1); 839 hwcfg2 = dwc2_readl(hsotg, GHWCFG2); 840 hwcfg3 = dwc2_readl(hsotg, GHWCFG3); 841 hwcfg4 = dwc2_readl(hsotg, GHWCFG4); 842 grxfsiz = dwc2_readl(hsotg, GRXFSIZ); 843 844 /* hwcfg1 */ 845 hw->dev_ep_dirs = hwcfg1; 846 847 /* hwcfg2 */ 848 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >> 849 GHWCFG2_OP_MODE_SHIFT; 850 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >> 851 GHWCFG2_ARCHITECTURE_SHIFT; 852 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO); 853 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >> 854 GHWCFG2_NUM_HOST_CHAN_SHIFT); 855 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >> 856 GHWCFG2_HS_PHY_TYPE_SHIFT; 857 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> 858 GHWCFG2_FS_PHY_TYPE_SHIFT; 859 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >> 860 GHWCFG2_NUM_DEV_EP_SHIFT; 861 hw->nperio_tx_q_depth = 862 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >> 863 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1; 864 hw->host_perio_tx_q_depth = 865 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >> 866 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1; 867 hw->dev_token_q_depth = 868 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >> 869 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT; 870 871 /* hwcfg3 */ 872 width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >> 873 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT; 874 hw->max_transfer_size = (1 << (width + 11)) - 1; 875 width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >> 876 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT; 877 hw->max_packet_count = (1 << (width + 4)) - 1; 878 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C); 879 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >> 880 GHWCFG3_DFIFO_DEPTH_SHIFT; 881 hw->lpm_mode = !!(hwcfg3 & GHWCFG3_OTG_LPM_EN); 882 883 /* hwcfg4 */ 884 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN); 885 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >> 886 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT; 887 hw->num_dev_in_eps = (hwcfg4 & GHWCFG4_NUM_IN_EPS_MASK) >> 888 GHWCFG4_NUM_IN_EPS_SHIFT; 889 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA); 890 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ); 891 hw->hibernation = !!(hwcfg4 & GHWCFG4_HIBER); 892 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >> 893 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT; 894 hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED); 895 hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED); 896 hw->service_interval_mode = !!(hwcfg4 & 897 GHWCFG4_SERVICE_INTERVAL_SUPPORTED); 898 899 /* fifo sizes */ 900 hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >> 901 GRXFSIZ_DEPTH_SHIFT; 902 /* 903 * Host specific hardware parameters. Reading these parameters 904 * requires the controller to be in host mode. The mode will 905 * be forced, if necessary, to read these values. 906 */ 907 dwc2_get_host_hwparams(hsotg); 908 dwc2_get_dev_hwparams(hsotg); 909 910 return 0; 911 } 912 913 typedef void (*set_params_cb)(struct dwc2_hsotg *data); 914 915 int dwc2_init_params(struct dwc2_hsotg *hsotg) 916 { 917 const struct of_device_id *match; 918 set_params_cb set_params; 919 920 dwc2_set_default_params(hsotg); 921 dwc2_get_device_properties(hsotg); 922 923 match = of_match_device(dwc2_of_match_table, hsotg->dev); 924 if (match && match->data) { 925 set_params = match->data; 926 set_params(hsotg); 927 } else { 928 const struct acpi_device_id *amatch; 929 930 amatch = acpi_match_device(dwc2_acpi_match, hsotg->dev); 931 if (amatch && amatch->driver_data) { 932 set_params = (set_params_cb)amatch->driver_data; 933 set_params(hsotg); 934 } 935 } 936 937 dwc2_check_params(hsotg); 938 939 return 0; 940 } 941