1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* 3 * Copyright (C) 2004-2016 Synopsys, Inc. 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/module.h> 8 #include <linux/of.h> 9 #include <linux/usb/of.h> 10 #include <linux/pci_ids.h> 11 #include <linux/pci.h> 12 13 #include "core.h" 14 15 #define PCI_PRODUCT_ID_HAPS_HSOTG 0xabc0 16 #define PCI_DEVICE_ID_LOONGSON_DWC2 0x7a04 17 18 static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg) 19 { 20 struct dwc2_core_params *p = &hsotg->params; 21 22 p->host_rx_fifo_size = 774; 23 p->max_transfer_size = 65535; 24 p->max_packet_count = 511; 25 p->ahbcfg = 0x10; 26 } 27 28 static void dwc2_set_his_params(struct dwc2_hsotg *hsotg) 29 { 30 struct dwc2_core_params *p = &hsotg->params; 31 32 p->otg_caps.hnp_support = false; 33 p->otg_caps.srp_support = false; 34 p->speed = DWC2_SPEED_PARAM_HIGH; 35 p->host_rx_fifo_size = 512; 36 p->host_nperio_tx_fifo_size = 512; 37 p->host_perio_tx_fifo_size = 512; 38 p->max_transfer_size = 65535; 39 p->max_packet_count = 511; 40 p->host_channels = 16; 41 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 42 p->phy_utmi_width = 8; 43 p->i2c_enable = false; 44 p->reload_ctl = false; 45 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 46 GAHBCFG_HBSTLEN_SHIFT; 47 p->change_speed_quirk = true; 48 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 49 } 50 51 static void dwc2_set_jz4775_params(struct dwc2_hsotg *hsotg) 52 { 53 struct dwc2_core_params *p = &hsotg->params; 54 55 p->otg_caps.hnp_support = false; 56 p->speed = DWC2_SPEED_PARAM_HIGH; 57 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 58 p->phy_utmi_width = 16; 59 p->activate_ingenic_overcurrent_detection = 60 !device_property_read_bool(hsotg->dev, "disable-over-current"); 61 } 62 63 static void dwc2_set_loongson_params(struct dwc2_hsotg *hsotg) 64 { 65 struct dwc2_core_params *p = &hsotg->params; 66 67 p->phy_utmi_width = 8; 68 p->power_down = DWC2_POWER_DOWN_PARAM_PARTIAL; 69 } 70 71 static void dwc2_set_x1600_params(struct dwc2_hsotg *hsotg) 72 { 73 struct dwc2_core_params *p = &hsotg->params; 74 75 p->otg_caps.hnp_support = false; 76 p->speed = DWC2_SPEED_PARAM_HIGH; 77 p->host_channels = 16; 78 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 79 p->phy_utmi_width = 16; 80 p->activate_ingenic_overcurrent_detection = 81 !device_property_read_bool(hsotg->dev, "disable-over-current"); 82 } 83 84 static void dwc2_set_x2000_params(struct dwc2_hsotg *hsotg) 85 { 86 struct dwc2_core_params *p = &hsotg->params; 87 88 p->otg_caps.hnp_support = false; 89 p->speed = DWC2_SPEED_PARAM_HIGH; 90 p->host_rx_fifo_size = 1024; 91 p->host_nperio_tx_fifo_size = 1024; 92 p->host_perio_tx_fifo_size = 1024; 93 p->host_channels = 16; 94 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 95 p->phy_utmi_width = 16; 96 p->activate_ingenic_overcurrent_detection = 97 !device_property_read_bool(hsotg->dev, "disable-over-current"); 98 } 99 100 static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg) 101 { 102 struct dwc2_core_params *p = &hsotg->params; 103 104 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 105 p->no_clock_gating = true; 106 p->phy_utmi_width = 8; 107 } 108 109 static void dwc2_set_socfpga_agilex_params(struct dwc2_hsotg *hsotg) 110 { 111 struct dwc2_core_params *p = &hsotg->params; 112 113 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 114 p->no_clock_gating = true; 115 } 116 117 static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg) 118 { 119 struct dwc2_core_params *p = &hsotg->params; 120 121 p->otg_caps.hnp_support = false; 122 p->otg_caps.srp_support = false; 123 p->host_rx_fifo_size = 525; 124 p->host_nperio_tx_fifo_size = 128; 125 p->host_perio_tx_fifo_size = 256; 126 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 127 GAHBCFG_HBSTLEN_SHIFT; 128 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 129 p->lpm = false; 130 p->lpm_clock_gating = false; 131 p->besl = false; 132 p->hird_threshold_en = false; 133 p->no_clock_gating = true; 134 } 135 136 static void dwc2_set_ltq_danube_params(struct dwc2_hsotg *hsotg) 137 { 138 struct dwc2_core_params *p = &hsotg->params; 139 140 p->otg_caps.hnp_support = false; 141 p->otg_caps.srp_support = false; 142 } 143 144 static void dwc2_set_ltq_ase_params(struct dwc2_hsotg *hsotg) 145 { 146 struct dwc2_core_params *p = &hsotg->params; 147 148 p->otg_caps.hnp_support = false; 149 p->otg_caps.srp_support = false; 150 p->host_rx_fifo_size = 288; 151 p->host_nperio_tx_fifo_size = 128; 152 p->host_perio_tx_fifo_size = 96; 153 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 154 GAHBCFG_HBSTLEN_SHIFT; 155 } 156 157 static void dwc2_set_ltq_xrx200_params(struct dwc2_hsotg *hsotg) 158 { 159 struct dwc2_core_params *p = &hsotg->params; 160 161 p->otg_caps.hnp_support = false; 162 p->otg_caps.srp_support = false; 163 p->host_rx_fifo_size = 288; 164 p->host_nperio_tx_fifo_size = 128; 165 p->host_perio_tx_fifo_size = 136; 166 } 167 168 static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg) 169 { 170 struct dwc2_core_params *p = &hsotg->params; 171 172 p->otg_caps.hnp_support = false; 173 p->otg_caps.srp_support = false; 174 p->speed = DWC2_SPEED_PARAM_HIGH; 175 p->host_rx_fifo_size = 512; 176 p->host_nperio_tx_fifo_size = 500; 177 p->host_perio_tx_fifo_size = 500; 178 p->host_channels = 16; 179 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 180 p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 << 181 GAHBCFG_HBSTLEN_SHIFT; 182 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 183 } 184 185 static void dwc2_set_amlogic_g12a_params(struct dwc2_hsotg *hsotg) 186 { 187 struct dwc2_core_params *p = &hsotg->params; 188 189 p->lpm = false; 190 p->lpm_clock_gating = false; 191 p->besl = false; 192 p->hird_threshold_en = false; 193 } 194 195 static void dwc2_set_amlogic_a1_params(struct dwc2_hsotg *hsotg) 196 { 197 struct dwc2_core_params *p = &hsotg->params; 198 199 p->otg_caps.hnp_support = false; 200 p->otg_caps.srp_support = false; 201 p->speed = DWC2_SPEED_PARAM_HIGH; 202 p->host_rx_fifo_size = 192; 203 p->host_nperio_tx_fifo_size = 128; 204 p->host_perio_tx_fifo_size = 128; 205 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 206 p->phy_utmi_width = 8; 207 p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 << GAHBCFG_HBSTLEN_SHIFT; 208 p->lpm = false; 209 p->lpm_clock_gating = false; 210 p->besl = false; 211 p->hird_threshold_en = false; 212 } 213 214 static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg) 215 { 216 struct dwc2_core_params *p = &hsotg->params; 217 218 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; 219 } 220 221 static void dwc2_set_cv1800_params(struct dwc2_hsotg *hsotg) 222 { 223 struct dwc2_core_params *p = &hsotg->params; 224 225 p->otg_caps.hnp_support = false; 226 p->otg_caps.srp_support = false; 227 p->host_dma = false; 228 p->g_dma = false; 229 p->speed = DWC2_SPEED_PARAM_HIGH; 230 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 231 p->phy_utmi_width = 16; 232 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; 233 p->lpm = false; 234 p->lpm_clock_gating = false; 235 p->besl = false; 236 p->hird_threshold_en = false; 237 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 238 } 239 240 static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg) 241 { 242 struct dwc2_core_params *p = &hsotg->params; 243 244 p->otg_caps.hnp_support = false; 245 p->otg_caps.srp_support = false; 246 p->speed = DWC2_SPEED_PARAM_FULL; 247 p->host_rx_fifo_size = 128; 248 p->host_nperio_tx_fifo_size = 96; 249 p->host_perio_tx_fifo_size = 96; 250 p->max_packet_count = 256; 251 p->phy_type = DWC2_PHY_TYPE_PARAM_FS; 252 p->i2c_enable = false; 253 p->activate_stm_fs_transceiver = true; 254 } 255 256 static void dwc2_set_stm32f7_hsotg_params(struct dwc2_hsotg *hsotg) 257 { 258 struct dwc2_core_params *p = &hsotg->params; 259 260 p->host_rx_fifo_size = 622; 261 p->host_nperio_tx_fifo_size = 128; 262 p->host_perio_tx_fifo_size = 256; 263 } 264 265 static void dwc2_set_stm32mp15_fsotg_params(struct dwc2_hsotg *hsotg) 266 { 267 struct dwc2_core_params *p = &hsotg->params; 268 269 p->otg_caps.hnp_support = false; 270 p->otg_caps.srp_support = false; 271 p->otg_caps.otg_rev = 0x200; 272 p->speed = DWC2_SPEED_PARAM_FULL; 273 p->host_rx_fifo_size = 128; 274 p->host_nperio_tx_fifo_size = 96; 275 p->host_perio_tx_fifo_size = 96; 276 p->max_packet_count = 256; 277 p->phy_type = DWC2_PHY_TYPE_PARAM_FS; 278 p->i2c_enable = false; 279 p->activate_stm_fs_transceiver = true; 280 p->activate_stm_id_vb_detection = true; 281 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; 282 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 283 p->host_support_fs_ls_low_power = true; 284 p->host_ls_low_power_phy_clk = true; 285 } 286 287 static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg) 288 { 289 struct dwc2_core_params *p = &hsotg->params; 290 291 p->otg_caps.hnp_support = false; 292 p->otg_caps.srp_support = false; 293 p->otg_caps.otg_rev = 0x200; 294 p->activate_stm_id_vb_detection = !device_property_read_bool(hsotg->dev, "usb-role-switch"); 295 p->host_rx_fifo_size = 440; 296 p->host_nperio_tx_fifo_size = 256; 297 p->host_perio_tx_fifo_size = 256; 298 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; 299 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 300 p->lpm = false; 301 p->lpm_clock_gating = false; 302 p->besl = false; 303 p->hird_threshold_en = false; 304 } 305 306 const struct of_device_id dwc2_of_match_table[] = { 307 { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params }, 308 { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params }, 309 { .compatible = "ingenic,jz4775-otg", .data = dwc2_set_jz4775_params }, 310 { .compatible = "ingenic,jz4780-otg", .data = dwc2_set_jz4775_params }, 311 { .compatible = "ingenic,x1000-otg", .data = dwc2_set_jz4775_params }, 312 { .compatible = "ingenic,x1600-otg", .data = dwc2_set_x1600_params }, 313 { .compatible = "ingenic,x1700-otg", .data = dwc2_set_x1600_params }, 314 { .compatible = "ingenic,x1830-otg", .data = dwc2_set_x1600_params }, 315 { .compatible = "ingenic,x2000-otg", .data = dwc2_set_x2000_params }, 316 { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params }, 317 { .compatible = "lantiq,danube-usb", .data = &dwc2_set_ltq_danube_params }, 318 { .compatible = "lantiq,ase-usb", .data = &dwc2_set_ltq_ase_params }, 319 { .compatible = "lantiq,arx100-usb", .data = &dwc2_set_ltq_ase_params }, 320 { .compatible = "lantiq,xrx200-usb", .data = &dwc2_set_ltq_xrx200_params }, 321 { .compatible = "lantiq,xrx300-usb", .data = &dwc2_set_ltq_xrx200_params }, 322 { .compatible = "snps,dwc2" }, 323 { .compatible = "samsung,s3c6400-hsotg", 324 .data = dwc2_set_s3c6400_params }, 325 { .compatible = "amlogic,meson8-usb", 326 .data = dwc2_set_amlogic_params }, 327 { .compatible = "amlogic,meson8b-usb", 328 .data = dwc2_set_amlogic_params }, 329 { .compatible = "amlogic,meson-gxbb-usb", 330 .data = dwc2_set_amlogic_params }, 331 { .compatible = "amlogic,meson-g12a-usb", 332 .data = dwc2_set_amlogic_g12a_params }, 333 { .compatible = "amlogic,meson-a1-usb", 334 .data = dwc2_set_amlogic_a1_params }, 335 { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params }, 336 { .compatible = "apm,apm82181-dwc-otg", .data = dwc2_set_amcc_params }, 337 { .compatible = "sophgo,cv1800-usb", 338 .data = dwc2_set_cv1800_params }, 339 { .compatible = "st,stm32f4x9-fsotg", 340 .data = dwc2_set_stm32f4x9_fsotg_params }, 341 { .compatible = "st,stm32f4x9-hsotg" }, 342 { .compatible = "st,stm32f7-hsotg", 343 .data = dwc2_set_stm32f7_hsotg_params }, 344 { .compatible = "st,stm32mp15-fsotg", 345 .data = dwc2_set_stm32mp15_fsotg_params }, 346 { .compatible = "st,stm32mp15-hsotg", 347 .data = dwc2_set_stm32mp15_hsotg_params }, 348 { .compatible = "intel,socfpga-agilex-hsotg", 349 .data = dwc2_set_socfpga_agilex_params }, 350 {}, 351 }; 352 MODULE_DEVICE_TABLE(of, dwc2_of_match_table); 353 354 const struct acpi_device_id dwc2_acpi_match[] = { 355 { "BCM2848", (kernel_ulong_t)dwc2_set_bcm_params }, 356 { }, 357 }; 358 MODULE_DEVICE_TABLE(acpi, dwc2_acpi_match); 359 360 const struct pci_device_id dwc2_pci_ids[] = { 361 { 362 PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS, PCI_PRODUCT_ID_HAPS_HSOTG), 363 }, 364 { 365 PCI_DEVICE(PCI_VENDOR_ID_STMICRO, 366 PCI_DEVICE_ID_STMICRO_USB_OTG), 367 }, 368 { 369 PCI_DEVICE(PCI_VENDOR_ID_LOONGSON, PCI_DEVICE_ID_LOONGSON_DWC2), 370 .driver_data = (unsigned long)dwc2_set_loongson_params, 371 }, 372 { /* end: all zeroes */ } 373 }; 374 MODULE_DEVICE_TABLE(pci, dwc2_pci_ids); 375 EXPORT_SYMBOL_GPL(dwc2_pci_ids); 376 377 static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg) 378 { 379 switch (hsotg->hw_params.op_mode) { 380 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 381 hsotg->params.otg_caps.hnp_support = true; 382 hsotg->params.otg_caps.srp_support = true; 383 break; 384 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 385 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 386 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 387 hsotg->params.otg_caps.hnp_support = false; 388 hsotg->params.otg_caps.srp_support = true; 389 break; 390 default: 391 hsotg->params.otg_caps.hnp_support = false; 392 hsotg->params.otg_caps.srp_support = false; 393 break; 394 } 395 } 396 397 static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg) 398 { 399 int val; 400 u32 hs_phy_type = hsotg->hw_params.hs_phy_type; 401 402 val = DWC2_PHY_TYPE_PARAM_FS; 403 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) { 404 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI || 405 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI) 406 val = DWC2_PHY_TYPE_PARAM_UTMI; 407 else 408 val = DWC2_PHY_TYPE_PARAM_ULPI; 409 } 410 411 if (dwc2_is_fs_iot(hsotg)) 412 hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS; 413 414 hsotg->params.phy_type = val; 415 } 416 417 static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg) 418 { 419 int val; 420 421 val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ? 422 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH; 423 424 if (dwc2_is_fs_iot(hsotg)) 425 val = DWC2_SPEED_PARAM_FULL; 426 427 if (dwc2_is_hs_iot(hsotg)) 428 val = DWC2_SPEED_PARAM_HIGH; 429 430 hsotg->params.speed = val; 431 } 432 433 static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg) 434 { 435 int val; 436 437 val = (hsotg->hw_params.utmi_phy_data_width == 438 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16; 439 440 if (hsotg->phy) { 441 /* 442 * If using the generic PHY framework, check if the PHY bus 443 * width is 8-bit and set the phyif appropriately. 444 */ 445 if (phy_get_bus_width(hsotg->phy) == 8) 446 val = 8; 447 } 448 449 hsotg->params.phy_utmi_width = val; 450 } 451 452 static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg) 453 { 454 struct dwc2_core_params *p = &hsotg->params; 455 int depth_average; 456 int fifo_count; 457 int i; 458 459 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 460 461 memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size)); 462 depth_average = dwc2_hsotg_tx_fifo_average_depth(hsotg); 463 for (i = 1; i <= fifo_count; i++) 464 p->g_tx_fifo_size[i] = depth_average; 465 } 466 467 static void dwc2_set_param_power_down(struct dwc2_hsotg *hsotg) 468 { 469 int val; 470 471 if (hsotg->hw_params.hibernation) 472 val = DWC2_POWER_DOWN_PARAM_HIBERNATION; 473 else if (hsotg->hw_params.power_optimized) 474 val = DWC2_POWER_DOWN_PARAM_PARTIAL; 475 else 476 val = DWC2_POWER_DOWN_PARAM_NONE; 477 478 hsotg->params.power_down = val; 479 } 480 481 static void dwc2_set_param_lpm(struct dwc2_hsotg *hsotg) 482 { 483 struct dwc2_core_params *p = &hsotg->params; 484 485 p->lpm = hsotg->hw_params.lpm_mode; 486 if (p->lpm) { 487 p->lpm_clock_gating = true; 488 p->besl = true; 489 p->hird_threshold_en = true; 490 p->hird_threshold = 4; 491 } else { 492 p->lpm_clock_gating = false; 493 p->besl = false; 494 p->hird_threshold_en = false; 495 } 496 } 497 498 /** 499 * dwc2_set_default_params() - Set all core parameters to their 500 * auto-detected default values. 501 * 502 * @hsotg: Programming view of the DWC_otg controller 503 * 504 */ 505 static void dwc2_set_default_params(struct dwc2_hsotg *hsotg) 506 { 507 struct dwc2_hw_params *hw = &hsotg->hw_params; 508 struct dwc2_core_params *p = &hsotg->params; 509 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); 510 511 dwc2_set_param_otg_cap(hsotg); 512 dwc2_set_param_phy_type(hsotg); 513 dwc2_set_param_speed(hsotg); 514 dwc2_set_param_phy_utmi_width(hsotg); 515 dwc2_set_param_power_down(hsotg); 516 dwc2_set_param_lpm(hsotg); 517 p->phy_ulpi_ddr = false; 518 p->phy_ulpi_ext_vbus = false; 519 p->eusb2_disc = false; 520 521 p->enable_dynamic_fifo = hw->enable_dynamic_fifo; 522 p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo; 523 p->i2c_enable = hw->i2c_enable; 524 p->acg_enable = hw->acg_enable; 525 p->ulpi_fs_ls = false; 526 p->ts_dline = false; 527 p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a); 528 p->uframe_sched = true; 529 p->external_id_pin_ctl = false; 530 p->ipg_isoc_en = false; 531 p->service_interval = false; 532 p->max_packet_count = hw->max_packet_count; 533 p->max_transfer_size = hw->max_transfer_size; 534 p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT; 535 p->ref_clk_per = 33333; 536 p->sof_cnt_wkup_alert = 100; 537 538 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || 539 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 540 p->host_dma = dma_capable; 541 p->dma_desc_enable = false; 542 p->dma_desc_fs_enable = false; 543 p->host_support_fs_ls_low_power = false; 544 p->host_ls_low_power_phy_clk = false; 545 p->host_channels = hw->host_channels; 546 p->host_rx_fifo_size = hw->rx_fifo_size; 547 p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size; 548 p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size; 549 } 550 551 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 552 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 553 p->g_dma = dma_capable; 554 p->g_dma_desc = hw->dma_desc_enable; 555 556 /* 557 * The values for g_rx_fifo_size (2048) and 558 * g_np_tx_fifo_size (1024) come from the legacy s3c 559 * gadget driver. These defaults have been hard-coded 560 * for some time so many platforms depend on these 561 * values. Leave them as defaults for now and only 562 * auto-detect if the hardware does not support the 563 * default. 564 */ 565 p->g_rx_fifo_size = 2048; 566 p->g_np_tx_fifo_size = 1024; 567 dwc2_set_param_tx_fifo_sizes(hsotg); 568 } 569 } 570 571 /** 572 * dwc2_get_device_properties() - Read in device properties. 573 * 574 * @hsotg: Programming view of the DWC_otg controller 575 * 576 * Read in the device properties and adjust core parameters if needed. 577 */ 578 static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg) 579 { 580 struct dwc2_core_params *p = &hsotg->params; 581 int num; 582 583 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 584 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 585 device_property_read_u32(hsotg->dev, "g-rx-fifo-size", 586 &p->g_rx_fifo_size); 587 588 device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size", 589 &p->g_np_tx_fifo_size); 590 591 num = device_property_count_u32(hsotg->dev, "g-tx-fifo-size"); 592 if (num > 0) { 593 num = min(num, 15); 594 memset(p->g_tx_fifo_size, 0, 595 sizeof(p->g_tx_fifo_size)); 596 device_property_read_u32_array(hsotg->dev, 597 "g-tx-fifo-size", 598 &p->g_tx_fifo_size[1], 599 num); 600 } 601 602 of_usb_update_otg_caps(hsotg->dev->of_node, &p->otg_caps); 603 } 604 605 p->oc_disable = of_property_read_bool(hsotg->dev->of_node, "disable-over-current"); 606 } 607 608 static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg) 609 { 610 int valid = 1; 611 612 if (hsotg->params.otg_caps.hnp_support && hsotg->params.otg_caps.srp_support) { 613 /* check HNP && SRP capable */ 614 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) 615 valid = 0; 616 } else if (!hsotg->params.otg_caps.hnp_support) { 617 /* check SRP only capable */ 618 if (hsotg->params.otg_caps.srp_support) { 619 switch (hsotg->hw_params.op_mode) { 620 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 621 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 622 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 623 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 624 break; 625 default: 626 valid = 0; 627 break; 628 } 629 } 630 /* else: NO HNP && NO SRP capable: always valid */ 631 } else { 632 valid = 0; 633 } 634 635 if (!valid) 636 dwc2_set_param_otg_cap(hsotg); 637 } 638 639 static void dwc2_check_param_phy_type(struct dwc2_hsotg *hsotg) 640 { 641 int valid = 0; 642 u32 hs_phy_type; 643 u32 fs_phy_type; 644 645 hs_phy_type = hsotg->hw_params.hs_phy_type; 646 fs_phy_type = hsotg->hw_params.fs_phy_type; 647 648 switch (hsotg->params.phy_type) { 649 case DWC2_PHY_TYPE_PARAM_FS: 650 if (fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) 651 valid = 1; 652 break; 653 case DWC2_PHY_TYPE_PARAM_UTMI: 654 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) || 655 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 656 valid = 1; 657 break; 658 case DWC2_PHY_TYPE_PARAM_ULPI: 659 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) || 660 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 661 valid = 1; 662 break; 663 default: 664 break; 665 } 666 667 if (!valid) 668 dwc2_set_param_phy_type(hsotg); 669 } 670 671 static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg) 672 { 673 int valid = 1; 674 int phy_type = hsotg->params.phy_type; 675 int speed = hsotg->params.speed; 676 677 switch (speed) { 678 case DWC2_SPEED_PARAM_HIGH: 679 if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) && 680 (phy_type == DWC2_PHY_TYPE_PARAM_FS)) 681 valid = 0; 682 break; 683 case DWC2_SPEED_PARAM_FULL: 684 case DWC2_SPEED_PARAM_LOW: 685 break; 686 default: 687 valid = 0; 688 break; 689 } 690 691 if (!valid) 692 dwc2_set_param_speed(hsotg); 693 } 694 695 static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg *hsotg) 696 { 697 int valid = 0; 698 int param = hsotg->params.phy_utmi_width; 699 int width = hsotg->hw_params.utmi_phy_data_width; 700 701 switch (width) { 702 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8: 703 valid = (param == 8); 704 break; 705 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16: 706 valid = (param == 16); 707 break; 708 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16: 709 valid = (param == 8 || param == 16); 710 break; 711 } 712 713 if (!valid) 714 dwc2_set_param_phy_utmi_width(hsotg); 715 } 716 717 static void dwc2_check_param_power_down(struct dwc2_hsotg *hsotg) 718 { 719 int param = hsotg->params.power_down; 720 721 switch (param) { 722 case DWC2_POWER_DOWN_PARAM_NONE: 723 break; 724 case DWC2_POWER_DOWN_PARAM_PARTIAL: 725 if (hsotg->hw_params.power_optimized) 726 break; 727 dev_dbg(hsotg->dev, 728 "Partial power down isn't supported by HW\n"); 729 param = DWC2_POWER_DOWN_PARAM_NONE; 730 break; 731 case DWC2_POWER_DOWN_PARAM_HIBERNATION: 732 if (hsotg->hw_params.hibernation) 733 break; 734 dev_dbg(hsotg->dev, 735 "Hibernation isn't supported by HW\n"); 736 param = DWC2_POWER_DOWN_PARAM_NONE; 737 break; 738 default: 739 dev_err(hsotg->dev, 740 "%s: Invalid parameter power_down=%d\n", 741 __func__, param); 742 param = DWC2_POWER_DOWN_PARAM_NONE; 743 break; 744 } 745 746 hsotg->params.power_down = param; 747 } 748 749 static void dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg) 750 { 751 int fifo_count; 752 int fifo; 753 int min; 754 u32 total = 0; 755 u32 dptxfszn; 756 757 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 758 min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4; 759 760 for (fifo = 1; fifo <= fifo_count; fifo++) 761 total += hsotg->params.g_tx_fifo_size[fifo]; 762 763 if (total > dwc2_hsotg_tx_fifo_total_depth(hsotg) || !total) { 764 dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n", 765 __func__); 766 dwc2_set_param_tx_fifo_sizes(hsotg); 767 } 768 769 for (fifo = 1; fifo <= fifo_count; fifo++) { 770 dptxfszn = hsotg->hw_params.g_tx_fifo_size[fifo]; 771 772 if (hsotg->params.g_tx_fifo_size[fifo] < min || 773 hsotg->params.g_tx_fifo_size[fifo] > dptxfszn) { 774 dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n", 775 __func__, fifo, 776 hsotg->params.g_tx_fifo_size[fifo]); 777 hsotg->params.g_tx_fifo_size[fifo] = dptxfszn; 778 } 779 } 780 } 781 782 static void dwc2_check_param_eusb2_disc(struct dwc2_hsotg *hsotg) 783 { 784 u32 gsnpsid; 785 786 if (!hsotg->params.eusb2_disc) 787 return; 788 gsnpsid = dwc2_readl(hsotg, GSNPSID); 789 /* 790 * eusb2_disc not supported by FS IOT devices. 791 * For other cores, it supported starting from version 5.00a 792 */ 793 if ((gsnpsid & ~DWC2_CORE_REV_MASK) == DWC2_FS_IOT_ID || 794 (gsnpsid & DWC2_CORE_REV_MASK) < 795 (DWC2_CORE_REV_5_00a & DWC2_CORE_REV_MASK)) { 796 hsotg->params.eusb2_disc = false; 797 return; 798 } 799 } 800 801 #define CHECK_RANGE(_param, _min, _max, _def) do { \ 802 if ((int)(hsotg->params._param) < (_min) || \ 803 (hsotg->params._param) > (_max)) { \ 804 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \ 805 __func__, #_param, hsotg->params._param); \ 806 hsotg->params._param = (_def); \ 807 } \ 808 } while (0) 809 810 #define CHECK_BOOL(_param, _check) do { \ 811 if (hsotg->params._param && !(_check)) { \ 812 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \ 813 __func__, #_param, hsotg->params._param); \ 814 hsotg->params._param = false; \ 815 } \ 816 } while (0) 817 818 static void dwc2_check_params(struct dwc2_hsotg *hsotg) 819 { 820 struct dwc2_hw_params *hw = &hsotg->hw_params; 821 struct dwc2_core_params *p = &hsotg->params; 822 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); 823 824 dwc2_check_param_otg_cap(hsotg); 825 dwc2_check_param_phy_type(hsotg); 826 dwc2_check_param_speed(hsotg); 827 dwc2_check_param_phy_utmi_width(hsotg); 828 dwc2_check_param_power_down(hsotg); 829 dwc2_check_param_eusb2_disc(hsotg); 830 831 CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo); 832 CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo); 833 CHECK_BOOL(i2c_enable, hw->i2c_enable); 834 CHECK_BOOL(ipg_isoc_en, hw->ipg_isoc_en); 835 CHECK_BOOL(acg_enable, hw->acg_enable); 836 CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a)); 837 CHECK_BOOL(lpm, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_80a)); 838 CHECK_BOOL(lpm, hw->lpm_mode); 839 CHECK_BOOL(lpm_clock_gating, hsotg->params.lpm); 840 CHECK_BOOL(besl, hsotg->params.lpm); 841 CHECK_BOOL(besl, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a)); 842 CHECK_BOOL(hird_threshold_en, hsotg->params.lpm); 843 CHECK_RANGE(hird_threshold, 0, hsotg->params.besl ? 12 : 7, 0); 844 CHECK_BOOL(service_interval, hw->service_interval_mode); 845 CHECK_RANGE(max_packet_count, 846 15, hw->max_packet_count, 847 hw->max_packet_count); 848 CHECK_RANGE(max_transfer_size, 849 2047, hw->max_transfer_size, 850 hw->max_transfer_size); 851 852 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || 853 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 854 CHECK_BOOL(host_dma, dma_capable); 855 CHECK_BOOL(dma_desc_enable, p->host_dma); 856 CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable); 857 CHECK_BOOL(host_ls_low_power_phy_clk, 858 p->phy_type == DWC2_PHY_TYPE_PARAM_FS); 859 CHECK_RANGE(host_channels, 860 1, hw->host_channels, 861 hw->host_channels); 862 CHECK_RANGE(host_rx_fifo_size, 863 16, hw->rx_fifo_size, 864 hw->rx_fifo_size); 865 CHECK_RANGE(host_nperio_tx_fifo_size, 866 16, hw->host_nperio_tx_fifo_size, 867 hw->host_nperio_tx_fifo_size); 868 CHECK_RANGE(host_perio_tx_fifo_size, 869 16, hw->host_perio_tx_fifo_size, 870 hw->host_perio_tx_fifo_size); 871 } 872 873 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 874 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 875 CHECK_BOOL(g_dma, dma_capable); 876 CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable)); 877 CHECK_RANGE(g_rx_fifo_size, 878 16, hw->rx_fifo_size, 879 hw->rx_fifo_size); 880 CHECK_RANGE(g_np_tx_fifo_size, 881 16, hw->dev_nperio_tx_fifo_size, 882 hw->dev_nperio_tx_fifo_size); 883 dwc2_check_param_tx_fifo_sizes(hsotg); 884 } 885 } 886 887 /* 888 * Gets host hardware parameters. Forces host mode if not currently in 889 * host mode. Should be called immediately after a core soft reset in 890 * order to get the reset values. 891 */ 892 static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg) 893 { 894 struct dwc2_hw_params *hw = &hsotg->hw_params; 895 u32 gnptxfsiz; 896 u32 hptxfsiz; 897 898 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) 899 return; 900 901 dwc2_force_mode(hsotg, true); 902 903 gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ); 904 hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ); 905 906 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 907 FIFOSIZE_DEPTH_SHIFT; 908 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >> 909 FIFOSIZE_DEPTH_SHIFT; 910 } 911 912 /* 913 * Gets device hardware parameters. Forces device mode if not 914 * currently in device mode. Should be called immediately after a core 915 * soft reset in order to get the reset values. 916 */ 917 static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg) 918 { 919 struct dwc2_hw_params *hw = &hsotg->hw_params; 920 u32 gnptxfsiz; 921 int fifo, fifo_count; 922 923 if (hsotg->dr_mode == USB_DR_MODE_HOST) 924 return; 925 926 dwc2_force_mode(hsotg, false); 927 928 gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ); 929 930 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 931 932 for (fifo = 1; fifo <= fifo_count; fifo++) { 933 hw->g_tx_fifo_size[fifo] = 934 (dwc2_readl(hsotg, DPTXFSIZN(fifo)) & 935 FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT; 936 } 937 938 hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 939 FIFOSIZE_DEPTH_SHIFT; 940 } 941 942 /** 943 * dwc2_get_hwparams() - During device initialization, read various hardware 944 * configuration registers and interpret the contents. 945 * 946 * @hsotg: Programming view of the DWC_otg controller 947 * 948 */ 949 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) 950 { 951 struct dwc2_hw_params *hw = &hsotg->hw_params; 952 unsigned int width; 953 u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4; 954 u32 grxfsiz; 955 956 hwcfg1 = dwc2_readl(hsotg, GHWCFG1); 957 hwcfg2 = dwc2_readl(hsotg, GHWCFG2); 958 hwcfg3 = dwc2_readl(hsotg, GHWCFG3); 959 hwcfg4 = dwc2_readl(hsotg, GHWCFG4); 960 grxfsiz = dwc2_readl(hsotg, GRXFSIZ); 961 962 /* hwcfg1 */ 963 hw->dev_ep_dirs = hwcfg1; 964 965 /* hwcfg2 */ 966 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >> 967 GHWCFG2_OP_MODE_SHIFT; 968 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >> 969 GHWCFG2_ARCHITECTURE_SHIFT; 970 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO); 971 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >> 972 GHWCFG2_NUM_HOST_CHAN_SHIFT); 973 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >> 974 GHWCFG2_HS_PHY_TYPE_SHIFT; 975 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> 976 GHWCFG2_FS_PHY_TYPE_SHIFT; 977 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >> 978 GHWCFG2_NUM_DEV_EP_SHIFT; 979 hw->nperio_tx_q_depth = 980 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >> 981 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1; 982 hw->host_perio_tx_q_depth = 983 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >> 984 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1; 985 hw->dev_token_q_depth = 986 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >> 987 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT; 988 989 /* hwcfg3 */ 990 width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >> 991 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT; 992 hw->max_transfer_size = (1 << (width + 11)) - 1; 993 width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >> 994 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT; 995 hw->max_packet_count = (1 << (width + 4)) - 1; 996 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C); 997 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >> 998 GHWCFG3_DFIFO_DEPTH_SHIFT; 999 hw->lpm_mode = !!(hwcfg3 & GHWCFG3_OTG_LPM_EN); 1000 1001 /* hwcfg4 */ 1002 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN); 1003 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >> 1004 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT; 1005 hw->num_dev_in_eps = (hwcfg4 & GHWCFG4_NUM_IN_EPS_MASK) >> 1006 GHWCFG4_NUM_IN_EPS_SHIFT; 1007 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA); 1008 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ); 1009 hw->hibernation = !!(hwcfg4 & GHWCFG4_HIBER); 1010 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >> 1011 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT; 1012 hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED); 1013 hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED); 1014 hw->service_interval_mode = !!(hwcfg4 & 1015 GHWCFG4_SERVICE_INTERVAL_SUPPORTED); 1016 1017 /* fifo sizes */ 1018 hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >> 1019 GRXFSIZ_DEPTH_SHIFT; 1020 /* 1021 * Host specific hardware parameters. Reading these parameters 1022 * requires the controller to be in host mode. The mode will 1023 * be forced, if necessary, to read these values. 1024 */ 1025 dwc2_get_host_hwparams(hsotg); 1026 dwc2_get_dev_hwparams(hsotg); 1027 1028 return 0; 1029 } 1030 1031 typedef void (*set_params_cb)(struct dwc2_hsotg *data); 1032 1033 int dwc2_init_params(struct dwc2_hsotg *hsotg) 1034 { 1035 set_params_cb set_params; 1036 1037 dwc2_set_default_params(hsotg); 1038 dwc2_get_device_properties(hsotg); 1039 1040 set_params = device_get_match_data(hsotg->dev); 1041 if (set_params) { 1042 set_params(hsotg); 1043 } else { 1044 const struct pci_device_id *pmatch = 1045 pci_match_id(dwc2_pci_ids, to_pci_dev(hsotg->dev->parent)); 1046 1047 if (pmatch && pmatch->driver_data) { 1048 set_params = (set_params_cb)pmatch->driver_data; 1049 set_params(hsotg); 1050 } 1051 } 1052 1053 dwc2_check_params(hsotg); 1054 1055 return 0; 1056 } 1057