xref: /linux/drivers/usb/dwc2/params.c (revision 151ebcf0797b1a3ba53c8843dc21748c80e098c7)
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /*
3  * Copyright (C) 2004-2016 Synopsys, Inc.
4  */
5 
6 #include <linux/kernel.h>
7 #include <linux/module.h>
8 #include <linux/of.h>
9 #include <linux/usb/of.h>
10 #include <linux/pci_ids.h>
11 #include <linux/pci.h>
12 
13 #include "core.h"
14 
15 #define PCI_PRODUCT_ID_HAPS_HSOTG	0xabc0
16 #define PCI_DEVICE_ID_LOONGSON_DWC2	0x7a04
17 
18 static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg)
19 {
20 	struct dwc2_core_params *p = &hsotg->params;
21 
22 	p->host_rx_fifo_size = 774;
23 	p->max_transfer_size = 65535;
24 	p->max_packet_count = 511;
25 	p->ahbcfg = 0x10;
26 }
27 
28 static void dwc2_set_his_params(struct dwc2_hsotg *hsotg)
29 {
30 	struct dwc2_core_params *p = &hsotg->params;
31 
32 	p->otg_caps.hnp_support = false;
33 	p->otg_caps.srp_support = false;
34 	p->speed = DWC2_SPEED_PARAM_HIGH;
35 	p->host_rx_fifo_size = 512;
36 	p->host_nperio_tx_fifo_size = 512;
37 	p->host_perio_tx_fifo_size = 512;
38 	p->max_transfer_size = 65535;
39 	p->max_packet_count = 511;
40 	p->host_channels = 16;
41 	p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
42 	p->phy_utmi_width = 8;
43 	p->i2c_enable = false;
44 	p->reload_ctl = false;
45 	p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
46 		GAHBCFG_HBSTLEN_SHIFT;
47 	p->change_speed_quirk = true;
48 	p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
49 }
50 
51 static void dwc2_set_jz4775_params(struct dwc2_hsotg *hsotg)
52 {
53 	struct dwc2_core_params *p = &hsotg->params;
54 
55 	p->otg_caps.hnp_support = false;
56 	p->speed = DWC2_SPEED_PARAM_HIGH;
57 	p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
58 	p->phy_utmi_width = 16;
59 	p->activate_ingenic_overcurrent_detection =
60 		!device_property_read_bool(hsotg->dev, "disable-over-current");
61 }
62 
63 static void dwc2_set_loongson_params(struct dwc2_hsotg *hsotg)
64 {
65 	struct dwc2_core_params *p = &hsotg->params;
66 
67 	p->phy_utmi_width = 8;
68 	p->power_down = DWC2_POWER_DOWN_PARAM_PARTIAL;
69 }
70 
71 static void dwc2_set_x1600_params(struct dwc2_hsotg *hsotg)
72 {
73 	struct dwc2_core_params *p = &hsotg->params;
74 
75 	p->otg_caps.hnp_support = false;
76 	p->speed = DWC2_SPEED_PARAM_HIGH;
77 	p->host_channels = 16;
78 	p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
79 	p->phy_utmi_width = 16;
80 	p->activate_ingenic_overcurrent_detection =
81 		!device_property_read_bool(hsotg->dev, "disable-over-current");
82 }
83 
84 static void dwc2_set_x2000_params(struct dwc2_hsotg *hsotg)
85 {
86 	struct dwc2_core_params *p = &hsotg->params;
87 
88 	p->otg_caps.hnp_support = false;
89 	p->speed = DWC2_SPEED_PARAM_HIGH;
90 	p->host_rx_fifo_size = 1024;
91 	p->host_nperio_tx_fifo_size = 1024;
92 	p->host_perio_tx_fifo_size = 1024;
93 	p->host_channels = 16;
94 	p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
95 	p->phy_utmi_width = 16;
96 	p->activate_ingenic_overcurrent_detection =
97 		!device_property_read_bool(hsotg->dev, "disable-over-current");
98 }
99 
100 static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg)
101 {
102 	struct dwc2_core_params *p = &hsotg->params;
103 
104 	p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
105 	p->no_clock_gating = true;
106 	p->phy_utmi_width = 8;
107 }
108 
109 static void dwc2_set_socfpga_agilex_params(struct dwc2_hsotg *hsotg)
110 {
111 	struct dwc2_core_params *p = &hsotg->params;
112 
113 	p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
114 	p->no_clock_gating = true;
115 }
116 
117 static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg)
118 {
119 	struct dwc2_core_params *p = &hsotg->params;
120 
121 	p->otg_caps.hnp_support = false;
122 	p->otg_caps.srp_support = false;
123 	p->host_rx_fifo_size = 525;
124 	p->host_nperio_tx_fifo_size = 128;
125 	p->host_perio_tx_fifo_size = 256;
126 	p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
127 		GAHBCFG_HBSTLEN_SHIFT;
128 	p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
129 	p->lpm = false;
130 	p->lpm_clock_gating = false;
131 	p->besl = false;
132 	p->hird_threshold_en = false;
133 	p->no_clock_gating = true;
134 }
135 
136 static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg)
137 {
138 	struct dwc2_core_params *p = &hsotg->params;
139 
140 	p->otg_caps.hnp_support = false;
141 	p->otg_caps.srp_support = false;
142 	p->host_rx_fifo_size = 288;
143 	p->host_nperio_tx_fifo_size = 128;
144 	p->host_perio_tx_fifo_size = 96;
145 	p->max_transfer_size = 65535;
146 	p->max_packet_count = 511;
147 	p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
148 		GAHBCFG_HBSTLEN_SHIFT;
149 }
150 
151 static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg)
152 {
153 	struct dwc2_core_params *p = &hsotg->params;
154 
155 	p->otg_caps.hnp_support = false;
156 	p->otg_caps.srp_support = false;
157 	p->speed = DWC2_SPEED_PARAM_HIGH;
158 	p->host_rx_fifo_size = 512;
159 	p->host_nperio_tx_fifo_size = 500;
160 	p->host_perio_tx_fifo_size = 500;
161 	p->host_channels = 16;
162 	p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
163 	p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 <<
164 		GAHBCFG_HBSTLEN_SHIFT;
165 	p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
166 }
167 
168 static void dwc2_set_amlogic_g12a_params(struct dwc2_hsotg *hsotg)
169 {
170 	struct dwc2_core_params *p = &hsotg->params;
171 
172 	p->lpm = false;
173 	p->lpm_clock_gating = false;
174 	p->besl = false;
175 	p->hird_threshold_en = false;
176 }
177 
178 static void dwc2_set_amlogic_a1_params(struct dwc2_hsotg *hsotg)
179 {
180 	struct dwc2_core_params *p = &hsotg->params;
181 
182 	p->otg_caps.hnp_support = false;
183 	p->otg_caps.srp_support = false;
184 	p->speed = DWC2_SPEED_PARAM_HIGH;
185 	p->host_rx_fifo_size = 192;
186 	p->host_nperio_tx_fifo_size = 128;
187 	p->host_perio_tx_fifo_size = 128;
188 	p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
189 	p->phy_utmi_width = 8;
190 	p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 << GAHBCFG_HBSTLEN_SHIFT;
191 	p->lpm = false;
192 	p->lpm_clock_gating = false;
193 	p->besl = false;
194 	p->hird_threshold_en = false;
195 }
196 
197 static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg)
198 {
199 	struct dwc2_core_params *p = &hsotg->params;
200 
201 	p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
202 }
203 
204 static void dwc2_set_cv1800_params(struct dwc2_hsotg *hsotg)
205 {
206 	struct dwc2_core_params *p = &hsotg->params;
207 
208 	p->otg_caps.hnp_support = false;
209 	p->otg_caps.srp_support = false;
210 	p->host_dma = false;
211 	p->g_dma = false;
212 	p->speed = DWC2_SPEED_PARAM_HIGH;
213 	p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
214 	p->phy_utmi_width = 16;
215 	p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
216 	p->lpm = false;
217 	p->lpm_clock_gating = false;
218 	p->besl = false;
219 	p->hird_threshold_en = false;
220 	p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
221 }
222 
223 static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg)
224 {
225 	struct dwc2_core_params *p = &hsotg->params;
226 
227 	p->otg_caps.hnp_support = false;
228 	p->otg_caps.srp_support = false;
229 	p->speed = DWC2_SPEED_PARAM_FULL;
230 	p->host_rx_fifo_size = 128;
231 	p->host_nperio_tx_fifo_size = 96;
232 	p->host_perio_tx_fifo_size = 96;
233 	p->max_packet_count = 256;
234 	p->phy_type = DWC2_PHY_TYPE_PARAM_FS;
235 	p->i2c_enable = false;
236 	p->activate_stm_fs_transceiver = true;
237 }
238 
239 static void dwc2_set_stm32f7_hsotg_params(struct dwc2_hsotg *hsotg)
240 {
241 	struct dwc2_core_params *p = &hsotg->params;
242 
243 	p->host_rx_fifo_size = 622;
244 	p->host_nperio_tx_fifo_size = 128;
245 	p->host_perio_tx_fifo_size = 256;
246 }
247 
248 static void dwc2_set_stm32mp15_fsotg_params(struct dwc2_hsotg *hsotg)
249 {
250 	struct dwc2_core_params *p = &hsotg->params;
251 
252 	p->otg_caps.hnp_support = false;
253 	p->otg_caps.srp_support = false;
254 	p->otg_caps.otg_rev = 0x200;
255 	p->speed = DWC2_SPEED_PARAM_FULL;
256 	p->host_rx_fifo_size = 128;
257 	p->host_nperio_tx_fifo_size = 96;
258 	p->host_perio_tx_fifo_size = 96;
259 	p->max_packet_count = 256;
260 	p->phy_type = DWC2_PHY_TYPE_PARAM_FS;
261 	p->i2c_enable = false;
262 	p->activate_stm_fs_transceiver = true;
263 	p->activate_stm_id_vb_detection = true;
264 	p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
265 	p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
266 	p->host_support_fs_ls_low_power = true;
267 	p->host_ls_low_power_phy_clk = true;
268 }
269 
270 static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg)
271 {
272 	struct dwc2_core_params *p = &hsotg->params;
273 
274 	p->otg_caps.hnp_support = false;
275 	p->otg_caps.srp_support = false;
276 	p->otg_caps.otg_rev = 0x200;
277 	p->activate_stm_id_vb_detection = !device_property_read_bool(hsotg->dev, "usb-role-switch");
278 	p->host_rx_fifo_size = 440;
279 	p->host_nperio_tx_fifo_size = 256;
280 	p->host_perio_tx_fifo_size = 256;
281 	p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
282 	p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
283 	p->lpm = false;
284 	p->lpm_clock_gating = false;
285 	p->besl = false;
286 	p->hird_threshold_en = false;
287 }
288 
289 const struct of_device_id dwc2_of_match_table[] = {
290 	{ .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
291 	{ .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params },
292 	{ .compatible = "ingenic,jz4775-otg", .data = dwc2_set_jz4775_params },
293 	{ .compatible = "ingenic,jz4780-otg", .data = dwc2_set_jz4775_params },
294 	{ .compatible = "ingenic,x1000-otg", .data = dwc2_set_jz4775_params },
295 	{ .compatible = "ingenic,x1600-otg", .data = dwc2_set_x1600_params },
296 	{ .compatible = "ingenic,x1700-otg", .data = dwc2_set_x1600_params },
297 	{ .compatible = "ingenic,x1830-otg", .data = dwc2_set_x1600_params },
298 	{ .compatible = "ingenic,x2000-otg", .data = dwc2_set_x2000_params },
299 	{ .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params },
300 	{ .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params },
301 	{ .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params },
302 	{ .compatible = "snps,dwc2" },
303 	{ .compatible = "samsung,s3c6400-hsotg",
304 	  .data = dwc2_set_s3c6400_params },
305 	{ .compatible = "amlogic,meson8-usb",
306 	  .data = dwc2_set_amlogic_params },
307 	{ .compatible = "amlogic,meson8b-usb",
308 	  .data = dwc2_set_amlogic_params },
309 	{ .compatible = "amlogic,meson-gxbb-usb",
310 	  .data = dwc2_set_amlogic_params },
311 	{ .compatible = "amlogic,meson-g12a-usb",
312 	  .data = dwc2_set_amlogic_g12a_params },
313 	{ .compatible = "amlogic,meson-a1-usb",
314 	  .data = dwc2_set_amlogic_a1_params },
315 	{ .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params },
316 	{ .compatible = "apm,apm82181-dwc-otg", .data = dwc2_set_amcc_params },
317 	{ .compatible = "sophgo,cv1800-usb",
318 	  .data = dwc2_set_cv1800_params },
319 	{ .compatible = "st,stm32f4x9-fsotg",
320 	  .data = dwc2_set_stm32f4x9_fsotg_params },
321 	{ .compatible = "st,stm32f4x9-hsotg" },
322 	{ .compatible = "st,stm32f7-hsotg",
323 	  .data = dwc2_set_stm32f7_hsotg_params },
324 	{ .compatible = "st,stm32mp15-fsotg",
325 	  .data = dwc2_set_stm32mp15_fsotg_params },
326 	{ .compatible = "st,stm32mp15-hsotg",
327 	  .data = dwc2_set_stm32mp15_hsotg_params },
328 	{ .compatible = "intel,socfpga-agilex-hsotg",
329 	  .data = dwc2_set_socfpga_agilex_params },
330 	{},
331 };
332 MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
333 
334 const struct acpi_device_id dwc2_acpi_match[] = {
335 	{ "BCM2848", (kernel_ulong_t)dwc2_set_bcm_params },
336 	{ },
337 };
338 MODULE_DEVICE_TABLE(acpi, dwc2_acpi_match);
339 
340 const struct pci_device_id dwc2_pci_ids[] = {
341 	{
342 		PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS, PCI_PRODUCT_ID_HAPS_HSOTG),
343 	},
344 	{
345 		PCI_DEVICE(PCI_VENDOR_ID_STMICRO,
346 			   PCI_DEVICE_ID_STMICRO_USB_OTG),
347 	},
348 	{
349 		PCI_DEVICE(PCI_VENDOR_ID_LOONGSON, PCI_DEVICE_ID_LOONGSON_DWC2),
350 		.driver_data = (unsigned long)dwc2_set_loongson_params,
351 	},
352 	{ /* end: all zeroes */ }
353 };
354 MODULE_DEVICE_TABLE(pci, dwc2_pci_ids);
355 EXPORT_SYMBOL_GPL(dwc2_pci_ids);
356 
357 static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg)
358 {
359 	switch (hsotg->hw_params.op_mode) {
360 	case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
361 		hsotg->params.otg_caps.hnp_support = true;
362 		hsotg->params.otg_caps.srp_support = true;
363 		break;
364 	case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
365 	case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
366 	case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
367 		hsotg->params.otg_caps.hnp_support = false;
368 		hsotg->params.otg_caps.srp_support = true;
369 		break;
370 	default:
371 		hsotg->params.otg_caps.hnp_support = false;
372 		hsotg->params.otg_caps.srp_support = false;
373 		break;
374 	}
375 }
376 
377 static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg)
378 {
379 	int val;
380 	u32 hs_phy_type = hsotg->hw_params.hs_phy_type;
381 
382 	val = DWC2_PHY_TYPE_PARAM_FS;
383 	if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) {
384 		if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
385 		    hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)
386 			val = DWC2_PHY_TYPE_PARAM_UTMI;
387 		else
388 			val = DWC2_PHY_TYPE_PARAM_ULPI;
389 	}
390 
391 	if (dwc2_is_fs_iot(hsotg))
392 		hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS;
393 
394 	hsotg->params.phy_type = val;
395 }
396 
397 static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg)
398 {
399 	int val;
400 
401 	val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ?
402 		DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH;
403 
404 	if (dwc2_is_fs_iot(hsotg))
405 		val = DWC2_SPEED_PARAM_FULL;
406 
407 	if (dwc2_is_hs_iot(hsotg))
408 		val = DWC2_SPEED_PARAM_HIGH;
409 
410 	hsotg->params.speed = val;
411 }
412 
413 static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
414 {
415 	int val;
416 
417 	val = (hsotg->hw_params.utmi_phy_data_width ==
418 	       GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
419 
420 	if (hsotg->phy) {
421 		/*
422 		 * If using the generic PHY framework, check if the PHY bus
423 		 * width is 8-bit and set the phyif appropriately.
424 		 */
425 		if (phy_get_bus_width(hsotg->phy) == 8)
426 			val = 8;
427 	}
428 
429 	hsotg->params.phy_utmi_width = val;
430 }
431 
432 static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
433 {
434 	struct dwc2_core_params *p = &hsotg->params;
435 	int depth_average;
436 	int fifo_count;
437 	int i;
438 
439 	fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
440 
441 	memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size));
442 	depth_average = dwc2_hsotg_tx_fifo_average_depth(hsotg);
443 	for (i = 1; i <= fifo_count; i++)
444 		p->g_tx_fifo_size[i] = depth_average;
445 }
446 
447 static void dwc2_set_param_power_down(struct dwc2_hsotg *hsotg)
448 {
449 	int val;
450 
451 	if (hsotg->hw_params.hibernation)
452 		val = DWC2_POWER_DOWN_PARAM_HIBERNATION;
453 	else if (hsotg->hw_params.power_optimized)
454 		val = DWC2_POWER_DOWN_PARAM_PARTIAL;
455 	else
456 		val = DWC2_POWER_DOWN_PARAM_NONE;
457 
458 	hsotg->params.power_down = val;
459 }
460 
461 static void dwc2_set_param_lpm(struct dwc2_hsotg *hsotg)
462 {
463 	struct dwc2_core_params *p = &hsotg->params;
464 
465 	p->lpm = hsotg->hw_params.lpm_mode;
466 	if (p->lpm) {
467 		p->lpm_clock_gating = true;
468 		p->besl = true;
469 		p->hird_threshold_en = true;
470 		p->hird_threshold = 4;
471 	} else {
472 		p->lpm_clock_gating = false;
473 		p->besl = false;
474 		p->hird_threshold_en = false;
475 	}
476 }
477 
478 /**
479  * dwc2_set_default_params() - Set all core parameters to their
480  * auto-detected default values.
481  *
482  * @hsotg: Programming view of the DWC_otg controller
483  *
484  */
485 static void dwc2_set_default_params(struct dwc2_hsotg *hsotg)
486 {
487 	struct dwc2_hw_params *hw = &hsotg->hw_params;
488 	struct dwc2_core_params *p = &hsotg->params;
489 	bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
490 
491 	dwc2_set_param_otg_cap(hsotg);
492 	dwc2_set_param_phy_type(hsotg);
493 	dwc2_set_param_speed(hsotg);
494 	dwc2_set_param_phy_utmi_width(hsotg);
495 	dwc2_set_param_power_down(hsotg);
496 	dwc2_set_param_lpm(hsotg);
497 	p->phy_ulpi_ddr = false;
498 	p->phy_ulpi_ext_vbus = false;
499 	p->eusb2_disc = false;
500 
501 	p->enable_dynamic_fifo = hw->enable_dynamic_fifo;
502 	p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo;
503 	p->i2c_enable = hw->i2c_enable;
504 	p->acg_enable = hw->acg_enable;
505 	p->ulpi_fs_ls = false;
506 	p->ts_dline = false;
507 	p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a);
508 	p->uframe_sched = true;
509 	p->external_id_pin_ctl = false;
510 	p->ipg_isoc_en = false;
511 	p->service_interval = false;
512 	p->max_packet_count = hw->max_packet_count;
513 	p->max_transfer_size = hw->max_transfer_size;
514 	p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT;
515 	p->ref_clk_per = 33333;
516 	p->sof_cnt_wkup_alert = 100;
517 
518 	if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
519 	    (hsotg->dr_mode == USB_DR_MODE_OTG)) {
520 		p->host_dma = dma_capable;
521 		p->dma_desc_enable = false;
522 		p->dma_desc_fs_enable = false;
523 		p->host_support_fs_ls_low_power = false;
524 		p->host_ls_low_power_phy_clk = false;
525 		p->host_channels = hw->host_channels;
526 		p->host_rx_fifo_size = hw->rx_fifo_size;
527 		p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size;
528 		p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size;
529 	}
530 
531 	if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
532 	    (hsotg->dr_mode == USB_DR_MODE_OTG)) {
533 		p->g_dma = dma_capable;
534 		p->g_dma_desc = hw->dma_desc_enable;
535 
536 		/*
537 		 * The values for g_rx_fifo_size (2048) and
538 		 * g_np_tx_fifo_size (1024) come from the legacy s3c
539 		 * gadget driver. These defaults have been hard-coded
540 		 * for some time so many platforms depend on these
541 		 * values. Leave them as defaults for now and only
542 		 * auto-detect if the hardware does not support the
543 		 * default.
544 		 */
545 		p->g_rx_fifo_size = 2048;
546 		p->g_np_tx_fifo_size = 1024;
547 		dwc2_set_param_tx_fifo_sizes(hsotg);
548 	}
549 }
550 
551 /**
552  * dwc2_get_device_properties() - Read in device properties.
553  *
554  * @hsotg: Programming view of the DWC_otg controller
555  *
556  * Read in the device properties and adjust core parameters if needed.
557  */
558 static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg)
559 {
560 	struct dwc2_core_params *p = &hsotg->params;
561 	int num;
562 
563 	if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
564 	    (hsotg->dr_mode == USB_DR_MODE_OTG)) {
565 		device_property_read_u32(hsotg->dev, "g-rx-fifo-size",
566 					 &p->g_rx_fifo_size);
567 
568 		device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size",
569 					 &p->g_np_tx_fifo_size);
570 
571 		num = device_property_count_u32(hsotg->dev, "g-tx-fifo-size");
572 		if (num > 0) {
573 			num = min(num, 15);
574 			memset(p->g_tx_fifo_size, 0,
575 			       sizeof(p->g_tx_fifo_size));
576 			device_property_read_u32_array(hsotg->dev,
577 						       "g-tx-fifo-size",
578 						       &p->g_tx_fifo_size[1],
579 						       num);
580 		}
581 
582 		of_usb_update_otg_caps(hsotg->dev->of_node, &p->otg_caps);
583 	}
584 
585 	p->oc_disable = of_property_read_bool(hsotg->dev->of_node, "disable-over-current");
586 }
587 
588 static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg)
589 {
590 	int valid = 1;
591 
592 	if (hsotg->params.otg_caps.hnp_support && hsotg->params.otg_caps.srp_support) {
593 		/* check HNP && SRP capable */
594 		if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE)
595 			valid = 0;
596 	} else if (!hsotg->params.otg_caps.hnp_support) {
597 		/* check SRP only capable */
598 		if (hsotg->params.otg_caps.srp_support) {
599 			switch (hsotg->hw_params.op_mode) {
600 			case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
601 			case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
602 			case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
603 			case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
604 				break;
605 			default:
606 				valid = 0;
607 				break;
608 			}
609 		}
610 		/* else: NO HNP && NO SRP capable: always valid */
611 	} else {
612 		valid = 0;
613 	}
614 
615 	if (!valid)
616 		dwc2_set_param_otg_cap(hsotg);
617 }
618 
619 static void dwc2_check_param_phy_type(struct dwc2_hsotg *hsotg)
620 {
621 	int valid = 0;
622 	u32 hs_phy_type;
623 	u32 fs_phy_type;
624 
625 	hs_phy_type = hsotg->hw_params.hs_phy_type;
626 	fs_phy_type = hsotg->hw_params.fs_phy_type;
627 
628 	switch (hsotg->params.phy_type) {
629 	case DWC2_PHY_TYPE_PARAM_FS:
630 		if (fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
631 			valid = 1;
632 		break;
633 	case DWC2_PHY_TYPE_PARAM_UTMI:
634 		if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
635 		    (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
636 			valid = 1;
637 		break;
638 	case DWC2_PHY_TYPE_PARAM_ULPI:
639 		if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
640 		    (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
641 			valid = 1;
642 		break;
643 	default:
644 		break;
645 	}
646 
647 	if (!valid)
648 		dwc2_set_param_phy_type(hsotg);
649 }
650 
651 static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg)
652 {
653 	int valid = 1;
654 	int phy_type = hsotg->params.phy_type;
655 	int speed = hsotg->params.speed;
656 
657 	switch (speed) {
658 	case DWC2_SPEED_PARAM_HIGH:
659 		if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) &&
660 		    (phy_type == DWC2_PHY_TYPE_PARAM_FS))
661 			valid = 0;
662 		break;
663 	case DWC2_SPEED_PARAM_FULL:
664 	case DWC2_SPEED_PARAM_LOW:
665 		break;
666 	default:
667 		valid = 0;
668 		break;
669 	}
670 
671 	if (!valid)
672 		dwc2_set_param_speed(hsotg);
673 }
674 
675 static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
676 {
677 	int valid = 0;
678 	int param = hsotg->params.phy_utmi_width;
679 	int width = hsotg->hw_params.utmi_phy_data_width;
680 
681 	switch (width) {
682 	case GHWCFG4_UTMI_PHY_DATA_WIDTH_8:
683 		valid = (param == 8);
684 		break;
685 	case GHWCFG4_UTMI_PHY_DATA_WIDTH_16:
686 		valid = (param == 16);
687 		break;
688 	case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16:
689 		valid = (param == 8 || param == 16);
690 		break;
691 	}
692 
693 	if (!valid)
694 		dwc2_set_param_phy_utmi_width(hsotg);
695 }
696 
697 static void dwc2_check_param_power_down(struct dwc2_hsotg *hsotg)
698 {
699 	int param = hsotg->params.power_down;
700 
701 	switch (param) {
702 	case DWC2_POWER_DOWN_PARAM_NONE:
703 		break;
704 	case DWC2_POWER_DOWN_PARAM_PARTIAL:
705 		if (hsotg->hw_params.power_optimized)
706 			break;
707 		dev_dbg(hsotg->dev,
708 			"Partial power down isn't supported by HW\n");
709 		param = DWC2_POWER_DOWN_PARAM_NONE;
710 		break;
711 	case DWC2_POWER_DOWN_PARAM_HIBERNATION:
712 		if (hsotg->hw_params.hibernation)
713 			break;
714 		dev_dbg(hsotg->dev,
715 			"Hibernation isn't supported by HW\n");
716 		param = DWC2_POWER_DOWN_PARAM_NONE;
717 		break;
718 	default:
719 		dev_err(hsotg->dev,
720 			"%s: Invalid parameter power_down=%d\n",
721 			__func__, param);
722 		param = DWC2_POWER_DOWN_PARAM_NONE;
723 		break;
724 	}
725 
726 	hsotg->params.power_down = param;
727 }
728 
729 static void dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
730 {
731 	int fifo_count;
732 	int fifo;
733 	int min;
734 	u32 total = 0;
735 	u32 dptxfszn;
736 
737 	fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
738 	min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4;
739 
740 	for (fifo = 1; fifo <= fifo_count; fifo++)
741 		total += hsotg->params.g_tx_fifo_size[fifo];
742 
743 	if (total > dwc2_hsotg_tx_fifo_total_depth(hsotg) || !total) {
744 		dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n",
745 			 __func__);
746 		dwc2_set_param_tx_fifo_sizes(hsotg);
747 	}
748 
749 	for (fifo = 1; fifo <= fifo_count; fifo++) {
750 		dptxfszn = hsotg->hw_params.g_tx_fifo_size[fifo];
751 
752 		if (hsotg->params.g_tx_fifo_size[fifo] < min ||
753 		    hsotg->params.g_tx_fifo_size[fifo] >  dptxfszn) {
754 			dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n",
755 				 __func__, fifo,
756 				 hsotg->params.g_tx_fifo_size[fifo]);
757 			hsotg->params.g_tx_fifo_size[fifo] = dptxfszn;
758 		}
759 	}
760 }
761 
762 static void dwc2_check_param_eusb2_disc(struct dwc2_hsotg *hsotg)
763 {
764 	u32 gsnpsid;
765 
766 	if (!hsotg->params.eusb2_disc)
767 		return;
768 	gsnpsid = dwc2_readl(hsotg, GSNPSID);
769 	/*
770 	 * eusb2_disc not supported by FS IOT devices.
771 	 * For other cores, it supported starting from version 5.00a
772 	 */
773 	if ((gsnpsid & ~DWC2_CORE_REV_MASK) == DWC2_FS_IOT_ID ||
774 	    (gsnpsid & DWC2_CORE_REV_MASK) <
775 	    (DWC2_CORE_REV_5_00a & DWC2_CORE_REV_MASK)) {
776 		hsotg->params.eusb2_disc = false;
777 		return;
778 	}
779 }
780 
781 #define CHECK_RANGE(_param, _min, _max, _def) do {			\
782 		if ((int)(hsotg->params._param) < (_min) ||		\
783 		    (hsotg->params._param) > (_max)) {			\
784 			dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
785 				 __func__, #_param, hsotg->params._param); \
786 			hsotg->params._param = (_def);			\
787 		}							\
788 	} while (0)
789 
790 #define CHECK_BOOL(_param, _check) do {					\
791 		if (hsotg->params._param && !(_check)) {		\
792 			dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
793 				 __func__, #_param, hsotg->params._param); \
794 			hsotg->params._param = false;			\
795 		}							\
796 	} while (0)
797 
798 static void dwc2_check_params(struct dwc2_hsotg *hsotg)
799 {
800 	struct dwc2_hw_params *hw = &hsotg->hw_params;
801 	struct dwc2_core_params *p = &hsotg->params;
802 	bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
803 
804 	dwc2_check_param_otg_cap(hsotg);
805 	dwc2_check_param_phy_type(hsotg);
806 	dwc2_check_param_speed(hsotg);
807 	dwc2_check_param_phy_utmi_width(hsotg);
808 	dwc2_check_param_power_down(hsotg);
809 	dwc2_check_param_eusb2_disc(hsotg);
810 
811 	CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo);
812 	CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo);
813 	CHECK_BOOL(i2c_enable, hw->i2c_enable);
814 	CHECK_BOOL(ipg_isoc_en, hw->ipg_isoc_en);
815 	CHECK_BOOL(acg_enable, hw->acg_enable);
816 	CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a));
817 	CHECK_BOOL(lpm, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_80a));
818 	CHECK_BOOL(lpm, hw->lpm_mode);
819 	CHECK_BOOL(lpm_clock_gating, hsotg->params.lpm);
820 	CHECK_BOOL(besl, hsotg->params.lpm);
821 	CHECK_BOOL(besl, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a));
822 	CHECK_BOOL(hird_threshold_en, hsotg->params.lpm);
823 	CHECK_RANGE(hird_threshold, 0, hsotg->params.besl ? 12 : 7, 0);
824 	CHECK_BOOL(service_interval, hw->service_interval_mode);
825 	CHECK_RANGE(max_packet_count,
826 		    15, hw->max_packet_count,
827 		    hw->max_packet_count);
828 	CHECK_RANGE(max_transfer_size,
829 		    2047, hw->max_transfer_size,
830 		    hw->max_transfer_size);
831 
832 	if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
833 	    (hsotg->dr_mode == USB_DR_MODE_OTG)) {
834 		CHECK_BOOL(host_dma, dma_capable);
835 		CHECK_BOOL(dma_desc_enable, p->host_dma);
836 		CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable);
837 		CHECK_BOOL(host_ls_low_power_phy_clk,
838 			   p->phy_type == DWC2_PHY_TYPE_PARAM_FS);
839 		CHECK_RANGE(host_channels,
840 			    1, hw->host_channels,
841 			    hw->host_channels);
842 		CHECK_RANGE(host_rx_fifo_size,
843 			    16, hw->rx_fifo_size,
844 			    hw->rx_fifo_size);
845 		CHECK_RANGE(host_nperio_tx_fifo_size,
846 			    16, hw->host_nperio_tx_fifo_size,
847 			    hw->host_nperio_tx_fifo_size);
848 		CHECK_RANGE(host_perio_tx_fifo_size,
849 			    16, hw->host_perio_tx_fifo_size,
850 			    hw->host_perio_tx_fifo_size);
851 	}
852 
853 	if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
854 	    (hsotg->dr_mode == USB_DR_MODE_OTG)) {
855 		CHECK_BOOL(g_dma, dma_capable);
856 		CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable));
857 		CHECK_RANGE(g_rx_fifo_size,
858 			    16, hw->rx_fifo_size,
859 			    hw->rx_fifo_size);
860 		CHECK_RANGE(g_np_tx_fifo_size,
861 			    16, hw->dev_nperio_tx_fifo_size,
862 			    hw->dev_nperio_tx_fifo_size);
863 		dwc2_check_param_tx_fifo_sizes(hsotg);
864 	}
865 }
866 
867 /*
868  * Gets host hardware parameters. Forces host mode if not currently in
869  * host mode. Should be called immediately after a core soft reset in
870  * order to get the reset values.
871  */
872 static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg)
873 {
874 	struct dwc2_hw_params *hw = &hsotg->hw_params;
875 	u32 gnptxfsiz;
876 	u32 hptxfsiz;
877 
878 	if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
879 		return;
880 
881 	dwc2_force_mode(hsotg, true);
882 
883 	gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
884 	hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ);
885 
886 	hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
887 				       FIFOSIZE_DEPTH_SHIFT;
888 	hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >>
889 				      FIFOSIZE_DEPTH_SHIFT;
890 }
891 
892 /*
893  * Gets device hardware parameters. Forces device mode if not
894  * currently in device mode. Should be called immediately after a core
895  * soft reset in order to get the reset values.
896  */
897 static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg)
898 {
899 	struct dwc2_hw_params *hw = &hsotg->hw_params;
900 	u32 gnptxfsiz;
901 	int fifo, fifo_count;
902 
903 	if (hsotg->dr_mode == USB_DR_MODE_HOST)
904 		return;
905 
906 	dwc2_force_mode(hsotg, false);
907 
908 	gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
909 
910 	fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
911 
912 	for (fifo = 1; fifo <= fifo_count; fifo++) {
913 		hw->g_tx_fifo_size[fifo] =
914 			(dwc2_readl(hsotg, DPTXFSIZN(fifo)) &
915 			 FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT;
916 	}
917 
918 	hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
919 				       FIFOSIZE_DEPTH_SHIFT;
920 }
921 
922 /**
923  * dwc2_get_hwparams() - During device initialization, read various hardware
924  *                       configuration registers and interpret the contents.
925  *
926  * @hsotg: Programming view of the DWC_otg controller
927  *
928  */
929 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
930 {
931 	struct dwc2_hw_params *hw = &hsotg->hw_params;
932 	unsigned int width;
933 	u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4;
934 	u32 grxfsiz;
935 
936 	hwcfg1 = dwc2_readl(hsotg, GHWCFG1);
937 	hwcfg2 = dwc2_readl(hsotg, GHWCFG2);
938 	hwcfg3 = dwc2_readl(hsotg, GHWCFG3);
939 	hwcfg4 = dwc2_readl(hsotg, GHWCFG4);
940 	grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
941 
942 	/* hwcfg1 */
943 	hw->dev_ep_dirs = hwcfg1;
944 
945 	/* hwcfg2 */
946 	hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
947 		      GHWCFG2_OP_MODE_SHIFT;
948 	hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
949 		   GHWCFG2_ARCHITECTURE_SHIFT;
950 	hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO);
951 	hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >>
952 				GHWCFG2_NUM_HOST_CHAN_SHIFT);
953 	hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
954 			  GHWCFG2_HS_PHY_TYPE_SHIFT;
955 	hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
956 			  GHWCFG2_FS_PHY_TYPE_SHIFT;
957 	hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >>
958 			 GHWCFG2_NUM_DEV_EP_SHIFT;
959 	hw->nperio_tx_q_depth =
960 		(hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >>
961 		GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1;
962 	hw->host_perio_tx_q_depth =
963 		(hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >>
964 		GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1;
965 	hw->dev_token_q_depth =
966 		(hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >>
967 		GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT;
968 
969 	/* hwcfg3 */
970 	width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >>
971 		GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT;
972 	hw->max_transfer_size = (1 << (width + 11)) - 1;
973 	width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >>
974 		GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT;
975 	hw->max_packet_count = (1 << (width + 4)) - 1;
976 	hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C);
977 	hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >>
978 			      GHWCFG3_DFIFO_DEPTH_SHIFT;
979 	hw->lpm_mode = !!(hwcfg3 & GHWCFG3_OTG_LPM_EN);
980 
981 	/* hwcfg4 */
982 	hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN);
983 	hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >>
984 				  GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT;
985 	hw->num_dev_in_eps = (hwcfg4 & GHWCFG4_NUM_IN_EPS_MASK) >>
986 			     GHWCFG4_NUM_IN_EPS_SHIFT;
987 	hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA);
988 	hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ);
989 	hw->hibernation = !!(hwcfg4 & GHWCFG4_HIBER);
990 	hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >>
991 				  GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT;
992 	hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED);
993 	hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED);
994 	hw->service_interval_mode = !!(hwcfg4 &
995 				       GHWCFG4_SERVICE_INTERVAL_SUPPORTED);
996 
997 	/* fifo sizes */
998 	hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >>
999 				GRXFSIZ_DEPTH_SHIFT;
1000 	/*
1001 	 * Host specific hardware parameters. Reading these parameters
1002 	 * requires the controller to be in host mode. The mode will
1003 	 * be forced, if necessary, to read these values.
1004 	 */
1005 	dwc2_get_host_hwparams(hsotg);
1006 	dwc2_get_dev_hwparams(hsotg);
1007 
1008 	return 0;
1009 }
1010 
1011 typedef void (*set_params_cb)(struct dwc2_hsotg *data);
1012 
1013 int dwc2_init_params(struct dwc2_hsotg *hsotg)
1014 {
1015 	set_params_cb set_params;
1016 
1017 	dwc2_set_default_params(hsotg);
1018 	dwc2_get_device_properties(hsotg);
1019 
1020 	set_params = device_get_match_data(hsotg->dev);
1021 	if (set_params) {
1022 		set_params(hsotg);
1023 	} else {
1024 		const struct pci_device_id *pmatch =
1025 			pci_match_id(dwc2_pci_ids, to_pci_dev(hsotg->dev->parent));
1026 
1027 		if (pmatch && pmatch->driver_data) {
1028 			set_params = (set_params_cb)pmatch->driver_data;
1029 			set_params(hsotg);
1030 		}
1031 	}
1032 
1033 	dwc2_check_params(hsotg);
1034 
1035 	return 0;
1036 }
1037