1 /* 2 * hcd_queue.c - DesignWare HS OTG Controller host queuing routines 3 * 4 * Copyright (C) 2004-2013 Synopsys, Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The names of the above-listed copyright holders may not be used 16 * to endorse or promote products derived from this software without 17 * specific prior written permission. 18 * 19 * ALTERNATIVELY, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") as published by the Free Software 21 * Foundation; either version 2 of the License, or (at your option) any 22 * later version. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * This file contains the functions to manage Queue Heads and Queue 39 * Transfer Descriptors for Host mode 40 */ 41 #include <linux/gcd.h> 42 #include <linux/kernel.h> 43 #include <linux/module.h> 44 #include <linux/spinlock.h> 45 #include <linux/interrupt.h> 46 #include <linux/dma-mapping.h> 47 #include <linux/io.h> 48 #include <linux/slab.h> 49 #include <linux/usb.h> 50 51 #include <linux/usb/hcd.h> 52 #include <linux/usb/ch11.h> 53 54 #include "core.h" 55 #include "hcd.h" 56 57 /* Wait this long before releasing periodic reservation */ 58 #define DWC2_UNRESERVE_DELAY (msecs_to_jiffies(5)) 59 60 /** 61 * dwc2_periodic_channel_available() - Checks that a channel is available for a 62 * periodic transfer 63 * 64 * @hsotg: The HCD state structure for the DWC OTG controller 65 * 66 * Return: 0 if successful, negative error code otherwise 67 */ 68 static int dwc2_periodic_channel_available(struct dwc2_hsotg *hsotg) 69 { 70 /* 71 * Currently assuming that there is a dedicated host channel for 72 * each periodic transaction plus at least one host channel for 73 * non-periodic transactions 74 */ 75 int status; 76 int num_channels; 77 78 num_channels = hsotg->params.host_channels; 79 if ((hsotg->periodic_channels + hsotg->non_periodic_channels < 80 num_channels) && (hsotg->periodic_channels < num_channels - 1)) { 81 status = 0; 82 } else { 83 dev_dbg(hsotg->dev, 84 "%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n", 85 __func__, num_channels, 86 hsotg->periodic_channels, hsotg->non_periodic_channels); 87 status = -ENOSPC; 88 } 89 90 return status; 91 } 92 93 /** 94 * dwc2_check_periodic_bandwidth() - Checks that there is sufficient bandwidth 95 * for the specified QH in the periodic schedule 96 * 97 * @hsotg: The HCD state structure for the DWC OTG controller 98 * @qh: QH containing periodic bandwidth required 99 * 100 * Return: 0 if successful, negative error code otherwise 101 * 102 * For simplicity, this calculation assumes that all the transfers in the 103 * periodic schedule may occur in the same (micro)frame 104 */ 105 static int dwc2_check_periodic_bandwidth(struct dwc2_hsotg *hsotg, 106 struct dwc2_qh *qh) 107 { 108 int status; 109 s16 max_claimed_usecs; 110 111 status = 0; 112 113 if (qh->dev_speed == USB_SPEED_HIGH || qh->do_split) { 114 /* 115 * High speed mode 116 * Max periodic usecs is 80% x 125 usec = 100 usec 117 */ 118 max_claimed_usecs = 100 - qh->host_us; 119 } else { 120 /* 121 * Full speed mode 122 * Max periodic usecs is 90% x 1000 usec = 900 usec 123 */ 124 max_claimed_usecs = 900 - qh->host_us; 125 } 126 127 if (hsotg->periodic_usecs > max_claimed_usecs) { 128 dev_err(hsotg->dev, 129 "%s: already claimed usecs %d, required usecs %d\n", 130 __func__, hsotg->periodic_usecs, qh->host_us); 131 status = -ENOSPC; 132 } 133 134 return status; 135 } 136 137 /** 138 * pmap_schedule() - Schedule time in a periodic bitmap (pmap). 139 * 140 * @map: The bitmap representing the schedule; will be updated 141 * upon success. 142 * @bits_per_period: The schedule represents several periods. This is how many 143 * bits are in each period. It's assumed that the beginning 144 * of the schedule will repeat after its end. 145 * @periods_in_map: The number of periods in the schedule. 146 * @num_bits: The number of bits we need per period we want to reserve 147 * in this function call. 148 * @interval: How often we need to be scheduled for the reservation this 149 * time. 1 means every period. 2 means every other period. 150 * ...you get the picture? 151 * @start: The bit number to start at. Normally 0. Must be within 152 * the interval or we return failure right away. 153 * @only_one_period: Normally we'll allow picking a start anywhere within the 154 * first interval, since we can still make all repetition 155 * requirements by doing that. However, if you pass true 156 * here then we'll return failure if we can't fit within 157 * the period that "start" is in. 158 * 159 * The idea here is that we want to schedule time for repeating events that all 160 * want the same resource. The resource is divided into fixed-sized periods 161 * and the events want to repeat every "interval" periods. The schedule 162 * granularity is one bit. 163 * 164 * To keep things "simple", we'll represent our schedule with a bitmap that 165 * contains a fixed number of periods. This gets rid of a lot of complexity 166 * but does mean that we need to handle things specially (and non-ideally) if 167 * the number of the periods in the schedule doesn't match well with the 168 * intervals that we're trying to schedule. 169 * 170 * Here's an explanation of the scheme we'll implement, assuming 8 periods. 171 * - If interval is 1, we need to take up space in each of the 8 172 * periods we're scheduling. Easy. 173 * - If interval is 2, we need to take up space in half of the 174 * periods. Again, easy. 175 * - If interval is 3, we actually need to fall back to interval 1. 176 * Why? Because we might need time in any period. AKA for the 177 * first 8 periods, we'll be in slot 0, 3, 6. Then we'll be 178 * in slot 1, 4, 7. Then we'll be in 2, 5. Then we'll be back to 179 * 0, 3, and 6. Since we could be in any frame we need to reserve 180 * for all of them. Sucks, but that's what you gotta do. Note that 181 * if we were instead scheduling 8 * 3 = 24 we'd do much better, but 182 * then we need more memory and time to do scheduling. 183 * - If interval is 4, easy. 184 * - If interval is 5, we again need interval 1. The schedule will be 185 * 0, 5, 2, 7, 4, 1, 6, 3, 0 186 * - If interval is 6, we need interval 2. 0, 6, 4, 2. 187 * - If interval is 7, we need interval 1. 188 * - If interval is 8, we need interval 8. 189 * 190 * If you do the math, you'll see that we need to pretend that interval is 191 * equal to the greatest_common_divisor(interval, periods_in_map). 192 * 193 * Note that at the moment this function tends to front-pack the schedule. 194 * In some cases that's really non-ideal (it's hard to schedule things that 195 * need to repeat every period). In other cases it's perfect (you can easily 196 * schedule bigger, less often repeating things). 197 * 198 * Here's the algorithm in action (8 periods, 5 bits per period): 199 * |** | |** | |** | |** | | OK 2 bits, intv 2 at 0 200 * |*****| ***|*****| ***|*****| ***|*****| ***| OK 3 bits, intv 3 at 2 201 * |*****|* ***|*****| ***|*****|* ***|*****| ***| OK 1 bits, intv 4 at 5 202 * |** |* |** | |** |* |** | | Remv 3 bits, intv 3 at 2 203 * |*** |* |*** | |*** |* |*** | | OK 1 bits, intv 6 at 2 204 * |**** |* * |**** | * |**** |* * |**** | * | OK 1 bits, intv 1 at 3 205 * |**** |**** |**** | *** |**** |**** |**** | *** | OK 2 bits, intv 2 at 6 206 * |*****|*****|*****| ****|*****|*****|*****| ****| OK 1 bits, intv 1 at 4 207 * |*****|*****|*****| ****|*****|*****|*****| ****| FAIL 1 bits, intv 1 208 * | ***|*****| ***| ****| ***|*****| ***| ****| Remv 2 bits, intv 2 at 0 209 * | ***| ****| ***| ****| ***| ****| ***| ****| Remv 1 bits, intv 4 at 5 210 * | **| ****| **| ****| **| ****| **| ****| Remv 1 bits, intv 6 at 2 211 * | *| ** *| *| ** *| *| ** *| *| ** *| Remv 1 bits, intv 1 at 3 212 * | *| *| *| *| *| *| *| *| Remv 2 bits, intv 2 at 6 213 * | | | | | | | | | Remv 1 bits, intv 1 at 4 214 * |** | |** | |** | |** | | OK 2 bits, intv 2 at 0 215 * |*** | |** | |*** | |** | | OK 1 bits, intv 4 at 2 216 * |*****| |** **| |*****| |** **| | OK 2 bits, intv 2 at 3 217 * |*****|* |** **| |*****|* |** **| | OK 1 bits, intv 4 at 5 218 * |*****|*** |** **| ** |*****|*** |** **| ** | OK 2 bits, intv 2 at 6 219 * |*****|*****|** **| ****|*****|*****|** **| ****| OK 2 bits, intv 2 at 8 220 * |*****|*****|*****| ****|*****|*****|*****| ****| OK 1 bits, intv 4 at 12 221 * 222 * This function is pretty generic and could be easily abstracted if anything 223 * needed similar scheduling. 224 * 225 * Returns either -ENOSPC or a >= 0 start bit which should be passed to the 226 * unschedule routine. The map bitmap will be updated on a non-error result. 227 */ 228 static int pmap_schedule(unsigned long *map, int bits_per_period, 229 int periods_in_map, int num_bits, 230 int interval, int start, bool only_one_period) 231 { 232 int interval_bits; 233 int to_reserve; 234 int first_end; 235 int i; 236 237 if (num_bits > bits_per_period) 238 return -ENOSPC; 239 240 /* Adjust interval as per description */ 241 interval = gcd(interval, periods_in_map); 242 243 interval_bits = bits_per_period * interval; 244 to_reserve = periods_in_map / interval; 245 246 /* If start has gotten us past interval then we can't schedule */ 247 if (start >= interval_bits) 248 return -ENOSPC; 249 250 if (only_one_period) 251 /* Must fit within same period as start; end at begin of next */ 252 first_end = (start / bits_per_period + 1) * bits_per_period; 253 else 254 /* Can fit anywhere in the first interval */ 255 first_end = interval_bits; 256 257 /* 258 * We'll try to pick the first repetition, then see if that time 259 * is free for each of the subsequent repetitions. If it's not 260 * we'll adjust the start time for the next search of the first 261 * repetition. 262 */ 263 while (start + num_bits <= first_end) { 264 int end; 265 266 /* Need to stay within this period */ 267 end = (start / bits_per_period + 1) * bits_per_period; 268 269 /* Look for num_bits us in this microframe starting at start */ 270 start = bitmap_find_next_zero_area(map, end, start, num_bits, 271 0); 272 273 /* 274 * We should get start >= end if we fail. We might be 275 * able to check the next microframe depending on the 276 * interval, so continue on (start already updated). 277 */ 278 if (start >= end) { 279 start = end; 280 continue; 281 } 282 283 /* At this point we have a valid point for first one */ 284 for (i = 1; i < to_reserve; i++) { 285 int ith_start = start + interval_bits * i; 286 int ith_end = end + interval_bits * i; 287 int ret; 288 289 /* Use this as a dumb "check if bits are 0" */ 290 ret = bitmap_find_next_zero_area( 291 map, ith_start + num_bits, ith_start, num_bits, 292 0); 293 294 /* We got the right place, continue checking */ 295 if (ret == ith_start) 296 continue; 297 298 /* Move start up for next time and exit for loop */ 299 ith_start = bitmap_find_next_zero_area( 300 map, ith_end, ith_start, num_bits, 0); 301 if (ith_start >= ith_end) 302 /* Need a while new period next time */ 303 start = end; 304 else 305 start = ith_start - interval_bits * i; 306 break; 307 } 308 309 /* If didn't exit the for loop with a break, we have success */ 310 if (i == to_reserve) 311 break; 312 } 313 314 if (start + num_bits > first_end) 315 return -ENOSPC; 316 317 for (i = 0; i < to_reserve; i++) { 318 int ith_start = start + interval_bits * i; 319 320 bitmap_set(map, ith_start, num_bits); 321 } 322 323 return start; 324 } 325 326 /** 327 * pmap_unschedule() - Undo work done by pmap_schedule() 328 * 329 * @map: See pmap_schedule(). 330 * @bits_per_period: See pmap_schedule(). 331 * @periods_in_map: See pmap_schedule(). 332 * @num_bits: The number of bits that was passed to schedule. 333 * @interval: The interval that was passed to schedule. 334 * @start: The return value from pmap_schedule(). 335 */ 336 static void pmap_unschedule(unsigned long *map, int bits_per_period, 337 int periods_in_map, int num_bits, 338 int interval, int start) 339 { 340 int interval_bits; 341 int to_release; 342 int i; 343 344 /* Adjust interval as per description in pmap_schedule() */ 345 interval = gcd(interval, periods_in_map); 346 347 interval_bits = bits_per_period * interval; 348 to_release = periods_in_map / interval; 349 350 for (i = 0; i < to_release; i++) { 351 int ith_start = start + interval_bits * i; 352 353 bitmap_clear(map, ith_start, num_bits); 354 } 355 } 356 357 /** 358 * dwc2_get_ls_map() - Get the map used for the given qh 359 * 360 * @hsotg: The HCD state structure for the DWC OTG controller. 361 * @qh: QH for the periodic transfer. 362 * 363 * We'll always get the periodic map out of our TT. Note that even if we're 364 * running the host straight in low speed / full speed mode it appears as if 365 * a TT is allocated for us, so we'll use it. If that ever changes we can 366 * add logic here to get a map out of "hsotg" if !qh->do_split. 367 * 368 * Returns: the map or NULL if a map couldn't be found. 369 */ 370 static unsigned long *dwc2_get_ls_map(struct dwc2_hsotg *hsotg, 371 struct dwc2_qh *qh) 372 { 373 unsigned long *map; 374 375 /* Don't expect to be missing a TT and be doing low speed scheduling */ 376 if (WARN_ON(!qh->dwc_tt)) 377 return NULL; 378 379 /* Get the map and adjust if this is a multi_tt hub */ 380 map = qh->dwc_tt->periodic_bitmaps; 381 if (qh->dwc_tt->usb_tt->multi) 382 map += DWC2_ELEMENTS_PER_LS_BITMAP * qh->ttport; 383 384 return map; 385 } 386 387 #ifdef DWC2_PRINT_SCHEDULE 388 /* 389 * cat_printf() - A printf() + strcat() helper 390 * 391 * This is useful for concatenating a bunch of strings where each string is 392 * constructed using printf. 393 * 394 * @buf: The destination buffer; will be updated to point after the printed 395 * data. 396 * @size: The number of bytes in the buffer (includes space for '\0'). 397 * @fmt: The format for printf. 398 * @...: The args for printf. 399 */ 400 static __printf(3, 4) 401 void cat_printf(char **buf, size_t *size, const char *fmt, ...) 402 { 403 va_list args; 404 int i; 405 406 if (*size == 0) 407 return; 408 409 va_start(args, fmt); 410 i = vsnprintf(*buf, *size, fmt, args); 411 va_end(args); 412 413 if (i >= *size) { 414 (*buf)[*size - 1] = '\0'; 415 *buf += *size; 416 *size = 0; 417 } else { 418 *buf += i; 419 *size -= i; 420 } 421 } 422 423 /* 424 * pmap_print() - Print the given periodic map 425 * 426 * Will attempt to print out the periodic schedule. 427 * 428 * @map: See pmap_schedule(). 429 * @bits_per_period: See pmap_schedule(). 430 * @periods_in_map: See pmap_schedule(). 431 * @period_name: The name of 1 period, like "uFrame" 432 * @units: The name of the units, like "us". 433 * @print_fn: The function to call for printing. 434 * @print_data: Opaque data to pass to the print function. 435 */ 436 static void pmap_print(unsigned long *map, int bits_per_period, 437 int periods_in_map, const char *period_name, 438 const char *units, 439 void (*print_fn)(const char *str, void *data), 440 void *print_data) 441 { 442 int period; 443 444 for (period = 0; period < periods_in_map; period++) { 445 char tmp[64]; 446 char *buf = tmp; 447 size_t buf_size = sizeof(tmp); 448 int period_start = period * bits_per_period; 449 int period_end = period_start + bits_per_period; 450 int start = 0; 451 int count = 0; 452 bool printed = false; 453 int i; 454 455 for (i = period_start; i < period_end + 1; i++) { 456 /* Handle case when ith bit is set */ 457 if (i < period_end && 458 bitmap_find_next_zero_area(map, i + 1, 459 i, 1, 0) != i) { 460 if (count == 0) 461 start = i - period_start; 462 count++; 463 continue; 464 } 465 466 /* ith bit isn't set; don't care if count == 0 */ 467 if (count == 0) 468 continue; 469 470 if (!printed) 471 cat_printf(&buf, &buf_size, "%s %d: ", 472 period_name, period); 473 else 474 cat_printf(&buf, &buf_size, ", "); 475 printed = true; 476 477 cat_printf(&buf, &buf_size, "%d %s -%3d %s", start, 478 units, start + count - 1, units); 479 count = 0; 480 } 481 482 if (printed) 483 print_fn(tmp, print_data); 484 } 485 } 486 487 struct dwc2_qh_print_data { 488 struct dwc2_hsotg *hsotg; 489 struct dwc2_qh *qh; 490 }; 491 492 /** 493 * dwc2_qh_print() - Helper function for dwc2_qh_schedule_print() 494 * 495 * @str: The string to print 496 * @data: A pointer to a struct dwc2_qh_print_data 497 */ 498 static void dwc2_qh_print(const char *str, void *data) 499 { 500 struct dwc2_qh_print_data *print_data = data; 501 502 dwc2_sch_dbg(print_data->hsotg, "QH=%p ...%s\n", print_data->qh, str); 503 } 504 505 /** 506 * dwc2_qh_schedule_print() - Print the periodic schedule 507 * 508 * @hsotg: The HCD state structure for the DWC OTG controller. 509 * @qh: QH to print. 510 */ 511 static void dwc2_qh_schedule_print(struct dwc2_hsotg *hsotg, 512 struct dwc2_qh *qh) 513 { 514 struct dwc2_qh_print_data print_data = { hsotg, qh }; 515 int i; 516 517 /* 518 * The printing functions are quite slow and inefficient. 519 * If we don't have tracing turned on, don't run unless the special 520 * define is turned on. 521 */ 522 523 if (qh->schedule_low_speed) { 524 unsigned long *map = dwc2_get_ls_map(hsotg, qh); 525 526 dwc2_sch_dbg(hsotg, "QH=%p LS/FS trans: %d=>%d us @ %d us", 527 qh, qh->device_us, 528 DWC2_ROUND_US_TO_SLICE(qh->device_us), 529 DWC2_US_PER_SLICE * qh->ls_start_schedule_slice); 530 531 if (map) { 532 dwc2_sch_dbg(hsotg, 533 "QH=%p Whole low/full speed map %p now:\n", 534 qh, map); 535 pmap_print(map, DWC2_LS_PERIODIC_SLICES_PER_FRAME, 536 DWC2_LS_SCHEDULE_FRAMES, "Frame ", "slices", 537 dwc2_qh_print, &print_data); 538 } 539 } 540 541 for (i = 0; i < qh->num_hs_transfers; i++) { 542 struct dwc2_hs_transfer_time *trans_time = qh->hs_transfers + i; 543 int uframe = trans_time->start_schedule_us / 544 DWC2_HS_PERIODIC_US_PER_UFRAME; 545 int rel_us = trans_time->start_schedule_us % 546 DWC2_HS_PERIODIC_US_PER_UFRAME; 547 548 dwc2_sch_dbg(hsotg, 549 "QH=%p HS trans #%d: %d us @ uFrame %d + %d us\n", 550 qh, i, trans_time->duration_us, uframe, rel_us); 551 } 552 if (qh->num_hs_transfers) { 553 dwc2_sch_dbg(hsotg, "QH=%p Whole high speed map now:\n", qh); 554 pmap_print(hsotg->hs_periodic_bitmap, 555 DWC2_HS_PERIODIC_US_PER_UFRAME, 556 DWC2_HS_SCHEDULE_UFRAMES, "uFrame", "us", 557 dwc2_qh_print, &print_data); 558 } 559 } 560 #else 561 static inline void dwc2_qh_schedule_print(struct dwc2_hsotg *hsotg, 562 struct dwc2_qh *qh) {}; 563 #endif 564 565 /** 566 * dwc2_ls_pmap_schedule() - Schedule a low speed QH 567 * 568 * @hsotg: The HCD state structure for the DWC OTG controller. 569 * @qh: QH for the periodic transfer. 570 * @search_slice: We'll start trying to schedule at the passed slice. 571 * Remember that slices are the units of the low speed 572 * schedule (think 25us or so). 573 * 574 * Wraps pmap_schedule() with the right parameters for low speed scheduling. 575 * 576 * Normally we schedule low speed devices on the map associated with the TT. 577 * 578 * Returns: 0 for success or an error code. 579 */ 580 static int dwc2_ls_pmap_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 581 int search_slice) 582 { 583 int slices = DIV_ROUND_UP(qh->device_us, DWC2_US_PER_SLICE); 584 unsigned long *map = dwc2_get_ls_map(hsotg, qh); 585 int slice; 586 587 if (!map) 588 return -EINVAL; 589 590 /* 591 * Schedule on the proper low speed map with our low speed scheduling 592 * parameters. Note that we use the "device_interval" here since 593 * we want the low speed interval and the only way we'd be in this 594 * function is if the device is low speed. 595 * 596 * If we happen to be doing low speed and high speed scheduling for the 597 * same transaction (AKA we have a split) we always do low speed first. 598 * That means we can always pass "false" for only_one_period (that 599 * parameters is only useful when we're trying to get one schedule to 600 * match what we already planned in the other schedule). 601 */ 602 slice = pmap_schedule(map, DWC2_LS_PERIODIC_SLICES_PER_FRAME, 603 DWC2_LS_SCHEDULE_FRAMES, slices, 604 qh->device_interval, search_slice, false); 605 606 if (slice < 0) 607 return slice; 608 609 qh->ls_start_schedule_slice = slice; 610 return 0; 611 } 612 613 /** 614 * dwc2_ls_pmap_unschedule() - Undo work done by dwc2_ls_pmap_schedule() 615 * 616 * @hsotg: The HCD state structure for the DWC OTG controller. 617 * @qh: QH for the periodic transfer. 618 */ 619 static void dwc2_ls_pmap_unschedule(struct dwc2_hsotg *hsotg, 620 struct dwc2_qh *qh) 621 { 622 int slices = DIV_ROUND_UP(qh->device_us, DWC2_US_PER_SLICE); 623 unsigned long *map = dwc2_get_ls_map(hsotg, qh); 624 625 /* Schedule should have failed, so no worries about no error code */ 626 if (!map) 627 return; 628 629 pmap_unschedule(map, DWC2_LS_PERIODIC_SLICES_PER_FRAME, 630 DWC2_LS_SCHEDULE_FRAMES, slices, qh->device_interval, 631 qh->ls_start_schedule_slice); 632 } 633 634 /** 635 * dwc2_hs_pmap_schedule - Schedule in the main high speed schedule 636 * 637 * This will schedule something on the main dwc2 schedule. 638 * 639 * We'll start looking in qh->hs_transfers[index].start_schedule_us. We'll 640 * update this with the result upon success. We also use the duration from 641 * the same structure. 642 * 643 * @hsotg: The HCD state structure for the DWC OTG controller. 644 * @qh: QH for the periodic transfer. 645 * @only_one_period: If true we will limit ourselves to just looking at 646 * one period (aka one 100us chunk). This is used if we have 647 * already scheduled something on the low speed schedule and 648 * need to find something that matches on the high speed one. 649 * @index: The index into qh->hs_transfers that we're working with. 650 * 651 * Returns: 0 for success or an error code. Upon success the 652 * dwc2_hs_transfer_time specified by "index" will be updated. 653 */ 654 static int dwc2_hs_pmap_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 655 bool only_one_period, int index) 656 { 657 struct dwc2_hs_transfer_time *trans_time = qh->hs_transfers + index; 658 int us; 659 660 us = pmap_schedule(hsotg->hs_periodic_bitmap, 661 DWC2_HS_PERIODIC_US_PER_UFRAME, 662 DWC2_HS_SCHEDULE_UFRAMES, trans_time->duration_us, 663 qh->host_interval, trans_time->start_schedule_us, 664 only_one_period); 665 666 if (us < 0) 667 return us; 668 669 trans_time->start_schedule_us = us; 670 return 0; 671 } 672 673 /** 674 * dwc2_ls_pmap_unschedule() - Undo work done by dwc2_hs_pmap_schedule() 675 * 676 * @hsotg: The HCD state structure for the DWC OTG controller. 677 * @qh: QH for the periodic transfer. 678 */ 679 static void dwc2_hs_pmap_unschedule(struct dwc2_hsotg *hsotg, 680 struct dwc2_qh *qh, int index) 681 { 682 struct dwc2_hs_transfer_time *trans_time = qh->hs_transfers + index; 683 684 pmap_unschedule(hsotg->hs_periodic_bitmap, 685 DWC2_HS_PERIODIC_US_PER_UFRAME, 686 DWC2_HS_SCHEDULE_UFRAMES, trans_time->duration_us, 687 qh->host_interval, trans_time->start_schedule_us); 688 } 689 690 /** 691 * dwc2_uframe_schedule_split - Schedule a QH for a periodic split xfer. 692 * 693 * This is the most complicated thing in USB. We have to find matching time 694 * in both the global high speed schedule for the port and the low speed 695 * schedule for the TT associated with the given device. 696 * 697 * Being here means that the host must be running in high speed mode and the 698 * device is in low or full speed mode (and behind a hub). 699 * 700 * @hsotg: The HCD state structure for the DWC OTG controller. 701 * @qh: QH for the periodic transfer. 702 */ 703 static int dwc2_uframe_schedule_split(struct dwc2_hsotg *hsotg, 704 struct dwc2_qh *qh) 705 { 706 int bytecount = dwc2_hb_mult(qh->maxp) * dwc2_max_packet(qh->maxp); 707 int ls_search_slice; 708 int err = 0; 709 int host_interval_in_sched; 710 711 /* 712 * The interval (how often to repeat) in the actual host schedule. 713 * See pmap_schedule() for gcd() explanation. 714 */ 715 host_interval_in_sched = gcd(qh->host_interval, 716 DWC2_HS_SCHEDULE_UFRAMES); 717 718 /* 719 * We always try to find space in the low speed schedule first, then 720 * try to find high speed time that matches. If we don't, we'll bump 721 * up the place we start searching in the low speed schedule and try 722 * again. To start we'll look right at the beginning of the low speed 723 * schedule. 724 * 725 * Note that this will tend to front-load the high speed schedule. 726 * We may eventually want to try to avoid this by either considering 727 * both schedules together or doing some sort of round robin. 728 */ 729 ls_search_slice = 0; 730 731 while (ls_search_slice < DWC2_LS_SCHEDULE_SLICES) { 732 int start_s_uframe; 733 int ssplit_s_uframe; 734 int second_s_uframe; 735 int rel_uframe; 736 int first_count; 737 int middle_count; 738 int end_count; 739 int first_data_bytes; 740 int other_data_bytes; 741 int i; 742 743 if (qh->schedule_low_speed) { 744 err = dwc2_ls_pmap_schedule(hsotg, qh, ls_search_slice); 745 746 /* 747 * If we got an error here there's no other magic we 748 * can do, so bail. All the looping above is only 749 * helpful to redo things if we got a low speed slot 750 * and then couldn't find a matching high speed slot. 751 */ 752 if (err) 753 return err; 754 } else { 755 /* Must be missing the tt structure? Why? */ 756 WARN_ON_ONCE(1); 757 } 758 759 /* 760 * This will give us a number 0 - 7 if 761 * DWC2_LS_SCHEDULE_FRAMES == 1, or 0 - 15 if == 2, or ... 762 */ 763 start_s_uframe = qh->ls_start_schedule_slice / 764 DWC2_SLICES_PER_UFRAME; 765 766 /* Get a number that's always 0 - 7 */ 767 rel_uframe = (start_s_uframe % 8); 768 769 /* 770 * If we were going to start in uframe 7 then we would need to 771 * issue a start split in uframe 6, which spec says is not OK. 772 * Move on to the next full frame (assuming there is one). 773 * 774 * See 11.18.4 Host Split Transaction Scheduling Requirements 775 * bullet 1. 776 */ 777 if (rel_uframe == 7) { 778 if (qh->schedule_low_speed) 779 dwc2_ls_pmap_unschedule(hsotg, qh); 780 ls_search_slice = 781 (qh->ls_start_schedule_slice / 782 DWC2_LS_PERIODIC_SLICES_PER_FRAME + 1) * 783 DWC2_LS_PERIODIC_SLICES_PER_FRAME; 784 continue; 785 } 786 787 /* 788 * For ISOC in: 789 * - start split (frame -1) 790 * - complete split w/ data (frame +1) 791 * - complete split w/ data (frame +2) 792 * - ... 793 * - complete split w/ data (frame +num_data_packets) 794 * - complete split w/ data (frame +num_data_packets+1) 795 * - complete split w/ data (frame +num_data_packets+2, max 8) 796 * ...though if frame was "0" then max is 7... 797 * 798 * For ISOC out we might need to do: 799 * - start split w/ data (frame -1) 800 * - start split w/ data (frame +0) 801 * - ... 802 * - start split w/ data (frame +num_data_packets-2) 803 * 804 * For INTERRUPT in we might need to do: 805 * - start split (frame -1) 806 * - complete split w/ data (frame +1) 807 * - complete split w/ data (frame +2) 808 * - complete split w/ data (frame +3, max 8) 809 * 810 * For INTERRUPT out we might need to do: 811 * - start split w/ data (frame -1) 812 * - complete split (frame +1) 813 * - complete split (frame +2) 814 * - complete split (frame +3, max 8) 815 * 816 * Start adjusting! 817 */ 818 ssplit_s_uframe = (start_s_uframe + 819 host_interval_in_sched - 1) % 820 host_interval_in_sched; 821 if (qh->ep_type == USB_ENDPOINT_XFER_ISOC && !qh->ep_is_in) 822 second_s_uframe = start_s_uframe; 823 else 824 second_s_uframe = start_s_uframe + 1; 825 826 /* First data transfer might not be all 188 bytes. */ 827 first_data_bytes = 188 - 828 DIV_ROUND_UP(188 * (qh->ls_start_schedule_slice % 829 DWC2_SLICES_PER_UFRAME), 830 DWC2_SLICES_PER_UFRAME); 831 if (first_data_bytes > bytecount) 832 first_data_bytes = bytecount; 833 other_data_bytes = bytecount - first_data_bytes; 834 835 /* 836 * For now, skip OUT xfers where first xfer is partial 837 * 838 * Main dwc2 code assumes: 839 * - INT transfers never get split in two. 840 * - ISOC transfers can always transfer 188 bytes the first 841 * time. 842 * 843 * Until that code is fixed, try again if the first transfer 844 * couldn't transfer everything. 845 * 846 * This code can be removed if/when the rest of dwc2 handles 847 * the above cases. Until it's fixed we just won't be able 848 * to schedule quite as tightly. 849 */ 850 if (!qh->ep_is_in && 851 (first_data_bytes != min_t(int, 188, bytecount))) { 852 dwc2_sch_dbg(hsotg, 853 "QH=%p avoiding broken 1st xfer (%d, %d)\n", 854 qh, first_data_bytes, bytecount); 855 if (qh->schedule_low_speed) 856 dwc2_ls_pmap_unschedule(hsotg, qh); 857 ls_search_slice = (start_s_uframe + 1) * 858 DWC2_SLICES_PER_UFRAME; 859 continue; 860 } 861 862 /* Start by assuming transfers for the bytes */ 863 qh->num_hs_transfers = 1 + DIV_ROUND_UP(other_data_bytes, 188); 864 865 /* 866 * Everything except ISOC OUT has extra transfers. Rules are 867 * complicated. See 11.18.4 Host Split Transaction Scheduling 868 * Requirements bullet 3. 869 */ 870 if (qh->ep_type == USB_ENDPOINT_XFER_INT) { 871 if (rel_uframe == 6) 872 qh->num_hs_transfers += 2; 873 else 874 qh->num_hs_transfers += 3; 875 876 if (qh->ep_is_in) { 877 /* 878 * First is start split, middle/end is data. 879 * Allocate full data bytes for all data. 880 */ 881 first_count = 4; 882 middle_count = bytecount; 883 end_count = bytecount; 884 } else { 885 /* 886 * First is data, middle/end is complete. 887 * First transfer and second can have data. 888 * Rest should just have complete split. 889 */ 890 first_count = first_data_bytes; 891 middle_count = max_t(int, 4, other_data_bytes); 892 end_count = 4; 893 } 894 } else { 895 if (qh->ep_is_in) { 896 int last; 897 898 /* Account for the start split */ 899 qh->num_hs_transfers++; 900 901 /* Calculate "L" value from spec */ 902 last = rel_uframe + qh->num_hs_transfers + 1; 903 904 /* Start with basic case */ 905 if (last <= 6) 906 qh->num_hs_transfers += 2; 907 else 908 qh->num_hs_transfers += 1; 909 910 /* Adjust downwards */ 911 if (last >= 6 && rel_uframe == 0) 912 qh->num_hs_transfers--; 913 914 /* 1st = start; rest can contain data */ 915 first_count = 4; 916 middle_count = min_t(int, 188, bytecount); 917 end_count = middle_count; 918 } else { 919 /* All contain data, last might be smaller */ 920 first_count = first_data_bytes; 921 middle_count = min_t(int, 188, 922 other_data_bytes); 923 end_count = other_data_bytes % 188; 924 } 925 } 926 927 /* Assign durations per uFrame */ 928 qh->hs_transfers[0].duration_us = HS_USECS_ISO(first_count); 929 for (i = 1; i < qh->num_hs_transfers - 1; i++) 930 qh->hs_transfers[i].duration_us = 931 HS_USECS_ISO(middle_count); 932 if (qh->num_hs_transfers > 1) 933 qh->hs_transfers[qh->num_hs_transfers - 1].duration_us = 934 HS_USECS_ISO(end_count); 935 936 /* 937 * Assign start us. The call below to dwc2_hs_pmap_schedule() 938 * will start with these numbers but may adjust within the same 939 * microframe. 940 */ 941 qh->hs_transfers[0].start_schedule_us = 942 ssplit_s_uframe * DWC2_HS_PERIODIC_US_PER_UFRAME; 943 for (i = 1; i < qh->num_hs_transfers; i++) 944 qh->hs_transfers[i].start_schedule_us = 945 ((second_s_uframe + i - 1) % 946 DWC2_HS_SCHEDULE_UFRAMES) * 947 DWC2_HS_PERIODIC_US_PER_UFRAME; 948 949 /* Try to schedule with filled in hs_transfers above */ 950 for (i = 0; i < qh->num_hs_transfers; i++) { 951 err = dwc2_hs_pmap_schedule(hsotg, qh, true, i); 952 if (err) 953 break; 954 } 955 956 /* If we scheduled all w/out breaking out then we're all good */ 957 if (i == qh->num_hs_transfers) 958 break; 959 960 for (; i >= 0; i--) 961 dwc2_hs_pmap_unschedule(hsotg, qh, i); 962 963 if (qh->schedule_low_speed) 964 dwc2_ls_pmap_unschedule(hsotg, qh); 965 966 /* Try again starting in the next microframe */ 967 ls_search_slice = (start_s_uframe + 1) * DWC2_SLICES_PER_UFRAME; 968 } 969 970 if (ls_search_slice >= DWC2_LS_SCHEDULE_SLICES) 971 return -ENOSPC; 972 973 return 0; 974 } 975 976 /** 977 * dwc2_uframe_schedule_hs - Schedule a QH for a periodic high speed xfer. 978 * 979 * Basically this just wraps dwc2_hs_pmap_schedule() to provide a clean 980 * interface. 981 * 982 * @hsotg: The HCD state structure for the DWC OTG controller. 983 * @qh: QH for the periodic transfer. 984 */ 985 static int dwc2_uframe_schedule_hs(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 986 { 987 /* In non-split host and device time are the same */ 988 WARN_ON(qh->host_us != qh->device_us); 989 WARN_ON(qh->host_interval != qh->device_interval); 990 WARN_ON(qh->num_hs_transfers != 1); 991 992 /* We'll have one transfer; init start to 0 before calling scheduler */ 993 qh->hs_transfers[0].start_schedule_us = 0; 994 qh->hs_transfers[0].duration_us = qh->host_us; 995 996 return dwc2_hs_pmap_schedule(hsotg, qh, false, 0); 997 } 998 999 /** 1000 * dwc2_uframe_schedule_ls - Schedule a QH for a periodic low/full speed xfer. 1001 * 1002 * Basically this just wraps dwc2_ls_pmap_schedule() to provide a clean 1003 * interface. 1004 * 1005 * @hsotg: The HCD state structure for the DWC OTG controller. 1006 * @qh: QH for the periodic transfer. 1007 */ 1008 static int dwc2_uframe_schedule_ls(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 1009 { 1010 /* In non-split host and device time are the same */ 1011 WARN_ON(qh->host_us != qh->device_us); 1012 WARN_ON(qh->host_interval != qh->device_interval); 1013 WARN_ON(!qh->schedule_low_speed); 1014 1015 /* Run on the main low speed schedule (no split = no hub = no TT) */ 1016 return dwc2_ls_pmap_schedule(hsotg, qh, 0); 1017 } 1018 1019 /** 1020 * dwc2_uframe_schedule - Schedule a QH for a periodic xfer. 1021 * 1022 * Calls one of the 3 sub-function depending on what type of transfer this QH 1023 * is for. Also adds some printing. 1024 * 1025 * @hsotg: The HCD state structure for the DWC OTG controller. 1026 * @qh: QH for the periodic transfer. 1027 */ 1028 static int dwc2_uframe_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 1029 { 1030 int ret; 1031 1032 if (qh->dev_speed == USB_SPEED_HIGH) 1033 ret = dwc2_uframe_schedule_hs(hsotg, qh); 1034 else if (!qh->do_split) 1035 ret = dwc2_uframe_schedule_ls(hsotg, qh); 1036 else 1037 ret = dwc2_uframe_schedule_split(hsotg, qh); 1038 1039 if (ret) 1040 dwc2_sch_dbg(hsotg, "QH=%p Failed to schedule %d\n", qh, ret); 1041 else 1042 dwc2_qh_schedule_print(hsotg, qh); 1043 1044 return ret; 1045 } 1046 1047 /** 1048 * dwc2_uframe_unschedule - Undoes dwc2_uframe_schedule(). 1049 * 1050 * @hsotg: The HCD state structure for the DWC OTG controller. 1051 * @qh: QH for the periodic transfer. 1052 */ 1053 static void dwc2_uframe_unschedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 1054 { 1055 int i; 1056 1057 for (i = 0; i < qh->num_hs_transfers; i++) 1058 dwc2_hs_pmap_unschedule(hsotg, qh, i); 1059 1060 if (qh->schedule_low_speed) 1061 dwc2_ls_pmap_unschedule(hsotg, qh); 1062 1063 dwc2_sch_dbg(hsotg, "QH=%p Unscheduled\n", qh); 1064 } 1065 1066 /** 1067 * dwc2_pick_first_frame() - Choose 1st frame for qh that's already scheduled 1068 * 1069 * Takes a qh that has already been scheduled (which means we know we have the 1070 * bandwdith reserved for us) and set the next_active_frame and the 1071 * start_active_frame. 1072 * 1073 * This is expected to be called on qh's that weren't previously actively 1074 * running. It just picks the next frame that we can fit into without any 1075 * thought about the past. 1076 * 1077 * @hsotg: The HCD state structure for the DWC OTG controller 1078 * @qh: QH for a periodic endpoint 1079 * 1080 */ 1081 static void dwc2_pick_first_frame(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 1082 { 1083 u16 frame_number; 1084 u16 earliest_frame; 1085 u16 next_active_frame; 1086 u16 relative_frame; 1087 u16 interval; 1088 1089 /* 1090 * Use the real frame number rather than the cached value as of the 1091 * last SOF to give us a little extra slop. 1092 */ 1093 frame_number = dwc2_hcd_get_frame_number(hsotg); 1094 1095 /* 1096 * We wouldn't want to start any earlier than the next frame just in 1097 * case the frame number ticks as we're doing this calculation. 1098 * 1099 * NOTE: if we could quantify how long till we actually get scheduled 1100 * we might be able to avoid the "+ 1" by looking at the upper part of 1101 * HFNUM (the FRREM field). For now we'll just use the + 1 though. 1102 */ 1103 earliest_frame = dwc2_frame_num_inc(frame_number, 1); 1104 next_active_frame = earliest_frame; 1105 1106 /* Get the "no microframe schduler" out of the way... */ 1107 if (!hsotg->params.uframe_sched) { 1108 if (qh->do_split) 1109 /* Splits are active at microframe 0 minus 1 */ 1110 next_active_frame |= 0x7; 1111 goto exit; 1112 } 1113 1114 if (qh->dev_speed == USB_SPEED_HIGH || qh->do_split) { 1115 /* 1116 * We're either at high speed or we're doing a split (which 1117 * means we're talking high speed to a hub). In any case 1118 * the first frame should be based on when the first scheduled 1119 * event is. 1120 */ 1121 WARN_ON(qh->num_hs_transfers < 1); 1122 1123 relative_frame = qh->hs_transfers[0].start_schedule_us / 1124 DWC2_HS_PERIODIC_US_PER_UFRAME; 1125 1126 /* Adjust interval as per high speed schedule */ 1127 interval = gcd(qh->host_interval, DWC2_HS_SCHEDULE_UFRAMES); 1128 1129 } else { 1130 /* 1131 * Low or full speed directly on dwc2. Just about the same 1132 * as high speed but on a different schedule and with slightly 1133 * different adjustments. Note that this works because when 1134 * the host and device are both low speed then frames in the 1135 * controller tick at low speed. 1136 */ 1137 relative_frame = qh->ls_start_schedule_slice / 1138 DWC2_LS_PERIODIC_SLICES_PER_FRAME; 1139 interval = gcd(qh->host_interval, DWC2_LS_SCHEDULE_FRAMES); 1140 } 1141 1142 /* Scheduler messed up if frame is past interval */ 1143 WARN_ON(relative_frame >= interval); 1144 1145 /* 1146 * We know interval must divide (HFNUM_MAX_FRNUM + 1) now that we've 1147 * done the gcd(), so it's safe to move to the beginning of the current 1148 * interval like this. 1149 * 1150 * After this we might be before earliest_frame, but don't worry, 1151 * we'll fix it... 1152 */ 1153 next_active_frame = (next_active_frame / interval) * interval; 1154 1155 /* 1156 * Actually choose to start at the frame number we've been 1157 * scheduled for. 1158 */ 1159 next_active_frame = dwc2_frame_num_inc(next_active_frame, 1160 relative_frame); 1161 1162 /* 1163 * We actually need 1 frame before since the next_active_frame is 1164 * the frame number we'll be put on the ready list and we won't be on 1165 * the bus until 1 frame later. 1166 */ 1167 next_active_frame = dwc2_frame_num_dec(next_active_frame, 1); 1168 1169 /* 1170 * By now we might actually be before the earliest_frame. Let's move 1171 * up intervals until we're not. 1172 */ 1173 while (dwc2_frame_num_gt(earliest_frame, next_active_frame)) 1174 next_active_frame = dwc2_frame_num_inc(next_active_frame, 1175 interval); 1176 1177 exit: 1178 qh->next_active_frame = next_active_frame; 1179 qh->start_active_frame = next_active_frame; 1180 1181 dwc2_sch_vdbg(hsotg, "QH=%p First fn=%04x nxt=%04x\n", 1182 qh, frame_number, qh->next_active_frame); 1183 } 1184 1185 /** 1186 * dwc2_do_reserve() - Make a periodic reservation 1187 * 1188 * Try to allocate space in the periodic schedule. Depending on parameters 1189 * this might use the microframe scheduler or the dumb scheduler. 1190 * 1191 * @hsotg: The HCD state structure for the DWC OTG controller 1192 * @qh: QH for the periodic transfer. 1193 * 1194 * Returns: 0 upon success; error upon failure. 1195 */ 1196 static int dwc2_do_reserve(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 1197 { 1198 int status; 1199 1200 if (hsotg->params.uframe_sched) { 1201 status = dwc2_uframe_schedule(hsotg, qh); 1202 } else { 1203 status = dwc2_periodic_channel_available(hsotg); 1204 if (status) { 1205 dev_info(hsotg->dev, 1206 "%s: No host channel available for periodic transfer\n", 1207 __func__); 1208 return status; 1209 } 1210 1211 status = dwc2_check_periodic_bandwidth(hsotg, qh); 1212 } 1213 1214 if (status) { 1215 dev_dbg(hsotg->dev, 1216 "%s: Insufficient periodic bandwidth for periodic transfer\n", 1217 __func__); 1218 return status; 1219 } 1220 1221 if (!hsotg->params.uframe_sched) 1222 /* Reserve periodic channel */ 1223 hsotg->periodic_channels++; 1224 1225 /* Update claimed usecs per (micro)frame */ 1226 hsotg->periodic_usecs += qh->host_us; 1227 1228 dwc2_pick_first_frame(hsotg, qh); 1229 1230 return 0; 1231 } 1232 1233 /** 1234 * dwc2_do_unreserve() - Actually release the periodic reservation 1235 * 1236 * This function actually releases the periodic bandwidth that was reserved 1237 * by the given qh. 1238 * 1239 * @hsotg: The HCD state structure for the DWC OTG controller 1240 * @qh: QH for the periodic transfer. 1241 */ 1242 static void dwc2_do_unreserve(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 1243 { 1244 assert_spin_locked(&hsotg->lock); 1245 1246 WARN_ON(!qh->unreserve_pending); 1247 1248 /* No more unreserve pending--we're doing it */ 1249 qh->unreserve_pending = false; 1250 1251 if (WARN_ON(!list_empty(&qh->qh_list_entry))) 1252 list_del_init(&qh->qh_list_entry); 1253 1254 /* Update claimed usecs per (micro)frame */ 1255 hsotg->periodic_usecs -= qh->host_us; 1256 1257 if (hsotg->params.uframe_sched) { 1258 dwc2_uframe_unschedule(hsotg, qh); 1259 } else { 1260 /* Release periodic channel reservation */ 1261 hsotg->periodic_channels--; 1262 } 1263 } 1264 1265 /** 1266 * dwc2_unreserve_timer_fn() - Timer function to release periodic reservation 1267 * 1268 * According to the kernel doc for usb_submit_urb() (specifically the part about 1269 * "Reserved Bandwidth Transfers"), we need to keep a reservation active as 1270 * long as a device driver keeps submitting. Since we're using HCD_BH to give 1271 * back the URB we need to give the driver a little bit of time before we 1272 * release the reservation. This worker is called after the appropriate 1273 * delay. 1274 * 1275 * @work: Pointer to a qh unreserve_work. 1276 */ 1277 static void dwc2_unreserve_timer_fn(unsigned long data) 1278 { 1279 struct dwc2_qh *qh = (struct dwc2_qh *)data; 1280 struct dwc2_hsotg *hsotg = qh->hsotg; 1281 unsigned long flags; 1282 1283 /* 1284 * Wait for the lock, or for us to be scheduled again. We 1285 * could be scheduled again if: 1286 * - We started executing but didn't get the lock yet. 1287 * - A new reservation came in, but cancel didn't take effect 1288 * because we already started executing. 1289 * - The timer has been kicked again. 1290 * In that case cancel and wait for the next call. 1291 */ 1292 while (!spin_trylock_irqsave(&hsotg->lock, flags)) { 1293 if (timer_pending(&qh->unreserve_timer)) 1294 return; 1295 } 1296 1297 /* 1298 * Might be no more unreserve pending if: 1299 * - We started executing but didn't get the lock yet. 1300 * - A new reservation came in, but cancel didn't take effect 1301 * because we already started executing. 1302 * 1303 * We can't put this in the loop above because unreserve_pending needs 1304 * to be accessed under lock, so we can only check it once we got the 1305 * lock. 1306 */ 1307 if (qh->unreserve_pending) 1308 dwc2_do_unreserve(hsotg, qh); 1309 1310 spin_unlock_irqrestore(&hsotg->lock, flags); 1311 } 1312 1313 /** 1314 * dwc2_check_max_xfer_size() - Checks that the max transfer size allowed in a 1315 * host channel is large enough to handle the maximum data transfer in a single 1316 * (micro)frame for a periodic transfer 1317 * 1318 * @hsotg: The HCD state structure for the DWC OTG controller 1319 * @qh: QH for a periodic endpoint 1320 * 1321 * Return: 0 if successful, negative error code otherwise 1322 */ 1323 static int dwc2_check_max_xfer_size(struct dwc2_hsotg *hsotg, 1324 struct dwc2_qh *qh) 1325 { 1326 u32 max_xfer_size; 1327 u32 max_channel_xfer_size; 1328 int status = 0; 1329 1330 max_xfer_size = dwc2_max_packet(qh->maxp) * dwc2_hb_mult(qh->maxp); 1331 max_channel_xfer_size = hsotg->params.max_transfer_size; 1332 1333 if (max_xfer_size > max_channel_xfer_size) { 1334 dev_err(hsotg->dev, 1335 "%s: Periodic xfer length %d > max xfer length for channel %d\n", 1336 __func__, max_xfer_size, max_channel_xfer_size); 1337 status = -ENOSPC; 1338 } 1339 1340 return status; 1341 } 1342 1343 /** 1344 * dwc2_schedule_periodic() - Schedules an interrupt or isochronous transfer in 1345 * the periodic schedule 1346 * 1347 * @hsotg: The HCD state structure for the DWC OTG controller 1348 * @qh: QH for the periodic transfer. The QH should already contain the 1349 * scheduling information. 1350 * 1351 * Return: 0 if successful, negative error code otherwise 1352 */ 1353 static int dwc2_schedule_periodic(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 1354 { 1355 int status; 1356 1357 status = dwc2_check_max_xfer_size(hsotg, qh); 1358 if (status) { 1359 dev_dbg(hsotg->dev, 1360 "%s: Channel max transfer size too small for periodic transfer\n", 1361 __func__); 1362 return status; 1363 } 1364 1365 /* Cancel pending unreserve; if canceled OK, unreserve was pending */ 1366 if (del_timer(&qh->unreserve_timer)) 1367 WARN_ON(!qh->unreserve_pending); 1368 1369 /* 1370 * Only need to reserve if there's not an unreserve pending, since if an 1371 * unreserve is pending then by definition our old reservation is still 1372 * valid. Unreserve might still be pending even if we didn't cancel if 1373 * dwc2_unreserve_timer_fn() already started. Code in the timer handles 1374 * that case. 1375 */ 1376 if (!qh->unreserve_pending) { 1377 status = dwc2_do_reserve(hsotg, qh); 1378 if (status) 1379 return status; 1380 } else { 1381 /* 1382 * It might have been a while, so make sure that frame_number 1383 * is still good. Note: we could also try to use the similar 1384 * dwc2_next_periodic_start() but that schedules much more 1385 * tightly and we might need to hurry and queue things up. 1386 */ 1387 if (dwc2_frame_num_le(qh->next_active_frame, 1388 hsotg->frame_number)) 1389 dwc2_pick_first_frame(hsotg, qh); 1390 } 1391 1392 qh->unreserve_pending = 0; 1393 1394 if (hsotg->params.dma_desc_enable) 1395 /* Don't rely on SOF and start in ready schedule */ 1396 list_add_tail(&qh->qh_list_entry, &hsotg->periodic_sched_ready); 1397 else 1398 /* Always start in inactive schedule */ 1399 list_add_tail(&qh->qh_list_entry, 1400 &hsotg->periodic_sched_inactive); 1401 1402 return 0; 1403 } 1404 1405 /** 1406 * dwc2_deschedule_periodic() - Removes an interrupt or isochronous transfer 1407 * from the periodic schedule 1408 * 1409 * @hsotg: The HCD state structure for the DWC OTG controller 1410 * @qh: QH for the periodic transfer 1411 */ 1412 static void dwc2_deschedule_periodic(struct dwc2_hsotg *hsotg, 1413 struct dwc2_qh *qh) 1414 { 1415 bool did_modify; 1416 1417 assert_spin_locked(&hsotg->lock); 1418 1419 /* 1420 * Schedule the unreserve to happen in a little bit. Cases here: 1421 * - Unreserve worker might be sitting there waiting to grab the lock. 1422 * In this case it will notice it's been schedule again and will 1423 * quit. 1424 * - Unreserve worker might not be scheduled. 1425 * 1426 * We should never already be scheduled since dwc2_schedule_periodic() 1427 * should have canceled the scheduled unreserve timer (hence the 1428 * warning on did_modify). 1429 * 1430 * We add + 1 to the timer to guarantee that at least 1 jiffy has 1431 * passed (otherwise if the jiffy counter might tick right after we 1432 * read it and we'll get no delay). 1433 */ 1434 did_modify = mod_timer(&qh->unreserve_timer, 1435 jiffies + DWC2_UNRESERVE_DELAY + 1); 1436 WARN_ON(did_modify); 1437 qh->unreserve_pending = 1; 1438 1439 list_del_init(&qh->qh_list_entry); 1440 } 1441 1442 /** 1443 * dwc2_qh_init() - Initializes a QH structure 1444 * 1445 * @hsotg: The HCD state structure for the DWC OTG controller 1446 * @qh: The QH to init 1447 * @urb: Holds the information about the device/endpoint needed to initialize 1448 * the QH 1449 * @mem_flags: Flags for allocating memory. 1450 */ 1451 static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 1452 struct dwc2_hcd_urb *urb, gfp_t mem_flags) 1453 { 1454 int dev_speed = dwc2_host_get_speed(hsotg, urb->priv); 1455 u8 ep_type = dwc2_hcd_get_pipe_type(&urb->pipe_info); 1456 bool ep_is_in = !!dwc2_hcd_is_pipe_in(&urb->pipe_info); 1457 bool ep_is_isoc = (ep_type == USB_ENDPOINT_XFER_ISOC); 1458 bool ep_is_int = (ep_type == USB_ENDPOINT_XFER_INT); 1459 u32 hprt = dwc2_readl(hsotg->regs + HPRT0); 1460 u32 prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 1461 bool do_split = (prtspd == HPRT0_SPD_HIGH_SPEED && 1462 dev_speed != USB_SPEED_HIGH); 1463 int maxp = dwc2_hcd_get_mps(&urb->pipe_info); 1464 int bytecount = dwc2_hb_mult(maxp) * dwc2_max_packet(maxp); 1465 char *speed, *type; 1466 1467 /* Initialize QH */ 1468 qh->hsotg = hsotg; 1469 setup_timer(&qh->unreserve_timer, dwc2_unreserve_timer_fn, 1470 (unsigned long)qh); 1471 qh->ep_type = ep_type; 1472 qh->ep_is_in = ep_is_in; 1473 1474 qh->data_toggle = DWC2_HC_PID_DATA0; 1475 qh->maxp = maxp; 1476 INIT_LIST_HEAD(&qh->qtd_list); 1477 INIT_LIST_HEAD(&qh->qh_list_entry); 1478 1479 qh->do_split = do_split; 1480 qh->dev_speed = dev_speed; 1481 1482 if (ep_is_int || ep_is_isoc) { 1483 /* Compute scheduling parameters once and save them */ 1484 int host_speed = do_split ? USB_SPEED_HIGH : dev_speed; 1485 struct dwc2_tt *dwc_tt = dwc2_host_get_tt_info(hsotg, urb->priv, 1486 mem_flags, 1487 &qh->ttport); 1488 int device_ns; 1489 1490 qh->dwc_tt = dwc_tt; 1491 1492 qh->host_us = NS_TO_US(usb_calc_bus_time(host_speed, ep_is_in, 1493 ep_is_isoc, bytecount)); 1494 device_ns = usb_calc_bus_time(dev_speed, ep_is_in, 1495 ep_is_isoc, bytecount); 1496 1497 if (do_split && dwc_tt) 1498 device_ns += dwc_tt->usb_tt->think_time; 1499 qh->device_us = NS_TO_US(device_ns); 1500 1501 qh->device_interval = urb->interval; 1502 qh->host_interval = urb->interval * (do_split ? 8 : 1); 1503 1504 /* 1505 * Schedule low speed if we're running the host in low or 1506 * full speed OR if we've got a "TT" to deal with to access this 1507 * device. 1508 */ 1509 qh->schedule_low_speed = prtspd != HPRT0_SPD_HIGH_SPEED || 1510 dwc_tt; 1511 1512 if (do_split) { 1513 /* We won't know num transfers until we schedule */ 1514 qh->num_hs_transfers = -1; 1515 } else if (dev_speed == USB_SPEED_HIGH) { 1516 qh->num_hs_transfers = 1; 1517 } else { 1518 qh->num_hs_transfers = 0; 1519 } 1520 1521 /* We'll schedule later when we have something to do */ 1522 } 1523 1524 switch (dev_speed) { 1525 case USB_SPEED_LOW: 1526 speed = "low"; 1527 break; 1528 case USB_SPEED_FULL: 1529 speed = "full"; 1530 break; 1531 case USB_SPEED_HIGH: 1532 speed = "high"; 1533 break; 1534 default: 1535 speed = "?"; 1536 break; 1537 } 1538 1539 switch (qh->ep_type) { 1540 case USB_ENDPOINT_XFER_ISOC: 1541 type = "isochronous"; 1542 break; 1543 case USB_ENDPOINT_XFER_INT: 1544 type = "interrupt"; 1545 break; 1546 case USB_ENDPOINT_XFER_CONTROL: 1547 type = "control"; 1548 break; 1549 case USB_ENDPOINT_XFER_BULK: 1550 type = "bulk"; 1551 break; 1552 default: 1553 type = "?"; 1554 break; 1555 } 1556 1557 dwc2_sch_dbg(hsotg, "QH=%p Init %s, %s speed, %d bytes:\n", qh, type, 1558 speed, bytecount); 1559 dwc2_sch_dbg(hsotg, "QH=%p ...addr=%d, ep=%d, %s\n", qh, 1560 dwc2_hcd_get_dev_addr(&urb->pipe_info), 1561 dwc2_hcd_get_ep_num(&urb->pipe_info), 1562 ep_is_in ? "IN" : "OUT"); 1563 if (ep_is_int || ep_is_isoc) { 1564 dwc2_sch_dbg(hsotg, 1565 "QH=%p ...duration: host=%d us, device=%d us\n", 1566 qh, qh->host_us, qh->device_us); 1567 dwc2_sch_dbg(hsotg, "QH=%p ...interval: host=%d, device=%d\n", 1568 qh, qh->host_interval, qh->device_interval); 1569 if (qh->schedule_low_speed) 1570 dwc2_sch_dbg(hsotg, "QH=%p ...low speed schedule=%p\n", 1571 qh, dwc2_get_ls_map(hsotg, qh)); 1572 } 1573 } 1574 1575 /** 1576 * dwc2_hcd_qh_create() - Allocates and initializes a QH 1577 * 1578 * @hsotg: The HCD state structure for the DWC OTG controller 1579 * @urb: Holds the information about the device/endpoint needed 1580 * to initialize the QH 1581 * @atomic_alloc: Flag to do atomic allocation if needed 1582 * 1583 * Return: Pointer to the newly allocated QH, or NULL on error 1584 */ 1585 struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg, 1586 struct dwc2_hcd_urb *urb, 1587 gfp_t mem_flags) 1588 { 1589 struct dwc2_qh *qh; 1590 1591 if (!urb->priv) 1592 return NULL; 1593 1594 /* Allocate memory */ 1595 qh = kzalloc(sizeof(*qh), mem_flags); 1596 if (!qh) 1597 return NULL; 1598 1599 dwc2_qh_init(hsotg, qh, urb, mem_flags); 1600 1601 if (hsotg->params.dma_desc_enable && 1602 dwc2_hcd_qh_init_ddma(hsotg, qh, mem_flags) < 0) { 1603 dwc2_hcd_qh_free(hsotg, qh); 1604 return NULL; 1605 } 1606 1607 return qh; 1608 } 1609 1610 /** 1611 * dwc2_hcd_qh_free() - Frees the QH 1612 * 1613 * @hsotg: HCD instance 1614 * @qh: The QH to free 1615 * 1616 * QH should already be removed from the list. QTD list should already be empty 1617 * if called from URB Dequeue. 1618 * 1619 * Must NOT be called with interrupt disabled or spinlock held 1620 */ 1621 void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 1622 { 1623 /* Make sure any unreserve work is finished. */ 1624 if (del_timer_sync(&qh->unreserve_timer)) { 1625 unsigned long flags; 1626 1627 spin_lock_irqsave(&hsotg->lock, flags); 1628 dwc2_do_unreserve(hsotg, qh); 1629 spin_unlock_irqrestore(&hsotg->lock, flags); 1630 } 1631 dwc2_host_put_tt_info(hsotg, qh->dwc_tt); 1632 1633 if (qh->desc_list) 1634 dwc2_hcd_qh_free_ddma(hsotg, qh); 1635 kfree(qh); 1636 } 1637 1638 /** 1639 * dwc2_hcd_qh_add() - Adds a QH to either the non periodic or periodic 1640 * schedule if it is not already in the schedule. If the QH is already in 1641 * the schedule, no action is taken. 1642 * 1643 * @hsotg: The HCD state structure for the DWC OTG controller 1644 * @qh: The QH to add 1645 * 1646 * Return: 0 if successful, negative error code otherwise 1647 */ 1648 int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 1649 { 1650 int status; 1651 u32 intr_mask; 1652 1653 if (dbg_qh(qh)) 1654 dev_vdbg(hsotg->dev, "%s()\n", __func__); 1655 1656 if (!list_empty(&qh->qh_list_entry)) 1657 /* QH already in a schedule */ 1658 return 0; 1659 1660 /* Add the new QH to the appropriate schedule */ 1661 if (dwc2_qh_is_non_per(qh)) { 1662 /* Schedule right away */ 1663 qh->start_active_frame = hsotg->frame_number; 1664 qh->next_active_frame = qh->start_active_frame; 1665 1666 /* Always start in inactive schedule */ 1667 list_add_tail(&qh->qh_list_entry, 1668 &hsotg->non_periodic_sched_inactive); 1669 return 0; 1670 } 1671 1672 status = dwc2_schedule_periodic(hsotg, qh); 1673 if (status) 1674 return status; 1675 if (!hsotg->periodic_qh_count) { 1676 intr_mask = dwc2_readl(hsotg->regs + GINTMSK); 1677 intr_mask |= GINTSTS_SOF; 1678 dwc2_writel(intr_mask, hsotg->regs + GINTMSK); 1679 } 1680 hsotg->periodic_qh_count++; 1681 1682 return 0; 1683 } 1684 1685 /** 1686 * dwc2_hcd_qh_unlink() - Removes a QH from either the non-periodic or periodic 1687 * schedule. Memory is not freed. 1688 * 1689 * @hsotg: The HCD state structure 1690 * @qh: QH to remove from schedule 1691 */ 1692 void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 1693 { 1694 u32 intr_mask; 1695 1696 dev_vdbg(hsotg->dev, "%s()\n", __func__); 1697 1698 if (list_empty(&qh->qh_list_entry)) 1699 /* QH is not in a schedule */ 1700 return; 1701 1702 if (dwc2_qh_is_non_per(qh)) { 1703 if (hsotg->non_periodic_qh_ptr == &qh->qh_list_entry) 1704 hsotg->non_periodic_qh_ptr = 1705 hsotg->non_periodic_qh_ptr->next; 1706 list_del_init(&qh->qh_list_entry); 1707 return; 1708 } 1709 1710 dwc2_deschedule_periodic(hsotg, qh); 1711 hsotg->periodic_qh_count--; 1712 if (!hsotg->periodic_qh_count && 1713 !hsotg->params.dma_desc_enable) { 1714 intr_mask = dwc2_readl(hsotg->regs + GINTMSK); 1715 intr_mask &= ~GINTSTS_SOF; 1716 dwc2_writel(intr_mask, hsotg->regs + GINTMSK); 1717 } 1718 } 1719 1720 /** 1721 * dwc2_next_for_periodic_split() - Set next_active_frame midway thru a split. 1722 * 1723 * This is called for setting next_active_frame for periodic splits for all but 1724 * the first packet of the split. Confusing? I thought so... 1725 * 1726 * Periodic splits are single low/full speed transfers that we end up splitting 1727 * up into several high speed transfers. They always fit into one full (1 ms) 1728 * frame but might be split over several microframes (125 us each). We to put 1729 * each of the parts on a very specific high speed frame. 1730 * 1731 * This function figures out where the next active uFrame needs to be. 1732 * 1733 * @hsotg: The HCD state structure 1734 * @qh: QH for the periodic transfer. 1735 * @frame_number: The current frame number. 1736 * 1737 * Return: number missed by (or 0 if we didn't miss). 1738 */ 1739 static int dwc2_next_for_periodic_split(struct dwc2_hsotg *hsotg, 1740 struct dwc2_qh *qh, u16 frame_number) 1741 { 1742 u16 old_frame = qh->next_active_frame; 1743 u16 prev_frame_number = dwc2_frame_num_dec(frame_number, 1); 1744 int missed = 0; 1745 u16 incr; 1746 1747 /* 1748 * See dwc2_uframe_schedule_split() for split scheduling. 1749 * 1750 * Basically: increment 1 normally, but 2 right after the start split 1751 * (except for ISOC out). 1752 */ 1753 if (old_frame == qh->start_active_frame && 1754 !(qh->ep_type == USB_ENDPOINT_XFER_ISOC && !qh->ep_is_in)) 1755 incr = 2; 1756 else 1757 incr = 1; 1758 1759 qh->next_active_frame = dwc2_frame_num_inc(old_frame, incr); 1760 1761 /* 1762 * Note that it's OK for frame_number to be 1 frame past 1763 * next_active_frame. Remember that next_active_frame is supposed to 1764 * be 1 frame _before_ when we want to be scheduled. If we're 1 frame 1765 * past it just means schedule ASAP. 1766 * 1767 * It's _not_ OK, however, if we're more than one frame past. 1768 */ 1769 if (dwc2_frame_num_gt(prev_frame_number, qh->next_active_frame)) { 1770 /* 1771 * OOPS, we missed. That's actually pretty bad since 1772 * the hub will be unhappy; try ASAP I guess. 1773 */ 1774 missed = dwc2_frame_num_dec(prev_frame_number, 1775 qh->next_active_frame); 1776 qh->next_active_frame = frame_number; 1777 } 1778 1779 return missed; 1780 } 1781 1782 /** 1783 * dwc2_next_periodic_start() - Set next_active_frame for next transfer start 1784 * 1785 * This is called for setting next_active_frame for a periodic transfer for 1786 * all cases other than midway through a periodic split. This will also update 1787 * start_active_frame. 1788 * 1789 * Since we _always_ keep start_active_frame as the start of the previous 1790 * transfer this is normally pretty easy: we just add our interval to 1791 * start_active_frame and we've got our answer. 1792 * 1793 * The tricks come into play if we miss. In that case we'll look for the next 1794 * slot we can fit into. 1795 * 1796 * @hsotg: The HCD state structure 1797 * @qh: QH for the periodic transfer. 1798 * @frame_number: The current frame number. 1799 * 1800 * Return: number missed by (or 0 if we didn't miss). 1801 */ 1802 static int dwc2_next_periodic_start(struct dwc2_hsotg *hsotg, 1803 struct dwc2_qh *qh, u16 frame_number) 1804 { 1805 int missed = 0; 1806 u16 interval = qh->host_interval; 1807 u16 prev_frame_number = dwc2_frame_num_dec(frame_number, 1); 1808 1809 qh->start_active_frame = dwc2_frame_num_inc(qh->start_active_frame, 1810 interval); 1811 1812 /* 1813 * The dwc2_frame_num_gt() function used below won't work terribly well 1814 * with if we just incremented by a really large intervals since the 1815 * frame counter only goes to 0x3fff. It's terribly unlikely that we 1816 * will have missed in this case anyway. Just go to exit. If we want 1817 * to try to do better we'll need to keep track of a bigger counter 1818 * somewhere in the driver and handle overflows. 1819 */ 1820 if (interval >= 0x1000) 1821 goto exit; 1822 1823 /* 1824 * Test for misses, which is when it's too late to schedule. 1825 * 1826 * A few things to note: 1827 * - We compare against prev_frame_number since start_active_frame 1828 * and next_active_frame are always 1 frame before we want things 1829 * to be active and we assume we can still get scheduled in the 1830 * current frame number. 1831 * - It's possible for start_active_frame (now incremented) to be 1832 * next_active_frame if we got an EO MISS (even_odd miss) which 1833 * basically means that we detected there wasn't enough time for 1834 * the last packet and dwc2_hc_set_even_odd_frame() rescheduled us 1835 * at the last second. We want to make sure we don't schedule 1836 * another transfer for the same frame. My test webcam doesn't seem 1837 * terribly upset by missing a transfer but really doesn't like when 1838 * we do two transfers in the same frame. 1839 * - Some misses are expected. Specifically, in order to work 1840 * perfectly dwc2 really needs quite spectacular interrupt latency 1841 * requirements. It needs to be able to handle its interrupts 1842 * completely within 125 us of them being asserted. That not only 1843 * means that the dwc2 interrupt handler needs to be fast but it 1844 * means that nothing else in the system has to block dwc2 for a long 1845 * time. We can help with the dwc2 parts of this, but it's hard to 1846 * guarantee that a system will have interrupt latency < 125 us, so 1847 * we have to be robust to some misses. 1848 */ 1849 if (qh->start_active_frame == qh->next_active_frame || 1850 dwc2_frame_num_gt(prev_frame_number, qh->start_active_frame)) { 1851 u16 ideal_start = qh->start_active_frame; 1852 int periods_in_map; 1853 1854 /* 1855 * Adjust interval as per gcd with map size. 1856 * See pmap_schedule() for more details here. 1857 */ 1858 if (qh->do_split || qh->dev_speed == USB_SPEED_HIGH) 1859 periods_in_map = DWC2_HS_SCHEDULE_UFRAMES; 1860 else 1861 periods_in_map = DWC2_LS_SCHEDULE_FRAMES; 1862 interval = gcd(interval, periods_in_map); 1863 1864 do { 1865 qh->start_active_frame = dwc2_frame_num_inc( 1866 qh->start_active_frame, interval); 1867 } while (dwc2_frame_num_gt(prev_frame_number, 1868 qh->start_active_frame)); 1869 1870 missed = dwc2_frame_num_dec(qh->start_active_frame, 1871 ideal_start); 1872 } 1873 1874 exit: 1875 qh->next_active_frame = qh->start_active_frame; 1876 1877 return missed; 1878 } 1879 1880 /* 1881 * Deactivates a QH. For non-periodic QHs, removes the QH from the active 1882 * non-periodic schedule. The QH is added to the inactive non-periodic 1883 * schedule if any QTDs are still attached to the QH. 1884 * 1885 * For periodic QHs, the QH is removed from the periodic queued schedule. If 1886 * there are any QTDs still attached to the QH, the QH is added to either the 1887 * periodic inactive schedule or the periodic ready schedule and its next 1888 * scheduled frame is calculated. The QH is placed in the ready schedule if 1889 * the scheduled frame has been reached already. Otherwise it's placed in the 1890 * inactive schedule. If there are no QTDs attached to the QH, the QH is 1891 * completely removed from the periodic schedule. 1892 */ 1893 void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 1894 int sched_next_periodic_split) 1895 { 1896 u16 old_frame = qh->next_active_frame; 1897 u16 frame_number; 1898 int missed; 1899 1900 if (dbg_qh(qh)) 1901 dev_vdbg(hsotg->dev, "%s()\n", __func__); 1902 1903 if (dwc2_qh_is_non_per(qh)) { 1904 dwc2_hcd_qh_unlink(hsotg, qh); 1905 if (!list_empty(&qh->qtd_list)) 1906 /* Add back to inactive non-periodic schedule */ 1907 dwc2_hcd_qh_add(hsotg, qh); 1908 return; 1909 } 1910 1911 /* 1912 * Use the real frame number rather than the cached value as of the 1913 * last SOF just to get us a little closer to reality. Note that 1914 * means we don't actually know if we've already handled the SOF 1915 * interrupt for this frame. 1916 */ 1917 frame_number = dwc2_hcd_get_frame_number(hsotg); 1918 1919 if (sched_next_periodic_split) 1920 missed = dwc2_next_for_periodic_split(hsotg, qh, frame_number); 1921 else 1922 missed = dwc2_next_periodic_start(hsotg, qh, frame_number); 1923 1924 dwc2_sch_vdbg(hsotg, 1925 "QH=%p next(%d) fn=%04x, sch=%04x=>%04x (%+d) miss=%d %s\n", 1926 qh, sched_next_periodic_split, frame_number, old_frame, 1927 qh->next_active_frame, 1928 dwc2_frame_num_dec(qh->next_active_frame, old_frame), 1929 missed, missed ? "MISS" : ""); 1930 1931 if (list_empty(&qh->qtd_list)) { 1932 dwc2_hcd_qh_unlink(hsotg, qh); 1933 return; 1934 } 1935 1936 /* 1937 * Remove from periodic_sched_queued and move to 1938 * appropriate queue 1939 * 1940 * Note: we purposely use the frame_number from the "hsotg" structure 1941 * since we know SOF interrupt will handle future frames. 1942 */ 1943 if (dwc2_frame_num_le(qh->next_active_frame, hsotg->frame_number)) 1944 list_move_tail(&qh->qh_list_entry, 1945 &hsotg->periodic_sched_ready); 1946 else 1947 list_move_tail(&qh->qh_list_entry, 1948 &hsotg->periodic_sched_inactive); 1949 } 1950 1951 /** 1952 * dwc2_hcd_qtd_init() - Initializes a QTD structure 1953 * 1954 * @qtd: The QTD to initialize 1955 * @urb: The associated URB 1956 */ 1957 void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 1958 { 1959 qtd->urb = urb; 1960 if (dwc2_hcd_get_pipe_type(&urb->pipe_info) == 1961 USB_ENDPOINT_XFER_CONTROL) { 1962 /* 1963 * The only time the QTD data toggle is used is on the data 1964 * phase of control transfers. This phase always starts with 1965 * DATA1. 1966 */ 1967 qtd->data_toggle = DWC2_HC_PID_DATA1; 1968 qtd->control_phase = DWC2_CONTROL_SETUP; 1969 } 1970 1971 /* Start split */ 1972 qtd->complete_split = 0; 1973 qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL; 1974 qtd->isoc_split_offset = 0; 1975 qtd->in_process = 0; 1976 1977 /* Store the qtd ptr in the urb to reference the QTD */ 1978 urb->qtd = qtd; 1979 } 1980 1981 /** 1982 * dwc2_hcd_qtd_add() - Adds a QTD to the QTD-list of a QH 1983 * Caller must hold driver lock. 1984 * 1985 * @hsotg: The DWC HCD structure 1986 * @qtd: The QTD to add 1987 * @qh: Queue head to add qtd to 1988 * 1989 * Return: 0 if successful, negative error code otherwise 1990 * 1991 * If the QH to which the QTD is added is not currently scheduled, it is placed 1992 * into the proper schedule based on its EP type. 1993 */ 1994 int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 1995 struct dwc2_qh *qh) 1996 { 1997 int retval; 1998 1999 if (unlikely(!qh)) { 2000 dev_err(hsotg->dev, "%s: Invalid QH\n", __func__); 2001 retval = -EINVAL; 2002 goto fail; 2003 } 2004 2005 retval = dwc2_hcd_qh_add(hsotg, qh); 2006 if (retval) 2007 goto fail; 2008 2009 qtd->qh = qh; 2010 list_add_tail(&qtd->qtd_list_entry, &qh->qtd_list); 2011 2012 return 0; 2013 fail: 2014 return retval; 2015 } 2016