1 /* 2 * hcd.c - DesignWare HS OTG Controller host-mode routines 3 * 4 * Copyright (C) 2004-2013 Synopsys, Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The names of the above-listed copyright holders may not be used 16 * to endorse or promote products derived from this software without 17 * specific prior written permission. 18 * 19 * ALTERNATIVELY, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") as published by the Free Software 21 * Foundation; either version 2 of the License, or (at your option) any 22 * later version. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * This file contains the core HCD code, and implements the Linux hc_driver 39 * API 40 */ 41 #include <linux/kernel.h> 42 #include <linux/module.h> 43 #include <linux/spinlock.h> 44 #include <linux/interrupt.h> 45 #include <linux/dma-mapping.h> 46 #include <linux/delay.h> 47 #include <linux/io.h> 48 #include <linux/slab.h> 49 #include <linux/usb.h> 50 51 #include <linux/usb/hcd.h> 52 #include <linux/usb/ch11.h> 53 54 #include "core.h" 55 #include "hcd.h" 56 57 /** 58 * dwc2_dump_channel_info() - Prints the state of a host channel 59 * 60 * @hsotg: Programming view of DWC_otg controller 61 * @chan: Pointer to the channel to dump 62 * 63 * Must be called with interrupt disabled and spinlock held 64 * 65 * NOTE: This function will be removed once the peripheral controller code 66 * is integrated and the driver is stable 67 */ 68 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg, 69 struct dwc2_host_chan *chan) 70 { 71 #ifdef VERBOSE_DEBUG 72 int num_channels = hsotg->core_params->host_channels; 73 struct dwc2_qh *qh; 74 u32 hcchar; 75 u32 hcsplt; 76 u32 hctsiz; 77 u32 hc_dma; 78 int i; 79 80 if (chan == NULL) 81 return; 82 83 hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); 84 hcsplt = readl(hsotg->regs + HCSPLT(chan->hc_num)); 85 hctsiz = readl(hsotg->regs + HCTSIZ(chan->hc_num)); 86 hc_dma = readl(hsotg->regs + HCDMA(chan->hc_num)); 87 88 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan); 89 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", 90 hcchar, hcsplt); 91 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", 92 hctsiz, hc_dma); 93 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 94 chan->dev_addr, chan->ep_num, chan->ep_is_in); 95 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 96 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 97 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start); 98 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started); 99 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 100 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 101 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 102 (unsigned long)chan->xfer_dma); 103 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 104 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 105 dev_dbg(hsotg->dev, " NP inactive sched:\n"); 106 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive, 107 qh_list_entry) 108 dev_dbg(hsotg->dev, " %p\n", qh); 109 dev_dbg(hsotg->dev, " NP active sched:\n"); 110 list_for_each_entry(qh, &hsotg->non_periodic_sched_active, 111 qh_list_entry) 112 dev_dbg(hsotg->dev, " %p\n", qh); 113 dev_dbg(hsotg->dev, " Channels:\n"); 114 for (i = 0; i < num_channels; i++) { 115 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 116 117 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan); 118 } 119 #endif /* VERBOSE_DEBUG */ 120 } 121 122 /* 123 * Processes all the URBs in a single list of QHs. Completes them with 124 * -ETIMEDOUT and frees the QTD. 125 * 126 * Must be called with interrupt disabled and spinlock held 127 */ 128 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg, 129 struct list_head *qh_list) 130 { 131 struct dwc2_qh *qh, *qh_tmp; 132 struct dwc2_qtd *qtd, *qtd_tmp; 133 134 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 135 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 136 qtd_list_entry) { 137 dwc2_host_complete(hsotg, qtd, -ETIMEDOUT); 138 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 139 } 140 } 141 } 142 143 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg, 144 struct list_head *qh_list) 145 { 146 struct dwc2_qtd *qtd, *qtd_tmp; 147 struct dwc2_qh *qh, *qh_tmp; 148 unsigned long flags; 149 150 if (!qh_list->next) 151 /* The list hasn't been initialized yet */ 152 return; 153 154 spin_lock_irqsave(&hsotg->lock, flags); 155 156 /* Ensure there are no QTDs or URBs left */ 157 dwc2_kill_urbs_in_qh_list(hsotg, qh_list); 158 159 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 160 dwc2_hcd_qh_unlink(hsotg, qh); 161 162 /* Free each QTD in the QH's QTD list */ 163 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 164 qtd_list_entry) 165 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 166 167 spin_unlock_irqrestore(&hsotg->lock, flags); 168 dwc2_hcd_qh_free(hsotg, qh); 169 spin_lock_irqsave(&hsotg->lock, flags); 170 } 171 172 spin_unlock_irqrestore(&hsotg->lock, flags); 173 } 174 175 /* 176 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic 177 * and periodic schedules. The QTD associated with each URB is removed from 178 * the schedule and freed. This function may be called when a disconnect is 179 * detected or when the HCD is being stopped. 180 * 181 * Must be called with interrupt disabled and spinlock held 182 */ 183 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg) 184 { 185 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive); 186 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active); 187 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive); 188 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready); 189 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned); 190 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued); 191 } 192 193 /** 194 * dwc2_hcd_start() - Starts the HCD when switching to Host mode 195 * 196 * @hsotg: Pointer to struct dwc2_hsotg 197 */ 198 void dwc2_hcd_start(struct dwc2_hsotg *hsotg) 199 { 200 u32 hprt0; 201 202 if (hsotg->op_state == OTG_STATE_B_HOST) { 203 /* 204 * Reset the port. During a HNP mode switch the reset 205 * needs to occur within 1ms and have a duration of at 206 * least 50ms. 207 */ 208 hprt0 = dwc2_read_hprt0(hsotg); 209 hprt0 |= HPRT0_RST; 210 writel(hprt0, hsotg->regs + HPRT0); 211 } 212 213 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work, 214 msecs_to_jiffies(50)); 215 } 216 217 /* Must be called with interrupt disabled and spinlock held */ 218 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg) 219 { 220 int num_channels = hsotg->core_params->host_channels; 221 struct dwc2_host_chan *channel; 222 u32 hcchar; 223 int i; 224 225 if (hsotg->core_params->dma_enable <= 0) { 226 /* Flush out any channel requests in slave mode */ 227 for (i = 0; i < num_channels; i++) { 228 channel = hsotg->hc_ptr_array[i]; 229 if (!list_empty(&channel->hc_list_entry)) 230 continue; 231 hcchar = readl(hsotg->regs + HCCHAR(i)); 232 if (hcchar & HCCHAR_CHENA) { 233 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR); 234 hcchar |= HCCHAR_CHDIS; 235 writel(hcchar, hsotg->regs + HCCHAR(i)); 236 } 237 } 238 } 239 240 for (i = 0; i < num_channels; i++) { 241 channel = hsotg->hc_ptr_array[i]; 242 if (!list_empty(&channel->hc_list_entry)) 243 continue; 244 hcchar = readl(hsotg->regs + HCCHAR(i)); 245 if (hcchar & HCCHAR_CHENA) { 246 /* Halt the channel */ 247 hcchar |= HCCHAR_CHDIS; 248 writel(hcchar, hsotg->regs + HCCHAR(i)); 249 } 250 251 dwc2_hc_cleanup(hsotg, channel); 252 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list); 253 /* 254 * Added for Descriptor DMA to prevent channel double cleanup in 255 * release_channel_ddma(), which is called from ep_disable when 256 * device disconnects 257 */ 258 channel->qh = NULL; 259 } 260 } 261 262 /** 263 * dwc2_hcd_disconnect() - Handles disconnect of the HCD 264 * 265 * @hsotg: Pointer to struct dwc2_hsotg 266 * 267 * Must be called with interrupt disabled and spinlock held 268 */ 269 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg) 270 { 271 u32 intr; 272 273 /* Set status flags for the hub driver */ 274 hsotg->flags.b.port_connect_status_change = 1; 275 hsotg->flags.b.port_connect_status = 0; 276 277 /* 278 * Shutdown any transfers in process by clearing the Tx FIFO Empty 279 * interrupt mask and status bits and disabling subsequent host 280 * channel interrupts. 281 */ 282 intr = readl(hsotg->regs + GINTMSK); 283 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT); 284 writel(intr, hsotg->regs + GINTMSK); 285 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT; 286 writel(intr, hsotg->regs + GINTSTS); 287 288 /* 289 * Turn off the vbus power only if the core has transitioned to device 290 * mode. If still in host mode, need to keep power on to detect a 291 * reconnection. 292 */ 293 if (dwc2_is_device_mode(hsotg)) { 294 if (hsotg->op_state != OTG_STATE_A_SUSPEND) { 295 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n"); 296 writel(0, hsotg->regs + HPRT0); 297 } 298 299 dwc2_disable_host_interrupts(hsotg); 300 } 301 302 /* Respond with an error status to all URBs in the schedule */ 303 dwc2_kill_all_urbs(hsotg); 304 305 if (dwc2_is_host_mode(hsotg)) 306 /* Clean up any host channels that were in use */ 307 dwc2_hcd_cleanup_channels(hsotg); 308 309 dwc2_host_disconnect(hsotg); 310 } 311 312 /** 313 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup 314 * 315 * @hsotg: Pointer to struct dwc2_hsotg 316 */ 317 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg) 318 { 319 if (hsotg->lx_state == DWC2_L2) 320 hsotg->flags.b.port_suspend_change = 1; 321 else 322 hsotg->flags.b.port_l1_change = 1; 323 } 324 325 /** 326 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner 327 * 328 * @hsotg: Pointer to struct dwc2_hsotg 329 * 330 * Must be called with interrupt disabled and spinlock held 331 */ 332 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg) 333 { 334 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n"); 335 336 /* 337 * The root hub should be disconnected before this function is called. 338 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue) 339 * and the QH lists (via ..._hcd_endpoint_disable). 340 */ 341 342 /* Turn off all host-specific interrupts */ 343 dwc2_disable_host_interrupts(hsotg); 344 345 /* Turn off the vbus power */ 346 dev_dbg(hsotg->dev, "PortPower off\n"); 347 writel(0, hsotg->regs + HPRT0); 348 } 349 350 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, 351 struct dwc2_hcd_urb *urb, void **ep_handle, 352 gfp_t mem_flags) 353 { 354 struct dwc2_qtd *qtd; 355 unsigned long flags; 356 u32 intr_mask; 357 int retval; 358 int dev_speed; 359 360 if (!hsotg->flags.b.port_connect_status) { 361 /* No longer connected */ 362 dev_err(hsotg->dev, "Not connected\n"); 363 return -ENODEV; 364 } 365 366 dev_speed = dwc2_host_get_speed(hsotg, urb->priv); 367 368 /* Some configurations cannot support LS traffic on a FS root port */ 369 if ((dev_speed == USB_SPEED_LOW) && 370 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) && 371 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) { 372 u32 hprt0 = readl(hsotg->regs + HPRT0); 373 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 374 375 if (prtspd == HPRT0_SPD_FULL_SPEED) 376 return -ENODEV; 377 } 378 379 qtd = kzalloc(sizeof(*qtd), mem_flags); 380 if (!qtd) 381 return -ENOMEM; 382 383 dwc2_hcd_qtd_init(qtd, urb); 384 retval = dwc2_hcd_qtd_add(hsotg, qtd, (struct dwc2_qh **)ep_handle, 385 mem_flags); 386 if (retval) { 387 dev_err(hsotg->dev, 388 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n", 389 retval); 390 kfree(qtd); 391 return retval; 392 } 393 394 intr_mask = readl(hsotg->regs + GINTMSK); 395 if (!(intr_mask & GINTSTS_SOF)) { 396 enum dwc2_transaction_type tr_type; 397 398 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK && 399 !(qtd->urb->flags & URB_GIVEBACK_ASAP)) 400 /* 401 * Do not schedule SG transactions until qtd has 402 * URB_GIVEBACK_ASAP set 403 */ 404 return 0; 405 406 spin_lock_irqsave(&hsotg->lock, flags); 407 tr_type = dwc2_hcd_select_transactions(hsotg); 408 if (tr_type != DWC2_TRANSACTION_NONE) 409 dwc2_hcd_queue_transactions(hsotg, tr_type); 410 spin_unlock_irqrestore(&hsotg->lock, flags); 411 } 412 413 return 0; 414 } 415 416 /* Must be called with interrupt disabled and spinlock held */ 417 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg, 418 struct dwc2_hcd_urb *urb) 419 { 420 struct dwc2_qh *qh; 421 struct dwc2_qtd *urb_qtd; 422 423 urb_qtd = urb->qtd; 424 if (!urb_qtd) { 425 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n"); 426 return -EINVAL; 427 } 428 429 qh = urb_qtd->qh; 430 if (!qh) { 431 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n"); 432 return -EINVAL; 433 } 434 435 urb->priv = NULL; 436 437 if (urb_qtd->in_process && qh->channel) { 438 dwc2_dump_channel_info(hsotg, qh->channel); 439 440 /* The QTD is in process (it has been assigned to a channel) */ 441 if (hsotg->flags.b.port_connect_status) 442 /* 443 * If still connected (i.e. in host mode), halt the 444 * channel so it can be used for other transfers. If 445 * no longer connected, the host registers can't be 446 * written to halt the channel since the core is in 447 * device mode. 448 */ 449 dwc2_hc_halt(hsotg, qh->channel, 450 DWC2_HC_XFER_URB_DEQUEUE); 451 } 452 453 /* 454 * Free the QTD and clean up the associated QH. Leave the QH in the 455 * schedule if it has any remaining QTDs. 456 */ 457 if (hsotg->core_params->dma_desc_enable <= 0) { 458 u8 in_process = urb_qtd->in_process; 459 460 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 461 if (in_process) { 462 dwc2_hcd_qh_deactivate(hsotg, qh, 0); 463 qh->channel = NULL; 464 } else if (list_empty(&qh->qtd_list)) { 465 dwc2_hcd_qh_unlink(hsotg, qh); 466 } 467 } else { 468 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 469 } 470 471 return 0; 472 } 473 474 /* Must NOT be called with interrupt disabled or spinlock held */ 475 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg, 476 struct usb_host_endpoint *ep, int retry) 477 { 478 struct dwc2_qtd *qtd, *qtd_tmp; 479 struct dwc2_qh *qh; 480 unsigned long flags; 481 int rc; 482 483 spin_lock_irqsave(&hsotg->lock, flags); 484 485 qh = ep->hcpriv; 486 if (!qh) { 487 rc = -EINVAL; 488 goto err; 489 } 490 491 while (!list_empty(&qh->qtd_list) && retry--) { 492 if (retry == 0) { 493 dev_err(hsotg->dev, 494 "## timeout in dwc2_hcd_endpoint_disable() ##\n"); 495 rc = -EBUSY; 496 goto err; 497 } 498 499 spin_unlock_irqrestore(&hsotg->lock, flags); 500 usleep_range(20000, 40000); 501 spin_lock_irqsave(&hsotg->lock, flags); 502 qh = ep->hcpriv; 503 if (!qh) { 504 rc = -EINVAL; 505 goto err; 506 } 507 } 508 509 dwc2_hcd_qh_unlink(hsotg, qh); 510 511 /* Free each QTD in the QH's QTD list */ 512 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) 513 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 514 515 ep->hcpriv = NULL; 516 spin_unlock_irqrestore(&hsotg->lock, flags); 517 dwc2_hcd_qh_free(hsotg, qh); 518 519 return 0; 520 521 err: 522 ep->hcpriv = NULL; 523 spin_unlock_irqrestore(&hsotg->lock, flags); 524 525 return rc; 526 } 527 528 /* Must be called with interrupt disabled and spinlock held */ 529 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg, 530 struct usb_host_endpoint *ep) 531 { 532 struct dwc2_qh *qh = ep->hcpriv; 533 534 if (!qh) 535 return -EINVAL; 536 537 qh->data_toggle = DWC2_HC_PID_DATA0; 538 539 return 0; 540 } 541 542 /* 543 * Initializes dynamic portions of the DWC_otg HCD state 544 * 545 * Must be called with interrupt disabled and spinlock held 546 */ 547 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg) 548 { 549 struct dwc2_host_chan *chan, *chan_tmp; 550 int num_channels; 551 int i; 552 553 hsotg->flags.d32 = 0; 554 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active; 555 556 if (hsotg->core_params->uframe_sched > 0) { 557 hsotg->available_host_channels = 558 hsotg->core_params->host_channels; 559 } else { 560 hsotg->non_periodic_channels = 0; 561 hsotg->periodic_channels = 0; 562 } 563 564 /* 565 * Put all channels in the free channel list and clean up channel 566 * states 567 */ 568 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list, 569 hc_list_entry) 570 list_del_init(&chan->hc_list_entry); 571 572 num_channels = hsotg->core_params->host_channels; 573 for (i = 0; i < num_channels; i++) { 574 chan = hsotg->hc_ptr_array[i]; 575 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list); 576 dwc2_hc_cleanup(hsotg, chan); 577 } 578 579 /* Initialize the DWC core for host mode operation */ 580 dwc2_core_host_init(hsotg); 581 } 582 583 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg, 584 struct dwc2_host_chan *chan, 585 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 586 { 587 int hub_addr, hub_port; 588 589 chan->do_split = 1; 590 chan->xact_pos = qtd->isoc_split_pos; 591 chan->complete_split = qtd->complete_split; 592 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port); 593 chan->hub_addr = (u8)hub_addr; 594 chan->hub_port = (u8)hub_port; 595 } 596 597 static void *dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg, 598 struct dwc2_host_chan *chan, 599 struct dwc2_qtd *qtd, void *bufptr) 600 { 601 struct dwc2_hcd_urb *urb = qtd->urb; 602 struct dwc2_hcd_iso_packet_desc *frame_desc; 603 604 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) { 605 case USB_ENDPOINT_XFER_CONTROL: 606 chan->ep_type = USB_ENDPOINT_XFER_CONTROL; 607 608 switch (qtd->control_phase) { 609 case DWC2_CONTROL_SETUP: 610 dev_vdbg(hsotg->dev, " Control setup transaction\n"); 611 chan->do_ping = 0; 612 chan->ep_is_in = 0; 613 chan->data_pid_start = DWC2_HC_PID_SETUP; 614 if (hsotg->core_params->dma_enable > 0) 615 chan->xfer_dma = urb->setup_dma; 616 else 617 chan->xfer_buf = urb->setup_packet; 618 chan->xfer_len = 8; 619 bufptr = NULL; 620 break; 621 622 case DWC2_CONTROL_DATA: 623 dev_vdbg(hsotg->dev, " Control data transaction\n"); 624 chan->data_pid_start = qtd->data_toggle; 625 break; 626 627 case DWC2_CONTROL_STATUS: 628 /* 629 * Direction is opposite of data direction or IN if no 630 * data 631 */ 632 dev_vdbg(hsotg->dev, " Control status transaction\n"); 633 if (urb->length == 0) 634 chan->ep_is_in = 1; 635 else 636 chan->ep_is_in = 637 dwc2_hcd_is_pipe_out(&urb->pipe_info); 638 if (chan->ep_is_in) 639 chan->do_ping = 0; 640 chan->data_pid_start = DWC2_HC_PID_DATA1; 641 chan->xfer_len = 0; 642 if (hsotg->core_params->dma_enable > 0) 643 chan->xfer_dma = hsotg->status_buf_dma; 644 else 645 chan->xfer_buf = hsotg->status_buf; 646 bufptr = NULL; 647 break; 648 } 649 break; 650 651 case USB_ENDPOINT_XFER_BULK: 652 chan->ep_type = USB_ENDPOINT_XFER_BULK; 653 break; 654 655 case USB_ENDPOINT_XFER_INT: 656 chan->ep_type = USB_ENDPOINT_XFER_INT; 657 break; 658 659 case USB_ENDPOINT_XFER_ISOC: 660 chan->ep_type = USB_ENDPOINT_XFER_ISOC; 661 if (hsotg->core_params->dma_desc_enable > 0) 662 break; 663 664 frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; 665 frame_desc->status = 0; 666 667 if (hsotg->core_params->dma_enable > 0) { 668 chan->xfer_dma = urb->dma; 669 chan->xfer_dma += frame_desc->offset + 670 qtd->isoc_split_offset; 671 } else { 672 chan->xfer_buf = urb->buf; 673 chan->xfer_buf += frame_desc->offset + 674 qtd->isoc_split_offset; 675 } 676 677 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset; 678 679 /* For non-dword aligned buffers */ 680 if (hsotg->core_params->dma_enable > 0 && 681 (chan->xfer_dma & 0x3)) 682 bufptr = (u8 *)urb->buf + frame_desc->offset + 683 qtd->isoc_split_offset; 684 else 685 bufptr = NULL; 686 687 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) { 688 if (chan->xfer_len <= 188) 689 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL; 690 else 691 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN; 692 } 693 break; 694 } 695 696 return bufptr; 697 } 698 699 static int dwc2_hc_setup_align_buf(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 700 struct dwc2_host_chan *chan, 701 struct dwc2_hcd_urb *urb, void *bufptr) 702 { 703 u32 buf_size; 704 struct urb *usb_urb; 705 struct usb_hcd *hcd; 706 707 if (!qh->dw_align_buf) { 708 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC) 709 buf_size = hsotg->core_params->max_transfer_size; 710 else 711 /* 3072 = 3 max-size Isoc packets */ 712 buf_size = 3072; 713 714 qh->dw_align_buf = dma_alloc_coherent(hsotg->dev, buf_size, 715 &qh->dw_align_buf_dma, 716 GFP_ATOMIC); 717 if (!qh->dw_align_buf) 718 return -ENOMEM; 719 qh->dw_align_buf_size = buf_size; 720 } 721 722 if (chan->xfer_len) { 723 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__); 724 usb_urb = urb->priv; 725 726 if (usb_urb) { 727 if (usb_urb->transfer_flags & 728 (URB_SETUP_MAP_SINGLE | URB_DMA_MAP_SG | 729 URB_DMA_MAP_PAGE | URB_DMA_MAP_SINGLE)) { 730 hcd = dwc2_hsotg_to_hcd(hsotg); 731 usb_hcd_unmap_urb_for_dma(hcd, usb_urb); 732 } 733 if (!chan->ep_is_in) 734 memcpy(qh->dw_align_buf, bufptr, 735 chan->xfer_len); 736 } else { 737 dev_warn(hsotg->dev, "no URB in dwc2_urb\n"); 738 } 739 } 740 741 chan->align_buf = qh->dw_align_buf_dma; 742 return 0; 743 } 744 745 /** 746 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host 747 * channel and initializes the host channel to perform the transactions. The 748 * host channel is removed from the free list. 749 * 750 * @hsotg: The HCD state structure 751 * @qh: Transactions from the first QTD for this QH are selected and assigned 752 * to a free host channel 753 */ 754 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 755 { 756 struct dwc2_host_chan *chan; 757 struct dwc2_hcd_urb *urb; 758 struct dwc2_qtd *qtd; 759 void *bufptr = NULL; 760 761 if (dbg_qh(qh)) 762 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh); 763 764 if (list_empty(&qh->qtd_list)) { 765 dev_dbg(hsotg->dev, "No QTDs in QH list\n"); 766 return -ENOMEM; 767 } 768 769 if (list_empty(&hsotg->free_hc_list)) { 770 dev_dbg(hsotg->dev, "No free channel to assign\n"); 771 return -ENOMEM; 772 } 773 774 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan, 775 hc_list_entry); 776 777 /* Remove host channel from free list */ 778 list_del_init(&chan->hc_list_entry); 779 780 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry); 781 urb = qtd->urb; 782 qh->channel = chan; 783 qtd->in_process = 1; 784 785 /* 786 * Use usb_pipedevice to determine device address. This address is 787 * 0 before the SET_ADDRESS command and the correct address afterward. 788 */ 789 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info); 790 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info); 791 chan->speed = qh->dev_speed; 792 chan->max_packet = dwc2_max_packet(qh->maxp); 793 794 chan->xfer_started = 0; 795 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS; 796 chan->error_state = (qtd->error_count > 0); 797 chan->halt_on_queue = 0; 798 chan->halt_pending = 0; 799 chan->requests = 0; 800 801 /* 802 * The following values may be modified in the transfer type section 803 * below. The xfer_len value may be reduced when the transfer is 804 * started to accommodate the max widths of the XferSize and PktCnt 805 * fields in the HCTSIZn register. 806 */ 807 808 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0); 809 if (chan->ep_is_in) 810 chan->do_ping = 0; 811 else 812 chan->do_ping = qh->ping_state; 813 814 chan->data_pid_start = qh->data_toggle; 815 chan->multi_count = 1; 816 817 if (urb->actual_length > urb->length && 818 !dwc2_hcd_is_pipe_in(&urb->pipe_info)) 819 urb->actual_length = urb->length; 820 821 if (hsotg->core_params->dma_enable > 0) { 822 chan->xfer_dma = urb->dma + urb->actual_length; 823 824 /* For non-dword aligned case */ 825 if (hsotg->core_params->dma_desc_enable <= 0 && 826 (chan->xfer_dma & 0x3)) 827 bufptr = (u8 *)urb->buf + urb->actual_length; 828 } else { 829 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length; 830 } 831 832 chan->xfer_len = urb->length - urb->actual_length; 833 chan->xfer_count = 0; 834 835 /* Set the split attributes if required */ 836 if (qh->do_split) 837 dwc2_hc_init_split(hsotg, chan, qtd, urb); 838 else 839 chan->do_split = 0; 840 841 /* Set the transfer attributes */ 842 bufptr = dwc2_hc_init_xfer(hsotg, chan, qtd, bufptr); 843 844 /* Non DWORD-aligned buffer case */ 845 if (bufptr) { 846 dev_vdbg(hsotg->dev, "Non-aligned buffer\n"); 847 if (dwc2_hc_setup_align_buf(hsotg, qh, chan, urb, bufptr)) { 848 dev_err(hsotg->dev, 849 "%s: Failed to allocate memory to handle non-dword aligned buffer\n", 850 __func__); 851 /* Add channel back to free list */ 852 chan->align_buf = 0; 853 chan->multi_count = 0; 854 list_add_tail(&chan->hc_list_entry, 855 &hsotg->free_hc_list); 856 qtd->in_process = 0; 857 qh->channel = NULL; 858 return -ENOMEM; 859 } 860 } else { 861 chan->align_buf = 0; 862 } 863 864 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 865 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 866 /* 867 * This value may be modified when the transfer is started 868 * to reflect the actual transfer length 869 */ 870 chan->multi_count = dwc2_hb_mult(qh->maxp); 871 872 if (hsotg->core_params->dma_desc_enable > 0) 873 chan->desc_list_addr = qh->desc_list_dma; 874 875 dwc2_hc_init(hsotg, chan); 876 chan->qh = qh; 877 878 return 0; 879 } 880 881 /** 882 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer 883 * schedule and assigns them to available host channels. Called from the HCD 884 * interrupt handler functions. 885 * 886 * @hsotg: The HCD state structure 887 * 888 * Return: The types of new transactions that were assigned to host channels 889 */ 890 enum dwc2_transaction_type dwc2_hcd_select_transactions( 891 struct dwc2_hsotg *hsotg) 892 { 893 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE; 894 struct list_head *qh_ptr; 895 struct dwc2_qh *qh; 896 int num_channels; 897 898 #ifdef DWC2_DEBUG_SOF 899 dev_vdbg(hsotg->dev, " Select Transactions\n"); 900 #endif 901 902 /* Process entries in the periodic ready list */ 903 qh_ptr = hsotg->periodic_sched_ready.next; 904 while (qh_ptr != &hsotg->periodic_sched_ready) { 905 if (list_empty(&hsotg->free_hc_list)) 906 break; 907 if (hsotg->core_params->uframe_sched > 0) { 908 if (hsotg->available_host_channels <= 1) 909 break; 910 hsotg->available_host_channels--; 911 } 912 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 913 if (dwc2_assign_and_init_hc(hsotg, qh)) 914 break; 915 916 /* 917 * Move the QH from the periodic ready schedule to the 918 * periodic assigned schedule 919 */ 920 qh_ptr = qh_ptr->next; 921 list_move(&qh->qh_list_entry, &hsotg->periodic_sched_assigned); 922 ret_val = DWC2_TRANSACTION_PERIODIC; 923 } 924 925 /* 926 * Process entries in the inactive portion of the non-periodic 927 * schedule. Some free host channels may not be used if they are 928 * reserved for periodic transfers. 929 */ 930 num_channels = hsotg->core_params->host_channels; 931 qh_ptr = hsotg->non_periodic_sched_inactive.next; 932 while (qh_ptr != &hsotg->non_periodic_sched_inactive) { 933 if (hsotg->core_params->uframe_sched <= 0 && 934 hsotg->non_periodic_channels >= num_channels - 935 hsotg->periodic_channels) 936 break; 937 if (list_empty(&hsotg->free_hc_list)) 938 break; 939 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 940 if (hsotg->core_params->uframe_sched > 0) { 941 if (hsotg->available_host_channels < 1) 942 break; 943 hsotg->available_host_channels--; 944 } 945 946 if (dwc2_assign_and_init_hc(hsotg, qh)) 947 break; 948 949 /* 950 * Move the QH from the non-periodic inactive schedule to the 951 * non-periodic active schedule 952 */ 953 qh_ptr = qh_ptr->next; 954 list_move(&qh->qh_list_entry, 955 &hsotg->non_periodic_sched_active); 956 957 if (ret_val == DWC2_TRANSACTION_NONE) 958 ret_val = DWC2_TRANSACTION_NON_PERIODIC; 959 else 960 ret_val = DWC2_TRANSACTION_ALL; 961 962 if (hsotg->core_params->uframe_sched <= 0) 963 hsotg->non_periodic_channels++; 964 } 965 966 return ret_val; 967 } 968 969 /** 970 * dwc2_queue_transaction() - Attempts to queue a single transaction request for 971 * a host channel associated with either a periodic or non-periodic transfer 972 * 973 * @hsotg: The HCD state structure 974 * @chan: Host channel descriptor associated with either a periodic or 975 * non-periodic transfer 976 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO 977 * for periodic transfers or the non-periodic Tx FIFO 978 * for non-periodic transfers 979 * 980 * Return: 1 if a request is queued and more requests may be needed to 981 * complete the transfer, 0 if no more requests are required for this 982 * transfer, -1 if there is insufficient space in the Tx FIFO 983 * 984 * This function assumes that there is space available in the appropriate 985 * request queue. For an OUT transfer or SETUP transaction in Slave mode, 986 * it checks whether space is available in the appropriate Tx FIFO. 987 * 988 * Must be called with interrupt disabled and spinlock held 989 */ 990 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg, 991 struct dwc2_host_chan *chan, 992 u16 fifo_dwords_avail) 993 { 994 int retval = 0; 995 996 if (hsotg->core_params->dma_enable > 0) { 997 if (hsotg->core_params->dma_desc_enable > 0) { 998 if (!chan->xfer_started || 999 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1000 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh); 1001 chan->qh->ping_state = 0; 1002 } 1003 } else if (!chan->xfer_started) { 1004 dwc2_hc_start_transfer(hsotg, chan); 1005 chan->qh->ping_state = 0; 1006 } 1007 } else if (chan->halt_pending) { 1008 /* Don't queue a request if the channel has been halted */ 1009 } else if (chan->halt_on_queue) { 1010 dwc2_hc_halt(hsotg, chan, chan->halt_status); 1011 } else if (chan->do_ping) { 1012 if (!chan->xfer_started) 1013 dwc2_hc_start_transfer(hsotg, chan); 1014 } else if (!chan->ep_is_in || 1015 chan->data_pid_start == DWC2_HC_PID_SETUP) { 1016 if ((fifo_dwords_avail * 4) >= chan->max_packet) { 1017 if (!chan->xfer_started) { 1018 dwc2_hc_start_transfer(hsotg, chan); 1019 retval = 1; 1020 } else { 1021 retval = dwc2_hc_continue_transfer(hsotg, chan); 1022 } 1023 } else { 1024 retval = -1; 1025 } 1026 } else { 1027 if (!chan->xfer_started) { 1028 dwc2_hc_start_transfer(hsotg, chan); 1029 retval = 1; 1030 } else { 1031 retval = dwc2_hc_continue_transfer(hsotg, chan); 1032 } 1033 } 1034 1035 return retval; 1036 } 1037 1038 /* 1039 * Processes periodic channels for the next frame and queues transactions for 1040 * these channels to the DWC_otg controller. After queueing transactions, the 1041 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions 1042 * to queue as Periodic Tx FIFO or request queue space becomes available. 1043 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. 1044 * 1045 * Must be called with interrupt disabled and spinlock held 1046 */ 1047 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) 1048 { 1049 struct list_head *qh_ptr; 1050 struct dwc2_qh *qh; 1051 u32 tx_status; 1052 u32 fspcavail; 1053 u32 gintmsk; 1054 int status; 1055 int no_queue_space = 0; 1056 int no_fifo_space = 0; 1057 u32 qspcavail; 1058 1059 if (dbg_perio()) 1060 dev_vdbg(hsotg->dev, "Queue periodic transactions\n"); 1061 1062 tx_status = readl(hsotg->regs + HPTXSTS); 1063 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1064 TXSTS_QSPCAVAIL_SHIFT; 1065 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1066 TXSTS_FSPCAVAIL_SHIFT; 1067 1068 if (dbg_perio()) { 1069 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n", 1070 qspcavail); 1071 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n", 1072 fspcavail); 1073 } 1074 1075 qh_ptr = hsotg->periodic_sched_assigned.next; 1076 while (qh_ptr != &hsotg->periodic_sched_assigned) { 1077 tx_status = readl(hsotg->regs + HPTXSTS); 1078 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1079 TXSTS_QSPCAVAIL_SHIFT; 1080 if (qspcavail == 0) { 1081 no_queue_space = 1; 1082 break; 1083 } 1084 1085 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 1086 if (!qh->channel) { 1087 qh_ptr = qh_ptr->next; 1088 continue; 1089 } 1090 1091 /* Make sure EP's TT buffer is clean before queueing qtds */ 1092 if (qh->tt_buffer_dirty) { 1093 qh_ptr = qh_ptr->next; 1094 continue; 1095 } 1096 1097 /* 1098 * Set a flag if we're queuing high-bandwidth in slave mode. 1099 * The flag prevents any halts to get into the request queue in 1100 * the middle of multiple high-bandwidth packets getting queued. 1101 */ 1102 if (hsotg->core_params->dma_enable <= 0 && 1103 qh->channel->multi_count > 1) 1104 hsotg->queuing_high_bandwidth = 1; 1105 1106 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1107 TXSTS_FSPCAVAIL_SHIFT; 1108 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 1109 if (status < 0) { 1110 no_fifo_space = 1; 1111 break; 1112 } 1113 1114 /* 1115 * In Slave mode, stay on the current transfer until there is 1116 * nothing more to do or the high-bandwidth request count is 1117 * reached. In DMA mode, only need to queue one request. The 1118 * controller automatically handles multiple packets for 1119 * high-bandwidth transfers. 1120 */ 1121 if (hsotg->core_params->dma_enable > 0 || status == 0 || 1122 qh->channel->requests == qh->channel->multi_count) { 1123 qh_ptr = qh_ptr->next; 1124 /* 1125 * Move the QH from the periodic assigned schedule to 1126 * the periodic queued schedule 1127 */ 1128 list_move(&qh->qh_list_entry, 1129 &hsotg->periodic_sched_queued); 1130 1131 /* done queuing high bandwidth */ 1132 hsotg->queuing_high_bandwidth = 0; 1133 } 1134 } 1135 1136 if (hsotg->core_params->dma_enable <= 0) { 1137 tx_status = readl(hsotg->regs + HPTXSTS); 1138 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1139 TXSTS_QSPCAVAIL_SHIFT; 1140 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1141 TXSTS_FSPCAVAIL_SHIFT; 1142 if (dbg_perio()) { 1143 dev_vdbg(hsotg->dev, 1144 " P Tx Req Queue Space Avail (after queue): %d\n", 1145 qspcavail); 1146 dev_vdbg(hsotg->dev, 1147 " P Tx FIFO Space Avail (after queue): %d\n", 1148 fspcavail); 1149 } 1150 1151 if (!list_empty(&hsotg->periodic_sched_assigned) || 1152 no_queue_space || no_fifo_space) { 1153 /* 1154 * May need to queue more transactions as the request 1155 * queue or Tx FIFO empties. Enable the periodic Tx 1156 * FIFO empty interrupt. (Always use the half-empty 1157 * level to ensure that new requests are loaded as 1158 * soon as possible.) 1159 */ 1160 gintmsk = readl(hsotg->regs + GINTMSK); 1161 gintmsk |= GINTSTS_PTXFEMP; 1162 writel(gintmsk, hsotg->regs + GINTMSK); 1163 } else { 1164 /* 1165 * Disable the Tx FIFO empty interrupt since there are 1166 * no more transactions that need to be queued right 1167 * now. This function is called from interrupt 1168 * handlers to queue more transactions as transfer 1169 * states change. 1170 */ 1171 gintmsk = readl(hsotg->regs + GINTMSK); 1172 gintmsk &= ~GINTSTS_PTXFEMP; 1173 writel(gintmsk, hsotg->regs + GINTMSK); 1174 } 1175 } 1176 } 1177 1178 /* 1179 * Processes active non-periodic channels and queues transactions for these 1180 * channels to the DWC_otg controller. After queueing transactions, the NP Tx 1181 * FIFO Empty interrupt is enabled if there are more transactions to queue as 1182 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx 1183 * FIFO Empty interrupt is disabled. 1184 * 1185 * Must be called with interrupt disabled and spinlock held 1186 */ 1187 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg) 1188 { 1189 struct list_head *orig_qh_ptr; 1190 struct dwc2_qh *qh; 1191 u32 tx_status; 1192 u32 qspcavail; 1193 u32 fspcavail; 1194 u32 gintmsk; 1195 int status; 1196 int no_queue_space = 0; 1197 int no_fifo_space = 0; 1198 int more_to_do = 0; 1199 1200 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n"); 1201 1202 tx_status = readl(hsotg->regs + GNPTXSTS); 1203 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1204 TXSTS_QSPCAVAIL_SHIFT; 1205 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1206 TXSTS_FSPCAVAIL_SHIFT; 1207 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n", 1208 qspcavail); 1209 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n", 1210 fspcavail); 1211 1212 /* 1213 * Keep track of the starting point. Skip over the start-of-list 1214 * entry. 1215 */ 1216 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active) 1217 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 1218 orig_qh_ptr = hsotg->non_periodic_qh_ptr; 1219 1220 /* 1221 * Process once through the active list or until no more space is 1222 * available in the request queue or the Tx FIFO 1223 */ 1224 do { 1225 tx_status = readl(hsotg->regs + GNPTXSTS); 1226 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1227 TXSTS_QSPCAVAIL_SHIFT; 1228 if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) { 1229 no_queue_space = 1; 1230 break; 1231 } 1232 1233 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh, 1234 qh_list_entry); 1235 if (!qh->channel) 1236 goto next; 1237 1238 /* Make sure EP's TT buffer is clean before queueing qtds */ 1239 if (qh->tt_buffer_dirty) 1240 goto next; 1241 1242 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1243 TXSTS_FSPCAVAIL_SHIFT; 1244 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 1245 1246 if (status > 0) { 1247 more_to_do = 1; 1248 } else if (status < 0) { 1249 no_fifo_space = 1; 1250 break; 1251 } 1252 next: 1253 /* Advance to next QH, skipping start-of-list entry */ 1254 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 1255 if (hsotg->non_periodic_qh_ptr == 1256 &hsotg->non_periodic_sched_active) 1257 hsotg->non_periodic_qh_ptr = 1258 hsotg->non_periodic_qh_ptr->next; 1259 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr); 1260 1261 if (hsotg->core_params->dma_enable <= 0) { 1262 tx_status = readl(hsotg->regs + GNPTXSTS); 1263 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1264 TXSTS_QSPCAVAIL_SHIFT; 1265 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1266 TXSTS_FSPCAVAIL_SHIFT; 1267 dev_vdbg(hsotg->dev, 1268 " NP Tx Req Queue Space Avail (after queue): %d\n", 1269 qspcavail); 1270 dev_vdbg(hsotg->dev, 1271 " NP Tx FIFO Space Avail (after queue): %d\n", 1272 fspcavail); 1273 1274 if (more_to_do || no_queue_space || no_fifo_space) { 1275 /* 1276 * May need to queue more transactions as the request 1277 * queue or Tx FIFO empties. Enable the non-periodic 1278 * Tx FIFO empty interrupt. (Always use the half-empty 1279 * level to ensure that new requests are loaded as 1280 * soon as possible.) 1281 */ 1282 gintmsk = readl(hsotg->regs + GINTMSK); 1283 gintmsk |= GINTSTS_NPTXFEMP; 1284 writel(gintmsk, hsotg->regs + GINTMSK); 1285 } else { 1286 /* 1287 * Disable the Tx FIFO empty interrupt since there are 1288 * no more transactions that need to be queued right 1289 * now. This function is called from interrupt 1290 * handlers to queue more transactions as transfer 1291 * states change. 1292 */ 1293 gintmsk = readl(hsotg->regs + GINTMSK); 1294 gintmsk &= ~GINTSTS_NPTXFEMP; 1295 writel(gintmsk, hsotg->regs + GINTMSK); 1296 } 1297 } 1298 } 1299 1300 /** 1301 * dwc2_hcd_queue_transactions() - Processes the currently active host channels 1302 * and queues transactions for these channels to the DWC_otg controller. Called 1303 * from the HCD interrupt handler functions. 1304 * 1305 * @hsotg: The HCD state structure 1306 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic, 1307 * or both) 1308 * 1309 * Must be called with interrupt disabled and spinlock held 1310 */ 1311 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 1312 enum dwc2_transaction_type tr_type) 1313 { 1314 #ifdef DWC2_DEBUG_SOF 1315 dev_vdbg(hsotg->dev, "Queue Transactions\n"); 1316 #endif 1317 /* Process host channels associated with periodic transfers */ 1318 if ((tr_type == DWC2_TRANSACTION_PERIODIC || 1319 tr_type == DWC2_TRANSACTION_ALL) && 1320 !list_empty(&hsotg->periodic_sched_assigned)) 1321 dwc2_process_periodic_channels(hsotg); 1322 1323 /* Process host channels associated with non-periodic transfers */ 1324 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC || 1325 tr_type == DWC2_TRANSACTION_ALL) { 1326 if (!list_empty(&hsotg->non_periodic_sched_active)) { 1327 dwc2_process_non_periodic_channels(hsotg); 1328 } else { 1329 /* 1330 * Ensure NP Tx FIFO empty interrupt is disabled when 1331 * there are no non-periodic transfers to process 1332 */ 1333 u32 gintmsk = readl(hsotg->regs + GINTMSK); 1334 1335 gintmsk &= ~GINTSTS_NPTXFEMP; 1336 writel(gintmsk, hsotg->regs + GINTMSK); 1337 } 1338 } 1339 } 1340 1341 static void dwc2_conn_id_status_change(struct work_struct *work) 1342 { 1343 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 1344 wf_otg); 1345 u32 count = 0; 1346 u32 gotgctl; 1347 1348 dev_dbg(hsotg->dev, "%s()\n", __func__); 1349 1350 gotgctl = readl(hsotg->regs + GOTGCTL); 1351 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl); 1352 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n", 1353 !!(gotgctl & GOTGCTL_CONID_B)); 1354 1355 /* B-Device connector (Device Mode) */ 1356 if (gotgctl & GOTGCTL_CONID_B) { 1357 /* Wait for switch to device mode */ 1358 dev_dbg(hsotg->dev, "connId B\n"); 1359 while (!dwc2_is_device_mode(hsotg)) { 1360 dev_info(hsotg->dev, 1361 "Waiting for Peripheral Mode, Mode=%s\n", 1362 dwc2_is_host_mode(hsotg) ? "Host" : 1363 "Peripheral"); 1364 usleep_range(20000, 40000); 1365 if (++count > 250) 1366 break; 1367 } 1368 if (count > 250) 1369 dev_err(hsotg->dev, 1370 "Connection id status change timed out\n"); 1371 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 1372 dwc2_core_init(hsotg, false, -1); 1373 dwc2_enable_global_interrupts(hsotg); 1374 s3c_hsotg_core_init_disconnected(hsotg); 1375 s3c_hsotg_core_connect(hsotg); 1376 } else { 1377 /* A-Device connector (Host Mode) */ 1378 dev_dbg(hsotg->dev, "connId A\n"); 1379 while (!dwc2_is_host_mode(hsotg)) { 1380 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n", 1381 dwc2_is_host_mode(hsotg) ? 1382 "Host" : "Peripheral"); 1383 usleep_range(20000, 40000); 1384 if (++count > 250) 1385 break; 1386 } 1387 if (count > 250) 1388 dev_err(hsotg->dev, 1389 "Connection id status change timed out\n"); 1390 hsotg->op_state = OTG_STATE_A_HOST; 1391 1392 /* Initialize the Core for Host mode */ 1393 dwc2_core_init(hsotg, false, -1); 1394 dwc2_enable_global_interrupts(hsotg); 1395 dwc2_hcd_start(hsotg); 1396 } 1397 } 1398 1399 static void dwc2_wakeup_detected(unsigned long data) 1400 { 1401 struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data; 1402 u32 hprt0; 1403 1404 dev_dbg(hsotg->dev, "%s()\n", __func__); 1405 1406 /* 1407 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms 1408 * so that OPT tests pass with all PHYs.) 1409 */ 1410 hprt0 = dwc2_read_hprt0(hsotg); 1411 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0); 1412 hprt0 &= ~HPRT0_RES; 1413 writel(hprt0, hsotg->regs + HPRT0); 1414 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n", 1415 readl(hsotg->regs + HPRT0)); 1416 1417 dwc2_hcd_rem_wakeup(hsotg); 1418 1419 /* Change to L0 state */ 1420 hsotg->lx_state = DWC2_L0; 1421 } 1422 1423 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg) 1424 { 1425 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 1426 1427 return hcd->self.b_hnp_enable; 1428 } 1429 1430 /* Must NOT be called with interrupt disabled or spinlock held */ 1431 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) 1432 { 1433 unsigned long flags; 1434 u32 hprt0; 1435 u32 pcgctl; 1436 u32 gotgctl; 1437 1438 dev_dbg(hsotg->dev, "%s()\n", __func__); 1439 1440 spin_lock_irqsave(&hsotg->lock, flags); 1441 1442 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) { 1443 gotgctl = readl(hsotg->regs + GOTGCTL); 1444 gotgctl |= GOTGCTL_HSTSETHNPEN; 1445 writel(gotgctl, hsotg->regs + GOTGCTL); 1446 hsotg->op_state = OTG_STATE_A_SUSPEND; 1447 } 1448 1449 hprt0 = dwc2_read_hprt0(hsotg); 1450 hprt0 |= HPRT0_SUSP; 1451 writel(hprt0, hsotg->regs + HPRT0); 1452 1453 /* Update lx_state */ 1454 hsotg->lx_state = DWC2_L2; 1455 1456 /* Suspend the Phy Clock */ 1457 pcgctl = readl(hsotg->regs + PCGCTL); 1458 pcgctl |= PCGCTL_STOPPCLK; 1459 writel(pcgctl, hsotg->regs + PCGCTL); 1460 udelay(10); 1461 1462 /* For HNP the bus must be suspended for at least 200ms */ 1463 if (dwc2_host_is_b_hnp_enabled(hsotg)) { 1464 pcgctl = readl(hsotg->regs + PCGCTL); 1465 pcgctl &= ~PCGCTL_STOPPCLK; 1466 writel(pcgctl, hsotg->regs + PCGCTL); 1467 1468 spin_unlock_irqrestore(&hsotg->lock, flags); 1469 1470 usleep_range(200000, 250000); 1471 } else { 1472 spin_unlock_irqrestore(&hsotg->lock, flags); 1473 } 1474 } 1475 1476 static void dwc2_port_resume(struct dwc2_hsotg *hsotg) 1477 { 1478 u32 hprt0; 1479 1480 /* After clear the Stop PHY clock bit, we should wait for a moment 1481 * for PLL work stable with clock output. 1482 */ 1483 writel(0, hsotg->regs + PCGCTL); 1484 usleep_range(2000, 4000); 1485 1486 hprt0 = dwc2_read_hprt0(hsotg); 1487 hprt0 |= HPRT0_RES; 1488 writel(hprt0, hsotg->regs + HPRT0); 1489 hprt0 &= ~HPRT0_SUSP; 1490 /* according to USB2.0 Spec 7.1.7.7, the host must send the resume 1491 * signal for at least 20ms 1492 */ 1493 usleep_range(20000, 25000); 1494 1495 hprt0 &= ~HPRT0_RES; 1496 writel(hprt0, hsotg->regs + HPRT0); 1497 hsotg->lx_state = DWC2_L0; 1498 } 1499 1500 /* Handles hub class-specific requests */ 1501 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, 1502 u16 wvalue, u16 windex, char *buf, u16 wlength) 1503 { 1504 struct usb_hub_descriptor *hub_desc; 1505 int retval = 0; 1506 u32 hprt0; 1507 u32 port_status; 1508 u32 speed; 1509 u32 pcgctl; 1510 1511 switch (typereq) { 1512 case ClearHubFeature: 1513 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue); 1514 1515 switch (wvalue) { 1516 case C_HUB_LOCAL_POWER: 1517 case C_HUB_OVER_CURRENT: 1518 /* Nothing required here */ 1519 break; 1520 1521 default: 1522 retval = -EINVAL; 1523 dev_err(hsotg->dev, 1524 "ClearHubFeature request %1xh unknown\n", 1525 wvalue); 1526 } 1527 break; 1528 1529 case ClearPortFeature: 1530 if (wvalue != USB_PORT_FEAT_L1) 1531 if (!windex || windex > 1) 1532 goto error; 1533 switch (wvalue) { 1534 case USB_PORT_FEAT_ENABLE: 1535 dev_dbg(hsotg->dev, 1536 "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); 1537 hprt0 = dwc2_read_hprt0(hsotg); 1538 hprt0 |= HPRT0_ENA; 1539 writel(hprt0, hsotg->regs + HPRT0); 1540 break; 1541 1542 case USB_PORT_FEAT_SUSPEND: 1543 dev_dbg(hsotg->dev, 1544 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); 1545 dwc2_port_resume(hsotg); 1546 break; 1547 1548 case USB_PORT_FEAT_POWER: 1549 dev_dbg(hsotg->dev, 1550 "ClearPortFeature USB_PORT_FEAT_POWER\n"); 1551 hprt0 = dwc2_read_hprt0(hsotg); 1552 hprt0 &= ~HPRT0_PWR; 1553 writel(hprt0, hsotg->regs + HPRT0); 1554 break; 1555 1556 case USB_PORT_FEAT_INDICATOR: 1557 dev_dbg(hsotg->dev, 1558 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); 1559 /* Port indicator not supported */ 1560 break; 1561 1562 case USB_PORT_FEAT_C_CONNECTION: 1563 /* 1564 * Clears driver's internal Connect Status Change flag 1565 */ 1566 dev_dbg(hsotg->dev, 1567 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); 1568 hsotg->flags.b.port_connect_status_change = 0; 1569 break; 1570 1571 case USB_PORT_FEAT_C_RESET: 1572 /* Clears driver's internal Port Reset Change flag */ 1573 dev_dbg(hsotg->dev, 1574 "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); 1575 hsotg->flags.b.port_reset_change = 0; 1576 break; 1577 1578 case USB_PORT_FEAT_C_ENABLE: 1579 /* 1580 * Clears the driver's internal Port Enable/Disable 1581 * Change flag 1582 */ 1583 dev_dbg(hsotg->dev, 1584 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); 1585 hsotg->flags.b.port_enable_change = 0; 1586 break; 1587 1588 case USB_PORT_FEAT_C_SUSPEND: 1589 /* 1590 * Clears the driver's internal Port Suspend Change 1591 * flag, which is set when resume signaling on the host 1592 * port is complete 1593 */ 1594 dev_dbg(hsotg->dev, 1595 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); 1596 hsotg->flags.b.port_suspend_change = 0; 1597 break; 1598 1599 case USB_PORT_FEAT_C_PORT_L1: 1600 dev_dbg(hsotg->dev, 1601 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n"); 1602 hsotg->flags.b.port_l1_change = 0; 1603 break; 1604 1605 case USB_PORT_FEAT_C_OVER_CURRENT: 1606 dev_dbg(hsotg->dev, 1607 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); 1608 hsotg->flags.b.port_over_current_change = 0; 1609 break; 1610 1611 default: 1612 retval = -EINVAL; 1613 dev_err(hsotg->dev, 1614 "ClearPortFeature request %1xh unknown or unsupported\n", 1615 wvalue); 1616 } 1617 break; 1618 1619 case GetHubDescriptor: 1620 dev_dbg(hsotg->dev, "GetHubDescriptor\n"); 1621 hub_desc = (struct usb_hub_descriptor *)buf; 1622 hub_desc->bDescLength = 9; 1623 hub_desc->bDescriptorType = 0x29; 1624 hub_desc->bNbrPorts = 1; 1625 hub_desc->wHubCharacteristics = cpu_to_le16(0x08); 1626 hub_desc->bPwrOn2PwrGood = 1; 1627 hub_desc->bHubContrCurrent = 0; 1628 hub_desc->u.hs.DeviceRemovable[0] = 0; 1629 hub_desc->u.hs.DeviceRemovable[1] = 0xff; 1630 break; 1631 1632 case GetHubStatus: 1633 dev_dbg(hsotg->dev, "GetHubStatus\n"); 1634 memset(buf, 0, 4); 1635 break; 1636 1637 case GetPortStatus: 1638 dev_vdbg(hsotg->dev, 1639 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex, 1640 hsotg->flags.d32); 1641 if (!windex || windex > 1) 1642 goto error; 1643 1644 port_status = 0; 1645 if (hsotg->flags.b.port_connect_status_change) 1646 port_status |= USB_PORT_STAT_C_CONNECTION << 16; 1647 if (hsotg->flags.b.port_enable_change) 1648 port_status |= USB_PORT_STAT_C_ENABLE << 16; 1649 if (hsotg->flags.b.port_suspend_change) 1650 port_status |= USB_PORT_STAT_C_SUSPEND << 16; 1651 if (hsotg->flags.b.port_l1_change) 1652 port_status |= USB_PORT_STAT_C_L1 << 16; 1653 if (hsotg->flags.b.port_reset_change) 1654 port_status |= USB_PORT_STAT_C_RESET << 16; 1655 if (hsotg->flags.b.port_over_current_change) { 1656 dev_warn(hsotg->dev, "Overcurrent change detected\n"); 1657 port_status |= USB_PORT_STAT_C_OVERCURRENT << 16; 1658 } 1659 1660 if (!hsotg->flags.b.port_connect_status) { 1661 /* 1662 * The port is disconnected, which means the core is 1663 * either in device mode or it soon will be. Just 1664 * return 0's for the remainder of the port status 1665 * since the port register can't be read if the core 1666 * is in device mode. 1667 */ 1668 *(__le32 *)buf = cpu_to_le32(port_status); 1669 break; 1670 } 1671 1672 hprt0 = readl(hsotg->regs + HPRT0); 1673 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0); 1674 1675 if (hprt0 & HPRT0_CONNSTS) 1676 port_status |= USB_PORT_STAT_CONNECTION; 1677 if (hprt0 & HPRT0_ENA) 1678 port_status |= USB_PORT_STAT_ENABLE; 1679 if (hprt0 & HPRT0_SUSP) 1680 port_status |= USB_PORT_STAT_SUSPEND; 1681 if (hprt0 & HPRT0_OVRCURRACT) 1682 port_status |= USB_PORT_STAT_OVERCURRENT; 1683 if (hprt0 & HPRT0_RST) 1684 port_status |= USB_PORT_STAT_RESET; 1685 if (hprt0 & HPRT0_PWR) 1686 port_status |= USB_PORT_STAT_POWER; 1687 1688 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 1689 if (speed == HPRT0_SPD_HIGH_SPEED) 1690 port_status |= USB_PORT_STAT_HIGH_SPEED; 1691 else if (speed == HPRT0_SPD_LOW_SPEED) 1692 port_status |= USB_PORT_STAT_LOW_SPEED; 1693 1694 if (hprt0 & HPRT0_TSTCTL_MASK) 1695 port_status |= USB_PORT_STAT_TEST; 1696 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ 1697 1698 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status); 1699 *(__le32 *)buf = cpu_to_le32(port_status); 1700 break; 1701 1702 case SetHubFeature: 1703 dev_dbg(hsotg->dev, "SetHubFeature\n"); 1704 /* No HUB features supported */ 1705 break; 1706 1707 case SetPortFeature: 1708 dev_dbg(hsotg->dev, "SetPortFeature\n"); 1709 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1)) 1710 goto error; 1711 1712 if (!hsotg->flags.b.port_connect_status) { 1713 /* 1714 * The port is disconnected, which means the core is 1715 * either in device mode or it soon will be. Just 1716 * return without doing anything since the port 1717 * register can't be written if the core is in device 1718 * mode. 1719 */ 1720 break; 1721 } 1722 1723 switch (wvalue) { 1724 case USB_PORT_FEAT_SUSPEND: 1725 dev_dbg(hsotg->dev, 1726 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); 1727 if (windex != hsotg->otg_port) 1728 goto error; 1729 dwc2_port_suspend(hsotg, windex); 1730 break; 1731 1732 case USB_PORT_FEAT_POWER: 1733 dev_dbg(hsotg->dev, 1734 "SetPortFeature - USB_PORT_FEAT_POWER\n"); 1735 hprt0 = dwc2_read_hprt0(hsotg); 1736 hprt0 |= HPRT0_PWR; 1737 writel(hprt0, hsotg->regs + HPRT0); 1738 break; 1739 1740 case USB_PORT_FEAT_RESET: 1741 hprt0 = dwc2_read_hprt0(hsotg); 1742 dev_dbg(hsotg->dev, 1743 "SetPortFeature - USB_PORT_FEAT_RESET\n"); 1744 pcgctl = readl(hsotg->regs + PCGCTL); 1745 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK); 1746 writel(pcgctl, hsotg->regs + PCGCTL); 1747 /* ??? Original driver does this */ 1748 writel(0, hsotg->regs + PCGCTL); 1749 1750 hprt0 = dwc2_read_hprt0(hsotg); 1751 /* Clear suspend bit if resetting from suspend state */ 1752 hprt0 &= ~HPRT0_SUSP; 1753 1754 /* 1755 * When B-Host the Port reset bit is set in the Start 1756 * HCD Callback function, so that the reset is started 1757 * within 1ms of the HNP success interrupt 1758 */ 1759 if (!dwc2_hcd_is_b_host(hsotg)) { 1760 hprt0 |= HPRT0_PWR | HPRT0_RST; 1761 dev_dbg(hsotg->dev, 1762 "In host mode, hprt0=%08x\n", hprt0); 1763 writel(hprt0, hsotg->regs + HPRT0); 1764 } 1765 1766 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ 1767 usleep_range(50000, 70000); 1768 hprt0 &= ~HPRT0_RST; 1769 writel(hprt0, hsotg->regs + HPRT0); 1770 hsotg->lx_state = DWC2_L0; /* Now back to On state */ 1771 break; 1772 1773 case USB_PORT_FEAT_INDICATOR: 1774 dev_dbg(hsotg->dev, 1775 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); 1776 /* Not supported */ 1777 break; 1778 1779 default: 1780 retval = -EINVAL; 1781 dev_err(hsotg->dev, 1782 "SetPortFeature %1xh unknown or unsupported\n", 1783 wvalue); 1784 break; 1785 } 1786 break; 1787 1788 default: 1789 error: 1790 retval = -EINVAL; 1791 dev_dbg(hsotg->dev, 1792 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n", 1793 typereq, windex, wvalue); 1794 break; 1795 } 1796 1797 return retval; 1798 } 1799 1800 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port) 1801 { 1802 int retval; 1803 1804 if (port != 1) 1805 return -EINVAL; 1806 1807 retval = (hsotg->flags.b.port_connect_status_change || 1808 hsotg->flags.b.port_reset_change || 1809 hsotg->flags.b.port_enable_change || 1810 hsotg->flags.b.port_suspend_change || 1811 hsotg->flags.b.port_over_current_change); 1812 1813 if (retval) { 1814 dev_dbg(hsotg->dev, 1815 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n"); 1816 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n", 1817 hsotg->flags.b.port_connect_status_change); 1818 dev_dbg(hsotg->dev, " port_reset_change: %d\n", 1819 hsotg->flags.b.port_reset_change); 1820 dev_dbg(hsotg->dev, " port_enable_change: %d\n", 1821 hsotg->flags.b.port_enable_change); 1822 dev_dbg(hsotg->dev, " port_suspend_change: %d\n", 1823 hsotg->flags.b.port_suspend_change); 1824 dev_dbg(hsotg->dev, " port_over_current_change: %d\n", 1825 hsotg->flags.b.port_over_current_change); 1826 } 1827 1828 return retval; 1829 } 1830 1831 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1832 { 1833 u32 hfnum = readl(hsotg->regs + HFNUM); 1834 1835 #ifdef DWC2_DEBUG_SOF 1836 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n", 1837 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT); 1838 #endif 1839 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 1840 } 1841 1842 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg) 1843 { 1844 return hsotg->op_state == OTG_STATE_B_HOST; 1845 } 1846 1847 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg, 1848 int iso_desc_count, 1849 gfp_t mem_flags) 1850 { 1851 struct dwc2_hcd_urb *urb; 1852 u32 size = sizeof(*urb) + iso_desc_count * 1853 sizeof(struct dwc2_hcd_iso_packet_desc); 1854 1855 urb = kzalloc(size, mem_flags); 1856 if (urb) 1857 urb->packet_count = iso_desc_count; 1858 return urb; 1859 } 1860 1861 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg, 1862 struct dwc2_hcd_urb *urb, u8 dev_addr, 1863 u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps) 1864 { 1865 if (dbg_perio() || 1866 ep_type == USB_ENDPOINT_XFER_BULK || 1867 ep_type == USB_ENDPOINT_XFER_CONTROL) 1868 dev_vdbg(hsotg->dev, 1869 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n", 1870 dev_addr, ep_num, ep_dir, ep_type, mps); 1871 urb->pipe_info.dev_addr = dev_addr; 1872 urb->pipe_info.ep_num = ep_num; 1873 urb->pipe_info.pipe_type = ep_type; 1874 urb->pipe_info.pipe_dir = ep_dir; 1875 urb->pipe_info.mps = mps; 1876 } 1877 1878 /* 1879 * NOTE: This function will be removed once the peripheral controller code 1880 * is integrated and the driver is stable 1881 */ 1882 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg) 1883 { 1884 #ifdef DEBUG 1885 struct dwc2_host_chan *chan; 1886 struct dwc2_hcd_urb *urb; 1887 struct dwc2_qtd *qtd; 1888 int num_channels; 1889 u32 np_tx_status; 1890 u32 p_tx_status; 1891 int i; 1892 1893 num_channels = hsotg->core_params->host_channels; 1894 dev_dbg(hsotg->dev, "\n"); 1895 dev_dbg(hsotg->dev, 1896 "************************************************************\n"); 1897 dev_dbg(hsotg->dev, "HCD State:\n"); 1898 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels); 1899 1900 for (i = 0; i < num_channels; i++) { 1901 chan = hsotg->hc_ptr_array[i]; 1902 dev_dbg(hsotg->dev, " Channel %d:\n", i); 1903 dev_dbg(hsotg->dev, 1904 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 1905 chan->dev_addr, chan->ep_num, chan->ep_is_in); 1906 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed); 1907 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 1908 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 1909 dev_dbg(hsotg->dev, " data_pid_start: %d\n", 1910 chan->data_pid_start); 1911 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count); 1912 dev_dbg(hsotg->dev, " xfer_started: %d\n", 1913 chan->xfer_started); 1914 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 1915 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 1916 (unsigned long)chan->xfer_dma); 1917 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 1918 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count); 1919 dev_dbg(hsotg->dev, " halt_on_queue: %d\n", 1920 chan->halt_on_queue); 1921 dev_dbg(hsotg->dev, " halt_pending: %d\n", 1922 chan->halt_pending); 1923 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 1924 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split); 1925 dev_dbg(hsotg->dev, " complete_split: %d\n", 1926 chan->complete_split); 1927 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr); 1928 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port); 1929 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos); 1930 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests); 1931 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 1932 1933 if (chan->xfer_started) { 1934 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk; 1935 1936 hfnum = readl(hsotg->regs + HFNUM); 1937 hcchar = readl(hsotg->regs + HCCHAR(i)); 1938 hctsiz = readl(hsotg->regs + HCTSIZ(i)); 1939 hcint = readl(hsotg->regs + HCINT(i)); 1940 hcintmsk = readl(hsotg->regs + HCINTMSK(i)); 1941 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum); 1942 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar); 1943 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz); 1944 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint); 1945 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk); 1946 } 1947 1948 if (!(chan->xfer_started && chan->qh)) 1949 continue; 1950 1951 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) { 1952 if (!qtd->in_process) 1953 break; 1954 urb = qtd->urb; 1955 dev_dbg(hsotg->dev, " URB Info:\n"); 1956 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n", 1957 qtd, urb); 1958 if (urb) { 1959 dev_dbg(hsotg->dev, 1960 " Dev: %d, EP: %d %s\n", 1961 dwc2_hcd_get_dev_addr(&urb->pipe_info), 1962 dwc2_hcd_get_ep_num(&urb->pipe_info), 1963 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 1964 "IN" : "OUT"); 1965 dev_dbg(hsotg->dev, 1966 " Max packet size: %d\n", 1967 dwc2_hcd_get_mps(&urb->pipe_info)); 1968 dev_dbg(hsotg->dev, 1969 " transfer_buffer: %p\n", 1970 urb->buf); 1971 dev_dbg(hsotg->dev, 1972 " transfer_dma: %08lx\n", 1973 (unsigned long)urb->dma); 1974 dev_dbg(hsotg->dev, 1975 " transfer_buffer_length: %d\n", 1976 urb->length); 1977 dev_dbg(hsotg->dev, " actual_length: %d\n", 1978 urb->actual_length); 1979 } 1980 } 1981 } 1982 1983 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n", 1984 hsotg->non_periodic_channels); 1985 dev_dbg(hsotg->dev, " periodic_channels: %d\n", 1986 hsotg->periodic_channels); 1987 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs); 1988 np_tx_status = readl(hsotg->regs + GNPTXSTS); 1989 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n", 1990 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 1991 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n", 1992 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 1993 p_tx_status = readl(hsotg->regs + HPTXSTS); 1994 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n", 1995 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 1996 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n", 1997 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 1998 dwc2_hcd_dump_frrem(hsotg); 1999 dwc2_dump_global_registers(hsotg); 2000 dwc2_dump_host_registers(hsotg); 2001 dev_dbg(hsotg->dev, 2002 "************************************************************\n"); 2003 dev_dbg(hsotg->dev, "\n"); 2004 #endif 2005 } 2006 2007 /* 2008 * NOTE: This function will be removed once the peripheral controller code 2009 * is integrated and the driver is stable 2010 */ 2011 void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg) 2012 { 2013 #ifdef DWC2_DUMP_FRREM 2014 dev_dbg(hsotg->dev, "Frame remaining at SOF:\n"); 2015 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2016 hsotg->frrem_samples, hsotg->frrem_accum, 2017 hsotg->frrem_samples > 0 ? 2018 hsotg->frrem_accum / hsotg->frrem_samples : 0); 2019 dev_dbg(hsotg->dev, "\n"); 2020 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n"); 2021 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2022 hsotg->hfnum_7_samples, 2023 hsotg->hfnum_7_frrem_accum, 2024 hsotg->hfnum_7_samples > 0 ? 2025 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0); 2026 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n"); 2027 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2028 hsotg->hfnum_0_samples, 2029 hsotg->hfnum_0_frrem_accum, 2030 hsotg->hfnum_0_samples > 0 ? 2031 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0); 2032 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n"); 2033 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2034 hsotg->hfnum_other_samples, 2035 hsotg->hfnum_other_frrem_accum, 2036 hsotg->hfnum_other_samples > 0 ? 2037 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples : 2038 0); 2039 dev_dbg(hsotg->dev, "\n"); 2040 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n"); 2041 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2042 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a, 2043 hsotg->hfnum_7_samples_a > 0 ? 2044 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0); 2045 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n"); 2046 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2047 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a, 2048 hsotg->hfnum_0_samples_a > 0 ? 2049 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0); 2050 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n"); 2051 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2052 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a, 2053 hsotg->hfnum_other_samples_a > 0 ? 2054 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a 2055 : 0); 2056 dev_dbg(hsotg->dev, "\n"); 2057 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n"); 2058 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2059 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b, 2060 hsotg->hfnum_7_samples_b > 0 ? 2061 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0); 2062 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n"); 2063 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2064 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b, 2065 (hsotg->hfnum_0_samples_b > 0) ? 2066 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0); 2067 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n"); 2068 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2069 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b, 2070 (hsotg->hfnum_other_samples_b > 0) ? 2071 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b 2072 : 0); 2073 #endif 2074 } 2075 2076 struct wrapper_priv_data { 2077 struct dwc2_hsotg *hsotg; 2078 }; 2079 2080 /* Gets the dwc2_hsotg from a usb_hcd */ 2081 static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd) 2082 { 2083 struct wrapper_priv_data *p; 2084 2085 p = (struct wrapper_priv_data *) &hcd->hcd_priv; 2086 return p->hsotg; 2087 } 2088 2089 static int _dwc2_hcd_start(struct usb_hcd *hcd); 2090 2091 void dwc2_host_start(struct dwc2_hsotg *hsotg) 2092 { 2093 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 2094 2095 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg); 2096 _dwc2_hcd_start(hcd); 2097 } 2098 2099 void dwc2_host_disconnect(struct dwc2_hsotg *hsotg) 2100 { 2101 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 2102 2103 hcd->self.is_b_host = 0; 2104 } 2105 2106 void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr, 2107 int *hub_port) 2108 { 2109 struct urb *urb = context; 2110 2111 if (urb->dev->tt) 2112 *hub_addr = urb->dev->tt->hub->devnum; 2113 else 2114 *hub_addr = 0; 2115 *hub_port = urb->dev->ttport; 2116 } 2117 2118 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context) 2119 { 2120 struct urb *urb = context; 2121 2122 return urb->dev->speed; 2123 } 2124 2125 static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw, 2126 struct urb *urb) 2127 { 2128 struct usb_bus *bus = hcd_to_bus(hcd); 2129 2130 if (urb->interval) 2131 bus->bandwidth_allocated += bw / urb->interval; 2132 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 2133 bus->bandwidth_isoc_reqs++; 2134 else 2135 bus->bandwidth_int_reqs++; 2136 } 2137 2138 static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw, 2139 struct urb *urb) 2140 { 2141 struct usb_bus *bus = hcd_to_bus(hcd); 2142 2143 if (urb->interval) 2144 bus->bandwidth_allocated -= bw / urb->interval; 2145 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 2146 bus->bandwidth_isoc_reqs--; 2147 else 2148 bus->bandwidth_int_reqs--; 2149 } 2150 2151 /* 2152 * Sets the final status of an URB and returns it to the upper layer. Any 2153 * required cleanup of the URB is performed. 2154 * 2155 * Must be called with interrupt disabled and spinlock held 2156 */ 2157 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 2158 int status) 2159 { 2160 struct urb *urb; 2161 int i; 2162 2163 if (!qtd) { 2164 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__); 2165 return; 2166 } 2167 2168 if (!qtd->urb) { 2169 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__); 2170 return; 2171 } 2172 2173 urb = qtd->urb->priv; 2174 if (!urb) { 2175 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__); 2176 return; 2177 } 2178 2179 urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb); 2180 2181 if (dbg_urb(urb)) 2182 dev_vdbg(hsotg->dev, 2183 "%s: urb %p device %d ep %d-%s status %d actual %d\n", 2184 __func__, urb, usb_pipedevice(urb->pipe), 2185 usb_pipeendpoint(urb->pipe), 2186 usb_pipein(urb->pipe) ? "IN" : "OUT", status, 2187 urb->actual_length); 2188 2189 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) { 2190 for (i = 0; i < urb->number_of_packets; i++) 2191 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n", 2192 i, urb->iso_frame_desc[i].status); 2193 } 2194 2195 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 2196 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb); 2197 for (i = 0; i < urb->number_of_packets; ++i) { 2198 urb->iso_frame_desc[i].actual_length = 2199 dwc2_hcd_urb_get_iso_desc_actual_length( 2200 qtd->urb, i); 2201 urb->iso_frame_desc[i].status = 2202 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i); 2203 } 2204 } 2205 2206 urb->status = status; 2207 if (!status) { 2208 if ((urb->transfer_flags & URB_SHORT_NOT_OK) && 2209 urb->actual_length < urb->transfer_buffer_length) 2210 urb->status = -EREMOTEIO; 2211 } 2212 2213 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || 2214 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { 2215 struct usb_host_endpoint *ep = urb->ep; 2216 2217 if (ep) 2218 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg), 2219 dwc2_hcd_get_ep_bandwidth(hsotg, ep), 2220 urb); 2221 } 2222 2223 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb); 2224 urb->hcpriv = NULL; 2225 kfree(qtd->urb); 2226 qtd->urb = NULL; 2227 2228 spin_unlock(&hsotg->lock); 2229 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status); 2230 spin_lock(&hsotg->lock); 2231 } 2232 2233 /* 2234 * Work queue function for starting the HCD when A-Cable is connected 2235 */ 2236 static void dwc2_hcd_start_func(struct work_struct *work) 2237 { 2238 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 2239 start_work.work); 2240 2241 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg); 2242 dwc2_host_start(hsotg); 2243 } 2244 2245 /* 2246 * Reset work queue function 2247 */ 2248 static void dwc2_hcd_reset_func(struct work_struct *work) 2249 { 2250 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 2251 reset_work.work); 2252 u32 hprt0; 2253 2254 dev_dbg(hsotg->dev, "USB RESET function called\n"); 2255 hprt0 = dwc2_read_hprt0(hsotg); 2256 hprt0 &= ~HPRT0_RST; 2257 writel(hprt0, hsotg->regs + HPRT0); 2258 hsotg->flags.b.port_reset_change = 1; 2259 } 2260 2261 /* 2262 * ========================================================================= 2263 * Linux HC Driver Functions 2264 * ========================================================================= 2265 */ 2266 2267 /* 2268 * Initializes the DWC_otg controller and its root hub and prepares it for host 2269 * mode operation. Activates the root port. Returns 0 on success and a negative 2270 * error code on failure. 2271 */ 2272 static int _dwc2_hcd_start(struct usb_hcd *hcd) 2273 { 2274 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2275 struct usb_bus *bus = hcd_to_bus(hcd); 2276 unsigned long flags; 2277 2278 dev_dbg(hsotg->dev, "DWC OTG HCD START\n"); 2279 2280 spin_lock_irqsave(&hsotg->lock, flags); 2281 2282 hcd->state = HC_STATE_RUNNING; 2283 2284 if (dwc2_is_device_mode(hsotg)) { 2285 spin_unlock_irqrestore(&hsotg->lock, flags); 2286 return 0; /* why 0 ?? */ 2287 } 2288 2289 dwc2_hcd_reinit(hsotg); 2290 2291 /* Initialize and connect root hub if one is not already attached */ 2292 if (bus->root_hub) { 2293 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n"); 2294 /* Inform the HUB driver to resume */ 2295 usb_hcd_resume_root_hub(hcd); 2296 } 2297 2298 spin_unlock_irqrestore(&hsotg->lock, flags); 2299 return 0; 2300 } 2301 2302 /* 2303 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are 2304 * stopped. 2305 */ 2306 static void _dwc2_hcd_stop(struct usb_hcd *hcd) 2307 { 2308 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2309 unsigned long flags; 2310 2311 spin_lock_irqsave(&hsotg->lock, flags); 2312 dwc2_hcd_stop(hsotg); 2313 spin_unlock_irqrestore(&hsotg->lock, flags); 2314 2315 usleep_range(1000, 3000); 2316 } 2317 2318 static int _dwc2_hcd_suspend(struct usb_hcd *hcd) 2319 { 2320 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2321 u32 hprt0; 2322 2323 if (!((hsotg->op_state == OTG_STATE_B_HOST) || 2324 (hsotg->op_state == OTG_STATE_A_HOST))) 2325 return 0; 2326 2327 /* TODO: We get into suspend from 'on' state, maybe we need to do 2328 * something if we get here from DWC2_L1(LPM sleep) state one day. 2329 */ 2330 if (hsotg->lx_state != DWC2_L0) 2331 return 0; 2332 2333 hprt0 = dwc2_read_hprt0(hsotg); 2334 if (hprt0 & HPRT0_CONNSTS) { 2335 dwc2_port_suspend(hsotg, 1); 2336 } else { 2337 u32 pcgctl = readl(hsotg->regs + PCGCTL); 2338 2339 pcgctl |= PCGCTL_STOPPCLK; 2340 writel(pcgctl, hsotg->regs + PCGCTL); 2341 } 2342 2343 return 0; 2344 } 2345 2346 static int _dwc2_hcd_resume(struct usb_hcd *hcd) 2347 { 2348 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2349 u32 hprt0; 2350 2351 if (!((hsotg->op_state == OTG_STATE_B_HOST) || 2352 (hsotg->op_state == OTG_STATE_A_HOST))) 2353 return 0; 2354 2355 if (hsotg->lx_state != DWC2_L2) 2356 return 0; 2357 2358 hprt0 = dwc2_read_hprt0(hsotg); 2359 if ((hprt0 & HPRT0_CONNSTS) && (hprt0 & HPRT0_SUSP)) 2360 dwc2_port_resume(hsotg); 2361 else 2362 writel(0, hsotg->regs + PCGCTL); 2363 2364 return 0; 2365 } 2366 2367 /* Returns the current frame number */ 2368 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd) 2369 { 2370 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2371 2372 return dwc2_hcd_get_frame_number(hsotg); 2373 } 2374 2375 static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb, 2376 char *fn_name) 2377 { 2378 #ifdef VERBOSE_DEBUG 2379 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2380 char *pipetype; 2381 char *speed; 2382 2383 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb); 2384 dev_vdbg(hsotg->dev, " Device address: %d\n", 2385 usb_pipedevice(urb->pipe)); 2386 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n", 2387 usb_pipeendpoint(urb->pipe), 2388 usb_pipein(urb->pipe) ? "IN" : "OUT"); 2389 2390 switch (usb_pipetype(urb->pipe)) { 2391 case PIPE_CONTROL: 2392 pipetype = "CONTROL"; 2393 break; 2394 case PIPE_BULK: 2395 pipetype = "BULK"; 2396 break; 2397 case PIPE_INTERRUPT: 2398 pipetype = "INTERRUPT"; 2399 break; 2400 case PIPE_ISOCHRONOUS: 2401 pipetype = "ISOCHRONOUS"; 2402 break; 2403 default: 2404 pipetype = "UNKNOWN"; 2405 break; 2406 } 2407 2408 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype, 2409 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ? 2410 "IN" : "OUT"); 2411 2412 switch (urb->dev->speed) { 2413 case USB_SPEED_HIGH: 2414 speed = "HIGH"; 2415 break; 2416 case USB_SPEED_FULL: 2417 speed = "FULL"; 2418 break; 2419 case USB_SPEED_LOW: 2420 speed = "LOW"; 2421 break; 2422 default: 2423 speed = "UNKNOWN"; 2424 break; 2425 } 2426 2427 dev_vdbg(hsotg->dev, " Speed: %s\n", speed); 2428 dev_vdbg(hsotg->dev, " Max packet size: %d\n", 2429 usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))); 2430 dev_vdbg(hsotg->dev, " Data buffer length: %d\n", 2431 urb->transfer_buffer_length); 2432 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n", 2433 urb->transfer_buffer, (unsigned long)urb->transfer_dma); 2434 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n", 2435 urb->setup_packet, (unsigned long)urb->setup_dma); 2436 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval); 2437 2438 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 2439 int i; 2440 2441 for (i = 0; i < urb->number_of_packets; i++) { 2442 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i); 2443 dev_vdbg(hsotg->dev, " offset: %d, length %d\n", 2444 urb->iso_frame_desc[i].offset, 2445 urb->iso_frame_desc[i].length); 2446 } 2447 } 2448 #endif 2449 } 2450 2451 /* 2452 * Starts processing a USB transfer request specified by a USB Request Block 2453 * (URB). mem_flags indicates the type of memory allocation to use while 2454 * processing this URB. 2455 */ 2456 static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, 2457 gfp_t mem_flags) 2458 { 2459 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2460 struct usb_host_endpoint *ep = urb->ep; 2461 struct dwc2_hcd_urb *dwc2_urb; 2462 int i; 2463 int retval; 2464 int alloc_bandwidth = 0; 2465 u8 ep_type = 0; 2466 u32 tflags = 0; 2467 void *buf; 2468 unsigned long flags; 2469 2470 if (dbg_urb(urb)) { 2471 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n"); 2472 dwc2_dump_urb_info(hcd, urb, "urb_enqueue"); 2473 } 2474 2475 if (ep == NULL) 2476 return -EINVAL; 2477 2478 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || 2479 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { 2480 spin_lock_irqsave(&hsotg->lock, flags); 2481 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep)) 2482 alloc_bandwidth = 1; 2483 spin_unlock_irqrestore(&hsotg->lock, flags); 2484 } 2485 2486 switch (usb_pipetype(urb->pipe)) { 2487 case PIPE_CONTROL: 2488 ep_type = USB_ENDPOINT_XFER_CONTROL; 2489 break; 2490 case PIPE_ISOCHRONOUS: 2491 ep_type = USB_ENDPOINT_XFER_ISOC; 2492 break; 2493 case PIPE_BULK: 2494 ep_type = USB_ENDPOINT_XFER_BULK; 2495 break; 2496 case PIPE_INTERRUPT: 2497 ep_type = USB_ENDPOINT_XFER_INT; 2498 break; 2499 default: 2500 dev_warn(hsotg->dev, "Wrong ep type\n"); 2501 } 2502 2503 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets, 2504 mem_flags); 2505 if (!dwc2_urb) 2506 return -ENOMEM; 2507 2508 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe), 2509 usb_pipeendpoint(urb->pipe), ep_type, 2510 usb_pipein(urb->pipe), 2511 usb_maxpacket(urb->dev, urb->pipe, 2512 !(usb_pipein(urb->pipe)))); 2513 2514 buf = urb->transfer_buffer; 2515 2516 if (hcd->self.uses_dma) { 2517 if (!buf && (urb->transfer_dma & 3)) { 2518 dev_err(hsotg->dev, 2519 "%s: unaligned transfer with no transfer_buffer", 2520 __func__); 2521 retval = -EINVAL; 2522 goto fail1; 2523 } 2524 } 2525 2526 if (!(urb->transfer_flags & URB_NO_INTERRUPT)) 2527 tflags |= URB_GIVEBACK_ASAP; 2528 if (urb->transfer_flags & URB_ZERO_PACKET) 2529 tflags |= URB_SEND_ZERO_PACKET; 2530 2531 dwc2_urb->priv = urb; 2532 dwc2_urb->buf = buf; 2533 dwc2_urb->dma = urb->transfer_dma; 2534 dwc2_urb->length = urb->transfer_buffer_length; 2535 dwc2_urb->setup_packet = urb->setup_packet; 2536 dwc2_urb->setup_dma = urb->setup_dma; 2537 dwc2_urb->flags = tflags; 2538 dwc2_urb->interval = urb->interval; 2539 dwc2_urb->status = -EINPROGRESS; 2540 2541 for (i = 0; i < urb->number_of_packets; ++i) 2542 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i, 2543 urb->iso_frame_desc[i].offset, 2544 urb->iso_frame_desc[i].length); 2545 2546 urb->hcpriv = dwc2_urb; 2547 2548 spin_lock_irqsave(&hsotg->lock, flags); 2549 retval = usb_hcd_link_urb_to_ep(hcd, urb); 2550 spin_unlock_irqrestore(&hsotg->lock, flags); 2551 if (retval) 2552 goto fail1; 2553 2554 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, &ep->hcpriv, mem_flags); 2555 if (retval) 2556 goto fail2; 2557 2558 if (alloc_bandwidth) { 2559 spin_lock_irqsave(&hsotg->lock, flags); 2560 dwc2_allocate_bus_bandwidth(hcd, 2561 dwc2_hcd_get_ep_bandwidth(hsotg, ep), 2562 urb); 2563 spin_unlock_irqrestore(&hsotg->lock, flags); 2564 } 2565 2566 return 0; 2567 2568 fail2: 2569 spin_lock_irqsave(&hsotg->lock, flags); 2570 dwc2_urb->priv = NULL; 2571 usb_hcd_unlink_urb_from_ep(hcd, urb); 2572 spin_unlock_irqrestore(&hsotg->lock, flags); 2573 fail1: 2574 urb->hcpriv = NULL; 2575 kfree(dwc2_urb); 2576 2577 return retval; 2578 } 2579 2580 /* 2581 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success. 2582 */ 2583 static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, 2584 int status) 2585 { 2586 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2587 int rc; 2588 unsigned long flags; 2589 2590 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n"); 2591 dwc2_dump_urb_info(hcd, urb, "urb_dequeue"); 2592 2593 spin_lock_irqsave(&hsotg->lock, flags); 2594 2595 rc = usb_hcd_check_unlink_urb(hcd, urb, status); 2596 if (rc) 2597 goto out; 2598 2599 if (!urb->hcpriv) { 2600 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n"); 2601 goto out; 2602 } 2603 2604 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv); 2605 2606 usb_hcd_unlink_urb_from_ep(hcd, urb); 2607 2608 kfree(urb->hcpriv); 2609 urb->hcpriv = NULL; 2610 2611 /* Higher layer software sets URB status */ 2612 spin_unlock(&hsotg->lock); 2613 usb_hcd_giveback_urb(hcd, urb, status); 2614 spin_lock(&hsotg->lock); 2615 2616 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n"); 2617 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status); 2618 out: 2619 spin_unlock_irqrestore(&hsotg->lock, flags); 2620 2621 return rc; 2622 } 2623 2624 /* 2625 * Frees resources in the DWC_otg controller related to a given endpoint. Also 2626 * clears state in the HCD related to the endpoint. Any URBs for the endpoint 2627 * must already be dequeued. 2628 */ 2629 static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd, 2630 struct usb_host_endpoint *ep) 2631 { 2632 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2633 2634 dev_dbg(hsotg->dev, 2635 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n", 2636 ep->desc.bEndpointAddress, ep->hcpriv); 2637 dwc2_hcd_endpoint_disable(hsotg, ep, 250); 2638 } 2639 2640 /* 2641 * Resets endpoint specific parameter values, in current version used to reset 2642 * the data toggle (as a WA). This function can be called from usb_clear_halt 2643 * routine. 2644 */ 2645 static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd, 2646 struct usb_host_endpoint *ep) 2647 { 2648 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2649 unsigned long flags; 2650 2651 dev_dbg(hsotg->dev, 2652 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n", 2653 ep->desc.bEndpointAddress); 2654 2655 spin_lock_irqsave(&hsotg->lock, flags); 2656 dwc2_hcd_endpoint_reset(hsotg, ep); 2657 spin_unlock_irqrestore(&hsotg->lock, flags); 2658 } 2659 2660 /* 2661 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if 2662 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid 2663 * interrupt. 2664 * 2665 * This function is called by the USB core when an interrupt occurs 2666 */ 2667 static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd) 2668 { 2669 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2670 2671 return dwc2_handle_hcd_intr(hsotg); 2672 } 2673 2674 /* 2675 * Creates Status Change bitmap for the root hub and root port. The bitmap is 2676 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1 2677 * is the status change indicator for the single root port. Returns 1 if either 2678 * change indicator is 1, otherwise returns 0. 2679 */ 2680 static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf) 2681 { 2682 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2683 2684 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1; 2685 return buf[0] != 0; 2686 } 2687 2688 /* Handles hub class-specific requests */ 2689 static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue, 2690 u16 windex, char *buf, u16 wlength) 2691 { 2692 int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq, 2693 wvalue, windex, buf, wlength); 2694 return retval; 2695 } 2696 2697 /* Handles hub TT buffer clear completions */ 2698 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd, 2699 struct usb_host_endpoint *ep) 2700 { 2701 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2702 struct dwc2_qh *qh; 2703 unsigned long flags; 2704 2705 qh = ep->hcpriv; 2706 if (!qh) 2707 return; 2708 2709 spin_lock_irqsave(&hsotg->lock, flags); 2710 qh->tt_buffer_dirty = 0; 2711 2712 if (hsotg->flags.b.port_connect_status) 2713 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL); 2714 2715 spin_unlock_irqrestore(&hsotg->lock, flags); 2716 } 2717 2718 static struct hc_driver dwc2_hc_driver = { 2719 .description = "dwc2_hsotg", 2720 .product_desc = "DWC OTG Controller", 2721 .hcd_priv_size = sizeof(struct wrapper_priv_data), 2722 2723 .irq = _dwc2_hcd_irq, 2724 .flags = HCD_MEMORY | HCD_USB2, 2725 2726 .start = _dwc2_hcd_start, 2727 .stop = _dwc2_hcd_stop, 2728 .urb_enqueue = _dwc2_hcd_urb_enqueue, 2729 .urb_dequeue = _dwc2_hcd_urb_dequeue, 2730 .endpoint_disable = _dwc2_hcd_endpoint_disable, 2731 .endpoint_reset = _dwc2_hcd_endpoint_reset, 2732 .get_frame_number = _dwc2_hcd_get_frame_number, 2733 2734 .hub_status_data = _dwc2_hcd_hub_status_data, 2735 .hub_control = _dwc2_hcd_hub_control, 2736 .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete, 2737 2738 .bus_suspend = _dwc2_hcd_suspend, 2739 .bus_resume = _dwc2_hcd_resume, 2740 }; 2741 2742 /* 2743 * Frees secondary storage associated with the dwc2_hsotg structure contained 2744 * in the struct usb_hcd field 2745 */ 2746 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg) 2747 { 2748 u32 ahbcfg; 2749 u32 dctl; 2750 int i; 2751 2752 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n"); 2753 2754 /* Free memory for QH/QTD lists */ 2755 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive); 2756 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active); 2757 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive); 2758 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready); 2759 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned); 2760 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued); 2761 2762 /* Free memory for the host channels */ 2763 for (i = 0; i < MAX_EPS_CHANNELS; i++) { 2764 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 2765 2766 if (chan != NULL) { 2767 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n", 2768 i, chan); 2769 hsotg->hc_ptr_array[i] = NULL; 2770 kfree(chan); 2771 } 2772 } 2773 2774 if (hsotg->core_params->dma_enable > 0) { 2775 if (hsotg->status_buf) { 2776 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE, 2777 hsotg->status_buf, 2778 hsotg->status_buf_dma); 2779 hsotg->status_buf = NULL; 2780 } 2781 } else { 2782 kfree(hsotg->status_buf); 2783 hsotg->status_buf = NULL; 2784 } 2785 2786 ahbcfg = readl(hsotg->regs + GAHBCFG); 2787 2788 /* Disable all interrupts */ 2789 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 2790 writel(ahbcfg, hsotg->regs + GAHBCFG); 2791 writel(0, hsotg->regs + GINTMSK); 2792 2793 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) { 2794 dctl = readl(hsotg->regs + DCTL); 2795 dctl |= DCTL_SFTDISCON; 2796 writel(dctl, hsotg->regs + DCTL); 2797 } 2798 2799 if (hsotg->wq_otg) { 2800 if (!cancel_work_sync(&hsotg->wf_otg)) 2801 flush_workqueue(hsotg->wq_otg); 2802 destroy_workqueue(hsotg->wq_otg); 2803 } 2804 2805 kfree(hsotg->core_params); 2806 hsotg->core_params = NULL; 2807 del_timer(&hsotg->wkp_timer); 2808 } 2809 2810 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg) 2811 { 2812 /* Turn off all host-specific interrupts */ 2813 dwc2_disable_host_interrupts(hsotg); 2814 2815 dwc2_hcd_free(hsotg); 2816 } 2817 2818 /* 2819 * Sets all parameters to the given value. 2820 * 2821 * Assumes that the dwc2_core_params struct contains only integers. 2822 */ 2823 void dwc2_set_all_params(struct dwc2_core_params *params, int value) 2824 { 2825 int *p = (int *)params; 2826 size_t size = sizeof(*params) / sizeof(*p); 2827 int i; 2828 2829 for (i = 0; i < size; i++) 2830 p[i] = value; 2831 } 2832 EXPORT_SYMBOL_GPL(dwc2_set_all_params); 2833 2834 /* 2835 * Initializes the HCD. This function allocates memory for and initializes the 2836 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the 2837 * USB bus with the core and calls the hc_driver->start() function. It returns 2838 * a negative error on failure. 2839 */ 2840 int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq, 2841 const struct dwc2_core_params *params) 2842 { 2843 struct usb_hcd *hcd; 2844 struct dwc2_host_chan *channel; 2845 u32 hcfg; 2846 int i, num_channels; 2847 int retval; 2848 2849 if (usb_disabled()) 2850 return -ENODEV; 2851 2852 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n"); 2853 2854 /* Detect config values from hardware */ 2855 retval = dwc2_get_hwparams(hsotg); 2856 2857 if (retval) 2858 return retval; 2859 2860 retval = -ENOMEM; 2861 2862 hcfg = readl(hsotg->regs + HCFG); 2863 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg); 2864 2865 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 2866 hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) * 2867 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL); 2868 if (!hsotg->frame_num_array) 2869 goto error1; 2870 hsotg->last_frame_num_array = kzalloc( 2871 sizeof(*hsotg->last_frame_num_array) * 2872 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL); 2873 if (!hsotg->last_frame_num_array) 2874 goto error1; 2875 hsotg->last_frame_num = HFNUM_MAX_FRNUM; 2876 #endif 2877 2878 hsotg->core_params = kzalloc(sizeof(*hsotg->core_params), GFP_KERNEL); 2879 if (!hsotg->core_params) 2880 goto error1; 2881 2882 dwc2_set_all_params(hsotg->core_params, -1); 2883 2884 /* Validate parameter values */ 2885 dwc2_set_parameters(hsotg, params); 2886 2887 /* Check if the bus driver or platform code has setup a dma_mask */ 2888 if (hsotg->core_params->dma_enable > 0 && 2889 hsotg->dev->dma_mask == NULL) { 2890 dev_warn(hsotg->dev, 2891 "dma_mask not set, disabling DMA\n"); 2892 hsotg->core_params->dma_enable = 0; 2893 hsotg->core_params->dma_desc_enable = 0; 2894 } 2895 2896 /* Set device flags indicating whether the HCD supports DMA */ 2897 if (hsotg->core_params->dma_enable > 0) { 2898 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) 2899 dev_warn(hsotg->dev, "can't set DMA mask\n"); 2900 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) 2901 dev_warn(hsotg->dev, "can't set coherent DMA mask\n"); 2902 } 2903 2904 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev)); 2905 if (!hcd) 2906 goto error1; 2907 2908 if (hsotg->core_params->dma_enable <= 0) 2909 hcd->self.uses_dma = 0; 2910 2911 hcd->has_tt = 1; 2912 2913 ((struct wrapper_priv_data *) &hcd->hcd_priv)->hsotg = hsotg; 2914 hsotg->priv = hcd; 2915 2916 /* 2917 * Disable the global interrupt until all the interrupt handlers are 2918 * installed 2919 */ 2920 dwc2_disable_global_interrupts(hsotg); 2921 2922 /* Initialize the DWC_otg core, and select the Phy type */ 2923 retval = dwc2_core_init(hsotg, true, irq); 2924 if (retval) 2925 goto error2; 2926 2927 /* Create new workqueue and init work */ 2928 retval = -ENOMEM; 2929 hsotg->wq_otg = create_singlethread_workqueue("dwc2"); 2930 if (!hsotg->wq_otg) { 2931 dev_err(hsotg->dev, "Failed to create workqueue\n"); 2932 goto error2; 2933 } 2934 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change); 2935 2936 setup_timer(&hsotg->wkp_timer, dwc2_wakeup_detected, 2937 (unsigned long)hsotg); 2938 2939 /* Initialize the non-periodic schedule */ 2940 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive); 2941 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active); 2942 2943 /* Initialize the periodic schedule */ 2944 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive); 2945 INIT_LIST_HEAD(&hsotg->periodic_sched_ready); 2946 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned); 2947 INIT_LIST_HEAD(&hsotg->periodic_sched_queued); 2948 2949 /* 2950 * Create a host channel descriptor for each host channel implemented 2951 * in the controller. Initialize the channel descriptor array. 2952 */ 2953 INIT_LIST_HEAD(&hsotg->free_hc_list); 2954 num_channels = hsotg->core_params->host_channels; 2955 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array)); 2956 2957 for (i = 0; i < num_channels; i++) { 2958 channel = kzalloc(sizeof(*channel), GFP_KERNEL); 2959 if (channel == NULL) 2960 goto error3; 2961 channel->hc_num = i; 2962 hsotg->hc_ptr_array[i] = channel; 2963 } 2964 2965 if (hsotg->core_params->uframe_sched > 0) 2966 dwc2_hcd_init_usecs(hsotg); 2967 2968 /* Initialize hsotg start work */ 2969 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func); 2970 2971 /* Initialize port reset work */ 2972 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func); 2973 2974 /* 2975 * Allocate space for storing data on status transactions. Normally no 2976 * data is sent, but this space acts as a bit bucket. This must be 2977 * done after usb_add_hcd since that function allocates the DMA buffer 2978 * pool. 2979 */ 2980 if (hsotg->core_params->dma_enable > 0) 2981 hsotg->status_buf = dma_alloc_coherent(hsotg->dev, 2982 DWC2_HCD_STATUS_BUF_SIZE, 2983 &hsotg->status_buf_dma, GFP_KERNEL); 2984 else 2985 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE, 2986 GFP_KERNEL); 2987 2988 if (!hsotg->status_buf) 2989 goto error3; 2990 2991 hsotg->otg_port = 1; 2992 hsotg->frame_list = NULL; 2993 hsotg->frame_list_dma = 0; 2994 hsotg->periodic_qh_count = 0; 2995 2996 /* Initiate lx_state to L3 disconnected state */ 2997 hsotg->lx_state = DWC2_L3; 2998 2999 hcd->self.otg_port = hsotg->otg_port; 3000 3001 /* Don't support SG list at this point */ 3002 hcd->self.sg_tablesize = 0; 3003 3004 /* 3005 * Finish generic HCD initialization and start the HCD. This function 3006 * allocates the DMA buffer pool, registers the USB bus, requests the 3007 * IRQ line, and calls hcd_start method. 3008 */ 3009 retval = usb_add_hcd(hcd, irq, IRQF_SHARED); 3010 if (retval < 0) 3011 goto error3; 3012 3013 device_wakeup_enable(hcd->self.controller); 3014 3015 dwc2_hcd_dump_state(hsotg); 3016 3017 dwc2_enable_global_interrupts(hsotg); 3018 3019 return 0; 3020 3021 error3: 3022 dwc2_hcd_release(hsotg); 3023 error2: 3024 usb_put_hcd(hcd); 3025 error1: 3026 kfree(hsotg->core_params); 3027 3028 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 3029 kfree(hsotg->last_frame_num_array); 3030 kfree(hsotg->frame_num_array); 3031 #endif 3032 3033 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval); 3034 return retval; 3035 } 3036 EXPORT_SYMBOL_GPL(dwc2_hcd_init); 3037 3038 /* 3039 * Removes the HCD. 3040 * Frees memory and resources associated with the HCD and deregisters the bus. 3041 */ 3042 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) 3043 { 3044 struct usb_hcd *hcd; 3045 3046 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n"); 3047 3048 hcd = dwc2_hsotg_to_hcd(hsotg); 3049 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd); 3050 3051 if (!hcd) { 3052 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n", 3053 __func__); 3054 return; 3055 } 3056 3057 usb_remove_hcd(hcd); 3058 hsotg->priv = NULL; 3059 dwc2_hcd_release(hsotg); 3060 usb_put_hcd(hcd); 3061 3062 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 3063 kfree(hsotg->last_frame_num_array); 3064 kfree(hsotg->frame_num_array); 3065 #endif 3066 } 3067 EXPORT_SYMBOL_GPL(dwc2_hcd_remove); 3068