1 /* 2 * hcd.c - DesignWare HS OTG Controller host-mode routines 3 * 4 * Copyright (C) 2004-2013 Synopsys, Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The names of the above-listed copyright holders may not be used 16 * to endorse or promote products derived from this software without 17 * specific prior written permission. 18 * 19 * ALTERNATIVELY, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") as published by the Free Software 21 * Foundation; either version 2 of the License, or (at your option) any 22 * later version. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * This file contains the core HCD code, and implements the Linux hc_driver 39 * API 40 */ 41 #include <linux/kernel.h> 42 #include <linux/module.h> 43 #include <linux/spinlock.h> 44 #include <linux/interrupt.h> 45 #include <linux/platform_device.h> 46 #include <linux/dma-mapping.h> 47 #include <linux/delay.h> 48 #include <linux/io.h> 49 #include <linux/slab.h> 50 #include <linux/usb.h> 51 52 #include <linux/usb/hcd.h> 53 #include <linux/usb/ch11.h> 54 55 #include "core.h" 56 #include "hcd.h" 57 58 static void dwc2_port_resume(struct dwc2_hsotg *hsotg); 59 60 /* 61 * ========================================================================= 62 * Host Core Layer Functions 63 * ========================================================================= 64 */ 65 66 /** 67 * dwc2_enable_common_interrupts() - Initializes the commmon interrupts, 68 * used in both device and host modes 69 * 70 * @hsotg: Programming view of the DWC_otg controller 71 */ 72 static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg) 73 { 74 u32 intmsk; 75 76 /* Clear any pending OTG Interrupts */ 77 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT); 78 79 /* Clear any pending interrupts */ 80 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); 81 82 /* Enable the interrupts in the GINTMSK */ 83 intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT; 84 85 if (!hsotg->params.host_dma) 86 intmsk |= GINTSTS_RXFLVL; 87 if (!hsotg->params.external_id_pin_ctl) 88 intmsk |= GINTSTS_CONIDSTSCHNG; 89 90 intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP | 91 GINTSTS_SESSREQINT; 92 93 dwc2_writel(intmsk, hsotg->regs + GINTMSK); 94 } 95 96 /* 97 * Initializes the FSLSPClkSel field of the HCFG register depending on the 98 * PHY type 99 */ 100 static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg) 101 { 102 u32 hcfg, val; 103 104 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && 105 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && 106 hsotg->params.ulpi_fs_ls) || 107 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) { 108 /* Full speed PHY */ 109 val = HCFG_FSLSPCLKSEL_48_MHZ; 110 } else { 111 /* High speed PHY running at full speed or high speed */ 112 val = HCFG_FSLSPCLKSEL_30_60_MHZ; 113 } 114 115 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val); 116 hcfg = dwc2_readl(hsotg->regs + HCFG); 117 hcfg &= ~HCFG_FSLSPCLKSEL_MASK; 118 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT; 119 dwc2_writel(hcfg, hsotg->regs + HCFG); 120 } 121 122 static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 123 { 124 u32 usbcfg, ggpio, i2cctl; 125 int retval = 0; 126 127 /* 128 * core_init() is now called on every switch so only call the 129 * following for the first time through 130 */ 131 if (select_phy) { 132 dev_dbg(hsotg->dev, "FS PHY selected\n"); 133 134 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 135 if (!(usbcfg & GUSBCFG_PHYSEL)) { 136 usbcfg |= GUSBCFG_PHYSEL; 137 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 138 139 /* Reset after a PHY select */ 140 retval = dwc2_core_reset_and_force_dr_mode(hsotg); 141 142 if (retval) { 143 dev_err(hsotg->dev, 144 "%s: Reset failed, aborting", __func__); 145 return retval; 146 } 147 } 148 149 if (hsotg->params.activate_stm_fs_transceiver) { 150 ggpio = dwc2_readl(hsotg->regs + GGPIO); 151 if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) { 152 dev_dbg(hsotg->dev, "Activating transceiver\n"); 153 /* 154 * STM32F4x9 uses the GGPIO register as general 155 * core configuration register. 156 */ 157 ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN; 158 dwc2_writel(ggpio, hsotg->regs + GGPIO); 159 } 160 } 161 } 162 163 /* 164 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also 165 * do this on HNP Dev/Host mode switches (done in dev_init and 166 * host_init). 167 */ 168 if (dwc2_is_host_mode(hsotg)) 169 dwc2_init_fs_ls_pclk_sel(hsotg); 170 171 if (hsotg->params.i2c_enable) { 172 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n"); 173 174 /* Program GUSBCFG.OtgUtmiFsSel to I2C */ 175 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 176 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL; 177 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 178 179 /* Program GI2CCTL.I2CEn */ 180 i2cctl = dwc2_readl(hsotg->regs + GI2CCTL); 181 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK; 182 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT; 183 i2cctl &= ~GI2CCTL_I2CEN; 184 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL); 185 i2cctl |= GI2CCTL_I2CEN; 186 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL); 187 } 188 189 return retval; 190 } 191 192 static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 193 { 194 u32 usbcfg, usbcfg_old; 195 int retval = 0; 196 197 if (!select_phy) 198 return 0; 199 200 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 201 usbcfg_old = usbcfg; 202 203 /* 204 * HS PHY parameters. These parameters are preserved during soft reset 205 * so only program the first time. Do a soft reset immediately after 206 * setting phyif. 207 */ 208 switch (hsotg->params.phy_type) { 209 case DWC2_PHY_TYPE_PARAM_ULPI: 210 /* ULPI interface */ 211 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n"); 212 usbcfg |= GUSBCFG_ULPI_UTMI_SEL; 213 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL); 214 if (hsotg->params.phy_ulpi_ddr) 215 usbcfg |= GUSBCFG_DDRSEL; 216 break; 217 case DWC2_PHY_TYPE_PARAM_UTMI: 218 /* UTMI+ interface */ 219 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n"); 220 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16); 221 if (hsotg->params.phy_utmi_width == 16) 222 usbcfg |= GUSBCFG_PHYIF16; 223 break; 224 default: 225 dev_err(hsotg->dev, "FS PHY selected at HS!\n"); 226 break; 227 } 228 229 if (usbcfg != usbcfg_old) { 230 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 231 232 /* Reset after setting the PHY parameters */ 233 retval = dwc2_core_reset_and_force_dr_mode(hsotg); 234 if (retval) { 235 dev_err(hsotg->dev, 236 "%s: Reset failed, aborting", __func__); 237 return retval; 238 } 239 } 240 241 return retval; 242 } 243 244 static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 245 { 246 u32 usbcfg; 247 int retval = 0; 248 249 if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL || 250 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) && 251 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) { 252 /* If FS/LS mode with FS/LS PHY */ 253 retval = dwc2_fs_phy_init(hsotg, select_phy); 254 if (retval) 255 return retval; 256 } else { 257 /* High speed PHY */ 258 retval = dwc2_hs_phy_init(hsotg, select_phy); 259 if (retval) 260 return retval; 261 } 262 263 if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && 264 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && 265 hsotg->params.ulpi_fs_ls) { 266 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n"); 267 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 268 usbcfg |= GUSBCFG_ULPI_FS_LS; 269 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M; 270 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 271 } else { 272 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 273 usbcfg &= ~GUSBCFG_ULPI_FS_LS; 274 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M; 275 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 276 } 277 278 return retval; 279 } 280 281 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg) 282 { 283 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 284 285 switch (hsotg->hw_params.arch) { 286 case GHWCFG2_EXT_DMA_ARCH: 287 dev_err(hsotg->dev, "External DMA Mode not supported\n"); 288 return -EINVAL; 289 290 case GHWCFG2_INT_DMA_ARCH: 291 dev_dbg(hsotg->dev, "Internal DMA Mode\n"); 292 if (hsotg->params.ahbcfg != -1) { 293 ahbcfg &= GAHBCFG_CTRL_MASK; 294 ahbcfg |= hsotg->params.ahbcfg & 295 ~GAHBCFG_CTRL_MASK; 296 } 297 break; 298 299 case GHWCFG2_SLAVE_ONLY_ARCH: 300 default: 301 dev_dbg(hsotg->dev, "Slave Only Mode\n"); 302 break; 303 } 304 305 dev_dbg(hsotg->dev, "host_dma:%d dma_desc_enable:%d\n", 306 hsotg->params.host_dma, 307 hsotg->params.dma_desc_enable); 308 309 if (hsotg->params.host_dma) { 310 if (hsotg->params.dma_desc_enable) 311 dev_dbg(hsotg->dev, "Using Descriptor DMA mode\n"); 312 else 313 dev_dbg(hsotg->dev, "Using Buffer DMA mode\n"); 314 } else { 315 dev_dbg(hsotg->dev, "Using Slave mode\n"); 316 hsotg->params.dma_desc_enable = false; 317 } 318 319 if (hsotg->params.host_dma) 320 ahbcfg |= GAHBCFG_DMA_EN; 321 322 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); 323 324 return 0; 325 } 326 327 static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg) 328 { 329 u32 usbcfg; 330 331 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 332 usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP); 333 334 switch (hsotg->hw_params.op_mode) { 335 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 336 if (hsotg->params.otg_cap == 337 DWC2_CAP_PARAM_HNP_SRP_CAPABLE) 338 usbcfg |= GUSBCFG_HNPCAP; 339 if (hsotg->params.otg_cap != 340 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE) 341 usbcfg |= GUSBCFG_SRPCAP; 342 break; 343 344 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 345 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 346 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 347 if (hsotg->params.otg_cap != 348 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE) 349 usbcfg |= GUSBCFG_SRPCAP; 350 break; 351 352 case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE: 353 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE: 354 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST: 355 default: 356 break; 357 } 358 359 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 360 } 361 362 /** 363 * dwc2_enable_host_interrupts() - Enables the Host mode interrupts 364 * 365 * @hsotg: Programming view of DWC_otg controller 366 */ 367 static void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg) 368 { 369 u32 intmsk; 370 371 dev_dbg(hsotg->dev, "%s()\n", __func__); 372 373 /* Disable all interrupts */ 374 dwc2_writel(0, hsotg->regs + GINTMSK); 375 dwc2_writel(0, hsotg->regs + HAINTMSK); 376 377 /* Enable the common interrupts */ 378 dwc2_enable_common_interrupts(hsotg); 379 380 /* Enable host mode interrupts without disturbing common interrupts */ 381 intmsk = dwc2_readl(hsotg->regs + GINTMSK); 382 intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT; 383 dwc2_writel(intmsk, hsotg->regs + GINTMSK); 384 } 385 386 /** 387 * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts 388 * 389 * @hsotg: Programming view of DWC_otg controller 390 */ 391 static void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg) 392 { 393 u32 intmsk = dwc2_readl(hsotg->regs + GINTMSK); 394 395 /* Disable host mode interrupts without disturbing common interrupts */ 396 intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT | 397 GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT); 398 dwc2_writel(intmsk, hsotg->regs + GINTMSK); 399 } 400 401 /* 402 * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size 403 * For system that have a total fifo depth that is smaller than the default 404 * RX + TX fifo size. 405 * 406 * @hsotg: Programming view of DWC_otg controller 407 */ 408 static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg) 409 { 410 struct dwc2_core_params *params = &hsotg->params; 411 struct dwc2_hw_params *hw = &hsotg->hw_params; 412 u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size; 413 414 total_fifo_size = hw->total_fifo_size; 415 rxfsiz = params->host_rx_fifo_size; 416 nptxfsiz = params->host_nperio_tx_fifo_size; 417 ptxfsiz = params->host_perio_tx_fifo_size; 418 419 /* 420 * Will use Method 2 defined in the DWC2 spec: minimum FIFO depth 421 * allocation with support for high bandwidth endpoints. Synopsys 422 * defines MPS(Max Packet size) for a periodic EP=1024, and for 423 * non-periodic as 512. 424 */ 425 if (total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)) { 426 /* 427 * For Buffer DMA mode/Scatter Gather DMA mode 428 * 2 * ((Largest Packet size / 4) + 1 + 1) + n 429 * with n = number of host channel. 430 * 2 * ((1024/4) + 2) = 516 431 */ 432 rxfsiz = 516 + hw->host_channels; 433 434 /* 435 * min non-periodic tx fifo depth 436 * 2 * (largest non-periodic USB packet used / 4) 437 * 2 * (512/4) = 256 438 */ 439 nptxfsiz = 256; 440 441 /* 442 * min periodic tx fifo depth 443 * (largest packet size*MC)/4 444 * (1024 * 3)/4 = 768 445 */ 446 ptxfsiz = 768; 447 448 params->host_rx_fifo_size = rxfsiz; 449 params->host_nperio_tx_fifo_size = nptxfsiz; 450 params->host_perio_tx_fifo_size = ptxfsiz; 451 } 452 453 /* 454 * If the summation of RX, NPTX and PTX fifo sizes is still 455 * bigger than the total_fifo_size, then we have a problem. 456 * 457 * We won't be able to allocate as many endpoints. Right now, 458 * we're just printing an error message, but ideally this FIFO 459 * allocation algorithm would be improved in the future. 460 * 461 * FIXME improve this FIFO allocation algorithm. 462 */ 463 if (unlikely(total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz))) 464 dev_err(hsotg->dev, "invalid fifo sizes\n"); 465 } 466 467 static void dwc2_config_fifos(struct dwc2_hsotg *hsotg) 468 { 469 struct dwc2_core_params *params = &hsotg->params; 470 u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz; 471 472 if (!params->enable_dynamic_fifo) 473 return; 474 475 dwc2_calculate_dynamic_fifo(hsotg); 476 477 /* Rx FIFO */ 478 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); 479 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz); 480 grxfsiz &= ~GRXFSIZ_DEPTH_MASK; 481 grxfsiz |= params->host_rx_fifo_size << 482 GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK; 483 dwc2_writel(grxfsiz, hsotg->regs + GRXFSIZ); 484 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", 485 dwc2_readl(hsotg->regs + GRXFSIZ)); 486 487 /* Non-periodic Tx FIFO */ 488 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n", 489 dwc2_readl(hsotg->regs + GNPTXFSIZ)); 490 nptxfsiz = params->host_nperio_tx_fifo_size << 491 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; 492 nptxfsiz |= params->host_rx_fifo_size << 493 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; 494 dwc2_writel(nptxfsiz, hsotg->regs + GNPTXFSIZ); 495 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n", 496 dwc2_readl(hsotg->regs + GNPTXFSIZ)); 497 498 /* Periodic Tx FIFO */ 499 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n", 500 dwc2_readl(hsotg->regs + HPTXFSIZ)); 501 hptxfsiz = params->host_perio_tx_fifo_size << 502 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; 503 hptxfsiz |= (params->host_rx_fifo_size + 504 params->host_nperio_tx_fifo_size) << 505 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; 506 dwc2_writel(hptxfsiz, hsotg->regs + HPTXFSIZ); 507 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n", 508 dwc2_readl(hsotg->regs + HPTXFSIZ)); 509 510 if (hsotg->params.en_multiple_tx_fifo && 511 hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_91a) { 512 /* 513 * This feature was implemented in 2.91a version 514 * Global DFIFOCFG calculation for Host mode - 515 * include RxFIFO, NPTXFIFO and HPTXFIFO 516 */ 517 dfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG); 518 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK; 519 dfifocfg |= (params->host_rx_fifo_size + 520 params->host_nperio_tx_fifo_size + 521 params->host_perio_tx_fifo_size) << 522 GDFIFOCFG_EPINFOBASE_SHIFT & 523 GDFIFOCFG_EPINFOBASE_MASK; 524 dwc2_writel(dfifocfg, hsotg->regs + GDFIFOCFG); 525 } 526 } 527 528 /** 529 * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for 530 * the HFIR register according to PHY type and speed 531 * 532 * @hsotg: Programming view of DWC_otg controller 533 * 534 * NOTE: The caller can modify the value of the HFIR register only after the 535 * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort) 536 * has been set 537 */ 538 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg) 539 { 540 u32 usbcfg; 541 u32 hprt0; 542 int clock = 60; /* default value */ 543 544 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 545 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 546 547 if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) && 548 !(usbcfg & GUSBCFG_PHYIF16)) 549 clock = 60; 550 if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type == 551 GHWCFG2_FS_PHY_TYPE_SHARED_ULPI) 552 clock = 48; 553 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 554 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16)) 555 clock = 30; 556 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 557 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16)) 558 clock = 60; 559 if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 560 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16)) 561 clock = 48; 562 if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) && 563 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI) 564 clock = 48; 565 if ((usbcfg & GUSBCFG_PHYSEL) && 566 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) 567 clock = 48; 568 569 if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED) 570 /* High speed case */ 571 return 125 * clock - 1; 572 573 /* FS/LS case */ 574 return 1000 * clock - 1; 575 } 576 577 /** 578 * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination 579 * buffer 580 * 581 * @core_if: Programming view of DWC_otg controller 582 * @dest: Destination buffer for the packet 583 * @bytes: Number of bytes to copy to the destination 584 */ 585 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes) 586 { 587 u32 __iomem *fifo = hsotg->regs + HCFIFO(0); 588 u32 *data_buf = (u32 *)dest; 589 int word_count = (bytes + 3) / 4; 590 int i; 591 592 /* 593 * Todo: Account for the case where dest is not dword aligned. This 594 * requires reading data from the FIFO into a u32 temp buffer, then 595 * moving it into the data buffer. 596 */ 597 598 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes); 599 600 for (i = 0; i < word_count; i++, data_buf++) 601 *data_buf = dwc2_readl(fifo); 602 } 603 604 /** 605 * dwc2_dump_channel_info() - Prints the state of a host channel 606 * 607 * @hsotg: Programming view of DWC_otg controller 608 * @chan: Pointer to the channel to dump 609 * 610 * Must be called with interrupt disabled and spinlock held 611 * 612 * NOTE: This function will be removed once the peripheral controller code 613 * is integrated and the driver is stable 614 */ 615 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg, 616 struct dwc2_host_chan *chan) 617 { 618 #ifdef VERBOSE_DEBUG 619 int num_channels = hsotg->params.host_channels; 620 struct dwc2_qh *qh; 621 u32 hcchar; 622 u32 hcsplt; 623 u32 hctsiz; 624 u32 hc_dma; 625 int i; 626 627 if (!chan) 628 return; 629 630 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 631 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num)); 632 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chan->hc_num)); 633 hc_dma = dwc2_readl(hsotg->regs + HCDMA(chan->hc_num)); 634 635 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan); 636 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", 637 hcchar, hcsplt); 638 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", 639 hctsiz, hc_dma); 640 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 641 chan->dev_addr, chan->ep_num, chan->ep_is_in); 642 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 643 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 644 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start); 645 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started); 646 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 647 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 648 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 649 (unsigned long)chan->xfer_dma); 650 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 651 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 652 dev_dbg(hsotg->dev, " NP inactive sched:\n"); 653 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive, 654 qh_list_entry) 655 dev_dbg(hsotg->dev, " %p\n", qh); 656 dev_dbg(hsotg->dev, " NP active sched:\n"); 657 list_for_each_entry(qh, &hsotg->non_periodic_sched_active, 658 qh_list_entry) 659 dev_dbg(hsotg->dev, " %p\n", qh); 660 dev_dbg(hsotg->dev, " Channels:\n"); 661 for (i = 0; i < num_channels; i++) { 662 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 663 664 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan); 665 } 666 #endif /* VERBOSE_DEBUG */ 667 } 668 669 static int _dwc2_hcd_start(struct usb_hcd *hcd); 670 671 static void dwc2_host_start(struct dwc2_hsotg *hsotg) 672 { 673 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 674 675 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg); 676 _dwc2_hcd_start(hcd); 677 } 678 679 static void dwc2_host_disconnect(struct dwc2_hsotg *hsotg) 680 { 681 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 682 683 hcd->self.is_b_host = 0; 684 } 685 686 static void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, 687 int *hub_addr, int *hub_port) 688 { 689 struct urb *urb = context; 690 691 if (urb->dev->tt) 692 *hub_addr = urb->dev->tt->hub->devnum; 693 else 694 *hub_addr = 0; 695 *hub_port = urb->dev->ttport; 696 } 697 698 /* 699 * ========================================================================= 700 * Low Level Host Channel Access Functions 701 * ========================================================================= 702 */ 703 704 static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg, 705 struct dwc2_host_chan *chan) 706 { 707 u32 hcintmsk = HCINTMSK_CHHLTD; 708 709 switch (chan->ep_type) { 710 case USB_ENDPOINT_XFER_CONTROL: 711 case USB_ENDPOINT_XFER_BULK: 712 dev_vdbg(hsotg->dev, "control/bulk\n"); 713 hcintmsk |= HCINTMSK_XFERCOMPL; 714 hcintmsk |= HCINTMSK_STALL; 715 hcintmsk |= HCINTMSK_XACTERR; 716 hcintmsk |= HCINTMSK_DATATGLERR; 717 if (chan->ep_is_in) { 718 hcintmsk |= HCINTMSK_BBLERR; 719 } else { 720 hcintmsk |= HCINTMSK_NAK; 721 hcintmsk |= HCINTMSK_NYET; 722 if (chan->do_ping) 723 hcintmsk |= HCINTMSK_ACK; 724 } 725 726 if (chan->do_split) { 727 hcintmsk |= HCINTMSK_NAK; 728 if (chan->complete_split) 729 hcintmsk |= HCINTMSK_NYET; 730 else 731 hcintmsk |= HCINTMSK_ACK; 732 } 733 734 if (chan->error_state) 735 hcintmsk |= HCINTMSK_ACK; 736 break; 737 738 case USB_ENDPOINT_XFER_INT: 739 if (dbg_perio()) 740 dev_vdbg(hsotg->dev, "intr\n"); 741 hcintmsk |= HCINTMSK_XFERCOMPL; 742 hcintmsk |= HCINTMSK_NAK; 743 hcintmsk |= HCINTMSK_STALL; 744 hcintmsk |= HCINTMSK_XACTERR; 745 hcintmsk |= HCINTMSK_DATATGLERR; 746 hcintmsk |= HCINTMSK_FRMOVRUN; 747 748 if (chan->ep_is_in) 749 hcintmsk |= HCINTMSK_BBLERR; 750 if (chan->error_state) 751 hcintmsk |= HCINTMSK_ACK; 752 if (chan->do_split) { 753 if (chan->complete_split) 754 hcintmsk |= HCINTMSK_NYET; 755 else 756 hcintmsk |= HCINTMSK_ACK; 757 } 758 break; 759 760 case USB_ENDPOINT_XFER_ISOC: 761 if (dbg_perio()) 762 dev_vdbg(hsotg->dev, "isoc\n"); 763 hcintmsk |= HCINTMSK_XFERCOMPL; 764 hcintmsk |= HCINTMSK_FRMOVRUN; 765 hcintmsk |= HCINTMSK_ACK; 766 767 if (chan->ep_is_in) { 768 hcintmsk |= HCINTMSK_XACTERR; 769 hcintmsk |= HCINTMSK_BBLERR; 770 } 771 break; 772 default: 773 dev_err(hsotg->dev, "## Unknown EP type ##\n"); 774 break; 775 } 776 777 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); 778 if (dbg_hc(chan)) 779 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); 780 } 781 782 static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg, 783 struct dwc2_host_chan *chan) 784 { 785 u32 hcintmsk = HCINTMSK_CHHLTD; 786 787 /* 788 * For Descriptor DMA mode core halts the channel on AHB error. 789 * Interrupt is not required. 790 */ 791 if (!hsotg->params.dma_desc_enable) { 792 if (dbg_hc(chan)) 793 dev_vdbg(hsotg->dev, "desc DMA disabled\n"); 794 hcintmsk |= HCINTMSK_AHBERR; 795 } else { 796 if (dbg_hc(chan)) 797 dev_vdbg(hsotg->dev, "desc DMA enabled\n"); 798 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 799 hcintmsk |= HCINTMSK_XFERCOMPL; 800 } 801 802 if (chan->error_state && !chan->do_split && 803 chan->ep_type != USB_ENDPOINT_XFER_ISOC) { 804 if (dbg_hc(chan)) 805 dev_vdbg(hsotg->dev, "setting ACK\n"); 806 hcintmsk |= HCINTMSK_ACK; 807 if (chan->ep_is_in) { 808 hcintmsk |= HCINTMSK_DATATGLERR; 809 if (chan->ep_type != USB_ENDPOINT_XFER_INT) 810 hcintmsk |= HCINTMSK_NAK; 811 } 812 } 813 814 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); 815 if (dbg_hc(chan)) 816 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); 817 } 818 819 static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg, 820 struct dwc2_host_chan *chan) 821 { 822 u32 intmsk; 823 824 if (hsotg->params.host_dma) { 825 if (dbg_hc(chan)) 826 dev_vdbg(hsotg->dev, "DMA enabled\n"); 827 dwc2_hc_enable_dma_ints(hsotg, chan); 828 } else { 829 if (dbg_hc(chan)) 830 dev_vdbg(hsotg->dev, "DMA disabled\n"); 831 dwc2_hc_enable_slave_ints(hsotg, chan); 832 } 833 834 /* Enable the top level host channel interrupt */ 835 intmsk = dwc2_readl(hsotg->regs + HAINTMSK); 836 intmsk |= 1 << chan->hc_num; 837 dwc2_writel(intmsk, hsotg->regs + HAINTMSK); 838 if (dbg_hc(chan)) 839 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk); 840 841 /* Make sure host channel interrupts are enabled */ 842 intmsk = dwc2_readl(hsotg->regs + GINTMSK); 843 intmsk |= GINTSTS_HCHINT; 844 dwc2_writel(intmsk, hsotg->regs + GINTMSK); 845 if (dbg_hc(chan)) 846 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk); 847 } 848 849 /** 850 * dwc2_hc_init() - Prepares a host channel for transferring packets to/from 851 * a specific endpoint 852 * 853 * @hsotg: Programming view of DWC_otg controller 854 * @chan: Information needed to initialize the host channel 855 * 856 * The HCCHARn register is set up with the characteristics specified in chan. 857 * Host channel interrupts that may need to be serviced while this transfer is 858 * in progress are enabled. 859 */ 860 static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) 861 { 862 u8 hc_num = chan->hc_num; 863 u32 hcintmsk; 864 u32 hcchar; 865 u32 hcsplt = 0; 866 867 if (dbg_hc(chan)) 868 dev_vdbg(hsotg->dev, "%s()\n", __func__); 869 870 /* Clear old interrupt conditions for this host channel */ 871 hcintmsk = 0xffffffff; 872 hcintmsk &= ~HCINTMSK_RESERVED14_31; 873 dwc2_writel(hcintmsk, hsotg->regs + HCINT(hc_num)); 874 875 /* Enable channel interrupts required for this transfer */ 876 dwc2_hc_enable_ints(hsotg, chan); 877 878 /* 879 * Program the HCCHARn register with the endpoint characteristics for 880 * the current transfer 881 */ 882 hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK; 883 hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK; 884 if (chan->ep_is_in) 885 hcchar |= HCCHAR_EPDIR; 886 if (chan->speed == USB_SPEED_LOW) 887 hcchar |= HCCHAR_LSPDDEV; 888 hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK; 889 hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK; 890 dwc2_writel(hcchar, hsotg->regs + HCCHAR(hc_num)); 891 if (dbg_hc(chan)) { 892 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n", 893 hc_num, hcchar); 894 895 dev_vdbg(hsotg->dev, "%s: Channel %d\n", 896 __func__, hc_num); 897 dev_vdbg(hsotg->dev, " Dev Addr: %d\n", 898 chan->dev_addr); 899 dev_vdbg(hsotg->dev, " Ep Num: %d\n", 900 chan->ep_num); 901 dev_vdbg(hsotg->dev, " Is In: %d\n", 902 chan->ep_is_in); 903 dev_vdbg(hsotg->dev, " Is Low Speed: %d\n", 904 chan->speed == USB_SPEED_LOW); 905 dev_vdbg(hsotg->dev, " Ep Type: %d\n", 906 chan->ep_type); 907 dev_vdbg(hsotg->dev, " Max Pkt: %d\n", 908 chan->max_packet); 909 } 910 911 /* Program the HCSPLT register for SPLITs */ 912 if (chan->do_split) { 913 if (dbg_hc(chan)) 914 dev_vdbg(hsotg->dev, 915 "Programming HC %d with split --> %s\n", 916 hc_num, 917 chan->complete_split ? "CSPLIT" : "SSPLIT"); 918 if (chan->complete_split) 919 hcsplt |= HCSPLT_COMPSPLT; 920 hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT & 921 HCSPLT_XACTPOS_MASK; 922 hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT & 923 HCSPLT_HUBADDR_MASK; 924 hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT & 925 HCSPLT_PRTADDR_MASK; 926 if (dbg_hc(chan)) { 927 dev_vdbg(hsotg->dev, " comp split %d\n", 928 chan->complete_split); 929 dev_vdbg(hsotg->dev, " xact pos %d\n", 930 chan->xact_pos); 931 dev_vdbg(hsotg->dev, " hub addr %d\n", 932 chan->hub_addr); 933 dev_vdbg(hsotg->dev, " hub port %d\n", 934 chan->hub_port); 935 dev_vdbg(hsotg->dev, " is_in %d\n", 936 chan->ep_is_in); 937 dev_vdbg(hsotg->dev, " Max Pkt %d\n", 938 chan->max_packet); 939 dev_vdbg(hsotg->dev, " xferlen %d\n", 940 chan->xfer_len); 941 } 942 } 943 944 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(hc_num)); 945 } 946 947 /** 948 * dwc2_hc_halt() - Attempts to halt a host channel 949 * 950 * @hsotg: Controller register interface 951 * @chan: Host channel to halt 952 * @halt_status: Reason for halting the channel 953 * 954 * This function should only be called in Slave mode or to abort a transfer in 955 * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the 956 * controller halts the channel when the transfer is complete or a condition 957 * occurs that requires application intervention. 958 * 959 * In slave mode, checks for a free request queue entry, then sets the Channel 960 * Enable and Channel Disable bits of the Host Channel Characteristics 961 * register of the specified channel to intiate the halt. If there is no free 962 * request queue entry, sets only the Channel Disable bit of the HCCHARn 963 * register to flush requests for this channel. In the latter case, sets a 964 * flag to indicate that the host channel needs to be halted when a request 965 * queue slot is open. 966 * 967 * In DMA mode, always sets the Channel Enable and Channel Disable bits of the 968 * HCCHARn register. The controller ensures there is space in the request 969 * queue before submitting the halt request. 970 * 971 * Some time may elapse before the core flushes any posted requests for this 972 * host channel and halts. The Channel Halted interrupt handler completes the 973 * deactivation of the host channel. 974 */ 975 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 976 enum dwc2_halt_status halt_status) 977 { 978 u32 nptxsts, hptxsts, hcchar; 979 980 if (dbg_hc(chan)) 981 dev_vdbg(hsotg->dev, "%s()\n", __func__); 982 if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS) 983 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status); 984 985 if (halt_status == DWC2_HC_XFER_URB_DEQUEUE || 986 halt_status == DWC2_HC_XFER_AHB_ERR) { 987 /* 988 * Disable all channel interrupts except Ch Halted. The QTD 989 * and QH state associated with this transfer has been cleared 990 * (in the case of URB_DEQUEUE), so the channel needs to be 991 * shut down carefully to prevent crashes. 992 */ 993 u32 hcintmsk = HCINTMSK_CHHLTD; 994 995 dev_vdbg(hsotg->dev, "dequeue/error\n"); 996 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); 997 998 /* 999 * Make sure no other interrupts besides halt are currently 1000 * pending. Handling another interrupt could cause a crash due 1001 * to the QTD and QH state. 1002 */ 1003 dwc2_writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num)); 1004 1005 /* 1006 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR 1007 * even if the channel was already halted for some other 1008 * reason 1009 */ 1010 chan->halt_status = halt_status; 1011 1012 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1013 if (!(hcchar & HCCHAR_CHENA)) { 1014 /* 1015 * The channel is either already halted or it hasn't 1016 * started yet. In DMA mode, the transfer may halt if 1017 * it finishes normally or a condition occurs that 1018 * requires driver intervention. Don't want to halt 1019 * the channel again. In either Slave or DMA mode, 1020 * it's possible that the transfer has been assigned 1021 * to a channel, but not started yet when an URB is 1022 * dequeued. Don't want to halt a channel that hasn't 1023 * started yet. 1024 */ 1025 return; 1026 } 1027 } 1028 if (chan->halt_pending) { 1029 /* 1030 * A halt has already been issued for this channel. This might 1031 * happen when a transfer is aborted by a higher level in 1032 * the stack. 1033 */ 1034 dev_vdbg(hsotg->dev, 1035 "*** %s: Channel %d, chan->halt_pending already set ***\n", 1036 __func__, chan->hc_num); 1037 return; 1038 } 1039 1040 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1041 1042 /* No need to set the bit in DDMA for disabling the channel */ 1043 /* TODO check it everywhere channel is disabled */ 1044 if (!hsotg->params.dma_desc_enable) { 1045 if (dbg_hc(chan)) 1046 dev_vdbg(hsotg->dev, "desc DMA disabled\n"); 1047 hcchar |= HCCHAR_CHENA; 1048 } else { 1049 if (dbg_hc(chan)) 1050 dev_dbg(hsotg->dev, "desc DMA enabled\n"); 1051 } 1052 hcchar |= HCCHAR_CHDIS; 1053 1054 if (!hsotg->params.host_dma) { 1055 if (dbg_hc(chan)) 1056 dev_vdbg(hsotg->dev, "DMA not enabled\n"); 1057 hcchar |= HCCHAR_CHENA; 1058 1059 /* Check for space in the request queue to issue the halt */ 1060 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL || 1061 chan->ep_type == USB_ENDPOINT_XFER_BULK) { 1062 dev_vdbg(hsotg->dev, "control/bulk\n"); 1063 nptxsts = dwc2_readl(hsotg->regs + GNPTXSTS); 1064 if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) { 1065 dev_vdbg(hsotg->dev, "Disabling channel\n"); 1066 hcchar &= ~HCCHAR_CHENA; 1067 } 1068 } else { 1069 if (dbg_perio()) 1070 dev_vdbg(hsotg->dev, "isoc/intr\n"); 1071 hptxsts = dwc2_readl(hsotg->regs + HPTXSTS); 1072 if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 || 1073 hsotg->queuing_high_bandwidth) { 1074 if (dbg_perio()) 1075 dev_vdbg(hsotg->dev, "Disabling channel\n"); 1076 hcchar &= ~HCCHAR_CHENA; 1077 } 1078 } 1079 } else { 1080 if (dbg_hc(chan)) 1081 dev_vdbg(hsotg->dev, "DMA enabled\n"); 1082 } 1083 1084 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1085 chan->halt_status = halt_status; 1086 1087 if (hcchar & HCCHAR_CHENA) { 1088 if (dbg_hc(chan)) 1089 dev_vdbg(hsotg->dev, "Channel enabled\n"); 1090 chan->halt_pending = 1; 1091 chan->halt_on_queue = 0; 1092 } else { 1093 if (dbg_hc(chan)) 1094 dev_vdbg(hsotg->dev, "Channel disabled\n"); 1095 chan->halt_on_queue = 1; 1096 } 1097 1098 if (dbg_hc(chan)) { 1099 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1100 chan->hc_num); 1101 dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n", 1102 hcchar); 1103 dev_vdbg(hsotg->dev, " halt_pending: %d\n", 1104 chan->halt_pending); 1105 dev_vdbg(hsotg->dev, " halt_on_queue: %d\n", 1106 chan->halt_on_queue); 1107 dev_vdbg(hsotg->dev, " halt_status: %d\n", 1108 chan->halt_status); 1109 } 1110 } 1111 1112 /** 1113 * dwc2_hc_cleanup() - Clears the transfer state for a host channel 1114 * 1115 * @hsotg: Programming view of DWC_otg controller 1116 * @chan: Identifies the host channel to clean up 1117 * 1118 * This function is normally called after a transfer is done and the host 1119 * channel is being released 1120 */ 1121 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) 1122 { 1123 u32 hcintmsk; 1124 1125 chan->xfer_started = 0; 1126 1127 list_del_init(&chan->split_order_list_entry); 1128 1129 /* 1130 * Clear channel interrupt enables and any unhandled channel interrupt 1131 * conditions 1132 */ 1133 dwc2_writel(0, hsotg->regs + HCINTMSK(chan->hc_num)); 1134 hcintmsk = 0xffffffff; 1135 hcintmsk &= ~HCINTMSK_RESERVED14_31; 1136 dwc2_writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num)); 1137 } 1138 1139 /** 1140 * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in 1141 * which frame a periodic transfer should occur 1142 * 1143 * @hsotg: Programming view of DWC_otg controller 1144 * @chan: Identifies the host channel to set up and its properties 1145 * @hcchar: Current value of the HCCHAR register for the specified host channel 1146 * 1147 * This function has no effect on non-periodic transfers 1148 */ 1149 static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg, 1150 struct dwc2_host_chan *chan, u32 *hcchar) 1151 { 1152 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1153 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1154 int host_speed; 1155 int xfer_ns; 1156 int xfer_us; 1157 int bytes_in_fifo; 1158 u16 fifo_space; 1159 u16 frame_number; 1160 u16 wire_frame; 1161 1162 /* 1163 * Try to figure out if we're an even or odd frame. If we set 1164 * even and the current frame number is even the the transfer 1165 * will happen immediately. Similar if both are odd. If one is 1166 * even and the other is odd then the transfer will happen when 1167 * the frame number ticks. 1168 * 1169 * There's a bit of a balancing act to get this right. 1170 * Sometimes we may want to send data in the current frame (AK 1171 * right away). We might want to do this if the frame number 1172 * _just_ ticked, but we might also want to do this in order 1173 * to continue a split transaction that happened late in a 1174 * microframe (so we didn't know to queue the next transfer 1175 * until the frame number had ticked). The problem is that we 1176 * need a lot of knowledge to know if there's actually still 1177 * time to send things or if it would be better to wait until 1178 * the next frame. 1179 * 1180 * We can look at how much time is left in the current frame 1181 * and make a guess about whether we'll have time to transfer. 1182 * We'll do that. 1183 */ 1184 1185 /* Get speed host is running at */ 1186 host_speed = (chan->speed != USB_SPEED_HIGH && 1187 !chan->do_split) ? chan->speed : USB_SPEED_HIGH; 1188 1189 /* See how many bytes are in the periodic FIFO right now */ 1190 fifo_space = (dwc2_readl(hsotg->regs + HPTXSTS) & 1191 TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT; 1192 bytes_in_fifo = sizeof(u32) * 1193 (hsotg->params.host_perio_tx_fifo_size - 1194 fifo_space); 1195 1196 /* 1197 * Roughly estimate bus time for everything in the periodic 1198 * queue + our new transfer. This is "rough" because we're 1199 * using a function that makes takes into account IN/OUT 1200 * and INT/ISO and we're just slamming in one value for all 1201 * transfers. This should be an over-estimate and that should 1202 * be OK, but we can probably tighten it. 1203 */ 1204 xfer_ns = usb_calc_bus_time(host_speed, false, false, 1205 chan->xfer_len + bytes_in_fifo); 1206 xfer_us = NS_TO_US(xfer_ns); 1207 1208 /* See what frame number we'll be at by the time we finish */ 1209 frame_number = dwc2_hcd_get_future_frame_number(hsotg, xfer_us); 1210 1211 /* This is when we were scheduled to be on the wire */ 1212 wire_frame = dwc2_frame_num_inc(chan->qh->next_active_frame, 1); 1213 1214 /* 1215 * If we'd finish _after_ the frame we're scheduled in then 1216 * it's hopeless. Just schedule right away and hope for the 1217 * best. Note that it _might_ be wise to call back into the 1218 * scheduler to pick a better frame, but this is better than 1219 * nothing. 1220 */ 1221 if (dwc2_frame_num_gt(frame_number, wire_frame)) { 1222 dwc2_sch_vdbg(hsotg, 1223 "QH=%p EO MISS fr=%04x=>%04x (%+d)\n", 1224 chan->qh, wire_frame, frame_number, 1225 dwc2_frame_num_dec(frame_number, 1226 wire_frame)); 1227 wire_frame = frame_number; 1228 1229 /* 1230 * We picked a different frame number; communicate this 1231 * back to the scheduler so it doesn't try to schedule 1232 * another in the same frame. 1233 * 1234 * Remember that next_active_frame is 1 before the wire 1235 * frame. 1236 */ 1237 chan->qh->next_active_frame = 1238 dwc2_frame_num_dec(frame_number, 1); 1239 } 1240 1241 if (wire_frame & 1) 1242 *hcchar |= HCCHAR_ODDFRM; 1243 else 1244 *hcchar &= ~HCCHAR_ODDFRM; 1245 } 1246 } 1247 1248 static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan) 1249 { 1250 /* Set up the initial PID for the transfer */ 1251 if (chan->speed == USB_SPEED_HIGH) { 1252 if (chan->ep_is_in) { 1253 if (chan->multi_count == 1) 1254 chan->data_pid_start = DWC2_HC_PID_DATA0; 1255 else if (chan->multi_count == 2) 1256 chan->data_pid_start = DWC2_HC_PID_DATA1; 1257 else 1258 chan->data_pid_start = DWC2_HC_PID_DATA2; 1259 } else { 1260 if (chan->multi_count == 1) 1261 chan->data_pid_start = DWC2_HC_PID_DATA0; 1262 else 1263 chan->data_pid_start = DWC2_HC_PID_MDATA; 1264 } 1265 } else { 1266 chan->data_pid_start = DWC2_HC_PID_DATA0; 1267 } 1268 } 1269 1270 /** 1271 * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with 1272 * the Host Channel 1273 * 1274 * @hsotg: Programming view of DWC_otg controller 1275 * @chan: Information needed to initialize the host channel 1276 * 1277 * This function should only be called in Slave mode. For a channel associated 1278 * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel 1279 * associated with a periodic EP, the periodic Tx FIFO is written. 1280 * 1281 * Upon return the xfer_buf and xfer_count fields in chan are incremented by 1282 * the number of bytes written to the Tx FIFO. 1283 */ 1284 static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg, 1285 struct dwc2_host_chan *chan) 1286 { 1287 u32 i; 1288 u32 remaining_count; 1289 u32 byte_count; 1290 u32 dword_count; 1291 u32 __iomem *data_fifo; 1292 u32 *data_buf = (u32 *)chan->xfer_buf; 1293 1294 if (dbg_hc(chan)) 1295 dev_vdbg(hsotg->dev, "%s()\n", __func__); 1296 1297 data_fifo = (u32 __iomem *)(hsotg->regs + HCFIFO(chan->hc_num)); 1298 1299 remaining_count = chan->xfer_len - chan->xfer_count; 1300 if (remaining_count > chan->max_packet) 1301 byte_count = chan->max_packet; 1302 else 1303 byte_count = remaining_count; 1304 1305 dword_count = (byte_count + 3) / 4; 1306 1307 if (((unsigned long)data_buf & 0x3) == 0) { 1308 /* xfer_buf is DWORD aligned */ 1309 for (i = 0; i < dword_count; i++, data_buf++) 1310 dwc2_writel(*data_buf, data_fifo); 1311 } else { 1312 /* xfer_buf is not DWORD aligned */ 1313 for (i = 0; i < dword_count; i++, data_buf++) { 1314 u32 data = data_buf[0] | data_buf[1] << 8 | 1315 data_buf[2] << 16 | data_buf[3] << 24; 1316 dwc2_writel(data, data_fifo); 1317 } 1318 } 1319 1320 chan->xfer_count += byte_count; 1321 chan->xfer_buf += byte_count; 1322 } 1323 1324 /** 1325 * dwc2_hc_do_ping() - Starts a PING transfer 1326 * 1327 * @hsotg: Programming view of DWC_otg controller 1328 * @chan: Information needed to initialize the host channel 1329 * 1330 * This function should only be called in Slave mode. The Do Ping bit is set in 1331 * the HCTSIZ register, then the channel is enabled. 1332 */ 1333 static void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, 1334 struct dwc2_host_chan *chan) 1335 { 1336 u32 hcchar; 1337 u32 hctsiz; 1338 1339 if (dbg_hc(chan)) 1340 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1341 chan->hc_num); 1342 1343 hctsiz = TSIZ_DOPNG; 1344 hctsiz |= 1 << TSIZ_PKTCNT_SHIFT; 1345 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); 1346 1347 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1348 hcchar |= HCCHAR_CHENA; 1349 hcchar &= ~HCCHAR_CHDIS; 1350 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1351 } 1352 1353 /** 1354 * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host 1355 * channel and starts the transfer 1356 * 1357 * @hsotg: Programming view of DWC_otg controller 1358 * @chan: Information needed to initialize the host channel. The xfer_len value 1359 * may be reduced to accommodate the max widths of the XferSize and 1360 * PktCnt fields in the HCTSIZn register. The multi_count value may be 1361 * changed to reflect the final xfer_len value. 1362 * 1363 * This function may be called in either Slave mode or DMA mode. In Slave mode, 1364 * the caller must ensure that there is sufficient space in the request queue 1365 * and Tx Data FIFO. 1366 * 1367 * For an OUT transfer in Slave mode, it loads a data packet into the 1368 * appropriate FIFO. If necessary, additional data packets are loaded in the 1369 * Host ISR. 1370 * 1371 * For an IN transfer in Slave mode, a data packet is requested. The data 1372 * packets are unloaded from the Rx FIFO in the Host ISR. If necessary, 1373 * additional data packets are requested in the Host ISR. 1374 * 1375 * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ 1376 * register along with a packet count of 1 and the channel is enabled. This 1377 * causes a single PING transaction to occur. Other fields in HCTSIZ are 1378 * simply set to 0 since no data transfer occurs in this case. 1379 * 1380 * For a PING transfer in DMA mode, the HCTSIZ register is initialized with 1381 * all the information required to perform the subsequent data transfer. In 1382 * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the 1383 * controller performs the entire PING protocol, then starts the data 1384 * transfer. 1385 */ 1386 static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 1387 struct dwc2_host_chan *chan) 1388 { 1389 u32 max_hc_xfer_size = hsotg->params.max_transfer_size; 1390 u16 max_hc_pkt_count = hsotg->params.max_packet_count; 1391 u32 hcchar; 1392 u32 hctsiz = 0; 1393 u16 num_packets; 1394 u32 ec_mc; 1395 1396 if (dbg_hc(chan)) 1397 dev_vdbg(hsotg->dev, "%s()\n", __func__); 1398 1399 if (chan->do_ping) { 1400 if (!hsotg->params.host_dma) { 1401 if (dbg_hc(chan)) 1402 dev_vdbg(hsotg->dev, "ping, no DMA\n"); 1403 dwc2_hc_do_ping(hsotg, chan); 1404 chan->xfer_started = 1; 1405 return; 1406 } 1407 1408 if (dbg_hc(chan)) 1409 dev_vdbg(hsotg->dev, "ping, DMA\n"); 1410 1411 hctsiz |= TSIZ_DOPNG; 1412 } 1413 1414 if (chan->do_split) { 1415 if (dbg_hc(chan)) 1416 dev_vdbg(hsotg->dev, "split\n"); 1417 num_packets = 1; 1418 1419 if (chan->complete_split && !chan->ep_is_in) 1420 /* 1421 * For CSPLIT OUT Transfer, set the size to 0 so the 1422 * core doesn't expect any data written to the FIFO 1423 */ 1424 chan->xfer_len = 0; 1425 else if (chan->ep_is_in || chan->xfer_len > chan->max_packet) 1426 chan->xfer_len = chan->max_packet; 1427 else if (!chan->ep_is_in && chan->xfer_len > 188) 1428 chan->xfer_len = 188; 1429 1430 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT & 1431 TSIZ_XFERSIZE_MASK; 1432 1433 /* For split set ec_mc for immediate retries */ 1434 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1435 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1436 ec_mc = 3; 1437 else 1438 ec_mc = 1; 1439 } else { 1440 if (dbg_hc(chan)) 1441 dev_vdbg(hsotg->dev, "no split\n"); 1442 /* 1443 * Ensure that the transfer length and packet count will fit 1444 * in the widths allocated for them in the HCTSIZn register 1445 */ 1446 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1447 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1448 /* 1449 * Make sure the transfer size is no larger than one 1450 * (micro)frame's worth of data. (A check was done 1451 * when the periodic transfer was accepted to ensure 1452 * that a (micro)frame's worth of data can be 1453 * programmed into a channel.) 1454 */ 1455 u32 max_periodic_len = 1456 chan->multi_count * chan->max_packet; 1457 1458 if (chan->xfer_len > max_periodic_len) 1459 chan->xfer_len = max_periodic_len; 1460 } else if (chan->xfer_len > max_hc_xfer_size) { 1461 /* 1462 * Make sure that xfer_len is a multiple of max packet 1463 * size 1464 */ 1465 chan->xfer_len = 1466 max_hc_xfer_size - chan->max_packet + 1; 1467 } 1468 1469 if (chan->xfer_len > 0) { 1470 num_packets = (chan->xfer_len + chan->max_packet - 1) / 1471 chan->max_packet; 1472 if (num_packets > max_hc_pkt_count) { 1473 num_packets = max_hc_pkt_count; 1474 chan->xfer_len = num_packets * chan->max_packet; 1475 } 1476 } else { 1477 /* Need 1 packet for transfer length of 0 */ 1478 num_packets = 1; 1479 } 1480 1481 if (chan->ep_is_in) 1482 /* 1483 * Always program an integral # of max packets for IN 1484 * transfers 1485 */ 1486 chan->xfer_len = num_packets * chan->max_packet; 1487 1488 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1489 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1490 /* 1491 * Make sure that the multi_count field matches the 1492 * actual transfer length 1493 */ 1494 chan->multi_count = num_packets; 1495 1496 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1497 dwc2_set_pid_isoc(chan); 1498 1499 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT & 1500 TSIZ_XFERSIZE_MASK; 1501 1502 /* The ec_mc gets the multi_count for non-split */ 1503 ec_mc = chan->multi_count; 1504 } 1505 1506 chan->start_pkt_count = num_packets; 1507 hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK; 1508 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & 1509 TSIZ_SC_MC_PID_MASK; 1510 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); 1511 if (dbg_hc(chan)) { 1512 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n", 1513 hctsiz, chan->hc_num); 1514 1515 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1516 chan->hc_num); 1517 dev_vdbg(hsotg->dev, " Xfer Size: %d\n", 1518 (hctsiz & TSIZ_XFERSIZE_MASK) >> 1519 TSIZ_XFERSIZE_SHIFT); 1520 dev_vdbg(hsotg->dev, " Num Pkts: %d\n", 1521 (hctsiz & TSIZ_PKTCNT_MASK) >> 1522 TSIZ_PKTCNT_SHIFT); 1523 dev_vdbg(hsotg->dev, " Start PID: %d\n", 1524 (hctsiz & TSIZ_SC_MC_PID_MASK) >> 1525 TSIZ_SC_MC_PID_SHIFT); 1526 } 1527 1528 if (hsotg->params.host_dma) { 1529 dwc2_writel((u32)chan->xfer_dma, 1530 hsotg->regs + HCDMA(chan->hc_num)); 1531 if (dbg_hc(chan)) 1532 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n", 1533 (unsigned long)chan->xfer_dma, chan->hc_num); 1534 } 1535 1536 /* Start the split */ 1537 if (chan->do_split) { 1538 u32 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num)); 1539 1540 hcsplt |= HCSPLT_SPLTENA; 1541 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num)); 1542 } 1543 1544 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1545 hcchar &= ~HCCHAR_MULTICNT_MASK; 1546 hcchar |= (ec_mc << HCCHAR_MULTICNT_SHIFT) & HCCHAR_MULTICNT_MASK; 1547 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); 1548 1549 if (hcchar & HCCHAR_CHDIS) 1550 dev_warn(hsotg->dev, 1551 "%s: chdis set, channel %d, hcchar 0x%08x\n", 1552 __func__, chan->hc_num, hcchar); 1553 1554 /* Set host channel enable after all other setup is complete */ 1555 hcchar |= HCCHAR_CHENA; 1556 hcchar &= ~HCCHAR_CHDIS; 1557 1558 if (dbg_hc(chan)) 1559 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", 1560 (hcchar & HCCHAR_MULTICNT_MASK) >> 1561 HCCHAR_MULTICNT_SHIFT); 1562 1563 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1564 if (dbg_hc(chan)) 1565 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, 1566 chan->hc_num); 1567 1568 chan->xfer_started = 1; 1569 chan->requests++; 1570 1571 if (!hsotg->params.host_dma && 1572 !chan->ep_is_in && chan->xfer_len > 0) 1573 /* Load OUT packet into the appropriate Tx FIFO */ 1574 dwc2_hc_write_packet(hsotg, chan); 1575 } 1576 1577 /** 1578 * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a 1579 * host channel and starts the transfer in Descriptor DMA mode 1580 * 1581 * @hsotg: Programming view of DWC_otg controller 1582 * @chan: Information needed to initialize the host channel 1583 * 1584 * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set. 1585 * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field 1586 * with micro-frame bitmap. 1587 * 1588 * Initializes HCDMA register with descriptor list address and CTD value then 1589 * starts the transfer via enabling the channel. 1590 */ 1591 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 1592 struct dwc2_host_chan *chan) 1593 { 1594 u32 hcchar; 1595 u32 hctsiz = 0; 1596 1597 if (chan->do_ping) 1598 hctsiz |= TSIZ_DOPNG; 1599 1600 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1601 dwc2_set_pid_isoc(chan); 1602 1603 /* Packet Count and Xfer Size are not used in Descriptor DMA mode */ 1604 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & 1605 TSIZ_SC_MC_PID_MASK; 1606 1607 /* 0 - 1 descriptor, 1 - 2 descriptors, etc */ 1608 hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK; 1609 1610 /* Non-zero only for high-speed interrupt endpoints */ 1611 hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK; 1612 1613 if (dbg_hc(chan)) { 1614 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1615 chan->hc_num); 1616 dev_vdbg(hsotg->dev, " Start PID: %d\n", 1617 chan->data_pid_start); 1618 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1); 1619 } 1620 1621 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); 1622 1623 dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr, 1624 chan->desc_list_sz, DMA_TO_DEVICE); 1625 1626 dwc2_writel(chan->desc_list_addr, hsotg->regs + HCDMA(chan->hc_num)); 1627 1628 if (dbg_hc(chan)) 1629 dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n", 1630 &chan->desc_list_addr, chan->hc_num); 1631 1632 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1633 hcchar &= ~HCCHAR_MULTICNT_MASK; 1634 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT & 1635 HCCHAR_MULTICNT_MASK; 1636 1637 if (hcchar & HCCHAR_CHDIS) 1638 dev_warn(hsotg->dev, 1639 "%s: chdis set, channel %d, hcchar 0x%08x\n", 1640 __func__, chan->hc_num, hcchar); 1641 1642 /* Set host channel enable after all other setup is complete */ 1643 hcchar |= HCCHAR_CHENA; 1644 hcchar &= ~HCCHAR_CHDIS; 1645 1646 if (dbg_hc(chan)) 1647 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", 1648 (hcchar & HCCHAR_MULTICNT_MASK) >> 1649 HCCHAR_MULTICNT_SHIFT); 1650 1651 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1652 if (dbg_hc(chan)) 1653 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, 1654 chan->hc_num); 1655 1656 chan->xfer_started = 1; 1657 chan->requests++; 1658 } 1659 1660 /** 1661 * dwc2_hc_continue_transfer() - Continues a data transfer that was started by 1662 * a previous call to dwc2_hc_start_transfer() 1663 * 1664 * @hsotg: Programming view of DWC_otg controller 1665 * @chan: Information needed to initialize the host channel 1666 * 1667 * The caller must ensure there is sufficient space in the request queue and Tx 1668 * Data FIFO. This function should only be called in Slave mode. In DMA mode, 1669 * the controller acts autonomously to complete transfers programmed to a host 1670 * channel. 1671 * 1672 * For an OUT transfer, a new data packet is loaded into the appropriate FIFO 1673 * if there is any data remaining to be queued. For an IN transfer, another 1674 * data packet is always requested. For the SETUP phase of a control transfer, 1675 * this function does nothing. 1676 * 1677 * Return: 1 if a new request is queued, 0 if no more requests are required 1678 * for this transfer 1679 */ 1680 static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, 1681 struct dwc2_host_chan *chan) 1682 { 1683 if (dbg_hc(chan)) 1684 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1685 chan->hc_num); 1686 1687 if (chan->do_split) 1688 /* SPLITs always queue just once per channel */ 1689 return 0; 1690 1691 if (chan->data_pid_start == DWC2_HC_PID_SETUP) 1692 /* SETUPs are queued only once since they can't be NAK'd */ 1693 return 0; 1694 1695 if (chan->ep_is_in) { 1696 /* 1697 * Always queue another request for other IN transfers. If 1698 * back-to-back INs are issued and NAKs are received for both, 1699 * the driver may still be processing the first NAK when the 1700 * second NAK is received. When the interrupt handler clears 1701 * the NAK interrupt for the first NAK, the second NAK will 1702 * not be seen. So we can't depend on the NAK interrupt 1703 * handler to requeue a NAK'd request. Instead, IN requests 1704 * are issued each time this function is called. When the 1705 * transfer completes, the extra requests for the channel will 1706 * be flushed. 1707 */ 1708 u32 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1709 1710 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); 1711 hcchar |= HCCHAR_CHENA; 1712 hcchar &= ~HCCHAR_CHDIS; 1713 if (dbg_hc(chan)) 1714 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n", 1715 hcchar); 1716 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1717 chan->requests++; 1718 return 1; 1719 } 1720 1721 /* OUT transfers */ 1722 1723 if (chan->xfer_count < chan->xfer_len) { 1724 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1725 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1726 u32 hcchar = dwc2_readl(hsotg->regs + 1727 HCCHAR(chan->hc_num)); 1728 1729 dwc2_hc_set_even_odd_frame(hsotg, chan, 1730 &hcchar); 1731 } 1732 1733 /* Load OUT packet into the appropriate Tx FIFO */ 1734 dwc2_hc_write_packet(hsotg, chan); 1735 chan->requests++; 1736 return 1; 1737 } 1738 1739 return 0; 1740 } 1741 1742 /* 1743 * ========================================================================= 1744 * HCD 1745 * ========================================================================= 1746 */ 1747 1748 /* 1749 * Processes all the URBs in a single list of QHs. Completes them with 1750 * -ETIMEDOUT and frees the QTD. 1751 * 1752 * Must be called with interrupt disabled and spinlock held 1753 */ 1754 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg, 1755 struct list_head *qh_list) 1756 { 1757 struct dwc2_qh *qh, *qh_tmp; 1758 struct dwc2_qtd *qtd, *qtd_tmp; 1759 1760 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 1761 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 1762 qtd_list_entry) { 1763 dwc2_host_complete(hsotg, qtd, -ECONNRESET); 1764 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 1765 } 1766 } 1767 } 1768 1769 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg, 1770 struct list_head *qh_list) 1771 { 1772 struct dwc2_qtd *qtd, *qtd_tmp; 1773 struct dwc2_qh *qh, *qh_tmp; 1774 unsigned long flags; 1775 1776 if (!qh_list->next) 1777 /* The list hasn't been initialized yet */ 1778 return; 1779 1780 spin_lock_irqsave(&hsotg->lock, flags); 1781 1782 /* Ensure there are no QTDs or URBs left */ 1783 dwc2_kill_urbs_in_qh_list(hsotg, qh_list); 1784 1785 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 1786 dwc2_hcd_qh_unlink(hsotg, qh); 1787 1788 /* Free each QTD in the QH's QTD list */ 1789 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 1790 qtd_list_entry) 1791 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 1792 1793 if (qh->channel && qh->channel->qh == qh) 1794 qh->channel->qh = NULL; 1795 1796 spin_unlock_irqrestore(&hsotg->lock, flags); 1797 dwc2_hcd_qh_free(hsotg, qh); 1798 spin_lock_irqsave(&hsotg->lock, flags); 1799 } 1800 1801 spin_unlock_irqrestore(&hsotg->lock, flags); 1802 } 1803 1804 /* 1805 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic 1806 * and periodic schedules. The QTD associated with each URB is removed from 1807 * the schedule and freed. This function may be called when a disconnect is 1808 * detected or when the HCD is being stopped. 1809 * 1810 * Must be called with interrupt disabled and spinlock held 1811 */ 1812 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg) 1813 { 1814 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive); 1815 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active); 1816 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive); 1817 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready); 1818 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned); 1819 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued); 1820 } 1821 1822 /** 1823 * dwc2_hcd_start() - Starts the HCD when switching to Host mode 1824 * 1825 * @hsotg: Pointer to struct dwc2_hsotg 1826 */ 1827 void dwc2_hcd_start(struct dwc2_hsotg *hsotg) 1828 { 1829 u32 hprt0; 1830 1831 if (hsotg->op_state == OTG_STATE_B_HOST) { 1832 /* 1833 * Reset the port. During a HNP mode switch the reset 1834 * needs to occur within 1ms and have a duration of at 1835 * least 50ms. 1836 */ 1837 hprt0 = dwc2_read_hprt0(hsotg); 1838 hprt0 |= HPRT0_RST; 1839 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1840 } 1841 1842 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work, 1843 msecs_to_jiffies(50)); 1844 } 1845 1846 /* Must be called with interrupt disabled and spinlock held */ 1847 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg) 1848 { 1849 int num_channels = hsotg->params.host_channels; 1850 struct dwc2_host_chan *channel; 1851 u32 hcchar; 1852 int i; 1853 1854 if (!hsotg->params.host_dma) { 1855 /* Flush out any channel requests in slave mode */ 1856 for (i = 0; i < num_channels; i++) { 1857 channel = hsotg->hc_ptr_array[i]; 1858 if (!list_empty(&channel->hc_list_entry)) 1859 continue; 1860 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 1861 if (hcchar & HCCHAR_CHENA) { 1862 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR); 1863 hcchar |= HCCHAR_CHDIS; 1864 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 1865 } 1866 } 1867 } 1868 1869 for (i = 0; i < num_channels; i++) { 1870 channel = hsotg->hc_ptr_array[i]; 1871 if (!list_empty(&channel->hc_list_entry)) 1872 continue; 1873 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 1874 if (hcchar & HCCHAR_CHENA) { 1875 /* Halt the channel */ 1876 hcchar |= HCCHAR_CHDIS; 1877 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 1878 } 1879 1880 dwc2_hc_cleanup(hsotg, channel); 1881 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list); 1882 /* 1883 * Added for Descriptor DMA to prevent channel double cleanup in 1884 * release_channel_ddma(), which is called from ep_disable when 1885 * device disconnects 1886 */ 1887 channel->qh = NULL; 1888 } 1889 /* All channels have been freed, mark them available */ 1890 if (hsotg->params.uframe_sched) { 1891 hsotg->available_host_channels = 1892 hsotg->params.host_channels; 1893 } else { 1894 hsotg->non_periodic_channels = 0; 1895 hsotg->periodic_channels = 0; 1896 } 1897 } 1898 1899 /** 1900 * dwc2_hcd_connect() - Handles connect of the HCD 1901 * 1902 * @hsotg: Pointer to struct dwc2_hsotg 1903 * 1904 * Must be called with interrupt disabled and spinlock held 1905 */ 1906 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) 1907 { 1908 if (hsotg->lx_state != DWC2_L0) 1909 usb_hcd_resume_root_hub(hsotg->priv); 1910 1911 hsotg->flags.b.port_connect_status_change = 1; 1912 hsotg->flags.b.port_connect_status = 1; 1913 } 1914 1915 /** 1916 * dwc2_hcd_disconnect() - Handles disconnect of the HCD 1917 * 1918 * @hsotg: Pointer to struct dwc2_hsotg 1919 * @force: If true, we won't try to reconnect even if we see device connected. 1920 * 1921 * Must be called with interrupt disabled and spinlock held 1922 */ 1923 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) 1924 { 1925 u32 intr; 1926 u32 hprt0; 1927 1928 /* Set status flags for the hub driver */ 1929 hsotg->flags.b.port_connect_status_change = 1; 1930 hsotg->flags.b.port_connect_status = 0; 1931 1932 /* 1933 * Shutdown any transfers in process by clearing the Tx FIFO Empty 1934 * interrupt mask and status bits and disabling subsequent host 1935 * channel interrupts. 1936 */ 1937 intr = dwc2_readl(hsotg->regs + GINTMSK); 1938 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT); 1939 dwc2_writel(intr, hsotg->regs + GINTMSK); 1940 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT; 1941 dwc2_writel(intr, hsotg->regs + GINTSTS); 1942 1943 /* 1944 * Turn off the vbus power only if the core has transitioned to device 1945 * mode. If still in host mode, need to keep power on to detect a 1946 * reconnection. 1947 */ 1948 if (dwc2_is_device_mode(hsotg)) { 1949 if (hsotg->op_state != OTG_STATE_A_SUSPEND) { 1950 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n"); 1951 dwc2_writel(0, hsotg->regs + HPRT0); 1952 } 1953 1954 dwc2_disable_host_interrupts(hsotg); 1955 } 1956 1957 /* Respond with an error status to all URBs in the schedule */ 1958 dwc2_kill_all_urbs(hsotg); 1959 1960 if (dwc2_is_host_mode(hsotg)) 1961 /* Clean up any host channels that were in use */ 1962 dwc2_hcd_cleanup_channels(hsotg); 1963 1964 dwc2_host_disconnect(hsotg); 1965 1966 /* 1967 * Add an extra check here to see if we're actually connected but 1968 * we don't have a detection interrupt pending. This can happen if: 1969 * 1. hardware sees connect 1970 * 2. hardware sees disconnect 1971 * 3. hardware sees connect 1972 * 4. dwc2_port_intr() - clears connect interrupt 1973 * 5. dwc2_handle_common_intr() - calls here 1974 * 1975 * Without the extra check here we will end calling disconnect 1976 * and won't get any future interrupts to handle the connect. 1977 */ 1978 if (!force) { 1979 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 1980 if (!(hprt0 & HPRT0_CONNDET) && (hprt0 & HPRT0_CONNSTS)) 1981 dwc2_hcd_connect(hsotg); 1982 } 1983 } 1984 1985 /** 1986 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup 1987 * 1988 * @hsotg: Pointer to struct dwc2_hsotg 1989 */ 1990 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg) 1991 { 1992 if (hsotg->bus_suspended) { 1993 hsotg->flags.b.port_suspend_change = 1; 1994 usb_hcd_resume_root_hub(hsotg->priv); 1995 } 1996 1997 if (hsotg->lx_state == DWC2_L1) 1998 hsotg->flags.b.port_l1_change = 1; 1999 } 2000 2001 /** 2002 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner 2003 * 2004 * @hsotg: Pointer to struct dwc2_hsotg 2005 * 2006 * Must be called with interrupt disabled and spinlock held 2007 */ 2008 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg) 2009 { 2010 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n"); 2011 2012 /* 2013 * The root hub should be disconnected before this function is called. 2014 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue) 2015 * and the QH lists (via ..._hcd_endpoint_disable). 2016 */ 2017 2018 /* Turn off all host-specific interrupts */ 2019 dwc2_disable_host_interrupts(hsotg); 2020 2021 /* Turn off the vbus power */ 2022 dev_dbg(hsotg->dev, "PortPower off\n"); 2023 dwc2_writel(0, hsotg->regs + HPRT0); 2024 } 2025 2026 /* Caller must hold driver lock */ 2027 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, 2028 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh, 2029 struct dwc2_qtd *qtd) 2030 { 2031 u32 intr_mask; 2032 int retval; 2033 int dev_speed; 2034 2035 if (!hsotg->flags.b.port_connect_status) { 2036 /* No longer connected */ 2037 dev_err(hsotg->dev, "Not connected\n"); 2038 return -ENODEV; 2039 } 2040 2041 dev_speed = dwc2_host_get_speed(hsotg, urb->priv); 2042 2043 /* Some configurations cannot support LS traffic on a FS root port */ 2044 if ((dev_speed == USB_SPEED_LOW) && 2045 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) && 2046 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) { 2047 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 2048 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 2049 2050 if (prtspd == HPRT0_SPD_FULL_SPEED) 2051 return -ENODEV; 2052 } 2053 2054 if (!qtd) 2055 return -EINVAL; 2056 2057 dwc2_hcd_qtd_init(qtd, urb); 2058 retval = dwc2_hcd_qtd_add(hsotg, qtd, qh); 2059 if (retval) { 2060 dev_err(hsotg->dev, 2061 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n", 2062 retval); 2063 return retval; 2064 } 2065 2066 intr_mask = dwc2_readl(hsotg->regs + GINTMSK); 2067 if (!(intr_mask & GINTSTS_SOF)) { 2068 enum dwc2_transaction_type tr_type; 2069 2070 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK && 2071 !(qtd->urb->flags & URB_GIVEBACK_ASAP)) 2072 /* 2073 * Do not schedule SG transactions until qtd has 2074 * URB_GIVEBACK_ASAP set 2075 */ 2076 return 0; 2077 2078 tr_type = dwc2_hcd_select_transactions(hsotg); 2079 if (tr_type != DWC2_TRANSACTION_NONE) 2080 dwc2_hcd_queue_transactions(hsotg, tr_type); 2081 } 2082 2083 return 0; 2084 } 2085 2086 /* Must be called with interrupt disabled and spinlock held */ 2087 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg, 2088 struct dwc2_hcd_urb *urb) 2089 { 2090 struct dwc2_qh *qh; 2091 struct dwc2_qtd *urb_qtd; 2092 2093 urb_qtd = urb->qtd; 2094 if (!urb_qtd) { 2095 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n"); 2096 return -EINVAL; 2097 } 2098 2099 qh = urb_qtd->qh; 2100 if (!qh) { 2101 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n"); 2102 return -EINVAL; 2103 } 2104 2105 urb->priv = NULL; 2106 2107 if (urb_qtd->in_process && qh->channel) { 2108 dwc2_dump_channel_info(hsotg, qh->channel); 2109 2110 /* The QTD is in process (it has been assigned to a channel) */ 2111 if (hsotg->flags.b.port_connect_status) 2112 /* 2113 * If still connected (i.e. in host mode), halt the 2114 * channel so it can be used for other transfers. If 2115 * no longer connected, the host registers can't be 2116 * written to halt the channel since the core is in 2117 * device mode. 2118 */ 2119 dwc2_hc_halt(hsotg, qh->channel, 2120 DWC2_HC_XFER_URB_DEQUEUE); 2121 } 2122 2123 /* 2124 * Free the QTD and clean up the associated QH. Leave the QH in the 2125 * schedule if it has any remaining QTDs. 2126 */ 2127 if (!hsotg->params.dma_desc_enable) { 2128 u8 in_process = urb_qtd->in_process; 2129 2130 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 2131 if (in_process) { 2132 dwc2_hcd_qh_deactivate(hsotg, qh, 0); 2133 qh->channel = NULL; 2134 } else if (list_empty(&qh->qtd_list)) { 2135 dwc2_hcd_qh_unlink(hsotg, qh); 2136 } 2137 } else { 2138 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 2139 } 2140 2141 return 0; 2142 } 2143 2144 /* Must NOT be called with interrupt disabled or spinlock held */ 2145 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg, 2146 struct usb_host_endpoint *ep, int retry) 2147 { 2148 struct dwc2_qtd *qtd, *qtd_tmp; 2149 struct dwc2_qh *qh; 2150 unsigned long flags; 2151 int rc; 2152 2153 spin_lock_irqsave(&hsotg->lock, flags); 2154 2155 qh = ep->hcpriv; 2156 if (!qh) { 2157 rc = -EINVAL; 2158 goto err; 2159 } 2160 2161 while (!list_empty(&qh->qtd_list) && retry--) { 2162 if (retry == 0) { 2163 dev_err(hsotg->dev, 2164 "## timeout in dwc2_hcd_endpoint_disable() ##\n"); 2165 rc = -EBUSY; 2166 goto err; 2167 } 2168 2169 spin_unlock_irqrestore(&hsotg->lock, flags); 2170 msleep(20); 2171 spin_lock_irqsave(&hsotg->lock, flags); 2172 qh = ep->hcpriv; 2173 if (!qh) { 2174 rc = -EINVAL; 2175 goto err; 2176 } 2177 } 2178 2179 dwc2_hcd_qh_unlink(hsotg, qh); 2180 2181 /* Free each QTD in the QH's QTD list */ 2182 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) 2183 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 2184 2185 ep->hcpriv = NULL; 2186 2187 if (qh->channel && qh->channel->qh == qh) 2188 qh->channel->qh = NULL; 2189 2190 spin_unlock_irqrestore(&hsotg->lock, flags); 2191 2192 dwc2_hcd_qh_free(hsotg, qh); 2193 2194 return 0; 2195 2196 err: 2197 ep->hcpriv = NULL; 2198 spin_unlock_irqrestore(&hsotg->lock, flags); 2199 2200 return rc; 2201 } 2202 2203 /* Must be called with interrupt disabled and spinlock held */ 2204 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg, 2205 struct usb_host_endpoint *ep) 2206 { 2207 struct dwc2_qh *qh = ep->hcpriv; 2208 2209 if (!qh) 2210 return -EINVAL; 2211 2212 qh->data_toggle = DWC2_HC_PID_DATA0; 2213 2214 return 0; 2215 } 2216 2217 /** 2218 * dwc2_core_init() - Initializes the DWC_otg controller registers and 2219 * prepares the core for device mode or host mode operation 2220 * 2221 * @hsotg: Programming view of the DWC_otg controller 2222 * @initial_setup: If true then this is the first init for this instance. 2223 */ 2224 static int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup) 2225 { 2226 u32 usbcfg, otgctl; 2227 int retval; 2228 2229 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); 2230 2231 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 2232 2233 /* Set ULPI External VBUS bit if needed */ 2234 usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV; 2235 if (hsotg->params.phy_ulpi_ext_vbus) 2236 usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV; 2237 2238 /* Set external TS Dline pulsing bit if needed */ 2239 usbcfg &= ~GUSBCFG_TERMSELDLPULSE; 2240 if (hsotg->params.ts_dline) 2241 usbcfg |= GUSBCFG_TERMSELDLPULSE; 2242 2243 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 2244 2245 /* 2246 * Reset the Controller 2247 * 2248 * We only need to reset the controller if this is a re-init. 2249 * For the first init we know for sure that earlier code reset us (it 2250 * needed to in order to properly detect various parameters). 2251 */ 2252 if (!initial_setup) { 2253 retval = dwc2_core_reset_and_force_dr_mode(hsotg); 2254 if (retval) { 2255 dev_err(hsotg->dev, "%s(): Reset failed, aborting\n", 2256 __func__); 2257 return retval; 2258 } 2259 } 2260 2261 /* 2262 * This needs to happen in FS mode before any other programming occurs 2263 */ 2264 retval = dwc2_phy_init(hsotg, initial_setup); 2265 if (retval) 2266 return retval; 2267 2268 /* Program the GAHBCFG Register */ 2269 retval = dwc2_gahbcfg_init(hsotg); 2270 if (retval) 2271 return retval; 2272 2273 /* Program the GUSBCFG register */ 2274 dwc2_gusbcfg_init(hsotg); 2275 2276 /* Program the GOTGCTL register */ 2277 otgctl = dwc2_readl(hsotg->regs + GOTGCTL); 2278 otgctl &= ~GOTGCTL_OTGVER; 2279 dwc2_writel(otgctl, hsotg->regs + GOTGCTL); 2280 2281 /* Clear the SRP success bit for FS-I2c */ 2282 hsotg->srp_success = 0; 2283 2284 /* Enable common interrupts */ 2285 dwc2_enable_common_interrupts(hsotg); 2286 2287 /* 2288 * Do device or host initialization based on mode during PCD and 2289 * HCD initialization 2290 */ 2291 if (dwc2_is_host_mode(hsotg)) { 2292 dev_dbg(hsotg->dev, "Host Mode\n"); 2293 hsotg->op_state = OTG_STATE_A_HOST; 2294 } else { 2295 dev_dbg(hsotg->dev, "Device Mode\n"); 2296 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 2297 } 2298 2299 return 0; 2300 } 2301 2302 /** 2303 * dwc2_core_host_init() - Initializes the DWC_otg controller registers for 2304 * Host mode 2305 * 2306 * @hsotg: Programming view of DWC_otg controller 2307 * 2308 * This function flushes the Tx and Rx FIFOs and flushes any entries in the 2309 * request queues. Host channels are reset to ensure that they are ready for 2310 * performing transfers. 2311 */ 2312 static void dwc2_core_host_init(struct dwc2_hsotg *hsotg) 2313 { 2314 u32 hcfg, hfir, otgctl; 2315 2316 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); 2317 2318 /* Restart the Phy Clock */ 2319 dwc2_writel(0, hsotg->regs + PCGCTL); 2320 2321 /* Initialize Host Configuration Register */ 2322 dwc2_init_fs_ls_pclk_sel(hsotg); 2323 if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL || 2324 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) { 2325 hcfg = dwc2_readl(hsotg->regs + HCFG); 2326 hcfg |= HCFG_FSLSSUPP; 2327 dwc2_writel(hcfg, hsotg->regs + HCFG); 2328 } 2329 2330 /* 2331 * This bit allows dynamic reloading of the HFIR register during 2332 * runtime. This bit needs to be programmed during initial configuration 2333 * and its value must not be changed during runtime. 2334 */ 2335 if (hsotg->params.reload_ctl) { 2336 hfir = dwc2_readl(hsotg->regs + HFIR); 2337 hfir |= HFIR_RLDCTRL; 2338 dwc2_writel(hfir, hsotg->regs + HFIR); 2339 } 2340 2341 if (hsotg->params.dma_desc_enable) { 2342 u32 op_mode = hsotg->hw_params.op_mode; 2343 2344 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a || 2345 !hsotg->hw_params.dma_desc_enable || 2346 op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE || 2347 op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE || 2348 op_mode == GHWCFG2_OP_MODE_UNDEFINED) { 2349 dev_err(hsotg->dev, 2350 "Hardware does not support descriptor DMA mode -\n"); 2351 dev_err(hsotg->dev, 2352 "falling back to buffer DMA mode.\n"); 2353 hsotg->params.dma_desc_enable = false; 2354 } else { 2355 hcfg = dwc2_readl(hsotg->regs + HCFG); 2356 hcfg |= HCFG_DESCDMA; 2357 dwc2_writel(hcfg, hsotg->regs + HCFG); 2358 } 2359 } 2360 2361 /* Configure data FIFO sizes */ 2362 dwc2_config_fifos(hsotg); 2363 2364 /* TODO - check this */ 2365 /* Clear Host Set HNP Enable in the OTG Control Register */ 2366 otgctl = dwc2_readl(hsotg->regs + GOTGCTL); 2367 otgctl &= ~GOTGCTL_HSTSETHNPEN; 2368 dwc2_writel(otgctl, hsotg->regs + GOTGCTL); 2369 2370 /* Make sure the FIFOs are flushed */ 2371 dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */); 2372 dwc2_flush_rx_fifo(hsotg); 2373 2374 /* Clear Host Set HNP Enable in the OTG Control Register */ 2375 otgctl = dwc2_readl(hsotg->regs + GOTGCTL); 2376 otgctl &= ~GOTGCTL_HSTSETHNPEN; 2377 dwc2_writel(otgctl, hsotg->regs + GOTGCTL); 2378 2379 if (!hsotg->params.dma_desc_enable) { 2380 int num_channels, i; 2381 u32 hcchar; 2382 2383 /* Flush out any leftover queued requests */ 2384 num_channels = hsotg->params.host_channels; 2385 for (i = 0; i < num_channels; i++) { 2386 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 2387 hcchar &= ~HCCHAR_CHENA; 2388 hcchar |= HCCHAR_CHDIS; 2389 hcchar &= ~HCCHAR_EPDIR; 2390 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 2391 } 2392 2393 /* Halt all channels to put them into a known state */ 2394 for (i = 0; i < num_channels; i++) { 2395 int count = 0; 2396 2397 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 2398 hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS; 2399 hcchar &= ~HCCHAR_EPDIR; 2400 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 2401 dev_dbg(hsotg->dev, "%s: Halt channel %d\n", 2402 __func__, i); 2403 do { 2404 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 2405 if (++count > 1000) { 2406 dev_err(hsotg->dev, 2407 "Unable to clear enable on channel %d\n", 2408 i); 2409 break; 2410 } 2411 udelay(1); 2412 } while (hcchar & HCCHAR_CHENA); 2413 } 2414 } 2415 2416 /* Turn on the vbus power */ 2417 dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state); 2418 if (hsotg->op_state == OTG_STATE_A_HOST) { 2419 u32 hprt0 = dwc2_read_hprt0(hsotg); 2420 2421 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n", 2422 !!(hprt0 & HPRT0_PWR)); 2423 if (!(hprt0 & HPRT0_PWR)) { 2424 hprt0 |= HPRT0_PWR; 2425 dwc2_writel(hprt0, hsotg->regs + HPRT0); 2426 } 2427 } 2428 2429 dwc2_enable_host_interrupts(hsotg); 2430 } 2431 2432 /* 2433 * Initializes dynamic portions of the DWC_otg HCD state 2434 * 2435 * Must be called with interrupt disabled and spinlock held 2436 */ 2437 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg) 2438 { 2439 struct dwc2_host_chan *chan, *chan_tmp; 2440 int num_channels; 2441 int i; 2442 2443 hsotg->flags.d32 = 0; 2444 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active; 2445 2446 if (hsotg->params.uframe_sched) { 2447 hsotg->available_host_channels = 2448 hsotg->params.host_channels; 2449 } else { 2450 hsotg->non_periodic_channels = 0; 2451 hsotg->periodic_channels = 0; 2452 } 2453 2454 /* 2455 * Put all channels in the free channel list and clean up channel 2456 * states 2457 */ 2458 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list, 2459 hc_list_entry) 2460 list_del_init(&chan->hc_list_entry); 2461 2462 num_channels = hsotg->params.host_channels; 2463 for (i = 0; i < num_channels; i++) { 2464 chan = hsotg->hc_ptr_array[i]; 2465 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list); 2466 dwc2_hc_cleanup(hsotg, chan); 2467 } 2468 2469 /* Initialize the DWC core for host mode operation */ 2470 dwc2_core_host_init(hsotg); 2471 } 2472 2473 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg, 2474 struct dwc2_host_chan *chan, 2475 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 2476 { 2477 int hub_addr, hub_port; 2478 2479 chan->do_split = 1; 2480 chan->xact_pos = qtd->isoc_split_pos; 2481 chan->complete_split = qtd->complete_split; 2482 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port); 2483 chan->hub_addr = (u8)hub_addr; 2484 chan->hub_port = (u8)hub_port; 2485 } 2486 2487 static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg, 2488 struct dwc2_host_chan *chan, 2489 struct dwc2_qtd *qtd) 2490 { 2491 struct dwc2_hcd_urb *urb = qtd->urb; 2492 struct dwc2_hcd_iso_packet_desc *frame_desc; 2493 2494 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) { 2495 case USB_ENDPOINT_XFER_CONTROL: 2496 chan->ep_type = USB_ENDPOINT_XFER_CONTROL; 2497 2498 switch (qtd->control_phase) { 2499 case DWC2_CONTROL_SETUP: 2500 dev_vdbg(hsotg->dev, " Control setup transaction\n"); 2501 chan->do_ping = 0; 2502 chan->ep_is_in = 0; 2503 chan->data_pid_start = DWC2_HC_PID_SETUP; 2504 if (hsotg->params.host_dma) 2505 chan->xfer_dma = urb->setup_dma; 2506 else 2507 chan->xfer_buf = urb->setup_packet; 2508 chan->xfer_len = 8; 2509 break; 2510 2511 case DWC2_CONTROL_DATA: 2512 dev_vdbg(hsotg->dev, " Control data transaction\n"); 2513 chan->data_pid_start = qtd->data_toggle; 2514 break; 2515 2516 case DWC2_CONTROL_STATUS: 2517 /* 2518 * Direction is opposite of data direction or IN if no 2519 * data 2520 */ 2521 dev_vdbg(hsotg->dev, " Control status transaction\n"); 2522 if (urb->length == 0) 2523 chan->ep_is_in = 1; 2524 else 2525 chan->ep_is_in = 2526 dwc2_hcd_is_pipe_out(&urb->pipe_info); 2527 if (chan->ep_is_in) 2528 chan->do_ping = 0; 2529 chan->data_pid_start = DWC2_HC_PID_DATA1; 2530 chan->xfer_len = 0; 2531 if (hsotg->params.host_dma) 2532 chan->xfer_dma = hsotg->status_buf_dma; 2533 else 2534 chan->xfer_buf = hsotg->status_buf; 2535 break; 2536 } 2537 break; 2538 2539 case USB_ENDPOINT_XFER_BULK: 2540 chan->ep_type = USB_ENDPOINT_XFER_BULK; 2541 break; 2542 2543 case USB_ENDPOINT_XFER_INT: 2544 chan->ep_type = USB_ENDPOINT_XFER_INT; 2545 break; 2546 2547 case USB_ENDPOINT_XFER_ISOC: 2548 chan->ep_type = USB_ENDPOINT_XFER_ISOC; 2549 if (hsotg->params.dma_desc_enable) 2550 break; 2551 2552 frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; 2553 frame_desc->status = 0; 2554 2555 if (hsotg->params.host_dma) { 2556 chan->xfer_dma = urb->dma; 2557 chan->xfer_dma += frame_desc->offset + 2558 qtd->isoc_split_offset; 2559 } else { 2560 chan->xfer_buf = urb->buf; 2561 chan->xfer_buf += frame_desc->offset + 2562 qtd->isoc_split_offset; 2563 } 2564 2565 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset; 2566 2567 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) { 2568 if (chan->xfer_len <= 188) 2569 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL; 2570 else 2571 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN; 2572 } 2573 break; 2574 } 2575 } 2576 2577 #define DWC2_USB_DMA_ALIGN 4 2578 2579 struct dma_aligned_buffer { 2580 void *kmalloc_ptr; 2581 void *old_xfer_buffer; 2582 u8 data[0]; 2583 }; 2584 2585 static void dwc2_free_dma_aligned_buffer(struct urb *urb) 2586 { 2587 struct dma_aligned_buffer *temp; 2588 2589 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER)) 2590 return; 2591 2592 temp = container_of(urb->transfer_buffer, 2593 struct dma_aligned_buffer, data); 2594 2595 if (usb_urb_dir_in(urb)) 2596 memcpy(temp->old_xfer_buffer, temp->data, 2597 urb->transfer_buffer_length); 2598 urb->transfer_buffer = temp->old_xfer_buffer; 2599 kfree(temp->kmalloc_ptr); 2600 2601 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER; 2602 } 2603 2604 static int dwc2_alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags) 2605 { 2606 struct dma_aligned_buffer *temp, *kmalloc_ptr; 2607 size_t kmalloc_size; 2608 2609 if (urb->num_sgs || urb->sg || 2610 urb->transfer_buffer_length == 0 || 2611 !((uintptr_t)urb->transfer_buffer & (DWC2_USB_DMA_ALIGN - 1))) 2612 return 0; 2613 2614 /* Allocate a buffer with enough padding for alignment */ 2615 kmalloc_size = urb->transfer_buffer_length + 2616 sizeof(struct dma_aligned_buffer) + DWC2_USB_DMA_ALIGN - 1; 2617 2618 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags); 2619 if (!kmalloc_ptr) 2620 return -ENOMEM; 2621 2622 /* Position our struct dma_aligned_buffer such that data is aligned */ 2623 temp = PTR_ALIGN(kmalloc_ptr + 1, DWC2_USB_DMA_ALIGN) - 1; 2624 temp->kmalloc_ptr = kmalloc_ptr; 2625 temp->old_xfer_buffer = urb->transfer_buffer; 2626 if (usb_urb_dir_out(urb)) 2627 memcpy(temp->data, urb->transfer_buffer, 2628 urb->transfer_buffer_length); 2629 urb->transfer_buffer = temp->data; 2630 2631 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER; 2632 2633 return 0; 2634 } 2635 2636 static int dwc2_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, 2637 gfp_t mem_flags) 2638 { 2639 int ret; 2640 2641 /* We assume setup_dma is always aligned; warn if not */ 2642 WARN_ON_ONCE(urb->setup_dma && 2643 (urb->setup_dma & (DWC2_USB_DMA_ALIGN - 1))); 2644 2645 ret = dwc2_alloc_dma_aligned_buffer(urb, mem_flags); 2646 if (ret) 2647 return ret; 2648 2649 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); 2650 if (ret) 2651 dwc2_free_dma_aligned_buffer(urb); 2652 2653 return ret; 2654 } 2655 2656 static void dwc2_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb) 2657 { 2658 usb_hcd_unmap_urb_for_dma(hcd, urb); 2659 dwc2_free_dma_aligned_buffer(urb); 2660 } 2661 2662 /** 2663 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host 2664 * channel and initializes the host channel to perform the transactions. The 2665 * host channel is removed from the free list. 2666 * 2667 * @hsotg: The HCD state structure 2668 * @qh: Transactions from the first QTD for this QH are selected and assigned 2669 * to a free host channel 2670 */ 2671 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 2672 { 2673 struct dwc2_host_chan *chan; 2674 struct dwc2_hcd_urb *urb; 2675 struct dwc2_qtd *qtd; 2676 2677 if (dbg_qh(qh)) 2678 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh); 2679 2680 if (list_empty(&qh->qtd_list)) { 2681 dev_dbg(hsotg->dev, "No QTDs in QH list\n"); 2682 return -ENOMEM; 2683 } 2684 2685 if (list_empty(&hsotg->free_hc_list)) { 2686 dev_dbg(hsotg->dev, "No free channel to assign\n"); 2687 return -ENOMEM; 2688 } 2689 2690 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan, 2691 hc_list_entry); 2692 2693 /* Remove host channel from free list */ 2694 list_del_init(&chan->hc_list_entry); 2695 2696 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry); 2697 urb = qtd->urb; 2698 qh->channel = chan; 2699 qtd->in_process = 1; 2700 2701 /* 2702 * Use usb_pipedevice to determine device address. This address is 2703 * 0 before the SET_ADDRESS command and the correct address afterward. 2704 */ 2705 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info); 2706 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info); 2707 chan->speed = qh->dev_speed; 2708 chan->max_packet = dwc2_max_packet(qh->maxp); 2709 2710 chan->xfer_started = 0; 2711 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS; 2712 chan->error_state = (qtd->error_count > 0); 2713 chan->halt_on_queue = 0; 2714 chan->halt_pending = 0; 2715 chan->requests = 0; 2716 2717 /* 2718 * The following values may be modified in the transfer type section 2719 * below. The xfer_len value may be reduced when the transfer is 2720 * started to accommodate the max widths of the XferSize and PktCnt 2721 * fields in the HCTSIZn register. 2722 */ 2723 2724 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0); 2725 if (chan->ep_is_in) 2726 chan->do_ping = 0; 2727 else 2728 chan->do_ping = qh->ping_state; 2729 2730 chan->data_pid_start = qh->data_toggle; 2731 chan->multi_count = 1; 2732 2733 if (urb->actual_length > urb->length && 2734 !dwc2_hcd_is_pipe_in(&urb->pipe_info)) 2735 urb->actual_length = urb->length; 2736 2737 if (hsotg->params.host_dma) 2738 chan->xfer_dma = urb->dma + urb->actual_length; 2739 else 2740 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length; 2741 2742 chan->xfer_len = urb->length - urb->actual_length; 2743 chan->xfer_count = 0; 2744 2745 /* Set the split attributes if required */ 2746 if (qh->do_split) 2747 dwc2_hc_init_split(hsotg, chan, qtd, urb); 2748 else 2749 chan->do_split = 0; 2750 2751 /* Set the transfer attributes */ 2752 dwc2_hc_init_xfer(hsotg, chan, qtd); 2753 2754 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 2755 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 2756 /* 2757 * This value may be modified when the transfer is started 2758 * to reflect the actual transfer length 2759 */ 2760 chan->multi_count = dwc2_hb_mult(qh->maxp); 2761 2762 if (hsotg->params.dma_desc_enable) { 2763 chan->desc_list_addr = qh->desc_list_dma; 2764 chan->desc_list_sz = qh->desc_list_sz; 2765 } 2766 2767 dwc2_hc_init(hsotg, chan); 2768 chan->qh = qh; 2769 2770 return 0; 2771 } 2772 2773 /** 2774 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer 2775 * schedule and assigns them to available host channels. Called from the HCD 2776 * interrupt handler functions. 2777 * 2778 * @hsotg: The HCD state structure 2779 * 2780 * Return: The types of new transactions that were assigned to host channels 2781 */ 2782 enum dwc2_transaction_type dwc2_hcd_select_transactions( 2783 struct dwc2_hsotg *hsotg) 2784 { 2785 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE; 2786 struct list_head *qh_ptr; 2787 struct dwc2_qh *qh; 2788 int num_channels; 2789 2790 #ifdef DWC2_DEBUG_SOF 2791 dev_vdbg(hsotg->dev, " Select Transactions\n"); 2792 #endif 2793 2794 /* Process entries in the periodic ready list */ 2795 qh_ptr = hsotg->periodic_sched_ready.next; 2796 while (qh_ptr != &hsotg->periodic_sched_ready) { 2797 if (list_empty(&hsotg->free_hc_list)) 2798 break; 2799 if (hsotg->params.uframe_sched) { 2800 if (hsotg->available_host_channels <= 1) 2801 break; 2802 hsotg->available_host_channels--; 2803 } 2804 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 2805 if (dwc2_assign_and_init_hc(hsotg, qh)) 2806 break; 2807 2808 /* 2809 * Move the QH from the periodic ready schedule to the 2810 * periodic assigned schedule 2811 */ 2812 qh_ptr = qh_ptr->next; 2813 list_move_tail(&qh->qh_list_entry, 2814 &hsotg->periodic_sched_assigned); 2815 ret_val = DWC2_TRANSACTION_PERIODIC; 2816 } 2817 2818 /* 2819 * Process entries in the inactive portion of the non-periodic 2820 * schedule. Some free host channels may not be used if they are 2821 * reserved for periodic transfers. 2822 */ 2823 num_channels = hsotg->params.host_channels; 2824 qh_ptr = hsotg->non_periodic_sched_inactive.next; 2825 while (qh_ptr != &hsotg->non_periodic_sched_inactive) { 2826 if (!hsotg->params.uframe_sched && 2827 hsotg->non_periodic_channels >= num_channels - 2828 hsotg->periodic_channels) 2829 break; 2830 if (list_empty(&hsotg->free_hc_list)) 2831 break; 2832 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 2833 if (hsotg->params.uframe_sched) { 2834 if (hsotg->available_host_channels < 1) 2835 break; 2836 hsotg->available_host_channels--; 2837 } 2838 2839 if (dwc2_assign_and_init_hc(hsotg, qh)) 2840 break; 2841 2842 /* 2843 * Move the QH from the non-periodic inactive schedule to the 2844 * non-periodic active schedule 2845 */ 2846 qh_ptr = qh_ptr->next; 2847 list_move_tail(&qh->qh_list_entry, 2848 &hsotg->non_periodic_sched_active); 2849 2850 if (ret_val == DWC2_TRANSACTION_NONE) 2851 ret_val = DWC2_TRANSACTION_NON_PERIODIC; 2852 else 2853 ret_val = DWC2_TRANSACTION_ALL; 2854 2855 if (!hsotg->params.uframe_sched) 2856 hsotg->non_periodic_channels++; 2857 } 2858 2859 return ret_val; 2860 } 2861 2862 /** 2863 * dwc2_queue_transaction() - Attempts to queue a single transaction request for 2864 * a host channel associated with either a periodic or non-periodic transfer 2865 * 2866 * @hsotg: The HCD state structure 2867 * @chan: Host channel descriptor associated with either a periodic or 2868 * non-periodic transfer 2869 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO 2870 * for periodic transfers or the non-periodic Tx FIFO 2871 * for non-periodic transfers 2872 * 2873 * Return: 1 if a request is queued and more requests may be needed to 2874 * complete the transfer, 0 if no more requests are required for this 2875 * transfer, -1 if there is insufficient space in the Tx FIFO 2876 * 2877 * This function assumes that there is space available in the appropriate 2878 * request queue. For an OUT transfer or SETUP transaction in Slave mode, 2879 * it checks whether space is available in the appropriate Tx FIFO. 2880 * 2881 * Must be called with interrupt disabled and spinlock held 2882 */ 2883 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg, 2884 struct dwc2_host_chan *chan, 2885 u16 fifo_dwords_avail) 2886 { 2887 int retval = 0; 2888 2889 if (chan->do_split) 2890 /* Put ourselves on the list to keep order straight */ 2891 list_move_tail(&chan->split_order_list_entry, 2892 &hsotg->split_order); 2893 2894 if (hsotg->params.host_dma) { 2895 if (hsotg->params.dma_desc_enable) { 2896 if (!chan->xfer_started || 2897 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 2898 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh); 2899 chan->qh->ping_state = 0; 2900 } 2901 } else if (!chan->xfer_started) { 2902 dwc2_hc_start_transfer(hsotg, chan); 2903 chan->qh->ping_state = 0; 2904 } 2905 } else if (chan->halt_pending) { 2906 /* Don't queue a request if the channel has been halted */ 2907 } else if (chan->halt_on_queue) { 2908 dwc2_hc_halt(hsotg, chan, chan->halt_status); 2909 } else if (chan->do_ping) { 2910 if (!chan->xfer_started) 2911 dwc2_hc_start_transfer(hsotg, chan); 2912 } else if (!chan->ep_is_in || 2913 chan->data_pid_start == DWC2_HC_PID_SETUP) { 2914 if ((fifo_dwords_avail * 4) >= chan->max_packet) { 2915 if (!chan->xfer_started) { 2916 dwc2_hc_start_transfer(hsotg, chan); 2917 retval = 1; 2918 } else { 2919 retval = dwc2_hc_continue_transfer(hsotg, chan); 2920 } 2921 } else { 2922 retval = -1; 2923 } 2924 } else { 2925 if (!chan->xfer_started) { 2926 dwc2_hc_start_transfer(hsotg, chan); 2927 retval = 1; 2928 } else { 2929 retval = dwc2_hc_continue_transfer(hsotg, chan); 2930 } 2931 } 2932 2933 return retval; 2934 } 2935 2936 /* 2937 * Processes periodic channels for the next frame and queues transactions for 2938 * these channels to the DWC_otg controller. After queueing transactions, the 2939 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions 2940 * to queue as Periodic Tx FIFO or request queue space becomes available. 2941 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. 2942 * 2943 * Must be called with interrupt disabled and spinlock held 2944 */ 2945 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) 2946 { 2947 struct list_head *qh_ptr; 2948 struct dwc2_qh *qh; 2949 u32 tx_status; 2950 u32 fspcavail; 2951 u32 gintmsk; 2952 int status; 2953 bool no_queue_space = false; 2954 bool no_fifo_space = false; 2955 u32 qspcavail; 2956 2957 /* If empty list then just adjust interrupt enables */ 2958 if (list_empty(&hsotg->periodic_sched_assigned)) 2959 goto exit; 2960 2961 if (dbg_perio()) 2962 dev_vdbg(hsotg->dev, "Queue periodic transactions\n"); 2963 2964 tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 2965 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 2966 TXSTS_QSPCAVAIL_SHIFT; 2967 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 2968 TXSTS_FSPCAVAIL_SHIFT; 2969 2970 if (dbg_perio()) { 2971 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n", 2972 qspcavail); 2973 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n", 2974 fspcavail); 2975 } 2976 2977 qh_ptr = hsotg->periodic_sched_assigned.next; 2978 while (qh_ptr != &hsotg->periodic_sched_assigned) { 2979 tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 2980 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 2981 TXSTS_QSPCAVAIL_SHIFT; 2982 if (qspcavail == 0) { 2983 no_queue_space = true; 2984 break; 2985 } 2986 2987 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 2988 if (!qh->channel) { 2989 qh_ptr = qh_ptr->next; 2990 continue; 2991 } 2992 2993 /* Make sure EP's TT buffer is clean before queueing qtds */ 2994 if (qh->tt_buffer_dirty) { 2995 qh_ptr = qh_ptr->next; 2996 continue; 2997 } 2998 2999 /* 3000 * Set a flag if we're queuing high-bandwidth in slave mode. 3001 * The flag prevents any halts to get into the request queue in 3002 * the middle of multiple high-bandwidth packets getting queued. 3003 */ 3004 if (!hsotg->params.host_dma && 3005 qh->channel->multi_count > 1) 3006 hsotg->queuing_high_bandwidth = 1; 3007 3008 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3009 TXSTS_FSPCAVAIL_SHIFT; 3010 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 3011 if (status < 0) { 3012 no_fifo_space = true; 3013 break; 3014 } 3015 3016 /* 3017 * In Slave mode, stay on the current transfer until there is 3018 * nothing more to do or the high-bandwidth request count is 3019 * reached. In DMA mode, only need to queue one request. The 3020 * controller automatically handles multiple packets for 3021 * high-bandwidth transfers. 3022 */ 3023 if (hsotg->params.host_dma || status == 0 || 3024 qh->channel->requests == qh->channel->multi_count) { 3025 qh_ptr = qh_ptr->next; 3026 /* 3027 * Move the QH from the periodic assigned schedule to 3028 * the periodic queued schedule 3029 */ 3030 list_move_tail(&qh->qh_list_entry, 3031 &hsotg->periodic_sched_queued); 3032 3033 /* done queuing high bandwidth */ 3034 hsotg->queuing_high_bandwidth = 0; 3035 } 3036 } 3037 3038 exit: 3039 if (no_queue_space || no_fifo_space || 3040 (!hsotg->params.host_dma && 3041 !list_empty(&hsotg->periodic_sched_assigned))) { 3042 /* 3043 * May need to queue more transactions as the request 3044 * queue or Tx FIFO empties. Enable the periodic Tx 3045 * FIFO empty interrupt. (Always use the half-empty 3046 * level to ensure that new requests are loaded as 3047 * soon as possible.) 3048 */ 3049 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3050 if (!(gintmsk & GINTSTS_PTXFEMP)) { 3051 gintmsk |= GINTSTS_PTXFEMP; 3052 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3053 } 3054 } else { 3055 /* 3056 * Disable the Tx FIFO empty interrupt since there are 3057 * no more transactions that need to be queued right 3058 * now. This function is called from interrupt 3059 * handlers to queue more transactions as transfer 3060 * states change. 3061 */ 3062 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3063 if (gintmsk & GINTSTS_PTXFEMP) { 3064 gintmsk &= ~GINTSTS_PTXFEMP; 3065 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3066 } 3067 } 3068 } 3069 3070 /* 3071 * Processes active non-periodic channels and queues transactions for these 3072 * channels to the DWC_otg controller. After queueing transactions, the NP Tx 3073 * FIFO Empty interrupt is enabled if there are more transactions to queue as 3074 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx 3075 * FIFO Empty interrupt is disabled. 3076 * 3077 * Must be called with interrupt disabled and spinlock held 3078 */ 3079 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg) 3080 { 3081 struct list_head *orig_qh_ptr; 3082 struct dwc2_qh *qh; 3083 u32 tx_status; 3084 u32 qspcavail; 3085 u32 fspcavail; 3086 u32 gintmsk; 3087 int status; 3088 int no_queue_space = 0; 3089 int no_fifo_space = 0; 3090 int more_to_do = 0; 3091 3092 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n"); 3093 3094 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 3095 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3096 TXSTS_QSPCAVAIL_SHIFT; 3097 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3098 TXSTS_FSPCAVAIL_SHIFT; 3099 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n", 3100 qspcavail); 3101 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n", 3102 fspcavail); 3103 3104 /* 3105 * Keep track of the starting point. Skip over the start-of-list 3106 * entry. 3107 */ 3108 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active) 3109 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 3110 orig_qh_ptr = hsotg->non_periodic_qh_ptr; 3111 3112 /* 3113 * Process once through the active list or until no more space is 3114 * available in the request queue or the Tx FIFO 3115 */ 3116 do { 3117 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 3118 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3119 TXSTS_QSPCAVAIL_SHIFT; 3120 if (!hsotg->params.host_dma && qspcavail == 0) { 3121 no_queue_space = 1; 3122 break; 3123 } 3124 3125 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh, 3126 qh_list_entry); 3127 if (!qh->channel) 3128 goto next; 3129 3130 /* Make sure EP's TT buffer is clean before queueing qtds */ 3131 if (qh->tt_buffer_dirty) 3132 goto next; 3133 3134 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3135 TXSTS_FSPCAVAIL_SHIFT; 3136 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 3137 3138 if (status > 0) { 3139 more_to_do = 1; 3140 } else if (status < 0) { 3141 no_fifo_space = 1; 3142 break; 3143 } 3144 next: 3145 /* Advance to next QH, skipping start-of-list entry */ 3146 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 3147 if (hsotg->non_periodic_qh_ptr == 3148 &hsotg->non_periodic_sched_active) 3149 hsotg->non_periodic_qh_ptr = 3150 hsotg->non_periodic_qh_ptr->next; 3151 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr); 3152 3153 if (!hsotg->params.host_dma) { 3154 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 3155 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3156 TXSTS_QSPCAVAIL_SHIFT; 3157 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3158 TXSTS_FSPCAVAIL_SHIFT; 3159 dev_vdbg(hsotg->dev, 3160 " NP Tx Req Queue Space Avail (after queue): %d\n", 3161 qspcavail); 3162 dev_vdbg(hsotg->dev, 3163 " NP Tx FIFO Space Avail (after queue): %d\n", 3164 fspcavail); 3165 3166 if (more_to_do || no_queue_space || no_fifo_space) { 3167 /* 3168 * May need to queue more transactions as the request 3169 * queue or Tx FIFO empties. Enable the non-periodic 3170 * Tx FIFO empty interrupt. (Always use the half-empty 3171 * level to ensure that new requests are loaded as 3172 * soon as possible.) 3173 */ 3174 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3175 gintmsk |= GINTSTS_NPTXFEMP; 3176 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3177 } else { 3178 /* 3179 * Disable the Tx FIFO empty interrupt since there are 3180 * no more transactions that need to be queued right 3181 * now. This function is called from interrupt 3182 * handlers to queue more transactions as transfer 3183 * states change. 3184 */ 3185 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3186 gintmsk &= ~GINTSTS_NPTXFEMP; 3187 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3188 } 3189 } 3190 } 3191 3192 /** 3193 * dwc2_hcd_queue_transactions() - Processes the currently active host channels 3194 * and queues transactions for these channels to the DWC_otg controller. Called 3195 * from the HCD interrupt handler functions. 3196 * 3197 * @hsotg: The HCD state structure 3198 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic, 3199 * or both) 3200 * 3201 * Must be called with interrupt disabled and spinlock held 3202 */ 3203 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 3204 enum dwc2_transaction_type tr_type) 3205 { 3206 #ifdef DWC2_DEBUG_SOF 3207 dev_vdbg(hsotg->dev, "Queue Transactions\n"); 3208 #endif 3209 /* Process host channels associated with periodic transfers */ 3210 if (tr_type == DWC2_TRANSACTION_PERIODIC || 3211 tr_type == DWC2_TRANSACTION_ALL) 3212 dwc2_process_periodic_channels(hsotg); 3213 3214 /* Process host channels associated with non-periodic transfers */ 3215 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC || 3216 tr_type == DWC2_TRANSACTION_ALL) { 3217 if (!list_empty(&hsotg->non_periodic_sched_active)) { 3218 dwc2_process_non_periodic_channels(hsotg); 3219 } else { 3220 /* 3221 * Ensure NP Tx FIFO empty interrupt is disabled when 3222 * there are no non-periodic transfers to process 3223 */ 3224 u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3225 3226 gintmsk &= ~GINTSTS_NPTXFEMP; 3227 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3228 } 3229 } 3230 } 3231 3232 static void dwc2_conn_id_status_change(struct work_struct *work) 3233 { 3234 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 3235 wf_otg); 3236 u32 count = 0; 3237 u32 gotgctl; 3238 unsigned long flags; 3239 3240 dev_dbg(hsotg->dev, "%s()\n", __func__); 3241 3242 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 3243 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl); 3244 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n", 3245 !!(gotgctl & GOTGCTL_CONID_B)); 3246 3247 /* B-Device connector (Device Mode) */ 3248 if (gotgctl & GOTGCTL_CONID_B) { 3249 /* Wait for switch to device mode */ 3250 dev_dbg(hsotg->dev, "connId B\n"); 3251 if (hsotg->bus_suspended) { 3252 dev_info(hsotg->dev, 3253 "Do port resume before switching to device mode\n"); 3254 dwc2_port_resume(hsotg); 3255 } 3256 while (!dwc2_is_device_mode(hsotg)) { 3257 dev_info(hsotg->dev, 3258 "Waiting for Peripheral Mode, Mode=%s\n", 3259 dwc2_is_host_mode(hsotg) ? "Host" : 3260 "Peripheral"); 3261 msleep(20); 3262 /* 3263 * Sometimes the initial GOTGCTRL read is wrong, so 3264 * check it again and jump to host mode if that was 3265 * the case. 3266 */ 3267 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 3268 if (!(gotgctl & GOTGCTL_CONID_B)) 3269 goto host; 3270 if (++count > 250) 3271 break; 3272 } 3273 if (count > 250) 3274 dev_err(hsotg->dev, 3275 "Connection id status change timed out\n"); 3276 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 3277 dwc2_core_init(hsotg, false); 3278 dwc2_enable_global_interrupts(hsotg); 3279 spin_lock_irqsave(&hsotg->lock, flags); 3280 dwc2_hsotg_disconnect(hsotg); 3281 dwc2_hsotg_core_init_disconnected(hsotg, false); 3282 spin_unlock_irqrestore(&hsotg->lock, flags); 3283 dwc2_hsotg_core_connect(hsotg); 3284 } else { 3285 host: 3286 /* A-Device connector (Host Mode) */ 3287 dev_dbg(hsotg->dev, "connId A\n"); 3288 while (!dwc2_is_host_mode(hsotg)) { 3289 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n", 3290 dwc2_is_host_mode(hsotg) ? 3291 "Host" : "Peripheral"); 3292 msleep(20); 3293 if (++count > 250) 3294 break; 3295 } 3296 if (count > 250) 3297 dev_err(hsotg->dev, 3298 "Connection id status change timed out\n"); 3299 hsotg->op_state = OTG_STATE_A_HOST; 3300 3301 /* Initialize the Core for Host mode */ 3302 dwc2_core_init(hsotg, false); 3303 dwc2_enable_global_interrupts(hsotg); 3304 dwc2_hcd_start(hsotg); 3305 } 3306 } 3307 3308 static void dwc2_wakeup_detected(unsigned long data) 3309 { 3310 struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data; 3311 u32 hprt0; 3312 3313 dev_dbg(hsotg->dev, "%s()\n", __func__); 3314 3315 /* 3316 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms 3317 * so that OPT tests pass with all PHYs.) 3318 */ 3319 hprt0 = dwc2_read_hprt0(hsotg); 3320 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0); 3321 hprt0 &= ~HPRT0_RES; 3322 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3323 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n", 3324 dwc2_readl(hsotg->regs + HPRT0)); 3325 3326 dwc2_hcd_rem_wakeup(hsotg); 3327 hsotg->bus_suspended = false; 3328 3329 /* Change to L0 state */ 3330 hsotg->lx_state = DWC2_L0; 3331 } 3332 3333 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg) 3334 { 3335 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 3336 3337 return hcd->self.b_hnp_enable; 3338 } 3339 3340 /* Must NOT be called with interrupt disabled or spinlock held */ 3341 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) 3342 { 3343 unsigned long flags; 3344 u32 hprt0; 3345 u32 pcgctl; 3346 u32 gotgctl; 3347 3348 dev_dbg(hsotg->dev, "%s()\n", __func__); 3349 3350 spin_lock_irqsave(&hsotg->lock, flags); 3351 3352 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) { 3353 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 3354 gotgctl |= GOTGCTL_HSTSETHNPEN; 3355 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL); 3356 hsotg->op_state = OTG_STATE_A_SUSPEND; 3357 } 3358 3359 hprt0 = dwc2_read_hprt0(hsotg); 3360 hprt0 |= HPRT0_SUSP; 3361 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3362 3363 hsotg->bus_suspended = true; 3364 3365 /* 3366 * If hibernation is supported, Phy clock will be suspended 3367 * after registers are backuped. 3368 */ 3369 if (!hsotg->params.hibernation) { 3370 /* Suspend the Phy Clock */ 3371 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 3372 pcgctl |= PCGCTL_STOPPCLK; 3373 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 3374 udelay(10); 3375 } 3376 3377 /* For HNP the bus must be suspended for at least 200ms */ 3378 if (dwc2_host_is_b_hnp_enabled(hsotg)) { 3379 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 3380 pcgctl &= ~PCGCTL_STOPPCLK; 3381 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 3382 3383 spin_unlock_irqrestore(&hsotg->lock, flags); 3384 3385 msleep(200); 3386 } else { 3387 spin_unlock_irqrestore(&hsotg->lock, flags); 3388 } 3389 } 3390 3391 /* Must NOT be called with interrupt disabled or spinlock held */ 3392 static void dwc2_port_resume(struct dwc2_hsotg *hsotg) 3393 { 3394 unsigned long flags; 3395 u32 hprt0; 3396 u32 pcgctl; 3397 3398 spin_lock_irqsave(&hsotg->lock, flags); 3399 3400 /* 3401 * If hibernation is supported, Phy clock is already resumed 3402 * after registers restore. 3403 */ 3404 if (!hsotg->params.hibernation) { 3405 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 3406 pcgctl &= ~PCGCTL_STOPPCLK; 3407 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 3408 spin_unlock_irqrestore(&hsotg->lock, flags); 3409 msleep(20); 3410 spin_lock_irqsave(&hsotg->lock, flags); 3411 } 3412 3413 hprt0 = dwc2_read_hprt0(hsotg); 3414 hprt0 |= HPRT0_RES; 3415 hprt0 &= ~HPRT0_SUSP; 3416 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3417 spin_unlock_irqrestore(&hsotg->lock, flags); 3418 3419 msleep(USB_RESUME_TIMEOUT); 3420 3421 spin_lock_irqsave(&hsotg->lock, flags); 3422 hprt0 = dwc2_read_hprt0(hsotg); 3423 hprt0 &= ~(HPRT0_RES | HPRT0_SUSP); 3424 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3425 hsotg->bus_suspended = false; 3426 spin_unlock_irqrestore(&hsotg->lock, flags); 3427 } 3428 3429 /* Handles hub class-specific requests */ 3430 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, 3431 u16 wvalue, u16 windex, char *buf, u16 wlength) 3432 { 3433 struct usb_hub_descriptor *hub_desc; 3434 int retval = 0; 3435 u32 hprt0; 3436 u32 port_status; 3437 u32 speed; 3438 u32 pcgctl; 3439 3440 switch (typereq) { 3441 case ClearHubFeature: 3442 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue); 3443 3444 switch (wvalue) { 3445 case C_HUB_LOCAL_POWER: 3446 case C_HUB_OVER_CURRENT: 3447 /* Nothing required here */ 3448 break; 3449 3450 default: 3451 retval = -EINVAL; 3452 dev_err(hsotg->dev, 3453 "ClearHubFeature request %1xh unknown\n", 3454 wvalue); 3455 } 3456 break; 3457 3458 case ClearPortFeature: 3459 if (wvalue != USB_PORT_FEAT_L1) 3460 if (!windex || windex > 1) 3461 goto error; 3462 switch (wvalue) { 3463 case USB_PORT_FEAT_ENABLE: 3464 dev_dbg(hsotg->dev, 3465 "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); 3466 hprt0 = dwc2_read_hprt0(hsotg); 3467 hprt0 |= HPRT0_ENA; 3468 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3469 break; 3470 3471 case USB_PORT_FEAT_SUSPEND: 3472 dev_dbg(hsotg->dev, 3473 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); 3474 3475 if (hsotg->bus_suspended) 3476 dwc2_port_resume(hsotg); 3477 break; 3478 3479 case USB_PORT_FEAT_POWER: 3480 dev_dbg(hsotg->dev, 3481 "ClearPortFeature USB_PORT_FEAT_POWER\n"); 3482 hprt0 = dwc2_read_hprt0(hsotg); 3483 hprt0 &= ~HPRT0_PWR; 3484 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3485 break; 3486 3487 case USB_PORT_FEAT_INDICATOR: 3488 dev_dbg(hsotg->dev, 3489 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); 3490 /* Port indicator not supported */ 3491 break; 3492 3493 case USB_PORT_FEAT_C_CONNECTION: 3494 /* 3495 * Clears driver's internal Connect Status Change flag 3496 */ 3497 dev_dbg(hsotg->dev, 3498 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); 3499 hsotg->flags.b.port_connect_status_change = 0; 3500 break; 3501 3502 case USB_PORT_FEAT_C_RESET: 3503 /* Clears driver's internal Port Reset Change flag */ 3504 dev_dbg(hsotg->dev, 3505 "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); 3506 hsotg->flags.b.port_reset_change = 0; 3507 break; 3508 3509 case USB_PORT_FEAT_C_ENABLE: 3510 /* 3511 * Clears the driver's internal Port Enable/Disable 3512 * Change flag 3513 */ 3514 dev_dbg(hsotg->dev, 3515 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); 3516 hsotg->flags.b.port_enable_change = 0; 3517 break; 3518 3519 case USB_PORT_FEAT_C_SUSPEND: 3520 /* 3521 * Clears the driver's internal Port Suspend Change 3522 * flag, which is set when resume signaling on the host 3523 * port is complete 3524 */ 3525 dev_dbg(hsotg->dev, 3526 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); 3527 hsotg->flags.b.port_suspend_change = 0; 3528 break; 3529 3530 case USB_PORT_FEAT_C_PORT_L1: 3531 dev_dbg(hsotg->dev, 3532 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n"); 3533 hsotg->flags.b.port_l1_change = 0; 3534 break; 3535 3536 case USB_PORT_FEAT_C_OVER_CURRENT: 3537 dev_dbg(hsotg->dev, 3538 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); 3539 hsotg->flags.b.port_over_current_change = 0; 3540 break; 3541 3542 default: 3543 retval = -EINVAL; 3544 dev_err(hsotg->dev, 3545 "ClearPortFeature request %1xh unknown or unsupported\n", 3546 wvalue); 3547 } 3548 break; 3549 3550 case GetHubDescriptor: 3551 dev_dbg(hsotg->dev, "GetHubDescriptor\n"); 3552 hub_desc = (struct usb_hub_descriptor *)buf; 3553 hub_desc->bDescLength = 9; 3554 hub_desc->bDescriptorType = USB_DT_HUB; 3555 hub_desc->bNbrPorts = 1; 3556 hub_desc->wHubCharacteristics = 3557 cpu_to_le16(HUB_CHAR_COMMON_LPSM | 3558 HUB_CHAR_INDV_PORT_OCPM); 3559 hub_desc->bPwrOn2PwrGood = 1; 3560 hub_desc->bHubContrCurrent = 0; 3561 hub_desc->u.hs.DeviceRemovable[0] = 0; 3562 hub_desc->u.hs.DeviceRemovable[1] = 0xff; 3563 break; 3564 3565 case GetHubStatus: 3566 dev_dbg(hsotg->dev, "GetHubStatus\n"); 3567 memset(buf, 0, 4); 3568 break; 3569 3570 case GetPortStatus: 3571 dev_vdbg(hsotg->dev, 3572 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex, 3573 hsotg->flags.d32); 3574 if (!windex || windex > 1) 3575 goto error; 3576 3577 port_status = 0; 3578 if (hsotg->flags.b.port_connect_status_change) 3579 port_status |= USB_PORT_STAT_C_CONNECTION << 16; 3580 if (hsotg->flags.b.port_enable_change) 3581 port_status |= USB_PORT_STAT_C_ENABLE << 16; 3582 if (hsotg->flags.b.port_suspend_change) 3583 port_status |= USB_PORT_STAT_C_SUSPEND << 16; 3584 if (hsotg->flags.b.port_l1_change) 3585 port_status |= USB_PORT_STAT_C_L1 << 16; 3586 if (hsotg->flags.b.port_reset_change) 3587 port_status |= USB_PORT_STAT_C_RESET << 16; 3588 if (hsotg->flags.b.port_over_current_change) { 3589 dev_warn(hsotg->dev, "Overcurrent change detected\n"); 3590 port_status |= USB_PORT_STAT_C_OVERCURRENT << 16; 3591 } 3592 3593 if (!hsotg->flags.b.port_connect_status) { 3594 /* 3595 * The port is disconnected, which means the core is 3596 * either in device mode or it soon will be. Just 3597 * return 0's for the remainder of the port status 3598 * since the port register can't be read if the core 3599 * is in device mode. 3600 */ 3601 *(__le32 *)buf = cpu_to_le32(port_status); 3602 break; 3603 } 3604 3605 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 3606 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0); 3607 3608 if (hprt0 & HPRT0_CONNSTS) 3609 port_status |= USB_PORT_STAT_CONNECTION; 3610 if (hprt0 & HPRT0_ENA) 3611 port_status |= USB_PORT_STAT_ENABLE; 3612 if (hprt0 & HPRT0_SUSP) 3613 port_status |= USB_PORT_STAT_SUSPEND; 3614 if (hprt0 & HPRT0_OVRCURRACT) 3615 port_status |= USB_PORT_STAT_OVERCURRENT; 3616 if (hprt0 & HPRT0_RST) 3617 port_status |= USB_PORT_STAT_RESET; 3618 if (hprt0 & HPRT0_PWR) 3619 port_status |= USB_PORT_STAT_POWER; 3620 3621 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 3622 if (speed == HPRT0_SPD_HIGH_SPEED) 3623 port_status |= USB_PORT_STAT_HIGH_SPEED; 3624 else if (speed == HPRT0_SPD_LOW_SPEED) 3625 port_status |= USB_PORT_STAT_LOW_SPEED; 3626 3627 if (hprt0 & HPRT0_TSTCTL_MASK) 3628 port_status |= USB_PORT_STAT_TEST; 3629 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ 3630 3631 if (hsotg->params.dma_desc_fs_enable) { 3632 /* 3633 * Enable descriptor DMA only if a full speed 3634 * device is connected. 3635 */ 3636 if (hsotg->new_connection && 3637 ((port_status & 3638 (USB_PORT_STAT_CONNECTION | 3639 USB_PORT_STAT_HIGH_SPEED | 3640 USB_PORT_STAT_LOW_SPEED)) == 3641 USB_PORT_STAT_CONNECTION)) { 3642 u32 hcfg; 3643 3644 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n"); 3645 hsotg->params.dma_desc_enable = true; 3646 hcfg = dwc2_readl(hsotg->regs + HCFG); 3647 hcfg |= HCFG_DESCDMA; 3648 dwc2_writel(hcfg, hsotg->regs + HCFG); 3649 hsotg->new_connection = false; 3650 } 3651 } 3652 3653 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status); 3654 *(__le32 *)buf = cpu_to_le32(port_status); 3655 break; 3656 3657 case SetHubFeature: 3658 dev_dbg(hsotg->dev, "SetHubFeature\n"); 3659 /* No HUB features supported */ 3660 break; 3661 3662 case SetPortFeature: 3663 dev_dbg(hsotg->dev, "SetPortFeature\n"); 3664 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1)) 3665 goto error; 3666 3667 if (!hsotg->flags.b.port_connect_status) { 3668 /* 3669 * The port is disconnected, which means the core is 3670 * either in device mode or it soon will be. Just 3671 * return without doing anything since the port 3672 * register can't be written if the core is in device 3673 * mode. 3674 */ 3675 break; 3676 } 3677 3678 switch (wvalue) { 3679 case USB_PORT_FEAT_SUSPEND: 3680 dev_dbg(hsotg->dev, 3681 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); 3682 if (windex != hsotg->otg_port) 3683 goto error; 3684 dwc2_port_suspend(hsotg, windex); 3685 break; 3686 3687 case USB_PORT_FEAT_POWER: 3688 dev_dbg(hsotg->dev, 3689 "SetPortFeature - USB_PORT_FEAT_POWER\n"); 3690 hprt0 = dwc2_read_hprt0(hsotg); 3691 hprt0 |= HPRT0_PWR; 3692 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3693 break; 3694 3695 case USB_PORT_FEAT_RESET: 3696 hprt0 = dwc2_read_hprt0(hsotg); 3697 dev_dbg(hsotg->dev, 3698 "SetPortFeature - USB_PORT_FEAT_RESET\n"); 3699 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 3700 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK); 3701 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 3702 /* ??? Original driver does this */ 3703 dwc2_writel(0, hsotg->regs + PCGCTL); 3704 3705 hprt0 = dwc2_read_hprt0(hsotg); 3706 /* Clear suspend bit if resetting from suspend state */ 3707 hprt0 &= ~HPRT0_SUSP; 3708 3709 /* 3710 * When B-Host the Port reset bit is set in the Start 3711 * HCD Callback function, so that the reset is started 3712 * within 1ms of the HNP success interrupt 3713 */ 3714 if (!dwc2_hcd_is_b_host(hsotg)) { 3715 hprt0 |= HPRT0_PWR | HPRT0_RST; 3716 dev_dbg(hsotg->dev, 3717 "In host mode, hprt0=%08x\n", hprt0); 3718 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3719 } 3720 3721 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ 3722 msleep(50); 3723 hprt0 &= ~HPRT0_RST; 3724 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3725 hsotg->lx_state = DWC2_L0; /* Now back to On state */ 3726 break; 3727 3728 case USB_PORT_FEAT_INDICATOR: 3729 dev_dbg(hsotg->dev, 3730 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); 3731 /* Not supported */ 3732 break; 3733 3734 case USB_PORT_FEAT_TEST: 3735 hprt0 = dwc2_read_hprt0(hsotg); 3736 dev_dbg(hsotg->dev, 3737 "SetPortFeature - USB_PORT_FEAT_TEST\n"); 3738 hprt0 &= ~HPRT0_TSTCTL_MASK; 3739 hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT; 3740 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3741 break; 3742 3743 default: 3744 retval = -EINVAL; 3745 dev_err(hsotg->dev, 3746 "SetPortFeature %1xh unknown or unsupported\n", 3747 wvalue); 3748 break; 3749 } 3750 break; 3751 3752 default: 3753 error: 3754 retval = -EINVAL; 3755 dev_dbg(hsotg->dev, 3756 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n", 3757 typereq, windex, wvalue); 3758 break; 3759 } 3760 3761 return retval; 3762 } 3763 3764 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port) 3765 { 3766 int retval; 3767 3768 if (port != 1) 3769 return -EINVAL; 3770 3771 retval = (hsotg->flags.b.port_connect_status_change || 3772 hsotg->flags.b.port_reset_change || 3773 hsotg->flags.b.port_enable_change || 3774 hsotg->flags.b.port_suspend_change || 3775 hsotg->flags.b.port_over_current_change); 3776 3777 if (retval) { 3778 dev_dbg(hsotg->dev, 3779 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n"); 3780 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n", 3781 hsotg->flags.b.port_connect_status_change); 3782 dev_dbg(hsotg->dev, " port_reset_change: %d\n", 3783 hsotg->flags.b.port_reset_change); 3784 dev_dbg(hsotg->dev, " port_enable_change: %d\n", 3785 hsotg->flags.b.port_enable_change); 3786 dev_dbg(hsotg->dev, " port_suspend_change: %d\n", 3787 hsotg->flags.b.port_suspend_change); 3788 dev_dbg(hsotg->dev, " port_over_current_change: %d\n", 3789 hsotg->flags.b.port_over_current_change); 3790 } 3791 3792 return retval; 3793 } 3794 3795 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 3796 { 3797 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM); 3798 3799 #ifdef DWC2_DEBUG_SOF 3800 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n", 3801 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT); 3802 #endif 3803 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 3804 } 3805 3806 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us) 3807 { 3808 u32 hprt = dwc2_readl(hsotg->regs + HPRT0); 3809 u32 hfir = dwc2_readl(hsotg->regs + HFIR); 3810 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM); 3811 unsigned int us_per_frame; 3812 unsigned int frame_number; 3813 unsigned int remaining; 3814 unsigned int interval; 3815 unsigned int phy_clks; 3816 3817 /* High speed has 125 us per (micro) frame; others are 1 ms per */ 3818 us_per_frame = (hprt & HPRT0_SPD_MASK) ? 1000 : 125; 3819 3820 /* Extract fields */ 3821 frame_number = (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 3822 remaining = (hfnum & HFNUM_FRREM_MASK) >> HFNUM_FRREM_SHIFT; 3823 interval = (hfir & HFIR_FRINT_MASK) >> HFIR_FRINT_SHIFT; 3824 3825 /* 3826 * Number of phy clocks since the last tick of the frame number after 3827 * "us" has passed. 3828 */ 3829 phy_clks = (interval - remaining) + 3830 DIV_ROUND_UP(interval * us, us_per_frame); 3831 3832 return dwc2_frame_num_inc(frame_number, phy_clks / interval); 3833 } 3834 3835 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg) 3836 { 3837 return hsotg->op_state == OTG_STATE_B_HOST; 3838 } 3839 3840 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg, 3841 int iso_desc_count, 3842 gfp_t mem_flags) 3843 { 3844 struct dwc2_hcd_urb *urb; 3845 u32 size = sizeof(*urb) + iso_desc_count * 3846 sizeof(struct dwc2_hcd_iso_packet_desc); 3847 3848 urb = kzalloc(size, mem_flags); 3849 if (urb) 3850 urb->packet_count = iso_desc_count; 3851 return urb; 3852 } 3853 3854 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg, 3855 struct dwc2_hcd_urb *urb, u8 dev_addr, 3856 u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps) 3857 { 3858 if (dbg_perio() || 3859 ep_type == USB_ENDPOINT_XFER_BULK || 3860 ep_type == USB_ENDPOINT_XFER_CONTROL) 3861 dev_vdbg(hsotg->dev, 3862 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n", 3863 dev_addr, ep_num, ep_dir, ep_type, mps); 3864 urb->pipe_info.dev_addr = dev_addr; 3865 urb->pipe_info.ep_num = ep_num; 3866 urb->pipe_info.pipe_type = ep_type; 3867 urb->pipe_info.pipe_dir = ep_dir; 3868 urb->pipe_info.mps = mps; 3869 } 3870 3871 /* 3872 * NOTE: This function will be removed once the peripheral controller code 3873 * is integrated and the driver is stable 3874 */ 3875 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg) 3876 { 3877 #ifdef DEBUG 3878 struct dwc2_host_chan *chan; 3879 struct dwc2_hcd_urb *urb; 3880 struct dwc2_qtd *qtd; 3881 int num_channels; 3882 u32 np_tx_status; 3883 u32 p_tx_status; 3884 int i; 3885 3886 num_channels = hsotg->params.host_channels; 3887 dev_dbg(hsotg->dev, "\n"); 3888 dev_dbg(hsotg->dev, 3889 "************************************************************\n"); 3890 dev_dbg(hsotg->dev, "HCD State:\n"); 3891 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels); 3892 3893 for (i = 0; i < num_channels; i++) { 3894 chan = hsotg->hc_ptr_array[i]; 3895 dev_dbg(hsotg->dev, " Channel %d:\n", i); 3896 dev_dbg(hsotg->dev, 3897 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 3898 chan->dev_addr, chan->ep_num, chan->ep_is_in); 3899 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed); 3900 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 3901 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 3902 dev_dbg(hsotg->dev, " data_pid_start: %d\n", 3903 chan->data_pid_start); 3904 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count); 3905 dev_dbg(hsotg->dev, " xfer_started: %d\n", 3906 chan->xfer_started); 3907 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 3908 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 3909 (unsigned long)chan->xfer_dma); 3910 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 3911 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count); 3912 dev_dbg(hsotg->dev, " halt_on_queue: %d\n", 3913 chan->halt_on_queue); 3914 dev_dbg(hsotg->dev, " halt_pending: %d\n", 3915 chan->halt_pending); 3916 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 3917 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split); 3918 dev_dbg(hsotg->dev, " complete_split: %d\n", 3919 chan->complete_split); 3920 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr); 3921 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port); 3922 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos); 3923 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests); 3924 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 3925 3926 if (chan->xfer_started) { 3927 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk; 3928 3929 hfnum = dwc2_readl(hsotg->regs + HFNUM); 3930 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 3931 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(i)); 3932 hcint = dwc2_readl(hsotg->regs + HCINT(i)); 3933 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(i)); 3934 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum); 3935 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar); 3936 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz); 3937 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint); 3938 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk); 3939 } 3940 3941 if (!(chan->xfer_started && chan->qh)) 3942 continue; 3943 3944 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) { 3945 if (!qtd->in_process) 3946 break; 3947 urb = qtd->urb; 3948 dev_dbg(hsotg->dev, " URB Info:\n"); 3949 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n", 3950 qtd, urb); 3951 if (urb) { 3952 dev_dbg(hsotg->dev, 3953 " Dev: %d, EP: %d %s\n", 3954 dwc2_hcd_get_dev_addr(&urb->pipe_info), 3955 dwc2_hcd_get_ep_num(&urb->pipe_info), 3956 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 3957 "IN" : "OUT"); 3958 dev_dbg(hsotg->dev, 3959 " Max packet size: %d\n", 3960 dwc2_hcd_get_mps(&urb->pipe_info)); 3961 dev_dbg(hsotg->dev, 3962 " transfer_buffer: %p\n", 3963 urb->buf); 3964 dev_dbg(hsotg->dev, 3965 " transfer_dma: %08lx\n", 3966 (unsigned long)urb->dma); 3967 dev_dbg(hsotg->dev, 3968 " transfer_buffer_length: %d\n", 3969 urb->length); 3970 dev_dbg(hsotg->dev, " actual_length: %d\n", 3971 urb->actual_length); 3972 } 3973 } 3974 } 3975 3976 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n", 3977 hsotg->non_periodic_channels); 3978 dev_dbg(hsotg->dev, " periodic_channels: %d\n", 3979 hsotg->periodic_channels); 3980 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs); 3981 np_tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 3982 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n", 3983 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 3984 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n", 3985 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 3986 p_tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 3987 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n", 3988 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 3989 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n", 3990 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 3991 dwc2_hcd_dump_frrem(hsotg); 3992 dwc2_dump_global_registers(hsotg); 3993 dwc2_dump_host_registers(hsotg); 3994 dev_dbg(hsotg->dev, 3995 "************************************************************\n"); 3996 dev_dbg(hsotg->dev, "\n"); 3997 #endif 3998 } 3999 4000 /* 4001 * NOTE: This function will be removed once the peripheral controller code 4002 * is integrated and the driver is stable 4003 */ 4004 void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg) 4005 { 4006 #ifdef DWC2_DUMP_FRREM 4007 dev_dbg(hsotg->dev, "Frame remaining at SOF:\n"); 4008 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4009 hsotg->frrem_samples, hsotg->frrem_accum, 4010 hsotg->frrem_samples > 0 ? 4011 hsotg->frrem_accum / hsotg->frrem_samples : 0); 4012 dev_dbg(hsotg->dev, "\n"); 4013 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n"); 4014 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4015 hsotg->hfnum_7_samples, 4016 hsotg->hfnum_7_frrem_accum, 4017 hsotg->hfnum_7_samples > 0 ? 4018 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0); 4019 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n"); 4020 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4021 hsotg->hfnum_0_samples, 4022 hsotg->hfnum_0_frrem_accum, 4023 hsotg->hfnum_0_samples > 0 ? 4024 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0); 4025 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n"); 4026 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4027 hsotg->hfnum_other_samples, 4028 hsotg->hfnum_other_frrem_accum, 4029 hsotg->hfnum_other_samples > 0 ? 4030 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples : 4031 0); 4032 dev_dbg(hsotg->dev, "\n"); 4033 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n"); 4034 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4035 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a, 4036 hsotg->hfnum_7_samples_a > 0 ? 4037 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0); 4038 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n"); 4039 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4040 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a, 4041 hsotg->hfnum_0_samples_a > 0 ? 4042 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0); 4043 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n"); 4044 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4045 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a, 4046 hsotg->hfnum_other_samples_a > 0 ? 4047 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a 4048 : 0); 4049 dev_dbg(hsotg->dev, "\n"); 4050 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n"); 4051 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4052 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b, 4053 hsotg->hfnum_7_samples_b > 0 ? 4054 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0); 4055 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n"); 4056 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4057 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b, 4058 (hsotg->hfnum_0_samples_b > 0) ? 4059 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0); 4060 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n"); 4061 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4062 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b, 4063 (hsotg->hfnum_other_samples_b > 0) ? 4064 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b 4065 : 0); 4066 #endif 4067 } 4068 4069 struct wrapper_priv_data { 4070 struct dwc2_hsotg *hsotg; 4071 }; 4072 4073 /* Gets the dwc2_hsotg from a usb_hcd */ 4074 static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd) 4075 { 4076 struct wrapper_priv_data *p; 4077 4078 p = (struct wrapper_priv_data *)&hcd->hcd_priv; 4079 return p->hsotg; 4080 } 4081 4082 /** 4083 * dwc2_host_get_tt_info() - Get the dwc2_tt associated with context 4084 * 4085 * This will get the dwc2_tt structure (and ttport) associated with the given 4086 * context (which is really just a struct urb pointer). 4087 * 4088 * The first time this is called for a given TT we allocate memory for our 4089 * structure. When everyone is done and has called dwc2_host_put_tt_info() 4090 * then the refcount for the structure will go to 0 and we'll free it. 4091 * 4092 * @hsotg: The HCD state structure for the DWC OTG controller. 4093 * @qh: The QH structure. 4094 * @context: The priv pointer from a struct dwc2_hcd_urb. 4095 * @mem_flags: Flags for allocating memory. 4096 * @ttport: We'll return this device's port number here. That's used to 4097 * reference into the bitmap if we're on a multi_tt hub. 4098 * 4099 * Return: a pointer to a struct dwc2_tt. Don't forget to call 4100 * dwc2_host_put_tt_info()! Returns NULL upon memory alloc failure. 4101 */ 4102 4103 struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context, 4104 gfp_t mem_flags, int *ttport) 4105 { 4106 struct urb *urb = context; 4107 struct dwc2_tt *dwc_tt = NULL; 4108 4109 if (urb->dev->tt) { 4110 *ttport = urb->dev->ttport; 4111 4112 dwc_tt = urb->dev->tt->hcpriv; 4113 if (!dwc_tt) { 4114 size_t bitmap_size; 4115 4116 /* 4117 * For single_tt we need one schedule. For multi_tt 4118 * we need one per port. 4119 */ 4120 bitmap_size = DWC2_ELEMENTS_PER_LS_BITMAP * 4121 sizeof(dwc_tt->periodic_bitmaps[0]); 4122 if (urb->dev->tt->multi) 4123 bitmap_size *= urb->dev->tt->hub->maxchild; 4124 4125 dwc_tt = kzalloc(sizeof(*dwc_tt) + bitmap_size, 4126 mem_flags); 4127 if (!dwc_tt) 4128 return NULL; 4129 4130 dwc_tt->usb_tt = urb->dev->tt; 4131 dwc_tt->usb_tt->hcpriv = dwc_tt; 4132 } 4133 4134 dwc_tt->refcount++; 4135 } 4136 4137 return dwc_tt; 4138 } 4139 4140 /** 4141 * dwc2_host_put_tt_info() - Put the dwc2_tt from dwc2_host_get_tt_info() 4142 * 4143 * Frees resources allocated by dwc2_host_get_tt_info() if all current holders 4144 * of the structure are done. 4145 * 4146 * It's OK to call this with NULL. 4147 * 4148 * @hsotg: The HCD state structure for the DWC OTG controller. 4149 * @dwc_tt: The pointer returned by dwc2_host_get_tt_info. 4150 */ 4151 void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, struct dwc2_tt *dwc_tt) 4152 { 4153 /* Model kfree and make put of NULL a no-op */ 4154 if (!dwc_tt) 4155 return; 4156 4157 WARN_ON(dwc_tt->refcount < 1); 4158 4159 dwc_tt->refcount--; 4160 if (!dwc_tt->refcount) { 4161 dwc_tt->usb_tt->hcpriv = NULL; 4162 kfree(dwc_tt); 4163 } 4164 } 4165 4166 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context) 4167 { 4168 struct urb *urb = context; 4169 4170 return urb->dev->speed; 4171 } 4172 4173 static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw, 4174 struct urb *urb) 4175 { 4176 struct usb_bus *bus = hcd_to_bus(hcd); 4177 4178 if (urb->interval) 4179 bus->bandwidth_allocated += bw / urb->interval; 4180 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 4181 bus->bandwidth_isoc_reqs++; 4182 else 4183 bus->bandwidth_int_reqs++; 4184 } 4185 4186 static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw, 4187 struct urb *urb) 4188 { 4189 struct usb_bus *bus = hcd_to_bus(hcd); 4190 4191 if (urb->interval) 4192 bus->bandwidth_allocated -= bw / urb->interval; 4193 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 4194 bus->bandwidth_isoc_reqs--; 4195 else 4196 bus->bandwidth_int_reqs--; 4197 } 4198 4199 /* 4200 * Sets the final status of an URB and returns it to the upper layer. Any 4201 * required cleanup of the URB is performed. 4202 * 4203 * Must be called with interrupt disabled and spinlock held 4204 */ 4205 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 4206 int status) 4207 { 4208 struct urb *urb; 4209 int i; 4210 4211 if (!qtd) { 4212 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__); 4213 return; 4214 } 4215 4216 if (!qtd->urb) { 4217 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__); 4218 return; 4219 } 4220 4221 urb = qtd->urb->priv; 4222 if (!urb) { 4223 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__); 4224 return; 4225 } 4226 4227 urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb); 4228 4229 if (dbg_urb(urb)) 4230 dev_vdbg(hsotg->dev, 4231 "%s: urb %p device %d ep %d-%s status %d actual %d\n", 4232 __func__, urb, usb_pipedevice(urb->pipe), 4233 usb_pipeendpoint(urb->pipe), 4234 usb_pipein(urb->pipe) ? "IN" : "OUT", status, 4235 urb->actual_length); 4236 4237 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 4238 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb); 4239 for (i = 0; i < urb->number_of_packets; ++i) { 4240 urb->iso_frame_desc[i].actual_length = 4241 dwc2_hcd_urb_get_iso_desc_actual_length( 4242 qtd->urb, i); 4243 urb->iso_frame_desc[i].status = 4244 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i); 4245 } 4246 } 4247 4248 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) { 4249 for (i = 0; i < urb->number_of_packets; i++) 4250 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n", 4251 i, urb->iso_frame_desc[i].status); 4252 } 4253 4254 urb->status = status; 4255 if (!status) { 4256 if ((urb->transfer_flags & URB_SHORT_NOT_OK) && 4257 urb->actual_length < urb->transfer_buffer_length) 4258 urb->status = -EREMOTEIO; 4259 } 4260 4261 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || 4262 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { 4263 struct usb_host_endpoint *ep = urb->ep; 4264 4265 if (ep) 4266 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg), 4267 dwc2_hcd_get_ep_bandwidth(hsotg, ep), 4268 urb); 4269 } 4270 4271 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb); 4272 urb->hcpriv = NULL; 4273 kfree(qtd->urb); 4274 qtd->urb = NULL; 4275 4276 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status); 4277 } 4278 4279 /* 4280 * Work queue function for starting the HCD when A-Cable is connected 4281 */ 4282 static void dwc2_hcd_start_func(struct work_struct *work) 4283 { 4284 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 4285 start_work.work); 4286 4287 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg); 4288 dwc2_host_start(hsotg); 4289 } 4290 4291 /* 4292 * Reset work queue function 4293 */ 4294 static void dwc2_hcd_reset_func(struct work_struct *work) 4295 { 4296 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 4297 reset_work.work); 4298 unsigned long flags; 4299 u32 hprt0; 4300 4301 dev_dbg(hsotg->dev, "USB RESET function called\n"); 4302 4303 spin_lock_irqsave(&hsotg->lock, flags); 4304 4305 hprt0 = dwc2_read_hprt0(hsotg); 4306 hprt0 &= ~HPRT0_RST; 4307 dwc2_writel(hprt0, hsotg->regs + HPRT0); 4308 hsotg->flags.b.port_reset_change = 1; 4309 4310 spin_unlock_irqrestore(&hsotg->lock, flags); 4311 } 4312 4313 /* 4314 * ========================================================================= 4315 * Linux HC Driver Functions 4316 * ========================================================================= 4317 */ 4318 4319 /* 4320 * Initializes the DWC_otg controller and its root hub and prepares it for host 4321 * mode operation. Activates the root port. Returns 0 on success and a negative 4322 * error code on failure. 4323 */ 4324 static int _dwc2_hcd_start(struct usb_hcd *hcd) 4325 { 4326 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4327 struct usb_bus *bus = hcd_to_bus(hcd); 4328 unsigned long flags; 4329 4330 dev_dbg(hsotg->dev, "DWC OTG HCD START\n"); 4331 4332 spin_lock_irqsave(&hsotg->lock, flags); 4333 hsotg->lx_state = DWC2_L0; 4334 hcd->state = HC_STATE_RUNNING; 4335 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4336 4337 if (dwc2_is_device_mode(hsotg)) { 4338 spin_unlock_irqrestore(&hsotg->lock, flags); 4339 return 0; /* why 0 ?? */ 4340 } 4341 4342 dwc2_hcd_reinit(hsotg); 4343 4344 /* Initialize and connect root hub if one is not already attached */ 4345 if (bus->root_hub) { 4346 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n"); 4347 /* Inform the HUB driver to resume */ 4348 usb_hcd_resume_root_hub(hcd); 4349 } 4350 4351 spin_unlock_irqrestore(&hsotg->lock, flags); 4352 return 0; 4353 } 4354 4355 /* 4356 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are 4357 * stopped. 4358 */ 4359 static void _dwc2_hcd_stop(struct usb_hcd *hcd) 4360 { 4361 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4362 unsigned long flags; 4363 4364 /* Turn off all host-specific interrupts */ 4365 dwc2_disable_host_interrupts(hsotg); 4366 4367 /* Wait for interrupt processing to finish */ 4368 synchronize_irq(hcd->irq); 4369 4370 spin_lock_irqsave(&hsotg->lock, flags); 4371 /* Ensure hcd is disconnected */ 4372 dwc2_hcd_disconnect(hsotg, true); 4373 dwc2_hcd_stop(hsotg); 4374 hsotg->lx_state = DWC2_L3; 4375 hcd->state = HC_STATE_HALT; 4376 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4377 spin_unlock_irqrestore(&hsotg->lock, flags); 4378 4379 usleep_range(1000, 3000); 4380 } 4381 4382 static int _dwc2_hcd_suspend(struct usb_hcd *hcd) 4383 { 4384 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4385 unsigned long flags; 4386 int ret = 0; 4387 u32 hprt0; 4388 4389 spin_lock_irqsave(&hsotg->lock, flags); 4390 4391 if (dwc2_is_device_mode(hsotg)) 4392 goto unlock; 4393 4394 if (hsotg->lx_state != DWC2_L0) 4395 goto unlock; 4396 4397 if (!HCD_HW_ACCESSIBLE(hcd)) 4398 goto unlock; 4399 4400 if (hsotg->op_state == OTG_STATE_B_PERIPHERAL) 4401 goto unlock; 4402 4403 if (!hsotg->params.hibernation) 4404 goto skip_power_saving; 4405 4406 /* 4407 * Drive USB suspend and disable port Power 4408 * if usb bus is not suspended. 4409 */ 4410 if (!hsotg->bus_suspended) { 4411 hprt0 = dwc2_read_hprt0(hsotg); 4412 hprt0 |= HPRT0_SUSP; 4413 hprt0 &= ~HPRT0_PWR; 4414 dwc2_writel(hprt0, hsotg->regs + HPRT0); 4415 } 4416 4417 /* Enter hibernation */ 4418 ret = dwc2_enter_hibernation(hsotg); 4419 if (ret) { 4420 if (ret != -ENOTSUPP) 4421 dev_err(hsotg->dev, 4422 "enter hibernation failed\n"); 4423 goto skip_power_saving; 4424 } 4425 4426 /* Ask phy to be suspended */ 4427 if (!IS_ERR_OR_NULL(hsotg->uphy)) { 4428 spin_unlock_irqrestore(&hsotg->lock, flags); 4429 usb_phy_set_suspend(hsotg->uphy, true); 4430 spin_lock_irqsave(&hsotg->lock, flags); 4431 } 4432 4433 /* After entering hibernation, hardware is no more accessible */ 4434 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4435 4436 skip_power_saving: 4437 hsotg->lx_state = DWC2_L2; 4438 unlock: 4439 spin_unlock_irqrestore(&hsotg->lock, flags); 4440 4441 return ret; 4442 } 4443 4444 static int _dwc2_hcd_resume(struct usb_hcd *hcd) 4445 { 4446 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4447 unsigned long flags; 4448 int ret = 0; 4449 4450 spin_lock_irqsave(&hsotg->lock, flags); 4451 4452 if (dwc2_is_device_mode(hsotg)) 4453 goto unlock; 4454 4455 if (hsotg->lx_state != DWC2_L2) 4456 goto unlock; 4457 4458 if (!hsotg->params.hibernation) { 4459 hsotg->lx_state = DWC2_L0; 4460 goto unlock; 4461 } 4462 4463 /* 4464 * Set HW accessible bit before powering on the controller 4465 * since an interrupt may rise. 4466 */ 4467 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4468 4469 /* 4470 * Enable power if not already done. 4471 * This must not be spinlocked since duration 4472 * of this call is unknown. 4473 */ 4474 if (!IS_ERR_OR_NULL(hsotg->uphy)) { 4475 spin_unlock_irqrestore(&hsotg->lock, flags); 4476 usb_phy_set_suspend(hsotg->uphy, false); 4477 spin_lock_irqsave(&hsotg->lock, flags); 4478 } 4479 4480 /* Exit hibernation */ 4481 ret = dwc2_exit_hibernation(hsotg, true); 4482 if (ret && (ret != -ENOTSUPP)) 4483 dev_err(hsotg->dev, "exit hibernation failed\n"); 4484 4485 hsotg->lx_state = DWC2_L0; 4486 4487 spin_unlock_irqrestore(&hsotg->lock, flags); 4488 4489 if (hsotg->bus_suspended) { 4490 spin_lock_irqsave(&hsotg->lock, flags); 4491 hsotg->flags.b.port_suspend_change = 1; 4492 spin_unlock_irqrestore(&hsotg->lock, flags); 4493 dwc2_port_resume(hsotg); 4494 } else { 4495 /* Wait for controller to correctly update D+/D- level */ 4496 usleep_range(3000, 5000); 4497 4498 /* 4499 * Clear Port Enable and Port Status changes. 4500 * Enable Port Power. 4501 */ 4502 dwc2_writel(HPRT0_PWR | HPRT0_CONNDET | 4503 HPRT0_ENACHG, hsotg->regs + HPRT0); 4504 /* Wait for controller to detect Port Connect */ 4505 usleep_range(5000, 7000); 4506 } 4507 4508 return ret; 4509 unlock: 4510 spin_unlock_irqrestore(&hsotg->lock, flags); 4511 4512 return ret; 4513 } 4514 4515 /* Returns the current frame number */ 4516 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd) 4517 { 4518 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4519 4520 return dwc2_hcd_get_frame_number(hsotg); 4521 } 4522 4523 static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb, 4524 char *fn_name) 4525 { 4526 #ifdef VERBOSE_DEBUG 4527 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4528 char *pipetype = NULL; 4529 char *speed = NULL; 4530 4531 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb); 4532 dev_vdbg(hsotg->dev, " Device address: %d\n", 4533 usb_pipedevice(urb->pipe)); 4534 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n", 4535 usb_pipeendpoint(urb->pipe), 4536 usb_pipein(urb->pipe) ? "IN" : "OUT"); 4537 4538 switch (usb_pipetype(urb->pipe)) { 4539 case PIPE_CONTROL: 4540 pipetype = "CONTROL"; 4541 break; 4542 case PIPE_BULK: 4543 pipetype = "BULK"; 4544 break; 4545 case PIPE_INTERRUPT: 4546 pipetype = "INTERRUPT"; 4547 break; 4548 case PIPE_ISOCHRONOUS: 4549 pipetype = "ISOCHRONOUS"; 4550 break; 4551 } 4552 4553 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype, 4554 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ? 4555 "IN" : "OUT"); 4556 4557 switch (urb->dev->speed) { 4558 case USB_SPEED_HIGH: 4559 speed = "HIGH"; 4560 break; 4561 case USB_SPEED_FULL: 4562 speed = "FULL"; 4563 break; 4564 case USB_SPEED_LOW: 4565 speed = "LOW"; 4566 break; 4567 default: 4568 speed = "UNKNOWN"; 4569 break; 4570 } 4571 4572 dev_vdbg(hsotg->dev, " Speed: %s\n", speed); 4573 dev_vdbg(hsotg->dev, " Max packet size: %d\n", 4574 usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))); 4575 dev_vdbg(hsotg->dev, " Data buffer length: %d\n", 4576 urb->transfer_buffer_length); 4577 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n", 4578 urb->transfer_buffer, (unsigned long)urb->transfer_dma); 4579 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n", 4580 urb->setup_packet, (unsigned long)urb->setup_dma); 4581 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval); 4582 4583 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 4584 int i; 4585 4586 for (i = 0; i < urb->number_of_packets; i++) { 4587 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i); 4588 dev_vdbg(hsotg->dev, " offset: %d, length %d\n", 4589 urb->iso_frame_desc[i].offset, 4590 urb->iso_frame_desc[i].length); 4591 } 4592 } 4593 #endif 4594 } 4595 4596 /* 4597 * Starts processing a USB transfer request specified by a USB Request Block 4598 * (URB). mem_flags indicates the type of memory allocation to use while 4599 * processing this URB. 4600 */ 4601 static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, 4602 gfp_t mem_flags) 4603 { 4604 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4605 struct usb_host_endpoint *ep = urb->ep; 4606 struct dwc2_hcd_urb *dwc2_urb; 4607 int i; 4608 int retval; 4609 int alloc_bandwidth = 0; 4610 u8 ep_type = 0; 4611 u32 tflags = 0; 4612 void *buf; 4613 unsigned long flags; 4614 struct dwc2_qh *qh; 4615 bool qh_allocated = false; 4616 struct dwc2_qtd *qtd; 4617 4618 if (dbg_urb(urb)) { 4619 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n"); 4620 dwc2_dump_urb_info(hcd, urb, "urb_enqueue"); 4621 } 4622 4623 if (!ep) 4624 return -EINVAL; 4625 4626 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || 4627 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { 4628 spin_lock_irqsave(&hsotg->lock, flags); 4629 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep)) 4630 alloc_bandwidth = 1; 4631 spin_unlock_irqrestore(&hsotg->lock, flags); 4632 } 4633 4634 switch (usb_pipetype(urb->pipe)) { 4635 case PIPE_CONTROL: 4636 ep_type = USB_ENDPOINT_XFER_CONTROL; 4637 break; 4638 case PIPE_ISOCHRONOUS: 4639 ep_type = USB_ENDPOINT_XFER_ISOC; 4640 break; 4641 case PIPE_BULK: 4642 ep_type = USB_ENDPOINT_XFER_BULK; 4643 break; 4644 case PIPE_INTERRUPT: 4645 ep_type = USB_ENDPOINT_XFER_INT; 4646 break; 4647 } 4648 4649 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets, 4650 mem_flags); 4651 if (!dwc2_urb) 4652 return -ENOMEM; 4653 4654 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe), 4655 usb_pipeendpoint(urb->pipe), ep_type, 4656 usb_pipein(urb->pipe), 4657 usb_maxpacket(urb->dev, urb->pipe, 4658 !(usb_pipein(urb->pipe)))); 4659 4660 buf = urb->transfer_buffer; 4661 4662 if (hcd->self.uses_dma) { 4663 if (!buf && (urb->transfer_dma & 3)) { 4664 dev_err(hsotg->dev, 4665 "%s: unaligned transfer with no transfer_buffer", 4666 __func__); 4667 retval = -EINVAL; 4668 goto fail0; 4669 } 4670 } 4671 4672 if (!(urb->transfer_flags & URB_NO_INTERRUPT)) 4673 tflags |= URB_GIVEBACK_ASAP; 4674 if (urb->transfer_flags & URB_ZERO_PACKET) 4675 tflags |= URB_SEND_ZERO_PACKET; 4676 4677 dwc2_urb->priv = urb; 4678 dwc2_urb->buf = buf; 4679 dwc2_urb->dma = urb->transfer_dma; 4680 dwc2_urb->length = urb->transfer_buffer_length; 4681 dwc2_urb->setup_packet = urb->setup_packet; 4682 dwc2_urb->setup_dma = urb->setup_dma; 4683 dwc2_urb->flags = tflags; 4684 dwc2_urb->interval = urb->interval; 4685 dwc2_urb->status = -EINPROGRESS; 4686 4687 for (i = 0; i < urb->number_of_packets; ++i) 4688 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i, 4689 urb->iso_frame_desc[i].offset, 4690 urb->iso_frame_desc[i].length); 4691 4692 urb->hcpriv = dwc2_urb; 4693 qh = (struct dwc2_qh *)ep->hcpriv; 4694 /* Create QH for the endpoint if it doesn't exist */ 4695 if (!qh) { 4696 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags); 4697 if (!qh) { 4698 retval = -ENOMEM; 4699 goto fail0; 4700 } 4701 ep->hcpriv = qh; 4702 qh_allocated = true; 4703 } 4704 4705 qtd = kzalloc(sizeof(*qtd), mem_flags); 4706 if (!qtd) { 4707 retval = -ENOMEM; 4708 goto fail1; 4709 } 4710 4711 spin_lock_irqsave(&hsotg->lock, flags); 4712 retval = usb_hcd_link_urb_to_ep(hcd, urb); 4713 if (retval) 4714 goto fail2; 4715 4716 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd); 4717 if (retval) 4718 goto fail3; 4719 4720 if (alloc_bandwidth) { 4721 dwc2_allocate_bus_bandwidth(hcd, 4722 dwc2_hcd_get_ep_bandwidth(hsotg, ep), 4723 urb); 4724 } 4725 4726 spin_unlock_irqrestore(&hsotg->lock, flags); 4727 4728 return 0; 4729 4730 fail3: 4731 dwc2_urb->priv = NULL; 4732 usb_hcd_unlink_urb_from_ep(hcd, urb); 4733 if (qh_allocated && qh->channel && qh->channel->qh == qh) 4734 qh->channel->qh = NULL; 4735 fail2: 4736 spin_unlock_irqrestore(&hsotg->lock, flags); 4737 urb->hcpriv = NULL; 4738 kfree(qtd); 4739 qtd = NULL; 4740 fail1: 4741 if (qh_allocated) { 4742 struct dwc2_qtd *qtd2, *qtd2_tmp; 4743 4744 ep->hcpriv = NULL; 4745 dwc2_hcd_qh_unlink(hsotg, qh); 4746 /* Free each QTD in the QH's QTD list */ 4747 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list, 4748 qtd_list_entry) 4749 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh); 4750 dwc2_hcd_qh_free(hsotg, qh); 4751 } 4752 fail0: 4753 kfree(dwc2_urb); 4754 4755 return retval; 4756 } 4757 4758 /* 4759 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success. 4760 */ 4761 static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, 4762 int status) 4763 { 4764 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4765 int rc; 4766 unsigned long flags; 4767 4768 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n"); 4769 dwc2_dump_urb_info(hcd, urb, "urb_dequeue"); 4770 4771 spin_lock_irqsave(&hsotg->lock, flags); 4772 4773 rc = usb_hcd_check_unlink_urb(hcd, urb, status); 4774 if (rc) 4775 goto out; 4776 4777 if (!urb->hcpriv) { 4778 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n"); 4779 goto out; 4780 } 4781 4782 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv); 4783 4784 usb_hcd_unlink_urb_from_ep(hcd, urb); 4785 4786 kfree(urb->hcpriv); 4787 urb->hcpriv = NULL; 4788 4789 /* Higher layer software sets URB status */ 4790 spin_unlock(&hsotg->lock); 4791 usb_hcd_giveback_urb(hcd, urb, status); 4792 spin_lock(&hsotg->lock); 4793 4794 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n"); 4795 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status); 4796 out: 4797 spin_unlock_irqrestore(&hsotg->lock, flags); 4798 4799 return rc; 4800 } 4801 4802 /* 4803 * Frees resources in the DWC_otg controller related to a given endpoint. Also 4804 * clears state in the HCD related to the endpoint. Any URBs for the endpoint 4805 * must already be dequeued. 4806 */ 4807 static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd, 4808 struct usb_host_endpoint *ep) 4809 { 4810 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4811 4812 dev_dbg(hsotg->dev, 4813 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n", 4814 ep->desc.bEndpointAddress, ep->hcpriv); 4815 dwc2_hcd_endpoint_disable(hsotg, ep, 250); 4816 } 4817 4818 /* 4819 * Resets endpoint specific parameter values, in current version used to reset 4820 * the data toggle (as a WA). This function can be called from usb_clear_halt 4821 * routine. 4822 */ 4823 static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd, 4824 struct usb_host_endpoint *ep) 4825 { 4826 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4827 unsigned long flags; 4828 4829 dev_dbg(hsotg->dev, 4830 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n", 4831 ep->desc.bEndpointAddress); 4832 4833 spin_lock_irqsave(&hsotg->lock, flags); 4834 dwc2_hcd_endpoint_reset(hsotg, ep); 4835 spin_unlock_irqrestore(&hsotg->lock, flags); 4836 } 4837 4838 /* 4839 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if 4840 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid 4841 * interrupt. 4842 * 4843 * This function is called by the USB core when an interrupt occurs 4844 */ 4845 static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd) 4846 { 4847 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4848 4849 return dwc2_handle_hcd_intr(hsotg); 4850 } 4851 4852 /* 4853 * Creates Status Change bitmap for the root hub and root port. The bitmap is 4854 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1 4855 * is the status change indicator for the single root port. Returns 1 if either 4856 * change indicator is 1, otherwise returns 0. 4857 */ 4858 static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf) 4859 { 4860 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4861 4862 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1; 4863 return buf[0] != 0; 4864 } 4865 4866 /* Handles hub class-specific requests */ 4867 static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue, 4868 u16 windex, char *buf, u16 wlength) 4869 { 4870 int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq, 4871 wvalue, windex, buf, wlength); 4872 return retval; 4873 } 4874 4875 /* Handles hub TT buffer clear completions */ 4876 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd, 4877 struct usb_host_endpoint *ep) 4878 { 4879 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4880 struct dwc2_qh *qh; 4881 unsigned long flags; 4882 4883 qh = ep->hcpriv; 4884 if (!qh) 4885 return; 4886 4887 spin_lock_irqsave(&hsotg->lock, flags); 4888 qh->tt_buffer_dirty = 0; 4889 4890 if (hsotg->flags.b.port_connect_status) 4891 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL); 4892 4893 spin_unlock_irqrestore(&hsotg->lock, flags); 4894 } 4895 4896 /* 4897 * HPRT0_SPD_HIGH_SPEED: high speed 4898 * HPRT0_SPD_FULL_SPEED: full speed 4899 */ 4900 static void dwc2_change_bus_speed(struct usb_hcd *hcd, int speed) 4901 { 4902 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4903 4904 if (hsotg->params.speed == speed) 4905 return; 4906 4907 hsotg->params.speed = speed; 4908 queue_work(hsotg->wq_otg, &hsotg->wf_otg); 4909 } 4910 4911 static void dwc2_free_dev(struct usb_hcd *hcd, struct usb_device *udev) 4912 { 4913 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4914 4915 if (!hsotg->params.change_speed_quirk) 4916 return; 4917 4918 /* 4919 * On removal, set speed to default high-speed. 4920 */ 4921 if (udev->parent && udev->parent->speed > USB_SPEED_UNKNOWN && 4922 udev->parent->speed < USB_SPEED_HIGH) { 4923 dev_info(hsotg->dev, "Set speed to default high-speed\n"); 4924 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED); 4925 } 4926 } 4927 4928 static int dwc2_reset_device(struct usb_hcd *hcd, struct usb_device *udev) 4929 { 4930 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4931 4932 if (!hsotg->params.change_speed_quirk) 4933 return 0; 4934 4935 if (udev->speed == USB_SPEED_HIGH) { 4936 dev_info(hsotg->dev, "Set speed to high-speed\n"); 4937 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED); 4938 } else if ((udev->speed == USB_SPEED_FULL || 4939 udev->speed == USB_SPEED_LOW)) { 4940 /* 4941 * Change speed setting to full-speed if there's 4942 * a full-speed or low-speed device plugged in. 4943 */ 4944 dev_info(hsotg->dev, "Set speed to full-speed\n"); 4945 dwc2_change_bus_speed(hcd, HPRT0_SPD_FULL_SPEED); 4946 } 4947 4948 return 0; 4949 } 4950 4951 static struct hc_driver dwc2_hc_driver = { 4952 .description = "dwc2_hsotg", 4953 .product_desc = "DWC OTG Controller", 4954 .hcd_priv_size = sizeof(struct wrapper_priv_data), 4955 4956 .irq = _dwc2_hcd_irq, 4957 .flags = HCD_MEMORY | HCD_USB2 | HCD_BH, 4958 4959 .start = _dwc2_hcd_start, 4960 .stop = _dwc2_hcd_stop, 4961 .urb_enqueue = _dwc2_hcd_urb_enqueue, 4962 .urb_dequeue = _dwc2_hcd_urb_dequeue, 4963 .endpoint_disable = _dwc2_hcd_endpoint_disable, 4964 .endpoint_reset = _dwc2_hcd_endpoint_reset, 4965 .get_frame_number = _dwc2_hcd_get_frame_number, 4966 4967 .hub_status_data = _dwc2_hcd_hub_status_data, 4968 .hub_control = _dwc2_hcd_hub_control, 4969 .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete, 4970 4971 .bus_suspend = _dwc2_hcd_suspend, 4972 .bus_resume = _dwc2_hcd_resume, 4973 4974 .map_urb_for_dma = dwc2_map_urb_for_dma, 4975 .unmap_urb_for_dma = dwc2_unmap_urb_for_dma, 4976 }; 4977 4978 /* 4979 * Frees secondary storage associated with the dwc2_hsotg structure contained 4980 * in the struct usb_hcd field 4981 */ 4982 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg) 4983 { 4984 u32 ahbcfg; 4985 u32 dctl; 4986 int i; 4987 4988 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n"); 4989 4990 /* Free memory for QH/QTD lists */ 4991 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive); 4992 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active); 4993 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive); 4994 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready); 4995 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned); 4996 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued); 4997 4998 /* Free memory for the host channels */ 4999 for (i = 0; i < MAX_EPS_CHANNELS; i++) { 5000 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 5001 5002 if (chan) { 5003 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n", 5004 i, chan); 5005 hsotg->hc_ptr_array[i] = NULL; 5006 kfree(chan); 5007 } 5008 } 5009 5010 if (hsotg->params.host_dma) { 5011 if (hsotg->status_buf) { 5012 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE, 5013 hsotg->status_buf, 5014 hsotg->status_buf_dma); 5015 hsotg->status_buf = NULL; 5016 } 5017 } else { 5018 kfree(hsotg->status_buf); 5019 hsotg->status_buf = NULL; 5020 } 5021 5022 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 5023 5024 /* Disable all interrupts */ 5025 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 5026 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); 5027 dwc2_writel(0, hsotg->regs + GINTMSK); 5028 5029 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) { 5030 dctl = dwc2_readl(hsotg->regs + DCTL); 5031 dctl |= DCTL_SFTDISCON; 5032 dwc2_writel(dctl, hsotg->regs + DCTL); 5033 } 5034 5035 if (hsotg->wq_otg) { 5036 if (!cancel_work_sync(&hsotg->wf_otg)) 5037 flush_workqueue(hsotg->wq_otg); 5038 destroy_workqueue(hsotg->wq_otg); 5039 } 5040 5041 del_timer(&hsotg->wkp_timer); 5042 } 5043 5044 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg) 5045 { 5046 /* Turn off all host-specific interrupts */ 5047 dwc2_disable_host_interrupts(hsotg); 5048 5049 dwc2_hcd_free(hsotg); 5050 } 5051 5052 /* 5053 * Initializes the HCD. This function allocates memory for and initializes the 5054 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the 5055 * USB bus with the core and calls the hc_driver->start() function. It returns 5056 * a negative error on failure. 5057 */ 5058 int dwc2_hcd_init(struct dwc2_hsotg *hsotg) 5059 { 5060 struct platform_device *pdev = to_platform_device(hsotg->dev); 5061 struct resource *res; 5062 struct usb_hcd *hcd; 5063 struct dwc2_host_chan *channel; 5064 u32 hcfg; 5065 int i, num_channels; 5066 int retval; 5067 5068 if (usb_disabled()) 5069 return -ENODEV; 5070 5071 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n"); 5072 5073 retval = -ENOMEM; 5074 5075 hcfg = dwc2_readl(hsotg->regs + HCFG); 5076 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg); 5077 5078 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 5079 hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) * 5080 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL); 5081 if (!hsotg->frame_num_array) 5082 goto error1; 5083 hsotg->last_frame_num_array = kzalloc( 5084 sizeof(*hsotg->last_frame_num_array) * 5085 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL); 5086 if (!hsotg->last_frame_num_array) 5087 goto error1; 5088 #endif 5089 hsotg->last_frame_num = HFNUM_MAX_FRNUM; 5090 5091 /* Check if the bus driver or platform code has setup a dma_mask */ 5092 if (hsotg->params.host_dma && 5093 !hsotg->dev->dma_mask) { 5094 dev_warn(hsotg->dev, 5095 "dma_mask not set, disabling DMA\n"); 5096 hsotg->params.host_dma = false; 5097 hsotg->params.dma_desc_enable = false; 5098 } 5099 5100 /* Set device flags indicating whether the HCD supports DMA */ 5101 if (hsotg->params.host_dma) { 5102 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) 5103 dev_warn(hsotg->dev, "can't set DMA mask\n"); 5104 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) 5105 dev_warn(hsotg->dev, "can't set coherent DMA mask\n"); 5106 } 5107 5108 if (hsotg->params.change_speed_quirk) { 5109 dwc2_hc_driver.free_dev = dwc2_free_dev; 5110 dwc2_hc_driver.reset_device = dwc2_reset_device; 5111 } 5112 5113 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev)); 5114 if (!hcd) 5115 goto error1; 5116 5117 if (!hsotg->params.host_dma) 5118 hcd->self.uses_dma = 0; 5119 5120 hcd->has_tt = 1; 5121 5122 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 5123 hcd->rsrc_start = res->start; 5124 hcd->rsrc_len = resource_size(res); 5125 5126 ((struct wrapper_priv_data *)&hcd->hcd_priv)->hsotg = hsotg; 5127 hsotg->priv = hcd; 5128 5129 /* 5130 * Disable the global interrupt until all the interrupt handlers are 5131 * installed 5132 */ 5133 dwc2_disable_global_interrupts(hsotg); 5134 5135 /* Initialize the DWC_otg core, and select the Phy type */ 5136 retval = dwc2_core_init(hsotg, true); 5137 if (retval) 5138 goto error2; 5139 5140 /* Create new workqueue and init work */ 5141 retval = -ENOMEM; 5142 hsotg->wq_otg = alloc_ordered_workqueue("dwc2", 0); 5143 if (!hsotg->wq_otg) { 5144 dev_err(hsotg->dev, "Failed to create workqueue\n"); 5145 goto error2; 5146 } 5147 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change); 5148 5149 setup_timer(&hsotg->wkp_timer, dwc2_wakeup_detected, 5150 (unsigned long)hsotg); 5151 5152 /* Initialize the non-periodic schedule */ 5153 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive); 5154 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active); 5155 5156 /* Initialize the periodic schedule */ 5157 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive); 5158 INIT_LIST_HEAD(&hsotg->periodic_sched_ready); 5159 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned); 5160 INIT_LIST_HEAD(&hsotg->periodic_sched_queued); 5161 5162 INIT_LIST_HEAD(&hsotg->split_order); 5163 5164 /* 5165 * Create a host channel descriptor for each host channel implemented 5166 * in the controller. Initialize the channel descriptor array. 5167 */ 5168 INIT_LIST_HEAD(&hsotg->free_hc_list); 5169 num_channels = hsotg->params.host_channels; 5170 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array)); 5171 5172 for (i = 0; i < num_channels; i++) { 5173 channel = kzalloc(sizeof(*channel), GFP_KERNEL); 5174 if (!channel) 5175 goto error3; 5176 channel->hc_num = i; 5177 INIT_LIST_HEAD(&channel->split_order_list_entry); 5178 hsotg->hc_ptr_array[i] = channel; 5179 } 5180 5181 /* Initialize hsotg start work */ 5182 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func); 5183 5184 /* Initialize port reset work */ 5185 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func); 5186 5187 /* 5188 * Allocate space for storing data on status transactions. Normally no 5189 * data is sent, but this space acts as a bit bucket. This must be 5190 * done after usb_add_hcd since that function allocates the DMA buffer 5191 * pool. 5192 */ 5193 if (hsotg->params.host_dma) 5194 hsotg->status_buf = dma_alloc_coherent(hsotg->dev, 5195 DWC2_HCD_STATUS_BUF_SIZE, 5196 &hsotg->status_buf_dma, GFP_KERNEL); 5197 else 5198 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE, 5199 GFP_KERNEL); 5200 5201 if (!hsotg->status_buf) 5202 goto error3; 5203 5204 /* 5205 * Create kmem caches to handle descriptor buffers in descriptor 5206 * DMA mode. 5207 * Alignment must be set to 512 bytes. 5208 */ 5209 if (hsotg->params.dma_desc_enable || 5210 hsotg->params.dma_desc_fs_enable) { 5211 hsotg->desc_gen_cache = kmem_cache_create("dwc2-gen-desc", 5212 sizeof(struct dwc2_dma_desc) * 5213 MAX_DMA_DESC_NUM_GENERIC, 512, SLAB_CACHE_DMA, 5214 NULL); 5215 if (!hsotg->desc_gen_cache) { 5216 dev_err(hsotg->dev, 5217 "unable to create dwc2 generic desc cache\n"); 5218 5219 /* 5220 * Disable descriptor dma mode since it will not be 5221 * usable. 5222 */ 5223 hsotg->params.dma_desc_enable = false; 5224 hsotg->params.dma_desc_fs_enable = false; 5225 } 5226 5227 hsotg->desc_hsisoc_cache = kmem_cache_create("dwc2-hsisoc-desc", 5228 sizeof(struct dwc2_dma_desc) * 5229 MAX_DMA_DESC_NUM_HS_ISOC, 512, 0, NULL); 5230 if (!hsotg->desc_hsisoc_cache) { 5231 dev_err(hsotg->dev, 5232 "unable to create dwc2 hs isoc desc cache\n"); 5233 5234 kmem_cache_destroy(hsotg->desc_gen_cache); 5235 5236 /* 5237 * Disable descriptor dma mode since it will not be 5238 * usable. 5239 */ 5240 hsotg->params.dma_desc_enable = false; 5241 hsotg->params.dma_desc_fs_enable = false; 5242 } 5243 } 5244 5245 hsotg->otg_port = 1; 5246 hsotg->frame_list = NULL; 5247 hsotg->frame_list_dma = 0; 5248 hsotg->periodic_qh_count = 0; 5249 5250 /* Initiate lx_state to L3 disconnected state */ 5251 hsotg->lx_state = DWC2_L3; 5252 5253 hcd->self.otg_port = hsotg->otg_port; 5254 5255 /* Don't support SG list at this point */ 5256 hcd->self.sg_tablesize = 0; 5257 5258 if (!IS_ERR_OR_NULL(hsotg->uphy)) 5259 otg_set_host(hsotg->uphy->otg, &hcd->self); 5260 5261 /* 5262 * Finish generic HCD initialization and start the HCD. This function 5263 * allocates the DMA buffer pool, registers the USB bus, requests the 5264 * IRQ line, and calls hcd_start method. 5265 */ 5266 retval = usb_add_hcd(hcd, hsotg->irq, IRQF_SHARED); 5267 if (retval < 0) 5268 goto error4; 5269 5270 device_wakeup_enable(hcd->self.controller); 5271 5272 dwc2_hcd_dump_state(hsotg); 5273 5274 dwc2_enable_global_interrupts(hsotg); 5275 5276 return 0; 5277 5278 error4: 5279 kmem_cache_destroy(hsotg->desc_gen_cache); 5280 kmem_cache_destroy(hsotg->desc_hsisoc_cache); 5281 error3: 5282 dwc2_hcd_release(hsotg); 5283 error2: 5284 usb_put_hcd(hcd); 5285 error1: 5286 5287 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 5288 kfree(hsotg->last_frame_num_array); 5289 kfree(hsotg->frame_num_array); 5290 #endif 5291 5292 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval); 5293 return retval; 5294 } 5295 5296 /* 5297 * Removes the HCD. 5298 * Frees memory and resources associated with the HCD and deregisters the bus. 5299 */ 5300 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) 5301 { 5302 struct usb_hcd *hcd; 5303 5304 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n"); 5305 5306 hcd = dwc2_hsotg_to_hcd(hsotg); 5307 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd); 5308 5309 if (!hcd) { 5310 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n", 5311 __func__); 5312 return; 5313 } 5314 5315 if (!IS_ERR_OR_NULL(hsotg->uphy)) 5316 otg_set_host(hsotg->uphy->otg, NULL); 5317 5318 usb_remove_hcd(hcd); 5319 hsotg->priv = NULL; 5320 5321 kmem_cache_destroy(hsotg->desc_gen_cache); 5322 kmem_cache_destroy(hsotg->desc_hsisoc_cache); 5323 5324 dwc2_hcd_release(hsotg); 5325 usb_put_hcd(hcd); 5326 5327 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 5328 kfree(hsotg->last_frame_num_array); 5329 kfree(hsotg->frame_num_array); 5330 #endif 5331 } 5332 5333 /** 5334 * dwc2_backup_host_registers() - Backup controller host registers. 5335 * When suspending usb bus, registers needs to be backuped 5336 * if controller power is disabled once suspended. 5337 * 5338 * @hsotg: Programming view of the DWC_otg controller 5339 */ 5340 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) 5341 { 5342 struct dwc2_hregs_backup *hr; 5343 int i; 5344 5345 dev_dbg(hsotg->dev, "%s\n", __func__); 5346 5347 /* Backup Host regs */ 5348 hr = &hsotg->hr_backup; 5349 hr->hcfg = dwc2_readl(hsotg->regs + HCFG); 5350 hr->haintmsk = dwc2_readl(hsotg->regs + HAINTMSK); 5351 for (i = 0; i < hsotg->params.host_channels; ++i) 5352 hr->hcintmsk[i] = dwc2_readl(hsotg->regs + HCINTMSK(i)); 5353 5354 hr->hprt0 = dwc2_read_hprt0(hsotg); 5355 hr->hfir = dwc2_readl(hsotg->regs + HFIR); 5356 hr->valid = true; 5357 5358 return 0; 5359 } 5360 5361 /** 5362 * dwc2_restore_host_registers() - Restore controller host registers. 5363 * When resuming usb bus, device registers needs to be restored 5364 * if controller power were disabled. 5365 * 5366 * @hsotg: Programming view of the DWC_otg controller 5367 */ 5368 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) 5369 { 5370 struct dwc2_hregs_backup *hr; 5371 int i; 5372 5373 dev_dbg(hsotg->dev, "%s\n", __func__); 5374 5375 /* Restore host regs */ 5376 hr = &hsotg->hr_backup; 5377 if (!hr->valid) { 5378 dev_err(hsotg->dev, "%s: no host registers to restore\n", 5379 __func__); 5380 return -EINVAL; 5381 } 5382 hr->valid = false; 5383 5384 dwc2_writel(hr->hcfg, hsotg->regs + HCFG); 5385 dwc2_writel(hr->haintmsk, hsotg->regs + HAINTMSK); 5386 5387 for (i = 0; i < hsotg->params.host_channels; ++i) 5388 dwc2_writel(hr->hcintmsk[i], hsotg->regs + HCINTMSK(i)); 5389 5390 dwc2_writel(hr->hprt0, hsotg->regs + HPRT0); 5391 dwc2_writel(hr->hfir, hsotg->regs + HFIR); 5392 hsotg->frame_number = 0; 5393 5394 return 0; 5395 } 5396