1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* 3 * hcd.c - DesignWare HS OTG Controller host-mode routines 4 * 5 * Copyright (C) 2004-2013 Synopsys, Inc. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The names of the above-listed copyright holders may not be used 17 * to endorse or promote products derived from this software without 18 * specific prior written permission. 19 * 20 * ALTERNATIVELY, this software may be distributed under the terms of the 21 * GNU General Public License ("GPL") as published by the Free Software 22 * Foundation; either version 2 of the License, or (at your option) any 23 * later version. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * This file contains the core HCD code, and implements the Linux hc_driver 40 * API 41 */ 42 #include <linux/kernel.h> 43 #include <linux/module.h> 44 #include <linux/spinlock.h> 45 #include <linux/interrupt.h> 46 #include <linux/platform_device.h> 47 #include <linux/dma-mapping.h> 48 #include <linux/delay.h> 49 #include <linux/io.h> 50 #include <linux/slab.h> 51 #include <linux/usb.h> 52 53 #include <linux/usb/hcd.h> 54 #include <linux/usb/ch11.h> 55 56 #include "core.h" 57 #include "hcd.h" 58 59 /* 60 * ========================================================================= 61 * Host Core Layer Functions 62 * ========================================================================= 63 */ 64 65 /** 66 * dwc2_enable_common_interrupts() - Initializes the commmon interrupts, 67 * used in both device and host modes 68 * 69 * @hsotg: Programming view of the DWC_otg controller 70 */ 71 static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg) 72 { 73 u32 intmsk; 74 75 /* Clear any pending OTG Interrupts */ 76 dwc2_writel(hsotg, 0xffffffff, GOTGINT); 77 78 /* Clear any pending interrupts */ 79 dwc2_writel(hsotg, 0xffffffff, GINTSTS); 80 81 /* Enable the interrupts in the GINTMSK */ 82 intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT; 83 84 if (!hsotg->params.host_dma) 85 intmsk |= GINTSTS_RXFLVL; 86 if (!hsotg->params.external_id_pin_ctl) 87 intmsk |= GINTSTS_CONIDSTSCHNG; 88 89 intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP | 90 GINTSTS_SESSREQINT; 91 92 if (dwc2_is_device_mode(hsotg) && hsotg->params.lpm) 93 intmsk |= GINTSTS_LPMTRANRCVD; 94 95 dwc2_writel(hsotg, intmsk, GINTMSK); 96 } 97 98 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg) 99 { 100 u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG); 101 102 switch (hsotg->hw_params.arch) { 103 case GHWCFG2_EXT_DMA_ARCH: 104 dev_err(hsotg->dev, "External DMA Mode not supported\n"); 105 return -EINVAL; 106 107 case GHWCFG2_INT_DMA_ARCH: 108 dev_dbg(hsotg->dev, "Internal DMA Mode\n"); 109 if (hsotg->params.ahbcfg != -1) { 110 ahbcfg &= GAHBCFG_CTRL_MASK; 111 ahbcfg |= hsotg->params.ahbcfg & 112 ~GAHBCFG_CTRL_MASK; 113 } 114 break; 115 116 case GHWCFG2_SLAVE_ONLY_ARCH: 117 default: 118 dev_dbg(hsotg->dev, "Slave Only Mode\n"); 119 break; 120 } 121 122 if (hsotg->params.host_dma) 123 ahbcfg |= GAHBCFG_DMA_EN; 124 else 125 hsotg->params.dma_desc_enable = false; 126 127 dwc2_writel(hsotg, ahbcfg, GAHBCFG); 128 129 return 0; 130 } 131 132 static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg) 133 { 134 u32 usbcfg; 135 136 usbcfg = dwc2_readl(hsotg, GUSBCFG); 137 usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP); 138 139 switch (hsotg->hw_params.op_mode) { 140 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 141 if (hsotg->params.otg_caps.hnp_support && 142 hsotg->params.otg_caps.srp_support) 143 usbcfg |= GUSBCFG_HNPCAP; 144 fallthrough; 145 146 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 147 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 148 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 149 if (hsotg->params.otg_caps.srp_support) 150 usbcfg |= GUSBCFG_SRPCAP; 151 break; 152 153 case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE: 154 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE: 155 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST: 156 default: 157 break; 158 } 159 160 dwc2_writel(hsotg, usbcfg, GUSBCFG); 161 } 162 163 static int dwc2_vbus_supply_init(struct dwc2_hsotg *hsotg) 164 { 165 if (hsotg->vbus_supply) 166 return regulator_enable(hsotg->vbus_supply); 167 168 return 0; 169 } 170 171 static int dwc2_vbus_supply_exit(struct dwc2_hsotg *hsotg) 172 { 173 if (hsotg->vbus_supply) 174 return regulator_disable(hsotg->vbus_supply); 175 176 return 0; 177 } 178 179 /** 180 * dwc2_enable_host_interrupts() - Enables the Host mode interrupts 181 * 182 * @hsotg: Programming view of DWC_otg controller 183 */ 184 static void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg) 185 { 186 u32 intmsk; 187 188 dev_dbg(hsotg->dev, "%s()\n", __func__); 189 190 /* Disable all interrupts */ 191 dwc2_writel(hsotg, 0, GINTMSK); 192 dwc2_writel(hsotg, 0, HAINTMSK); 193 194 /* Enable the common interrupts */ 195 dwc2_enable_common_interrupts(hsotg); 196 197 /* Enable host mode interrupts without disturbing common interrupts */ 198 intmsk = dwc2_readl(hsotg, GINTMSK); 199 intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT; 200 dwc2_writel(hsotg, intmsk, GINTMSK); 201 } 202 203 /** 204 * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts 205 * 206 * @hsotg: Programming view of DWC_otg controller 207 */ 208 static void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg) 209 { 210 u32 intmsk = dwc2_readl(hsotg, GINTMSK); 211 212 /* Disable host mode interrupts without disturbing common interrupts */ 213 intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT | 214 GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT); 215 dwc2_writel(hsotg, intmsk, GINTMSK); 216 } 217 218 /* 219 * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size 220 * For system that have a total fifo depth that is smaller than the default 221 * RX + TX fifo size. 222 * 223 * @hsotg: Programming view of DWC_otg controller 224 */ 225 static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg) 226 { 227 struct dwc2_core_params *params = &hsotg->params; 228 struct dwc2_hw_params *hw = &hsotg->hw_params; 229 u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size; 230 231 total_fifo_size = hw->total_fifo_size; 232 rxfsiz = params->host_rx_fifo_size; 233 nptxfsiz = params->host_nperio_tx_fifo_size; 234 ptxfsiz = params->host_perio_tx_fifo_size; 235 236 /* 237 * Will use Method 2 defined in the DWC2 spec: minimum FIFO depth 238 * allocation with support for high bandwidth endpoints. Synopsys 239 * defines MPS(Max Packet size) for a periodic EP=1024, and for 240 * non-periodic as 512. 241 */ 242 if (total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)) { 243 /* 244 * For Buffer DMA mode/Scatter Gather DMA mode 245 * 2 * ((Largest Packet size / 4) + 1 + 1) + n 246 * with n = number of host channel. 247 * 2 * ((1024/4) + 2) = 516 248 */ 249 rxfsiz = 516 + hw->host_channels; 250 251 /* 252 * min non-periodic tx fifo depth 253 * 2 * (largest non-periodic USB packet used / 4) 254 * 2 * (512/4) = 256 255 */ 256 nptxfsiz = 256; 257 258 /* 259 * min periodic tx fifo depth 260 * (largest packet size*MC)/4 261 * (1024 * 3)/4 = 768 262 */ 263 ptxfsiz = 768; 264 265 params->host_rx_fifo_size = rxfsiz; 266 params->host_nperio_tx_fifo_size = nptxfsiz; 267 params->host_perio_tx_fifo_size = ptxfsiz; 268 } 269 270 /* 271 * If the summation of RX, NPTX and PTX fifo sizes is still 272 * bigger than the total_fifo_size, then we have a problem. 273 * 274 * We won't be able to allocate as many endpoints. Right now, 275 * we're just printing an error message, but ideally this FIFO 276 * allocation algorithm would be improved in the future. 277 * 278 * FIXME improve this FIFO allocation algorithm. 279 */ 280 if (unlikely(total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz))) 281 dev_err(hsotg->dev, "invalid fifo sizes\n"); 282 } 283 284 static void dwc2_config_fifos(struct dwc2_hsotg *hsotg) 285 { 286 struct dwc2_core_params *params = &hsotg->params; 287 u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz; 288 289 if (!params->enable_dynamic_fifo) 290 return; 291 292 dwc2_calculate_dynamic_fifo(hsotg); 293 294 /* Rx FIFO */ 295 grxfsiz = dwc2_readl(hsotg, GRXFSIZ); 296 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz); 297 grxfsiz &= ~GRXFSIZ_DEPTH_MASK; 298 grxfsiz |= params->host_rx_fifo_size << 299 GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK; 300 dwc2_writel(hsotg, grxfsiz, GRXFSIZ); 301 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", 302 dwc2_readl(hsotg, GRXFSIZ)); 303 304 /* Non-periodic Tx FIFO */ 305 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n", 306 dwc2_readl(hsotg, GNPTXFSIZ)); 307 nptxfsiz = params->host_nperio_tx_fifo_size << 308 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; 309 nptxfsiz |= params->host_rx_fifo_size << 310 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; 311 dwc2_writel(hsotg, nptxfsiz, GNPTXFSIZ); 312 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n", 313 dwc2_readl(hsotg, GNPTXFSIZ)); 314 315 /* Periodic Tx FIFO */ 316 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n", 317 dwc2_readl(hsotg, HPTXFSIZ)); 318 hptxfsiz = params->host_perio_tx_fifo_size << 319 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; 320 hptxfsiz |= (params->host_rx_fifo_size + 321 params->host_nperio_tx_fifo_size) << 322 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; 323 dwc2_writel(hsotg, hptxfsiz, HPTXFSIZ); 324 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n", 325 dwc2_readl(hsotg, HPTXFSIZ)); 326 327 if (hsotg->params.en_multiple_tx_fifo && 328 hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_91a) { 329 /* 330 * This feature was implemented in 2.91a version 331 * Global DFIFOCFG calculation for Host mode - 332 * include RxFIFO, NPTXFIFO and HPTXFIFO 333 */ 334 dfifocfg = dwc2_readl(hsotg, GDFIFOCFG); 335 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK; 336 dfifocfg |= (params->host_rx_fifo_size + 337 params->host_nperio_tx_fifo_size + 338 params->host_perio_tx_fifo_size) << 339 GDFIFOCFG_EPINFOBASE_SHIFT & 340 GDFIFOCFG_EPINFOBASE_MASK; 341 dwc2_writel(hsotg, dfifocfg, GDFIFOCFG); 342 } 343 } 344 345 /** 346 * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for 347 * the HFIR register according to PHY type and speed 348 * 349 * @hsotg: Programming view of DWC_otg controller 350 * 351 * NOTE: The caller can modify the value of the HFIR register only after the 352 * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort) 353 * has been set 354 */ 355 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg) 356 { 357 u32 usbcfg; 358 u32 hprt0; 359 int clock = 60; /* default value */ 360 361 usbcfg = dwc2_readl(hsotg, GUSBCFG); 362 hprt0 = dwc2_readl(hsotg, HPRT0); 363 364 if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) && 365 !(usbcfg & GUSBCFG_PHYIF16)) 366 clock = 60; 367 if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type == 368 GHWCFG2_FS_PHY_TYPE_SHARED_ULPI) 369 clock = 48; 370 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 371 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16)) 372 clock = 30; 373 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 374 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16)) 375 clock = 60; 376 if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 377 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16)) 378 clock = 48; 379 if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) && 380 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI) 381 clock = 48; 382 if ((usbcfg & GUSBCFG_PHYSEL) && 383 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) 384 clock = 48; 385 386 if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED) 387 /* High speed case */ 388 return 125 * clock - 1; 389 390 /* FS/LS case */ 391 return 1000 * clock - 1; 392 } 393 394 /** 395 * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination 396 * buffer 397 * 398 * @hsotg: Programming view of DWC_otg controller 399 * @dest: Destination buffer for the packet 400 * @bytes: Number of bytes to copy to the destination 401 */ 402 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes) 403 { 404 u32 *data_buf = (u32 *)dest; 405 int word_count = (bytes + 3) / 4; 406 int i; 407 408 /* 409 * Todo: Account for the case where dest is not dword aligned. This 410 * requires reading data from the FIFO into a u32 temp buffer, then 411 * moving it into the data buffer. 412 */ 413 414 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes); 415 416 for (i = 0; i < word_count; i++, data_buf++) 417 *data_buf = dwc2_readl(hsotg, HCFIFO(0)); 418 } 419 420 /** 421 * dwc2_dump_channel_info() - Prints the state of a host channel 422 * 423 * @hsotg: Programming view of DWC_otg controller 424 * @chan: Pointer to the channel to dump 425 * 426 * Must be called with interrupt disabled and spinlock held 427 * 428 * NOTE: This function will be removed once the peripheral controller code 429 * is integrated and the driver is stable 430 */ 431 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg, 432 struct dwc2_host_chan *chan) 433 { 434 #ifdef VERBOSE_DEBUG 435 int num_channels = hsotg->params.host_channels; 436 struct dwc2_qh *qh; 437 u32 hcchar; 438 u32 hcsplt; 439 u32 hctsiz; 440 u32 hc_dma; 441 int i; 442 443 if (!chan) 444 return; 445 446 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num)); 447 hcsplt = dwc2_readl(hsotg, HCSPLT(chan->hc_num)); 448 hctsiz = dwc2_readl(hsotg, HCTSIZ(chan->hc_num)); 449 hc_dma = dwc2_readl(hsotg, HCDMA(chan->hc_num)); 450 451 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan); 452 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", 453 hcchar, hcsplt); 454 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", 455 hctsiz, hc_dma); 456 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 457 chan->dev_addr, chan->ep_num, chan->ep_is_in); 458 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 459 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 460 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start); 461 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started); 462 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 463 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 464 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 465 (unsigned long)chan->xfer_dma); 466 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 467 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 468 dev_dbg(hsotg->dev, " NP inactive sched:\n"); 469 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive, 470 qh_list_entry) 471 dev_dbg(hsotg->dev, " %p\n", qh); 472 dev_dbg(hsotg->dev, " NP waiting sched:\n"); 473 list_for_each_entry(qh, &hsotg->non_periodic_sched_waiting, 474 qh_list_entry) 475 dev_dbg(hsotg->dev, " %p\n", qh); 476 dev_dbg(hsotg->dev, " NP active sched:\n"); 477 list_for_each_entry(qh, &hsotg->non_periodic_sched_active, 478 qh_list_entry) 479 dev_dbg(hsotg->dev, " %p\n", qh); 480 dev_dbg(hsotg->dev, " Channels:\n"); 481 for (i = 0; i < num_channels; i++) { 482 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 483 484 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan); 485 } 486 #endif /* VERBOSE_DEBUG */ 487 } 488 489 static int _dwc2_hcd_start(struct usb_hcd *hcd); 490 491 static void dwc2_host_start(struct dwc2_hsotg *hsotg) 492 { 493 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 494 495 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg); 496 _dwc2_hcd_start(hcd); 497 } 498 499 static void dwc2_host_disconnect(struct dwc2_hsotg *hsotg) 500 { 501 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 502 503 hcd->self.is_b_host = 0; 504 } 505 506 static void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, 507 int *hub_addr, int *hub_port) 508 { 509 struct urb *urb = context; 510 511 if (urb->dev->tt) 512 *hub_addr = urb->dev->tt->hub->devnum; 513 else 514 *hub_addr = 0; 515 *hub_port = urb->dev->ttport; 516 } 517 518 /* 519 * ========================================================================= 520 * Low Level Host Channel Access Functions 521 * ========================================================================= 522 */ 523 524 static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg, 525 struct dwc2_host_chan *chan) 526 { 527 u32 hcintmsk = HCINTMSK_CHHLTD; 528 529 switch (chan->ep_type) { 530 case USB_ENDPOINT_XFER_CONTROL: 531 case USB_ENDPOINT_XFER_BULK: 532 dev_vdbg(hsotg->dev, "control/bulk\n"); 533 hcintmsk |= HCINTMSK_XFERCOMPL; 534 hcintmsk |= HCINTMSK_STALL; 535 hcintmsk |= HCINTMSK_XACTERR; 536 hcintmsk |= HCINTMSK_DATATGLERR; 537 if (chan->ep_is_in) { 538 hcintmsk |= HCINTMSK_BBLERR; 539 } else { 540 hcintmsk |= HCINTMSK_NAK; 541 hcintmsk |= HCINTMSK_NYET; 542 if (chan->do_ping) 543 hcintmsk |= HCINTMSK_ACK; 544 } 545 546 if (chan->do_split) { 547 hcintmsk |= HCINTMSK_NAK; 548 if (chan->complete_split) 549 hcintmsk |= HCINTMSK_NYET; 550 else 551 hcintmsk |= HCINTMSK_ACK; 552 } 553 554 if (chan->error_state) 555 hcintmsk |= HCINTMSK_ACK; 556 break; 557 558 case USB_ENDPOINT_XFER_INT: 559 if (dbg_perio()) 560 dev_vdbg(hsotg->dev, "intr\n"); 561 hcintmsk |= HCINTMSK_XFERCOMPL; 562 hcintmsk |= HCINTMSK_NAK; 563 hcintmsk |= HCINTMSK_STALL; 564 hcintmsk |= HCINTMSK_XACTERR; 565 hcintmsk |= HCINTMSK_DATATGLERR; 566 hcintmsk |= HCINTMSK_FRMOVRUN; 567 568 if (chan->ep_is_in) 569 hcintmsk |= HCINTMSK_BBLERR; 570 if (chan->error_state) 571 hcintmsk |= HCINTMSK_ACK; 572 if (chan->do_split) { 573 if (chan->complete_split) 574 hcintmsk |= HCINTMSK_NYET; 575 else 576 hcintmsk |= HCINTMSK_ACK; 577 } 578 break; 579 580 case USB_ENDPOINT_XFER_ISOC: 581 if (dbg_perio()) 582 dev_vdbg(hsotg->dev, "isoc\n"); 583 hcintmsk |= HCINTMSK_XFERCOMPL; 584 hcintmsk |= HCINTMSK_FRMOVRUN; 585 hcintmsk |= HCINTMSK_ACK; 586 587 if (chan->ep_is_in) { 588 hcintmsk |= HCINTMSK_XACTERR; 589 hcintmsk |= HCINTMSK_BBLERR; 590 } 591 break; 592 default: 593 dev_err(hsotg->dev, "## Unknown EP type ##\n"); 594 break; 595 } 596 597 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num)); 598 if (dbg_hc(chan)) 599 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); 600 } 601 602 static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg, 603 struct dwc2_host_chan *chan) 604 { 605 u32 hcintmsk = HCINTMSK_CHHLTD; 606 607 /* 608 * For Descriptor DMA mode core halts the channel on AHB error. 609 * Interrupt is not required. 610 */ 611 if (!hsotg->params.dma_desc_enable) { 612 if (dbg_hc(chan)) 613 dev_vdbg(hsotg->dev, "desc DMA disabled\n"); 614 hcintmsk |= HCINTMSK_AHBERR; 615 } else { 616 if (dbg_hc(chan)) 617 dev_vdbg(hsotg->dev, "desc DMA enabled\n"); 618 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 619 hcintmsk |= HCINTMSK_XFERCOMPL; 620 } 621 622 if (chan->error_state && !chan->do_split && 623 chan->ep_type != USB_ENDPOINT_XFER_ISOC) { 624 if (dbg_hc(chan)) 625 dev_vdbg(hsotg->dev, "setting ACK\n"); 626 hcintmsk |= HCINTMSK_ACK; 627 if (chan->ep_is_in) { 628 hcintmsk |= HCINTMSK_DATATGLERR; 629 if (chan->ep_type != USB_ENDPOINT_XFER_INT) 630 hcintmsk |= HCINTMSK_NAK; 631 } 632 } 633 634 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num)); 635 if (dbg_hc(chan)) 636 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); 637 } 638 639 static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg, 640 struct dwc2_host_chan *chan) 641 { 642 u32 intmsk; 643 644 if (hsotg->params.host_dma) { 645 if (dbg_hc(chan)) 646 dev_vdbg(hsotg->dev, "DMA enabled\n"); 647 dwc2_hc_enable_dma_ints(hsotg, chan); 648 } else { 649 if (dbg_hc(chan)) 650 dev_vdbg(hsotg->dev, "DMA disabled\n"); 651 dwc2_hc_enable_slave_ints(hsotg, chan); 652 } 653 654 /* Enable the top level host channel interrupt */ 655 intmsk = dwc2_readl(hsotg, HAINTMSK); 656 intmsk |= 1 << chan->hc_num; 657 dwc2_writel(hsotg, intmsk, HAINTMSK); 658 if (dbg_hc(chan)) 659 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk); 660 661 /* Make sure host channel interrupts are enabled */ 662 intmsk = dwc2_readl(hsotg, GINTMSK); 663 intmsk |= GINTSTS_HCHINT; 664 dwc2_writel(hsotg, intmsk, GINTMSK); 665 if (dbg_hc(chan)) 666 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk); 667 } 668 669 /** 670 * dwc2_hc_init() - Prepares a host channel for transferring packets to/from 671 * a specific endpoint 672 * 673 * @hsotg: Programming view of DWC_otg controller 674 * @chan: Information needed to initialize the host channel 675 * 676 * The HCCHARn register is set up with the characteristics specified in chan. 677 * Host channel interrupts that may need to be serviced while this transfer is 678 * in progress are enabled. 679 */ 680 static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) 681 { 682 u8 hc_num = chan->hc_num; 683 u32 hcintmsk; 684 u32 hcchar; 685 u32 hcsplt = 0; 686 687 if (dbg_hc(chan)) 688 dev_vdbg(hsotg->dev, "%s()\n", __func__); 689 690 /* Clear old interrupt conditions for this host channel */ 691 hcintmsk = 0xffffffff; 692 hcintmsk &= ~HCINTMSK_RESERVED14_31; 693 dwc2_writel(hsotg, hcintmsk, HCINT(hc_num)); 694 695 /* Enable channel interrupts required for this transfer */ 696 dwc2_hc_enable_ints(hsotg, chan); 697 698 /* 699 * Program the HCCHARn register with the endpoint characteristics for 700 * the current transfer 701 */ 702 hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK; 703 hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK; 704 if (chan->ep_is_in) 705 hcchar |= HCCHAR_EPDIR; 706 if (chan->speed == USB_SPEED_LOW) 707 hcchar |= HCCHAR_LSPDDEV; 708 hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK; 709 hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK; 710 dwc2_writel(hsotg, hcchar, HCCHAR(hc_num)); 711 if (dbg_hc(chan)) { 712 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n", 713 hc_num, hcchar); 714 715 dev_vdbg(hsotg->dev, "%s: Channel %d\n", 716 __func__, hc_num); 717 dev_vdbg(hsotg->dev, " Dev Addr: %d\n", 718 chan->dev_addr); 719 dev_vdbg(hsotg->dev, " Ep Num: %d\n", 720 chan->ep_num); 721 dev_vdbg(hsotg->dev, " Is In: %d\n", 722 chan->ep_is_in); 723 dev_vdbg(hsotg->dev, " Is Low Speed: %d\n", 724 chan->speed == USB_SPEED_LOW); 725 dev_vdbg(hsotg->dev, " Ep Type: %d\n", 726 chan->ep_type); 727 dev_vdbg(hsotg->dev, " Max Pkt: %d\n", 728 chan->max_packet); 729 } 730 731 /* Program the HCSPLT register for SPLITs */ 732 if (chan->do_split) { 733 if (dbg_hc(chan)) 734 dev_vdbg(hsotg->dev, 735 "Programming HC %d with split --> %s\n", 736 hc_num, 737 chan->complete_split ? "CSPLIT" : "SSPLIT"); 738 if (chan->complete_split) 739 hcsplt |= HCSPLT_COMPSPLT; 740 hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT & 741 HCSPLT_XACTPOS_MASK; 742 hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT & 743 HCSPLT_HUBADDR_MASK; 744 hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT & 745 HCSPLT_PRTADDR_MASK; 746 if (dbg_hc(chan)) { 747 dev_vdbg(hsotg->dev, " comp split %d\n", 748 chan->complete_split); 749 dev_vdbg(hsotg->dev, " xact pos %d\n", 750 chan->xact_pos); 751 dev_vdbg(hsotg->dev, " hub addr %d\n", 752 chan->hub_addr); 753 dev_vdbg(hsotg->dev, " hub port %d\n", 754 chan->hub_port); 755 dev_vdbg(hsotg->dev, " is_in %d\n", 756 chan->ep_is_in); 757 dev_vdbg(hsotg->dev, " Max Pkt %d\n", 758 chan->max_packet); 759 dev_vdbg(hsotg->dev, " xferlen %d\n", 760 chan->xfer_len); 761 } 762 } 763 764 dwc2_writel(hsotg, hcsplt, HCSPLT(hc_num)); 765 } 766 767 /** 768 * dwc2_hc_halt() - Attempts to halt a host channel 769 * 770 * @hsotg: Controller register interface 771 * @chan: Host channel to halt 772 * @halt_status: Reason for halting the channel 773 * 774 * This function should only be called in Slave mode or to abort a transfer in 775 * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the 776 * controller halts the channel when the transfer is complete or a condition 777 * occurs that requires application intervention. 778 * 779 * In slave mode, checks for a free request queue entry, then sets the Channel 780 * Enable and Channel Disable bits of the Host Channel Characteristics 781 * register of the specified channel to intiate the halt. If there is no free 782 * request queue entry, sets only the Channel Disable bit of the HCCHARn 783 * register to flush requests for this channel. In the latter case, sets a 784 * flag to indicate that the host channel needs to be halted when a request 785 * queue slot is open. 786 * 787 * In DMA mode, always sets the Channel Enable and Channel Disable bits of the 788 * HCCHARn register. The controller ensures there is space in the request 789 * queue before submitting the halt request. 790 * 791 * Some time may elapse before the core flushes any posted requests for this 792 * host channel and halts. The Channel Halted interrupt handler completes the 793 * deactivation of the host channel. 794 */ 795 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 796 enum dwc2_halt_status halt_status) 797 { 798 u32 nptxsts, hptxsts, hcchar; 799 800 if (dbg_hc(chan)) 801 dev_vdbg(hsotg->dev, "%s()\n", __func__); 802 803 /* 804 * In buffer DMA or external DMA mode channel can't be halted 805 * for non-split periodic channels. At the end of the next 806 * uframe/frame (in the worst case), the core generates a channel 807 * halted and disables the channel automatically. 808 */ 809 if ((hsotg->params.g_dma && !hsotg->params.g_dma_desc) || 810 hsotg->hw_params.arch == GHWCFG2_EXT_DMA_ARCH) { 811 if (!chan->do_split && 812 (chan->ep_type == USB_ENDPOINT_XFER_ISOC || 813 chan->ep_type == USB_ENDPOINT_XFER_INT)) { 814 dev_err(hsotg->dev, "%s() Channel can't be halted\n", 815 __func__); 816 return; 817 } 818 } 819 820 if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS) 821 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status); 822 823 if (halt_status == DWC2_HC_XFER_URB_DEQUEUE || 824 halt_status == DWC2_HC_XFER_AHB_ERR) { 825 /* 826 * Disable all channel interrupts except Ch Halted. The QTD 827 * and QH state associated with this transfer has been cleared 828 * (in the case of URB_DEQUEUE), so the channel needs to be 829 * shut down carefully to prevent crashes. 830 */ 831 u32 hcintmsk = HCINTMSK_CHHLTD; 832 833 dev_vdbg(hsotg->dev, "dequeue/error\n"); 834 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num)); 835 836 /* 837 * Make sure no other interrupts besides halt are currently 838 * pending. Handling another interrupt could cause a crash due 839 * to the QTD and QH state. 840 */ 841 dwc2_writel(hsotg, ~hcintmsk, HCINT(chan->hc_num)); 842 843 /* 844 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR 845 * even if the channel was already halted for some other 846 * reason 847 */ 848 chan->halt_status = halt_status; 849 850 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num)); 851 if (!(hcchar & HCCHAR_CHENA)) { 852 /* 853 * The channel is either already halted or it hasn't 854 * started yet. In DMA mode, the transfer may halt if 855 * it finishes normally or a condition occurs that 856 * requires driver intervention. Don't want to halt 857 * the channel again. In either Slave or DMA mode, 858 * it's possible that the transfer has been assigned 859 * to a channel, but not started yet when an URB is 860 * dequeued. Don't want to halt a channel that hasn't 861 * started yet. 862 */ 863 return; 864 } 865 } 866 if (chan->halt_pending) { 867 /* 868 * A halt has already been issued for this channel. This might 869 * happen when a transfer is aborted by a higher level in 870 * the stack. 871 */ 872 dev_vdbg(hsotg->dev, 873 "*** %s: Channel %d, chan->halt_pending already set ***\n", 874 __func__, chan->hc_num); 875 return; 876 } 877 878 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num)); 879 880 /* No need to set the bit in DDMA for disabling the channel */ 881 /* TODO check it everywhere channel is disabled */ 882 if (!hsotg->params.dma_desc_enable) { 883 if (dbg_hc(chan)) 884 dev_vdbg(hsotg->dev, "desc DMA disabled\n"); 885 hcchar |= HCCHAR_CHENA; 886 } else { 887 if (dbg_hc(chan)) 888 dev_dbg(hsotg->dev, "desc DMA enabled\n"); 889 } 890 hcchar |= HCCHAR_CHDIS; 891 892 if (!hsotg->params.host_dma) { 893 if (dbg_hc(chan)) 894 dev_vdbg(hsotg->dev, "DMA not enabled\n"); 895 hcchar |= HCCHAR_CHENA; 896 897 /* Check for space in the request queue to issue the halt */ 898 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL || 899 chan->ep_type == USB_ENDPOINT_XFER_BULK) { 900 dev_vdbg(hsotg->dev, "control/bulk\n"); 901 nptxsts = dwc2_readl(hsotg, GNPTXSTS); 902 if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) { 903 dev_vdbg(hsotg->dev, "Disabling channel\n"); 904 hcchar &= ~HCCHAR_CHENA; 905 } 906 } else { 907 if (dbg_perio()) 908 dev_vdbg(hsotg->dev, "isoc/intr\n"); 909 hptxsts = dwc2_readl(hsotg, HPTXSTS); 910 if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 || 911 hsotg->queuing_high_bandwidth) { 912 if (dbg_perio()) 913 dev_vdbg(hsotg->dev, "Disabling channel\n"); 914 hcchar &= ~HCCHAR_CHENA; 915 } 916 } 917 } else { 918 if (dbg_hc(chan)) 919 dev_vdbg(hsotg->dev, "DMA enabled\n"); 920 } 921 922 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num)); 923 chan->halt_status = halt_status; 924 925 if (hcchar & HCCHAR_CHENA) { 926 if (dbg_hc(chan)) 927 dev_vdbg(hsotg->dev, "Channel enabled\n"); 928 chan->halt_pending = 1; 929 chan->halt_on_queue = 0; 930 } else { 931 if (dbg_hc(chan)) 932 dev_vdbg(hsotg->dev, "Channel disabled\n"); 933 chan->halt_on_queue = 1; 934 } 935 936 if (dbg_hc(chan)) { 937 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 938 chan->hc_num); 939 dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n", 940 hcchar); 941 dev_vdbg(hsotg->dev, " halt_pending: %d\n", 942 chan->halt_pending); 943 dev_vdbg(hsotg->dev, " halt_on_queue: %d\n", 944 chan->halt_on_queue); 945 dev_vdbg(hsotg->dev, " halt_status: %d\n", 946 chan->halt_status); 947 } 948 } 949 950 /** 951 * dwc2_hc_cleanup() - Clears the transfer state for a host channel 952 * 953 * @hsotg: Programming view of DWC_otg controller 954 * @chan: Identifies the host channel to clean up 955 * 956 * This function is normally called after a transfer is done and the host 957 * channel is being released 958 */ 959 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) 960 { 961 u32 hcintmsk; 962 963 chan->xfer_started = 0; 964 965 list_del_init(&chan->split_order_list_entry); 966 967 /* 968 * Clear channel interrupt enables and any unhandled channel interrupt 969 * conditions 970 */ 971 dwc2_writel(hsotg, 0, HCINTMSK(chan->hc_num)); 972 hcintmsk = 0xffffffff; 973 hcintmsk &= ~HCINTMSK_RESERVED14_31; 974 dwc2_writel(hsotg, hcintmsk, HCINT(chan->hc_num)); 975 } 976 977 /** 978 * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in 979 * which frame a periodic transfer should occur 980 * 981 * @hsotg: Programming view of DWC_otg controller 982 * @chan: Identifies the host channel to set up and its properties 983 * @hcchar: Current value of the HCCHAR register for the specified host channel 984 * 985 * This function has no effect on non-periodic transfers 986 */ 987 static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg, 988 struct dwc2_host_chan *chan, u32 *hcchar) 989 { 990 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 991 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 992 int host_speed; 993 int xfer_ns; 994 int xfer_us; 995 int bytes_in_fifo; 996 u16 fifo_space; 997 u16 frame_number; 998 u16 wire_frame; 999 1000 /* 1001 * Try to figure out if we're an even or odd frame. If we set 1002 * even and the current frame number is even the the transfer 1003 * will happen immediately. Similar if both are odd. If one is 1004 * even and the other is odd then the transfer will happen when 1005 * the frame number ticks. 1006 * 1007 * There's a bit of a balancing act to get this right. 1008 * Sometimes we may want to send data in the current frame (AK 1009 * right away). We might want to do this if the frame number 1010 * _just_ ticked, but we might also want to do this in order 1011 * to continue a split transaction that happened late in a 1012 * microframe (so we didn't know to queue the next transfer 1013 * until the frame number had ticked). The problem is that we 1014 * need a lot of knowledge to know if there's actually still 1015 * time to send things or if it would be better to wait until 1016 * the next frame. 1017 * 1018 * We can look at how much time is left in the current frame 1019 * and make a guess about whether we'll have time to transfer. 1020 * We'll do that. 1021 */ 1022 1023 /* Get speed host is running at */ 1024 host_speed = (chan->speed != USB_SPEED_HIGH && 1025 !chan->do_split) ? chan->speed : USB_SPEED_HIGH; 1026 1027 /* See how many bytes are in the periodic FIFO right now */ 1028 fifo_space = (dwc2_readl(hsotg, HPTXSTS) & 1029 TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT; 1030 bytes_in_fifo = sizeof(u32) * 1031 (hsotg->params.host_perio_tx_fifo_size - 1032 fifo_space); 1033 1034 /* 1035 * Roughly estimate bus time for everything in the periodic 1036 * queue + our new transfer. This is "rough" because we're 1037 * using a function that makes takes into account IN/OUT 1038 * and INT/ISO and we're just slamming in one value for all 1039 * transfers. This should be an over-estimate and that should 1040 * be OK, but we can probably tighten it. 1041 */ 1042 xfer_ns = usb_calc_bus_time(host_speed, false, false, 1043 chan->xfer_len + bytes_in_fifo); 1044 xfer_us = NS_TO_US(xfer_ns); 1045 1046 /* See what frame number we'll be at by the time we finish */ 1047 frame_number = dwc2_hcd_get_future_frame_number(hsotg, xfer_us); 1048 1049 /* This is when we were scheduled to be on the wire */ 1050 wire_frame = dwc2_frame_num_inc(chan->qh->next_active_frame, 1); 1051 1052 /* 1053 * If we'd finish _after_ the frame we're scheduled in then 1054 * it's hopeless. Just schedule right away and hope for the 1055 * best. Note that it _might_ be wise to call back into the 1056 * scheduler to pick a better frame, but this is better than 1057 * nothing. 1058 */ 1059 if (dwc2_frame_num_gt(frame_number, wire_frame)) { 1060 dwc2_sch_vdbg(hsotg, 1061 "QH=%p EO MISS fr=%04x=>%04x (%+d)\n", 1062 chan->qh, wire_frame, frame_number, 1063 dwc2_frame_num_dec(frame_number, 1064 wire_frame)); 1065 wire_frame = frame_number; 1066 1067 /* 1068 * We picked a different frame number; communicate this 1069 * back to the scheduler so it doesn't try to schedule 1070 * another in the same frame. 1071 * 1072 * Remember that next_active_frame is 1 before the wire 1073 * frame. 1074 */ 1075 chan->qh->next_active_frame = 1076 dwc2_frame_num_dec(frame_number, 1); 1077 } 1078 1079 if (wire_frame & 1) 1080 *hcchar |= HCCHAR_ODDFRM; 1081 else 1082 *hcchar &= ~HCCHAR_ODDFRM; 1083 } 1084 } 1085 1086 static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan) 1087 { 1088 /* Set up the initial PID for the transfer */ 1089 if (chan->speed == USB_SPEED_HIGH) { 1090 if (chan->ep_is_in) { 1091 if (chan->multi_count == 1) 1092 chan->data_pid_start = DWC2_HC_PID_DATA0; 1093 else if (chan->multi_count == 2) 1094 chan->data_pid_start = DWC2_HC_PID_DATA1; 1095 else 1096 chan->data_pid_start = DWC2_HC_PID_DATA2; 1097 } else { 1098 if (chan->multi_count == 1) 1099 chan->data_pid_start = DWC2_HC_PID_DATA0; 1100 else 1101 chan->data_pid_start = DWC2_HC_PID_MDATA; 1102 } 1103 } else { 1104 chan->data_pid_start = DWC2_HC_PID_DATA0; 1105 } 1106 } 1107 1108 /** 1109 * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with 1110 * the Host Channel 1111 * 1112 * @hsotg: Programming view of DWC_otg controller 1113 * @chan: Information needed to initialize the host channel 1114 * 1115 * This function should only be called in Slave mode. For a channel associated 1116 * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel 1117 * associated with a periodic EP, the periodic Tx FIFO is written. 1118 * 1119 * Upon return the xfer_buf and xfer_count fields in chan are incremented by 1120 * the number of bytes written to the Tx FIFO. 1121 */ 1122 static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg, 1123 struct dwc2_host_chan *chan) 1124 { 1125 u32 i; 1126 u32 remaining_count; 1127 u32 byte_count; 1128 u32 dword_count; 1129 u32 *data_buf = (u32 *)chan->xfer_buf; 1130 1131 if (dbg_hc(chan)) 1132 dev_vdbg(hsotg->dev, "%s()\n", __func__); 1133 1134 remaining_count = chan->xfer_len - chan->xfer_count; 1135 if (remaining_count > chan->max_packet) 1136 byte_count = chan->max_packet; 1137 else 1138 byte_count = remaining_count; 1139 1140 dword_count = (byte_count + 3) / 4; 1141 1142 if (((unsigned long)data_buf & 0x3) == 0) { 1143 /* xfer_buf is DWORD aligned */ 1144 for (i = 0; i < dword_count; i++, data_buf++) 1145 dwc2_writel(hsotg, *data_buf, HCFIFO(chan->hc_num)); 1146 } else { 1147 /* xfer_buf is not DWORD aligned */ 1148 for (i = 0; i < dword_count; i++, data_buf++) { 1149 u32 data = data_buf[0] | data_buf[1] << 8 | 1150 data_buf[2] << 16 | data_buf[3] << 24; 1151 dwc2_writel(hsotg, data, HCFIFO(chan->hc_num)); 1152 } 1153 } 1154 1155 chan->xfer_count += byte_count; 1156 chan->xfer_buf += byte_count; 1157 } 1158 1159 /** 1160 * dwc2_hc_do_ping() - Starts a PING transfer 1161 * 1162 * @hsotg: Programming view of DWC_otg controller 1163 * @chan: Information needed to initialize the host channel 1164 * 1165 * This function should only be called in Slave mode. The Do Ping bit is set in 1166 * the HCTSIZ register, then the channel is enabled. 1167 */ 1168 static void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, 1169 struct dwc2_host_chan *chan) 1170 { 1171 u32 hcchar; 1172 u32 hctsiz; 1173 1174 if (dbg_hc(chan)) 1175 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1176 chan->hc_num); 1177 1178 hctsiz = TSIZ_DOPNG; 1179 hctsiz |= 1 << TSIZ_PKTCNT_SHIFT; 1180 dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num)); 1181 1182 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num)); 1183 hcchar |= HCCHAR_CHENA; 1184 hcchar &= ~HCCHAR_CHDIS; 1185 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num)); 1186 } 1187 1188 /** 1189 * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host 1190 * channel and starts the transfer 1191 * 1192 * @hsotg: Programming view of DWC_otg controller 1193 * @chan: Information needed to initialize the host channel. The xfer_len value 1194 * may be reduced to accommodate the max widths of the XferSize and 1195 * PktCnt fields in the HCTSIZn register. The multi_count value may be 1196 * changed to reflect the final xfer_len value. 1197 * 1198 * This function may be called in either Slave mode or DMA mode. In Slave mode, 1199 * the caller must ensure that there is sufficient space in the request queue 1200 * and Tx Data FIFO. 1201 * 1202 * For an OUT transfer in Slave mode, it loads a data packet into the 1203 * appropriate FIFO. If necessary, additional data packets are loaded in the 1204 * Host ISR. 1205 * 1206 * For an IN transfer in Slave mode, a data packet is requested. The data 1207 * packets are unloaded from the Rx FIFO in the Host ISR. If necessary, 1208 * additional data packets are requested in the Host ISR. 1209 * 1210 * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ 1211 * register along with a packet count of 1 and the channel is enabled. This 1212 * causes a single PING transaction to occur. Other fields in HCTSIZ are 1213 * simply set to 0 since no data transfer occurs in this case. 1214 * 1215 * For a PING transfer in DMA mode, the HCTSIZ register is initialized with 1216 * all the information required to perform the subsequent data transfer. In 1217 * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the 1218 * controller performs the entire PING protocol, then starts the data 1219 * transfer. 1220 */ 1221 static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 1222 struct dwc2_host_chan *chan) 1223 { 1224 u32 max_hc_xfer_size = hsotg->params.max_transfer_size; 1225 u16 max_hc_pkt_count = hsotg->params.max_packet_count; 1226 u32 hcchar; 1227 u32 hctsiz = 0; 1228 u16 num_packets; 1229 u32 ec_mc; 1230 1231 if (dbg_hc(chan)) 1232 dev_vdbg(hsotg->dev, "%s()\n", __func__); 1233 1234 if (chan->do_ping) { 1235 if (!hsotg->params.host_dma) { 1236 if (dbg_hc(chan)) 1237 dev_vdbg(hsotg->dev, "ping, no DMA\n"); 1238 dwc2_hc_do_ping(hsotg, chan); 1239 chan->xfer_started = 1; 1240 return; 1241 } 1242 1243 if (dbg_hc(chan)) 1244 dev_vdbg(hsotg->dev, "ping, DMA\n"); 1245 1246 hctsiz |= TSIZ_DOPNG; 1247 } 1248 1249 if (chan->do_split) { 1250 if (dbg_hc(chan)) 1251 dev_vdbg(hsotg->dev, "split\n"); 1252 num_packets = 1; 1253 1254 if (chan->complete_split && !chan->ep_is_in) 1255 /* 1256 * For CSPLIT OUT Transfer, set the size to 0 so the 1257 * core doesn't expect any data written to the FIFO 1258 */ 1259 chan->xfer_len = 0; 1260 else if (chan->ep_is_in || chan->xfer_len > chan->max_packet) 1261 chan->xfer_len = chan->max_packet; 1262 else if (!chan->ep_is_in && chan->xfer_len > 188) 1263 chan->xfer_len = 188; 1264 1265 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT & 1266 TSIZ_XFERSIZE_MASK; 1267 1268 /* For split set ec_mc for immediate retries */ 1269 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1270 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1271 ec_mc = 3; 1272 else 1273 ec_mc = 1; 1274 } else { 1275 if (dbg_hc(chan)) 1276 dev_vdbg(hsotg->dev, "no split\n"); 1277 /* 1278 * Ensure that the transfer length and packet count will fit 1279 * in the widths allocated for them in the HCTSIZn register 1280 */ 1281 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1282 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1283 /* 1284 * Make sure the transfer size is no larger than one 1285 * (micro)frame's worth of data. (A check was done 1286 * when the periodic transfer was accepted to ensure 1287 * that a (micro)frame's worth of data can be 1288 * programmed into a channel.) 1289 */ 1290 u32 max_periodic_len = 1291 chan->multi_count * chan->max_packet; 1292 1293 if (chan->xfer_len > max_periodic_len) 1294 chan->xfer_len = max_periodic_len; 1295 } else if (chan->xfer_len > max_hc_xfer_size) { 1296 /* 1297 * Make sure that xfer_len is a multiple of max packet 1298 * size 1299 */ 1300 chan->xfer_len = 1301 max_hc_xfer_size - chan->max_packet + 1; 1302 } 1303 1304 if (chan->xfer_len > 0) { 1305 num_packets = (chan->xfer_len + chan->max_packet - 1) / 1306 chan->max_packet; 1307 if (num_packets > max_hc_pkt_count) { 1308 num_packets = max_hc_pkt_count; 1309 chan->xfer_len = num_packets * chan->max_packet; 1310 } else if (chan->ep_is_in) { 1311 /* 1312 * Always program an integral # of max packets 1313 * for IN transfers. 1314 * Note: This assumes that the input buffer is 1315 * aligned and sized accordingly. 1316 */ 1317 chan->xfer_len = num_packets * chan->max_packet; 1318 } 1319 } else { 1320 /* Need 1 packet for transfer length of 0 */ 1321 num_packets = 1; 1322 } 1323 1324 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1325 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1326 /* 1327 * Make sure that the multi_count field matches the 1328 * actual transfer length 1329 */ 1330 chan->multi_count = num_packets; 1331 1332 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1333 dwc2_set_pid_isoc(chan); 1334 1335 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT & 1336 TSIZ_XFERSIZE_MASK; 1337 1338 /* The ec_mc gets the multi_count for non-split */ 1339 ec_mc = chan->multi_count; 1340 } 1341 1342 chan->start_pkt_count = num_packets; 1343 hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK; 1344 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & 1345 TSIZ_SC_MC_PID_MASK; 1346 dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num)); 1347 if (dbg_hc(chan)) { 1348 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n", 1349 hctsiz, chan->hc_num); 1350 1351 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1352 chan->hc_num); 1353 dev_vdbg(hsotg->dev, " Xfer Size: %d\n", 1354 (hctsiz & TSIZ_XFERSIZE_MASK) >> 1355 TSIZ_XFERSIZE_SHIFT); 1356 dev_vdbg(hsotg->dev, " Num Pkts: %d\n", 1357 (hctsiz & TSIZ_PKTCNT_MASK) >> 1358 TSIZ_PKTCNT_SHIFT); 1359 dev_vdbg(hsotg->dev, " Start PID: %d\n", 1360 (hctsiz & TSIZ_SC_MC_PID_MASK) >> 1361 TSIZ_SC_MC_PID_SHIFT); 1362 } 1363 1364 if (hsotg->params.host_dma) { 1365 dma_addr_t dma_addr; 1366 1367 if (chan->align_buf) { 1368 if (dbg_hc(chan)) 1369 dev_vdbg(hsotg->dev, "align_buf\n"); 1370 dma_addr = chan->align_buf; 1371 } else { 1372 dma_addr = chan->xfer_dma; 1373 } 1374 dwc2_writel(hsotg, (u32)dma_addr, HCDMA(chan->hc_num)); 1375 1376 if (dbg_hc(chan)) 1377 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n", 1378 (unsigned long)dma_addr, chan->hc_num); 1379 } 1380 1381 /* Start the split */ 1382 if (chan->do_split) { 1383 u32 hcsplt = dwc2_readl(hsotg, HCSPLT(chan->hc_num)); 1384 1385 hcsplt |= HCSPLT_SPLTENA; 1386 dwc2_writel(hsotg, hcsplt, HCSPLT(chan->hc_num)); 1387 } 1388 1389 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num)); 1390 hcchar &= ~HCCHAR_MULTICNT_MASK; 1391 hcchar |= (ec_mc << HCCHAR_MULTICNT_SHIFT) & HCCHAR_MULTICNT_MASK; 1392 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); 1393 1394 if (hcchar & HCCHAR_CHDIS) 1395 dev_warn(hsotg->dev, 1396 "%s: chdis set, channel %d, hcchar 0x%08x\n", 1397 __func__, chan->hc_num, hcchar); 1398 1399 /* Set host channel enable after all other setup is complete */ 1400 hcchar |= HCCHAR_CHENA; 1401 hcchar &= ~HCCHAR_CHDIS; 1402 1403 if (dbg_hc(chan)) 1404 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", 1405 (hcchar & HCCHAR_MULTICNT_MASK) >> 1406 HCCHAR_MULTICNT_SHIFT); 1407 1408 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num)); 1409 if (dbg_hc(chan)) 1410 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, 1411 chan->hc_num); 1412 1413 chan->xfer_started = 1; 1414 chan->requests++; 1415 1416 if (!hsotg->params.host_dma && 1417 !chan->ep_is_in && chan->xfer_len > 0) 1418 /* Load OUT packet into the appropriate Tx FIFO */ 1419 dwc2_hc_write_packet(hsotg, chan); 1420 } 1421 1422 /** 1423 * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a 1424 * host channel and starts the transfer in Descriptor DMA mode 1425 * 1426 * @hsotg: Programming view of DWC_otg controller 1427 * @chan: Information needed to initialize the host channel 1428 * 1429 * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set. 1430 * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field 1431 * with micro-frame bitmap. 1432 * 1433 * Initializes HCDMA register with descriptor list address and CTD value then 1434 * starts the transfer via enabling the channel. 1435 */ 1436 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 1437 struct dwc2_host_chan *chan) 1438 { 1439 u32 hcchar; 1440 u32 hctsiz = 0; 1441 1442 if (chan->do_ping) 1443 hctsiz |= TSIZ_DOPNG; 1444 1445 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1446 dwc2_set_pid_isoc(chan); 1447 1448 /* Packet Count and Xfer Size are not used in Descriptor DMA mode */ 1449 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & 1450 TSIZ_SC_MC_PID_MASK; 1451 1452 /* 0 - 1 descriptor, 1 - 2 descriptors, etc */ 1453 hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK; 1454 1455 /* Non-zero only for high-speed interrupt endpoints */ 1456 hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK; 1457 1458 if (dbg_hc(chan)) { 1459 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1460 chan->hc_num); 1461 dev_vdbg(hsotg->dev, " Start PID: %d\n", 1462 chan->data_pid_start); 1463 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1); 1464 } 1465 1466 dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num)); 1467 1468 dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr, 1469 chan->desc_list_sz, DMA_TO_DEVICE); 1470 1471 dwc2_writel(hsotg, chan->desc_list_addr, HCDMA(chan->hc_num)); 1472 1473 if (dbg_hc(chan)) 1474 dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n", 1475 &chan->desc_list_addr, chan->hc_num); 1476 1477 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num)); 1478 hcchar &= ~HCCHAR_MULTICNT_MASK; 1479 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT & 1480 HCCHAR_MULTICNT_MASK; 1481 1482 if (hcchar & HCCHAR_CHDIS) 1483 dev_warn(hsotg->dev, 1484 "%s: chdis set, channel %d, hcchar 0x%08x\n", 1485 __func__, chan->hc_num, hcchar); 1486 1487 /* Set host channel enable after all other setup is complete */ 1488 hcchar |= HCCHAR_CHENA; 1489 hcchar &= ~HCCHAR_CHDIS; 1490 1491 if (dbg_hc(chan)) 1492 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", 1493 (hcchar & HCCHAR_MULTICNT_MASK) >> 1494 HCCHAR_MULTICNT_SHIFT); 1495 1496 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num)); 1497 if (dbg_hc(chan)) 1498 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, 1499 chan->hc_num); 1500 1501 chan->xfer_started = 1; 1502 chan->requests++; 1503 } 1504 1505 /** 1506 * dwc2_hc_continue_transfer() - Continues a data transfer that was started by 1507 * a previous call to dwc2_hc_start_transfer() 1508 * 1509 * @hsotg: Programming view of DWC_otg controller 1510 * @chan: Information needed to initialize the host channel 1511 * 1512 * The caller must ensure there is sufficient space in the request queue and Tx 1513 * Data FIFO. This function should only be called in Slave mode. In DMA mode, 1514 * the controller acts autonomously to complete transfers programmed to a host 1515 * channel. 1516 * 1517 * For an OUT transfer, a new data packet is loaded into the appropriate FIFO 1518 * if there is any data remaining to be queued. For an IN transfer, another 1519 * data packet is always requested. For the SETUP phase of a control transfer, 1520 * this function does nothing. 1521 * 1522 * Return: 1 if a new request is queued, 0 if no more requests are required 1523 * for this transfer 1524 */ 1525 static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, 1526 struct dwc2_host_chan *chan) 1527 { 1528 if (dbg_hc(chan)) 1529 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1530 chan->hc_num); 1531 1532 if (chan->do_split) 1533 /* SPLITs always queue just once per channel */ 1534 return 0; 1535 1536 if (chan->data_pid_start == DWC2_HC_PID_SETUP) 1537 /* SETUPs are queued only once since they can't be NAK'd */ 1538 return 0; 1539 1540 if (chan->ep_is_in) { 1541 /* 1542 * Always queue another request for other IN transfers. If 1543 * back-to-back INs are issued and NAKs are received for both, 1544 * the driver may still be processing the first NAK when the 1545 * second NAK is received. When the interrupt handler clears 1546 * the NAK interrupt for the first NAK, the second NAK will 1547 * not be seen. So we can't depend on the NAK interrupt 1548 * handler to requeue a NAK'd request. Instead, IN requests 1549 * are issued each time this function is called. When the 1550 * transfer completes, the extra requests for the channel will 1551 * be flushed. 1552 */ 1553 u32 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num)); 1554 1555 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); 1556 hcchar |= HCCHAR_CHENA; 1557 hcchar &= ~HCCHAR_CHDIS; 1558 if (dbg_hc(chan)) 1559 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n", 1560 hcchar); 1561 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num)); 1562 chan->requests++; 1563 return 1; 1564 } 1565 1566 /* OUT transfers */ 1567 1568 if (chan->xfer_count < chan->xfer_len) { 1569 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1570 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1571 u32 hcchar = dwc2_readl(hsotg, 1572 HCCHAR(chan->hc_num)); 1573 1574 dwc2_hc_set_even_odd_frame(hsotg, chan, 1575 &hcchar); 1576 } 1577 1578 /* Load OUT packet into the appropriate Tx FIFO */ 1579 dwc2_hc_write_packet(hsotg, chan); 1580 chan->requests++; 1581 return 1; 1582 } 1583 1584 return 0; 1585 } 1586 1587 /* 1588 * ========================================================================= 1589 * HCD 1590 * ========================================================================= 1591 */ 1592 1593 /* 1594 * Processes all the URBs in a single list of QHs. Completes them with 1595 * -ETIMEDOUT and frees the QTD. 1596 * 1597 * Must be called with interrupt disabled and spinlock held 1598 */ 1599 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg, 1600 struct list_head *qh_list) 1601 { 1602 struct dwc2_qh *qh, *qh_tmp; 1603 struct dwc2_qtd *qtd, *qtd_tmp; 1604 1605 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 1606 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 1607 qtd_list_entry) { 1608 dwc2_host_complete(hsotg, qtd, -ECONNRESET); 1609 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 1610 } 1611 } 1612 } 1613 1614 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg, 1615 struct list_head *qh_list) 1616 { 1617 struct dwc2_qtd *qtd, *qtd_tmp; 1618 struct dwc2_qh *qh, *qh_tmp; 1619 unsigned long flags; 1620 1621 if (!qh_list->next) 1622 /* The list hasn't been initialized yet */ 1623 return; 1624 1625 spin_lock_irqsave(&hsotg->lock, flags); 1626 1627 /* Ensure there are no QTDs or URBs left */ 1628 dwc2_kill_urbs_in_qh_list(hsotg, qh_list); 1629 1630 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 1631 dwc2_hcd_qh_unlink(hsotg, qh); 1632 1633 /* Free each QTD in the QH's QTD list */ 1634 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 1635 qtd_list_entry) 1636 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 1637 1638 if (qh->channel && qh->channel->qh == qh) 1639 qh->channel->qh = NULL; 1640 1641 spin_unlock_irqrestore(&hsotg->lock, flags); 1642 dwc2_hcd_qh_free(hsotg, qh); 1643 spin_lock_irqsave(&hsotg->lock, flags); 1644 } 1645 1646 spin_unlock_irqrestore(&hsotg->lock, flags); 1647 } 1648 1649 /* 1650 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic 1651 * and periodic schedules. The QTD associated with each URB is removed from 1652 * the schedule and freed. This function may be called when a disconnect is 1653 * detected or when the HCD is being stopped. 1654 * 1655 * Must be called with interrupt disabled and spinlock held 1656 */ 1657 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg) 1658 { 1659 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive); 1660 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_waiting); 1661 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active); 1662 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive); 1663 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready); 1664 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned); 1665 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued); 1666 } 1667 1668 /** 1669 * dwc2_hcd_start() - Starts the HCD when switching to Host mode 1670 * 1671 * @hsotg: Pointer to struct dwc2_hsotg 1672 */ 1673 void dwc2_hcd_start(struct dwc2_hsotg *hsotg) 1674 { 1675 u32 hprt0; 1676 1677 if (hsotg->op_state == OTG_STATE_B_HOST) { 1678 /* 1679 * Reset the port. During a HNP mode switch the reset 1680 * needs to occur within 1ms and have a duration of at 1681 * least 50ms. 1682 */ 1683 hprt0 = dwc2_read_hprt0(hsotg); 1684 hprt0 |= HPRT0_RST; 1685 dwc2_writel(hsotg, hprt0, HPRT0); 1686 } 1687 1688 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work, 1689 msecs_to_jiffies(50)); 1690 } 1691 1692 /* Must be called with interrupt disabled and spinlock held */ 1693 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg) 1694 { 1695 int num_channels = hsotg->params.host_channels; 1696 struct dwc2_host_chan *channel; 1697 u32 hcchar; 1698 int i; 1699 1700 if (!hsotg->params.host_dma) { 1701 /* Flush out any channel requests in slave mode */ 1702 for (i = 0; i < num_channels; i++) { 1703 channel = hsotg->hc_ptr_array[i]; 1704 if (!list_empty(&channel->hc_list_entry)) 1705 continue; 1706 hcchar = dwc2_readl(hsotg, HCCHAR(i)); 1707 if (hcchar & HCCHAR_CHENA) { 1708 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR); 1709 hcchar |= HCCHAR_CHDIS; 1710 dwc2_writel(hsotg, hcchar, HCCHAR(i)); 1711 } 1712 } 1713 } 1714 1715 for (i = 0; i < num_channels; i++) { 1716 channel = hsotg->hc_ptr_array[i]; 1717 if (!list_empty(&channel->hc_list_entry)) 1718 continue; 1719 hcchar = dwc2_readl(hsotg, HCCHAR(i)); 1720 if (hcchar & HCCHAR_CHENA) { 1721 /* Halt the channel */ 1722 hcchar |= HCCHAR_CHDIS; 1723 dwc2_writel(hsotg, hcchar, HCCHAR(i)); 1724 } 1725 1726 dwc2_hc_cleanup(hsotg, channel); 1727 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list); 1728 /* 1729 * Added for Descriptor DMA to prevent channel double cleanup in 1730 * release_channel_ddma(), which is called from ep_disable when 1731 * device disconnects 1732 */ 1733 channel->qh = NULL; 1734 } 1735 /* All channels have been freed, mark them available */ 1736 if (hsotg->params.uframe_sched) { 1737 hsotg->available_host_channels = 1738 hsotg->params.host_channels; 1739 } else { 1740 hsotg->non_periodic_channels = 0; 1741 hsotg->periodic_channels = 0; 1742 } 1743 } 1744 1745 /** 1746 * dwc2_hcd_connect() - Handles connect of the HCD 1747 * 1748 * @hsotg: Pointer to struct dwc2_hsotg 1749 * 1750 * Must be called with interrupt disabled and spinlock held 1751 */ 1752 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) 1753 { 1754 if (hsotg->lx_state != DWC2_L0) 1755 usb_hcd_resume_root_hub(hsotg->priv); 1756 1757 hsotg->flags.b.port_connect_status_change = 1; 1758 hsotg->flags.b.port_connect_status = 1; 1759 } 1760 1761 /** 1762 * dwc2_hcd_disconnect() - Handles disconnect of the HCD 1763 * 1764 * @hsotg: Pointer to struct dwc2_hsotg 1765 * @force: If true, we won't try to reconnect even if we see device connected. 1766 * 1767 * Must be called with interrupt disabled and spinlock held 1768 */ 1769 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) 1770 { 1771 u32 intr; 1772 u32 hprt0; 1773 1774 /* Set status flags for the hub driver */ 1775 hsotg->flags.b.port_connect_status_change = 1; 1776 hsotg->flags.b.port_connect_status = 0; 1777 1778 /* 1779 * Shutdown any transfers in process by clearing the Tx FIFO Empty 1780 * interrupt mask and status bits and disabling subsequent host 1781 * channel interrupts. 1782 */ 1783 intr = dwc2_readl(hsotg, GINTMSK); 1784 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT); 1785 dwc2_writel(hsotg, intr, GINTMSK); 1786 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT; 1787 dwc2_writel(hsotg, intr, GINTSTS); 1788 1789 /* 1790 * Turn off the vbus power only if the core has transitioned to device 1791 * mode. If still in host mode, need to keep power on to detect a 1792 * reconnection. 1793 */ 1794 if (dwc2_is_device_mode(hsotg)) { 1795 if (hsotg->op_state != OTG_STATE_A_SUSPEND) { 1796 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n"); 1797 dwc2_writel(hsotg, 0, HPRT0); 1798 } 1799 1800 dwc2_disable_host_interrupts(hsotg); 1801 } 1802 1803 /* Respond with an error status to all URBs in the schedule */ 1804 dwc2_kill_all_urbs(hsotg); 1805 1806 if (dwc2_is_host_mode(hsotg)) 1807 /* Clean up any host channels that were in use */ 1808 dwc2_hcd_cleanup_channels(hsotg); 1809 1810 dwc2_host_disconnect(hsotg); 1811 1812 /* 1813 * Add an extra check here to see if we're actually connected but 1814 * we don't have a detection interrupt pending. This can happen if: 1815 * 1. hardware sees connect 1816 * 2. hardware sees disconnect 1817 * 3. hardware sees connect 1818 * 4. dwc2_port_intr() - clears connect interrupt 1819 * 5. dwc2_handle_common_intr() - calls here 1820 * 1821 * Without the extra check here we will end calling disconnect 1822 * and won't get any future interrupts to handle the connect. 1823 */ 1824 if (!force) { 1825 hprt0 = dwc2_readl(hsotg, HPRT0); 1826 if (!(hprt0 & HPRT0_CONNDET) && (hprt0 & HPRT0_CONNSTS)) 1827 dwc2_hcd_connect(hsotg); 1828 } 1829 } 1830 1831 /** 1832 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup 1833 * 1834 * @hsotg: Pointer to struct dwc2_hsotg 1835 */ 1836 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg) 1837 { 1838 if (hsotg->bus_suspended) { 1839 hsotg->flags.b.port_suspend_change = 1; 1840 usb_hcd_resume_root_hub(hsotg->priv); 1841 } 1842 1843 if (hsotg->lx_state == DWC2_L1) 1844 hsotg->flags.b.port_l1_change = 1; 1845 } 1846 1847 /** 1848 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner 1849 * 1850 * @hsotg: Pointer to struct dwc2_hsotg 1851 * 1852 * Must be called with interrupt disabled and spinlock held 1853 */ 1854 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg) 1855 { 1856 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n"); 1857 1858 /* 1859 * The root hub should be disconnected before this function is called. 1860 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue) 1861 * and the QH lists (via ..._hcd_endpoint_disable). 1862 */ 1863 1864 /* Turn off all host-specific interrupts */ 1865 dwc2_disable_host_interrupts(hsotg); 1866 1867 /* Turn off the vbus power */ 1868 dev_dbg(hsotg->dev, "PortPower off\n"); 1869 dwc2_writel(hsotg, 0, HPRT0); 1870 } 1871 1872 /* Caller must hold driver lock */ 1873 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, 1874 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh, 1875 struct dwc2_qtd *qtd) 1876 { 1877 u32 intr_mask; 1878 int retval; 1879 int dev_speed; 1880 1881 if (!hsotg->flags.b.port_connect_status) { 1882 /* No longer connected */ 1883 dev_err(hsotg->dev, "Not connected\n"); 1884 return -ENODEV; 1885 } 1886 1887 dev_speed = dwc2_host_get_speed(hsotg, urb->priv); 1888 1889 /* Some configurations cannot support LS traffic on a FS root port */ 1890 if ((dev_speed == USB_SPEED_LOW) && 1891 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) && 1892 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) { 1893 u32 hprt0 = dwc2_readl(hsotg, HPRT0); 1894 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 1895 1896 if (prtspd == HPRT0_SPD_FULL_SPEED) 1897 return -ENODEV; 1898 } 1899 1900 if (!qtd) 1901 return -EINVAL; 1902 1903 dwc2_hcd_qtd_init(qtd, urb); 1904 retval = dwc2_hcd_qtd_add(hsotg, qtd, qh); 1905 if (retval) { 1906 dev_err(hsotg->dev, 1907 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n", 1908 retval); 1909 return retval; 1910 } 1911 1912 intr_mask = dwc2_readl(hsotg, GINTMSK); 1913 if (!(intr_mask & GINTSTS_SOF)) { 1914 enum dwc2_transaction_type tr_type; 1915 1916 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK && 1917 !(qtd->urb->flags & URB_GIVEBACK_ASAP)) 1918 /* 1919 * Do not schedule SG transactions until qtd has 1920 * URB_GIVEBACK_ASAP set 1921 */ 1922 return 0; 1923 1924 tr_type = dwc2_hcd_select_transactions(hsotg); 1925 if (tr_type != DWC2_TRANSACTION_NONE) 1926 dwc2_hcd_queue_transactions(hsotg, tr_type); 1927 } 1928 1929 return 0; 1930 } 1931 1932 /* Must be called with interrupt disabled and spinlock held */ 1933 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg, 1934 struct dwc2_hcd_urb *urb) 1935 { 1936 struct dwc2_qh *qh; 1937 struct dwc2_qtd *urb_qtd; 1938 1939 urb_qtd = urb->qtd; 1940 if (!urb_qtd) { 1941 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n"); 1942 return -EINVAL; 1943 } 1944 1945 qh = urb_qtd->qh; 1946 if (!qh) { 1947 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n"); 1948 return -EINVAL; 1949 } 1950 1951 urb->priv = NULL; 1952 1953 if (urb_qtd->in_process && qh->channel) { 1954 dwc2_dump_channel_info(hsotg, qh->channel); 1955 1956 /* The QTD is in process (it has been assigned to a channel) */ 1957 if (hsotg->flags.b.port_connect_status) 1958 /* 1959 * If still connected (i.e. in host mode), halt the 1960 * channel so it can be used for other transfers. If 1961 * no longer connected, the host registers can't be 1962 * written to halt the channel since the core is in 1963 * device mode. 1964 */ 1965 dwc2_hc_halt(hsotg, qh->channel, 1966 DWC2_HC_XFER_URB_DEQUEUE); 1967 } 1968 1969 /* 1970 * Free the QTD and clean up the associated QH. Leave the QH in the 1971 * schedule if it has any remaining QTDs. 1972 */ 1973 if (!hsotg->params.dma_desc_enable) { 1974 u8 in_process = urb_qtd->in_process; 1975 1976 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 1977 if (in_process) { 1978 dwc2_hcd_qh_deactivate(hsotg, qh, 0); 1979 qh->channel = NULL; 1980 } else if (list_empty(&qh->qtd_list)) { 1981 dwc2_hcd_qh_unlink(hsotg, qh); 1982 } 1983 } else { 1984 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 1985 } 1986 1987 return 0; 1988 } 1989 1990 /* Must NOT be called with interrupt disabled or spinlock held */ 1991 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg, 1992 struct usb_host_endpoint *ep, int retry) 1993 { 1994 struct dwc2_qtd *qtd, *qtd_tmp; 1995 struct dwc2_qh *qh; 1996 unsigned long flags; 1997 int rc; 1998 1999 spin_lock_irqsave(&hsotg->lock, flags); 2000 2001 qh = ep->hcpriv; 2002 if (!qh) { 2003 rc = -EINVAL; 2004 goto err; 2005 } 2006 2007 while (!list_empty(&qh->qtd_list) && retry--) { 2008 if (retry == 0) { 2009 dev_err(hsotg->dev, 2010 "## timeout in dwc2_hcd_endpoint_disable() ##\n"); 2011 rc = -EBUSY; 2012 goto err; 2013 } 2014 2015 spin_unlock_irqrestore(&hsotg->lock, flags); 2016 msleep(20); 2017 spin_lock_irqsave(&hsotg->lock, flags); 2018 qh = ep->hcpriv; 2019 if (!qh) { 2020 rc = -EINVAL; 2021 goto err; 2022 } 2023 } 2024 2025 dwc2_hcd_qh_unlink(hsotg, qh); 2026 2027 /* Free each QTD in the QH's QTD list */ 2028 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) 2029 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 2030 2031 ep->hcpriv = NULL; 2032 2033 if (qh->channel && qh->channel->qh == qh) 2034 qh->channel->qh = NULL; 2035 2036 spin_unlock_irqrestore(&hsotg->lock, flags); 2037 2038 dwc2_hcd_qh_free(hsotg, qh); 2039 2040 return 0; 2041 2042 err: 2043 ep->hcpriv = NULL; 2044 spin_unlock_irqrestore(&hsotg->lock, flags); 2045 2046 return rc; 2047 } 2048 2049 /* Must be called with interrupt disabled and spinlock held */ 2050 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg, 2051 struct usb_host_endpoint *ep) 2052 { 2053 struct dwc2_qh *qh = ep->hcpriv; 2054 2055 if (!qh) 2056 return -EINVAL; 2057 2058 qh->data_toggle = DWC2_HC_PID_DATA0; 2059 2060 return 0; 2061 } 2062 2063 /** 2064 * dwc2_core_init() - Initializes the DWC_otg controller registers and 2065 * prepares the core for device mode or host mode operation 2066 * 2067 * @hsotg: Programming view of the DWC_otg controller 2068 * @initial_setup: If true then this is the first init for this instance. 2069 */ 2070 int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup) 2071 { 2072 u32 usbcfg, otgctl; 2073 int retval; 2074 2075 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); 2076 2077 usbcfg = dwc2_readl(hsotg, GUSBCFG); 2078 2079 /* Set ULPI External VBUS bit if needed */ 2080 usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV; 2081 if (hsotg->params.phy_ulpi_ext_vbus) 2082 usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV; 2083 2084 /* Set external TS Dline pulsing bit if needed */ 2085 usbcfg &= ~GUSBCFG_TERMSELDLPULSE; 2086 if (hsotg->params.ts_dline) 2087 usbcfg |= GUSBCFG_TERMSELDLPULSE; 2088 2089 dwc2_writel(hsotg, usbcfg, GUSBCFG); 2090 2091 /* 2092 * Reset the Controller 2093 * 2094 * We only need to reset the controller if this is a re-init. 2095 * For the first init we know for sure that earlier code reset us (it 2096 * needed to in order to properly detect various parameters). 2097 */ 2098 if (!initial_setup) { 2099 retval = dwc2_core_reset(hsotg, false); 2100 if (retval) { 2101 dev_err(hsotg->dev, "%s(): Reset failed, aborting\n", 2102 __func__); 2103 return retval; 2104 } 2105 } 2106 2107 /* 2108 * This needs to happen in FS mode before any other programming occurs 2109 */ 2110 retval = dwc2_phy_init(hsotg, initial_setup); 2111 if (retval) 2112 return retval; 2113 2114 /* Program the GAHBCFG Register */ 2115 retval = dwc2_gahbcfg_init(hsotg); 2116 if (retval) 2117 return retval; 2118 2119 /* Program the GUSBCFG register */ 2120 dwc2_gusbcfg_init(hsotg); 2121 2122 /* Program the GOTGCTL register */ 2123 otgctl = dwc2_readl(hsotg, GOTGCTL); 2124 otgctl &= ~GOTGCTL_OTGVER; 2125 dwc2_writel(hsotg, otgctl, GOTGCTL); 2126 2127 /* Clear the SRP success bit for FS-I2c */ 2128 hsotg->srp_success = 0; 2129 2130 /* Enable common interrupts */ 2131 dwc2_enable_common_interrupts(hsotg); 2132 2133 /* 2134 * Do device or host initialization based on mode during PCD and 2135 * HCD initialization 2136 */ 2137 if (dwc2_is_host_mode(hsotg)) { 2138 dev_dbg(hsotg->dev, "Host Mode\n"); 2139 hsotg->op_state = OTG_STATE_A_HOST; 2140 } else { 2141 dev_dbg(hsotg->dev, "Device Mode\n"); 2142 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 2143 } 2144 2145 return 0; 2146 } 2147 2148 /** 2149 * dwc2_core_host_init() - Initializes the DWC_otg controller registers for 2150 * Host mode 2151 * 2152 * @hsotg: Programming view of DWC_otg controller 2153 * 2154 * This function flushes the Tx and Rx FIFOs and flushes any entries in the 2155 * request queues. Host channels are reset to ensure that they are ready for 2156 * performing transfers. 2157 */ 2158 static void dwc2_core_host_init(struct dwc2_hsotg *hsotg) 2159 { 2160 u32 hcfg, hfir, otgctl, usbcfg; 2161 2162 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); 2163 2164 /* Set HS/FS Timeout Calibration to 7 (max available value). 2165 * The number of PHY clocks that the application programs in 2166 * this field is added to the high/full speed interpacket timeout 2167 * duration in the core to account for any additional delays 2168 * introduced by the PHY. This can be required, because the delay 2169 * introduced by the PHY in generating the linestate condition 2170 * can vary from one PHY to another. 2171 */ 2172 usbcfg = dwc2_readl(hsotg, GUSBCFG); 2173 usbcfg |= GUSBCFG_TOUTCAL(7); 2174 dwc2_writel(hsotg, usbcfg, GUSBCFG); 2175 2176 /* Restart the Phy Clock */ 2177 dwc2_writel(hsotg, 0, PCGCTL); 2178 2179 /* Initialize Host Configuration Register */ 2180 dwc2_init_fs_ls_pclk_sel(hsotg); 2181 if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL || 2182 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) { 2183 hcfg = dwc2_readl(hsotg, HCFG); 2184 hcfg |= HCFG_FSLSSUPP; 2185 dwc2_writel(hsotg, hcfg, HCFG); 2186 } 2187 2188 /* 2189 * This bit allows dynamic reloading of the HFIR register during 2190 * runtime. This bit needs to be programmed during initial configuration 2191 * and its value must not be changed during runtime. 2192 */ 2193 if (hsotg->params.reload_ctl) { 2194 hfir = dwc2_readl(hsotg, HFIR); 2195 hfir |= HFIR_RLDCTRL; 2196 dwc2_writel(hsotg, hfir, HFIR); 2197 } 2198 2199 if (hsotg->params.dma_desc_enable) { 2200 u32 op_mode = hsotg->hw_params.op_mode; 2201 2202 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a || 2203 !hsotg->hw_params.dma_desc_enable || 2204 op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE || 2205 op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE || 2206 op_mode == GHWCFG2_OP_MODE_UNDEFINED) { 2207 dev_err(hsotg->dev, 2208 "Hardware does not support descriptor DMA mode -\n"); 2209 dev_err(hsotg->dev, 2210 "falling back to buffer DMA mode.\n"); 2211 hsotg->params.dma_desc_enable = false; 2212 } else { 2213 hcfg = dwc2_readl(hsotg, HCFG); 2214 hcfg |= HCFG_DESCDMA; 2215 dwc2_writel(hsotg, hcfg, HCFG); 2216 } 2217 } 2218 2219 /* Configure data FIFO sizes */ 2220 dwc2_config_fifos(hsotg); 2221 2222 /* TODO - check this */ 2223 /* Clear Host Set HNP Enable in the OTG Control Register */ 2224 otgctl = dwc2_readl(hsotg, GOTGCTL); 2225 otgctl &= ~GOTGCTL_HSTSETHNPEN; 2226 dwc2_writel(hsotg, otgctl, GOTGCTL); 2227 2228 /* Make sure the FIFOs are flushed */ 2229 dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */); 2230 dwc2_flush_rx_fifo(hsotg); 2231 2232 /* Clear Host Set HNP Enable in the OTG Control Register */ 2233 otgctl = dwc2_readl(hsotg, GOTGCTL); 2234 otgctl &= ~GOTGCTL_HSTSETHNPEN; 2235 dwc2_writel(hsotg, otgctl, GOTGCTL); 2236 2237 if (!hsotg->params.dma_desc_enable) { 2238 int num_channels, i; 2239 u32 hcchar; 2240 2241 /* Flush out any leftover queued requests */ 2242 num_channels = hsotg->params.host_channels; 2243 for (i = 0; i < num_channels; i++) { 2244 hcchar = dwc2_readl(hsotg, HCCHAR(i)); 2245 if (hcchar & HCCHAR_CHENA) { 2246 hcchar &= ~HCCHAR_CHENA; 2247 hcchar |= HCCHAR_CHDIS; 2248 hcchar &= ~HCCHAR_EPDIR; 2249 dwc2_writel(hsotg, hcchar, HCCHAR(i)); 2250 } 2251 } 2252 2253 /* Halt all channels to put them into a known state */ 2254 for (i = 0; i < num_channels; i++) { 2255 hcchar = dwc2_readl(hsotg, HCCHAR(i)); 2256 if (hcchar & HCCHAR_CHENA) { 2257 hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS; 2258 hcchar &= ~HCCHAR_EPDIR; 2259 dwc2_writel(hsotg, hcchar, HCCHAR(i)); 2260 dev_dbg(hsotg->dev, "%s: Halt channel %d\n", 2261 __func__, i); 2262 2263 if (dwc2_hsotg_wait_bit_clear(hsotg, HCCHAR(i), 2264 HCCHAR_CHENA, 2265 1000)) { 2266 dev_warn(hsotg->dev, 2267 "Unable to clear enable on channel %d\n", 2268 i); 2269 } 2270 } 2271 } 2272 } 2273 2274 /* Enable ACG feature in host mode, if supported */ 2275 dwc2_enable_acg(hsotg); 2276 2277 /* Turn on the vbus power */ 2278 dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state); 2279 if (hsotg->op_state == OTG_STATE_A_HOST) { 2280 u32 hprt0 = dwc2_read_hprt0(hsotg); 2281 2282 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n", 2283 !!(hprt0 & HPRT0_PWR)); 2284 if (!(hprt0 & HPRT0_PWR)) { 2285 hprt0 |= HPRT0_PWR; 2286 dwc2_writel(hsotg, hprt0, HPRT0); 2287 } 2288 } 2289 2290 dwc2_enable_host_interrupts(hsotg); 2291 } 2292 2293 /* 2294 * Initializes dynamic portions of the DWC_otg HCD state 2295 * 2296 * Must be called with interrupt disabled and spinlock held 2297 */ 2298 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg) 2299 { 2300 struct dwc2_host_chan *chan, *chan_tmp; 2301 int num_channels; 2302 int i; 2303 2304 hsotg->flags.d32 = 0; 2305 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active; 2306 2307 if (hsotg->params.uframe_sched) { 2308 hsotg->available_host_channels = 2309 hsotg->params.host_channels; 2310 } else { 2311 hsotg->non_periodic_channels = 0; 2312 hsotg->periodic_channels = 0; 2313 } 2314 2315 /* 2316 * Put all channels in the free channel list and clean up channel 2317 * states 2318 */ 2319 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list, 2320 hc_list_entry) 2321 list_del_init(&chan->hc_list_entry); 2322 2323 num_channels = hsotg->params.host_channels; 2324 for (i = 0; i < num_channels; i++) { 2325 chan = hsotg->hc_ptr_array[i]; 2326 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list); 2327 dwc2_hc_cleanup(hsotg, chan); 2328 } 2329 2330 /* Initialize the DWC core for host mode operation */ 2331 dwc2_core_host_init(hsotg); 2332 } 2333 2334 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg, 2335 struct dwc2_host_chan *chan, 2336 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 2337 { 2338 int hub_addr, hub_port; 2339 2340 chan->do_split = 1; 2341 chan->xact_pos = qtd->isoc_split_pos; 2342 chan->complete_split = qtd->complete_split; 2343 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port); 2344 chan->hub_addr = (u8)hub_addr; 2345 chan->hub_port = (u8)hub_port; 2346 } 2347 2348 static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg, 2349 struct dwc2_host_chan *chan, 2350 struct dwc2_qtd *qtd) 2351 { 2352 struct dwc2_hcd_urb *urb = qtd->urb; 2353 struct dwc2_hcd_iso_packet_desc *frame_desc; 2354 2355 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) { 2356 case USB_ENDPOINT_XFER_CONTROL: 2357 chan->ep_type = USB_ENDPOINT_XFER_CONTROL; 2358 2359 switch (qtd->control_phase) { 2360 case DWC2_CONTROL_SETUP: 2361 dev_vdbg(hsotg->dev, " Control setup transaction\n"); 2362 chan->do_ping = 0; 2363 chan->ep_is_in = 0; 2364 chan->data_pid_start = DWC2_HC_PID_SETUP; 2365 if (hsotg->params.host_dma) 2366 chan->xfer_dma = urb->setup_dma; 2367 else 2368 chan->xfer_buf = urb->setup_packet; 2369 chan->xfer_len = 8; 2370 break; 2371 2372 case DWC2_CONTROL_DATA: 2373 dev_vdbg(hsotg->dev, " Control data transaction\n"); 2374 chan->data_pid_start = qtd->data_toggle; 2375 break; 2376 2377 case DWC2_CONTROL_STATUS: 2378 /* 2379 * Direction is opposite of data direction or IN if no 2380 * data 2381 */ 2382 dev_vdbg(hsotg->dev, " Control status transaction\n"); 2383 if (urb->length == 0) 2384 chan->ep_is_in = 1; 2385 else 2386 chan->ep_is_in = 2387 dwc2_hcd_is_pipe_out(&urb->pipe_info); 2388 if (chan->ep_is_in) 2389 chan->do_ping = 0; 2390 chan->data_pid_start = DWC2_HC_PID_DATA1; 2391 chan->xfer_len = 0; 2392 if (hsotg->params.host_dma) 2393 chan->xfer_dma = hsotg->status_buf_dma; 2394 else 2395 chan->xfer_buf = hsotg->status_buf; 2396 break; 2397 } 2398 break; 2399 2400 case USB_ENDPOINT_XFER_BULK: 2401 chan->ep_type = USB_ENDPOINT_XFER_BULK; 2402 break; 2403 2404 case USB_ENDPOINT_XFER_INT: 2405 chan->ep_type = USB_ENDPOINT_XFER_INT; 2406 break; 2407 2408 case USB_ENDPOINT_XFER_ISOC: 2409 chan->ep_type = USB_ENDPOINT_XFER_ISOC; 2410 if (hsotg->params.dma_desc_enable) 2411 break; 2412 2413 frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; 2414 frame_desc->status = 0; 2415 2416 if (hsotg->params.host_dma) { 2417 chan->xfer_dma = urb->dma; 2418 chan->xfer_dma += frame_desc->offset + 2419 qtd->isoc_split_offset; 2420 } else { 2421 chan->xfer_buf = urb->buf; 2422 chan->xfer_buf += frame_desc->offset + 2423 qtd->isoc_split_offset; 2424 } 2425 2426 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset; 2427 2428 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) { 2429 if (chan->xfer_len <= 188) 2430 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL; 2431 else 2432 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN; 2433 } 2434 break; 2435 } 2436 } 2437 2438 static int dwc2_alloc_split_dma_aligned_buf(struct dwc2_hsotg *hsotg, 2439 struct dwc2_qh *qh, 2440 struct dwc2_host_chan *chan) 2441 { 2442 if (!hsotg->unaligned_cache || 2443 chan->max_packet > DWC2_KMEM_UNALIGNED_BUF_SIZE) 2444 return -ENOMEM; 2445 2446 if (!qh->dw_align_buf) { 2447 qh->dw_align_buf = kmem_cache_alloc(hsotg->unaligned_cache, 2448 GFP_ATOMIC | GFP_DMA); 2449 if (!qh->dw_align_buf) 2450 return -ENOMEM; 2451 } 2452 2453 qh->dw_align_buf_dma = dma_map_single(hsotg->dev, qh->dw_align_buf, 2454 DWC2_KMEM_UNALIGNED_BUF_SIZE, 2455 DMA_FROM_DEVICE); 2456 2457 if (dma_mapping_error(hsotg->dev, qh->dw_align_buf_dma)) { 2458 dev_err(hsotg->dev, "can't map align_buf\n"); 2459 chan->align_buf = 0; 2460 return -EINVAL; 2461 } 2462 2463 chan->align_buf = qh->dw_align_buf_dma; 2464 return 0; 2465 } 2466 2467 #define DWC2_USB_DMA_ALIGN 4 2468 2469 static void dwc2_free_dma_aligned_buffer(struct urb *urb) 2470 { 2471 void *stored_xfer_buffer; 2472 size_t length; 2473 2474 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER)) 2475 return; 2476 2477 /* Restore urb->transfer_buffer from the end of the allocated area */ 2478 memcpy(&stored_xfer_buffer, 2479 PTR_ALIGN(urb->transfer_buffer + urb->transfer_buffer_length, 2480 dma_get_cache_alignment()), 2481 sizeof(urb->transfer_buffer)); 2482 2483 if (usb_urb_dir_in(urb)) { 2484 if (usb_pipeisoc(urb->pipe)) 2485 length = urb->transfer_buffer_length; 2486 else 2487 length = urb->actual_length; 2488 2489 memcpy(stored_xfer_buffer, urb->transfer_buffer, length); 2490 } 2491 kfree(urb->transfer_buffer); 2492 urb->transfer_buffer = stored_xfer_buffer; 2493 2494 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER; 2495 } 2496 2497 static int dwc2_alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags) 2498 { 2499 void *kmalloc_ptr; 2500 size_t kmalloc_size; 2501 2502 if (urb->num_sgs || urb->sg || 2503 urb->transfer_buffer_length == 0 || 2504 !((uintptr_t)urb->transfer_buffer & (DWC2_USB_DMA_ALIGN - 1))) 2505 return 0; 2506 2507 /* 2508 * Allocate a buffer with enough padding for original transfer_buffer 2509 * pointer. This allocation is guaranteed to be aligned properly for 2510 * DMA 2511 */ 2512 kmalloc_size = urb->transfer_buffer_length + 2513 (dma_get_cache_alignment() - 1) + 2514 sizeof(urb->transfer_buffer); 2515 2516 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags); 2517 if (!kmalloc_ptr) 2518 return -ENOMEM; 2519 2520 /* 2521 * Position value of original urb->transfer_buffer pointer to the end 2522 * of allocation for later referencing 2523 */ 2524 memcpy(PTR_ALIGN(kmalloc_ptr + urb->transfer_buffer_length, 2525 dma_get_cache_alignment()), 2526 &urb->transfer_buffer, sizeof(urb->transfer_buffer)); 2527 2528 if (usb_urb_dir_out(urb)) 2529 memcpy(kmalloc_ptr, urb->transfer_buffer, 2530 urb->transfer_buffer_length); 2531 urb->transfer_buffer = kmalloc_ptr; 2532 2533 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER; 2534 2535 return 0; 2536 } 2537 2538 static int dwc2_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, 2539 gfp_t mem_flags) 2540 { 2541 int ret; 2542 2543 /* We assume setup_dma is always aligned; warn if not */ 2544 WARN_ON_ONCE(urb->setup_dma && 2545 (urb->setup_dma & (DWC2_USB_DMA_ALIGN - 1))); 2546 2547 ret = dwc2_alloc_dma_aligned_buffer(urb, mem_flags); 2548 if (ret) 2549 return ret; 2550 2551 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); 2552 if (ret) 2553 dwc2_free_dma_aligned_buffer(urb); 2554 2555 return ret; 2556 } 2557 2558 static void dwc2_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb) 2559 { 2560 usb_hcd_unmap_urb_for_dma(hcd, urb); 2561 dwc2_free_dma_aligned_buffer(urb); 2562 } 2563 2564 /** 2565 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host 2566 * channel and initializes the host channel to perform the transactions. The 2567 * host channel is removed from the free list. 2568 * 2569 * @hsotg: The HCD state structure 2570 * @qh: Transactions from the first QTD for this QH are selected and assigned 2571 * to a free host channel 2572 */ 2573 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 2574 { 2575 struct dwc2_host_chan *chan; 2576 struct dwc2_hcd_urb *urb; 2577 struct dwc2_qtd *qtd; 2578 2579 if (dbg_qh(qh)) 2580 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh); 2581 2582 if (list_empty(&qh->qtd_list)) { 2583 dev_dbg(hsotg->dev, "No QTDs in QH list\n"); 2584 return -ENOMEM; 2585 } 2586 2587 if (list_empty(&hsotg->free_hc_list)) { 2588 dev_dbg(hsotg->dev, "No free channel to assign\n"); 2589 return -ENOMEM; 2590 } 2591 2592 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan, 2593 hc_list_entry); 2594 2595 /* Remove host channel from free list */ 2596 list_del_init(&chan->hc_list_entry); 2597 2598 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry); 2599 urb = qtd->urb; 2600 qh->channel = chan; 2601 qtd->in_process = 1; 2602 2603 /* 2604 * Use usb_pipedevice to determine device address. This address is 2605 * 0 before the SET_ADDRESS command and the correct address afterward. 2606 */ 2607 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info); 2608 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info); 2609 chan->speed = qh->dev_speed; 2610 chan->max_packet = qh->maxp; 2611 2612 chan->xfer_started = 0; 2613 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS; 2614 chan->error_state = (qtd->error_count > 0); 2615 chan->halt_on_queue = 0; 2616 chan->halt_pending = 0; 2617 chan->requests = 0; 2618 2619 /* 2620 * The following values may be modified in the transfer type section 2621 * below. The xfer_len value may be reduced when the transfer is 2622 * started to accommodate the max widths of the XferSize and PktCnt 2623 * fields in the HCTSIZn register. 2624 */ 2625 2626 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0); 2627 if (chan->ep_is_in) 2628 chan->do_ping = 0; 2629 else 2630 chan->do_ping = qh->ping_state; 2631 2632 chan->data_pid_start = qh->data_toggle; 2633 chan->multi_count = 1; 2634 2635 if (urb->actual_length > urb->length && 2636 !dwc2_hcd_is_pipe_in(&urb->pipe_info)) 2637 urb->actual_length = urb->length; 2638 2639 if (hsotg->params.host_dma) 2640 chan->xfer_dma = urb->dma + urb->actual_length; 2641 else 2642 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length; 2643 2644 chan->xfer_len = urb->length - urb->actual_length; 2645 chan->xfer_count = 0; 2646 2647 /* Set the split attributes if required */ 2648 if (qh->do_split) 2649 dwc2_hc_init_split(hsotg, chan, qtd, urb); 2650 else 2651 chan->do_split = 0; 2652 2653 /* Set the transfer attributes */ 2654 dwc2_hc_init_xfer(hsotg, chan, qtd); 2655 2656 /* For non-dword aligned buffers */ 2657 if (hsotg->params.host_dma && qh->do_split && 2658 chan->ep_is_in && (chan->xfer_dma & 0x3)) { 2659 dev_vdbg(hsotg->dev, "Non-aligned buffer\n"); 2660 if (dwc2_alloc_split_dma_aligned_buf(hsotg, qh, chan)) { 2661 dev_err(hsotg->dev, 2662 "Failed to allocate memory to handle non-aligned buffer\n"); 2663 /* Add channel back to free list */ 2664 chan->align_buf = 0; 2665 chan->multi_count = 0; 2666 list_add_tail(&chan->hc_list_entry, 2667 &hsotg->free_hc_list); 2668 qtd->in_process = 0; 2669 qh->channel = NULL; 2670 return -ENOMEM; 2671 } 2672 } else { 2673 /* 2674 * We assume that DMA is always aligned in non-split 2675 * case or split out case. Warn if not. 2676 */ 2677 WARN_ON_ONCE(hsotg->params.host_dma && 2678 (chan->xfer_dma & 0x3)); 2679 chan->align_buf = 0; 2680 } 2681 2682 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 2683 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 2684 /* 2685 * This value may be modified when the transfer is started 2686 * to reflect the actual transfer length 2687 */ 2688 chan->multi_count = qh->maxp_mult; 2689 2690 if (hsotg->params.dma_desc_enable) { 2691 chan->desc_list_addr = qh->desc_list_dma; 2692 chan->desc_list_sz = qh->desc_list_sz; 2693 } 2694 2695 dwc2_hc_init(hsotg, chan); 2696 chan->qh = qh; 2697 2698 return 0; 2699 } 2700 2701 /** 2702 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer 2703 * schedule and assigns them to available host channels. Called from the HCD 2704 * interrupt handler functions. 2705 * 2706 * @hsotg: The HCD state structure 2707 * 2708 * Return: The types of new transactions that were assigned to host channels 2709 */ 2710 enum dwc2_transaction_type dwc2_hcd_select_transactions( 2711 struct dwc2_hsotg *hsotg) 2712 { 2713 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE; 2714 struct list_head *qh_ptr; 2715 struct dwc2_qh *qh; 2716 int num_channels; 2717 2718 #ifdef DWC2_DEBUG_SOF 2719 dev_vdbg(hsotg->dev, " Select Transactions\n"); 2720 #endif 2721 2722 /* Process entries in the periodic ready list */ 2723 qh_ptr = hsotg->periodic_sched_ready.next; 2724 while (qh_ptr != &hsotg->periodic_sched_ready) { 2725 if (list_empty(&hsotg->free_hc_list)) 2726 break; 2727 if (hsotg->params.uframe_sched) { 2728 if (hsotg->available_host_channels <= 1) 2729 break; 2730 hsotg->available_host_channels--; 2731 } 2732 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 2733 if (dwc2_assign_and_init_hc(hsotg, qh)) 2734 break; 2735 2736 /* 2737 * Move the QH from the periodic ready schedule to the 2738 * periodic assigned schedule 2739 */ 2740 qh_ptr = qh_ptr->next; 2741 list_move_tail(&qh->qh_list_entry, 2742 &hsotg->periodic_sched_assigned); 2743 ret_val = DWC2_TRANSACTION_PERIODIC; 2744 } 2745 2746 /* 2747 * Process entries in the inactive portion of the non-periodic 2748 * schedule. Some free host channels may not be used if they are 2749 * reserved for periodic transfers. 2750 */ 2751 num_channels = hsotg->params.host_channels; 2752 qh_ptr = hsotg->non_periodic_sched_inactive.next; 2753 while (qh_ptr != &hsotg->non_periodic_sched_inactive) { 2754 if (!hsotg->params.uframe_sched && 2755 hsotg->non_periodic_channels >= num_channels - 2756 hsotg->periodic_channels) 2757 break; 2758 if (list_empty(&hsotg->free_hc_list)) 2759 break; 2760 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 2761 if (hsotg->params.uframe_sched) { 2762 if (hsotg->available_host_channels < 1) 2763 break; 2764 hsotg->available_host_channels--; 2765 } 2766 2767 if (dwc2_assign_and_init_hc(hsotg, qh)) 2768 break; 2769 2770 /* 2771 * Move the QH from the non-periodic inactive schedule to the 2772 * non-periodic active schedule 2773 */ 2774 qh_ptr = qh_ptr->next; 2775 list_move_tail(&qh->qh_list_entry, 2776 &hsotg->non_periodic_sched_active); 2777 2778 if (ret_val == DWC2_TRANSACTION_NONE) 2779 ret_val = DWC2_TRANSACTION_NON_PERIODIC; 2780 else 2781 ret_val = DWC2_TRANSACTION_ALL; 2782 2783 if (!hsotg->params.uframe_sched) 2784 hsotg->non_periodic_channels++; 2785 } 2786 2787 return ret_val; 2788 } 2789 2790 /** 2791 * dwc2_queue_transaction() - Attempts to queue a single transaction request for 2792 * a host channel associated with either a periodic or non-periodic transfer 2793 * 2794 * @hsotg: The HCD state structure 2795 * @chan: Host channel descriptor associated with either a periodic or 2796 * non-periodic transfer 2797 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO 2798 * for periodic transfers or the non-periodic Tx FIFO 2799 * for non-periodic transfers 2800 * 2801 * Return: 1 if a request is queued and more requests may be needed to 2802 * complete the transfer, 0 if no more requests are required for this 2803 * transfer, -1 if there is insufficient space in the Tx FIFO 2804 * 2805 * This function assumes that there is space available in the appropriate 2806 * request queue. For an OUT transfer or SETUP transaction in Slave mode, 2807 * it checks whether space is available in the appropriate Tx FIFO. 2808 * 2809 * Must be called with interrupt disabled and spinlock held 2810 */ 2811 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg, 2812 struct dwc2_host_chan *chan, 2813 u16 fifo_dwords_avail) 2814 { 2815 int retval = 0; 2816 2817 if (chan->do_split) 2818 /* Put ourselves on the list to keep order straight */ 2819 list_move_tail(&chan->split_order_list_entry, 2820 &hsotg->split_order); 2821 2822 if (hsotg->params.host_dma && chan->qh) { 2823 if (hsotg->params.dma_desc_enable) { 2824 if (!chan->xfer_started || 2825 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 2826 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh); 2827 chan->qh->ping_state = 0; 2828 } 2829 } else if (!chan->xfer_started) { 2830 dwc2_hc_start_transfer(hsotg, chan); 2831 chan->qh->ping_state = 0; 2832 } 2833 } else if (chan->halt_pending) { 2834 /* Don't queue a request if the channel has been halted */ 2835 } else if (chan->halt_on_queue) { 2836 dwc2_hc_halt(hsotg, chan, chan->halt_status); 2837 } else if (chan->do_ping) { 2838 if (!chan->xfer_started) 2839 dwc2_hc_start_transfer(hsotg, chan); 2840 } else if (!chan->ep_is_in || 2841 chan->data_pid_start == DWC2_HC_PID_SETUP) { 2842 if ((fifo_dwords_avail * 4) >= chan->max_packet) { 2843 if (!chan->xfer_started) { 2844 dwc2_hc_start_transfer(hsotg, chan); 2845 retval = 1; 2846 } else { 2847 retval = dwc2_hc_continue_transfer(hsotg, chan); 2848 } 2849 } else { 2850 retval = -1; 2851 } 2852 } else { 2853 if (!chan->xfer_started) { 2854 dwc2_hc_start_transfer(hsotg, chan); 2855 retval = 1; 2856 } else { 2857 retval = dwc2_hc_continue_transfer(hsotg, chan); 2858 } 2859 } 2860 2861 return retval; 2862 } 2863 2864 /* 2865 * Processes periodic channels for the next frame and queues transactions for 2866 * these channels to the DWC_otg controller. After queueing transactions, the 2867 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions 2868 * to queue as Periodic Tx FIFO or request queue space becomes available. 2869 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. 2870 * 2871 * Must be called with interrupt disabled and spinlock held 2872 */ 2873 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) 2874 { 2875 struct list_head *qh_ptr; 2876 struct dwc2_qh *qh; 2877 u32 tx_status; 2878 u32 fspcavail; 2879 u32 gintmsk; 2880 int status; 2881 bool no_queue_space = false; 2882 bool no_fifo_space = false; 2883 u32 qspcavail; 2884 2885 /* If empty list then just adjust interrupt enables */ 2886 if (list_empty(&hsotg->periodic_sched_assigned)) 2887 goto exit; 2888 2889 if (dbg_perio()) 2890 dev_vdbg(hsotg->dev, "Queue periodic transactions\n"); 2891 2892 tx_status = dwc2_readl(hsotg, HPTXSTS); 2893 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 2894 TXSTS_QSPCAVAIL_SHIFT; 2895 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 2896 TXSTS_FSPCAVAIL_SHIFT; 2897 2898 if (dbg_perio()) { 2899 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n", 2900 qspcavail); 2901 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n", 2902 fspcavail); 2903 } 2904 2905 qh_ptr = hsotg->periodic_sched_assigned.next; 2906 while (qh_ptr != &hsotg->periodic_sched_assigned) { 2907 tx_status = dwc2_readl(hsotg, HPTXSTS); 2908 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 2909 TXSTS_QSPCAVAIL_SHIFT; 2910 if (qspcavail == 0) { 2911 no_queue_space = true; 2912 break; 2913 } 2914 2915 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 2916 if (!qh->channel) { 2917 qh_ptr = qh_ptr->next; 2918 continue; 2919 } 2920 2921 /* Make sure EP's TT buffer is clean before queueing qtds */ 2922 if (qh->tt_buffer_dirty) { 2923 qh_ptr = qh_ptr->next; 2924 continue; 2925 } 2926 2927 /* 2928 * Set a flag if we're queuing high-bandwidth in slave mode. 2929 * The flag prevents any halts to get into the request queue in 2930 * the middle of multiple high-bandwidth packets getting queued. 2931 */ 2932 if (!hsotg->params.host_dma && 2933 qh->channel->multi_count > 1) 2934 hsotg->queuing_high_bandwidth = 1; 2935 2936 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 2937 TXSTS_FSPCAVAIL_SHIFT; 2938 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 2939 if (status < 0) { 2940 no_fifo_space = true; 2941 break; 2942 } 2943 2944 /* 2945 * In Slave mode, stay on the current transfer until there is 2946 * nothing more to do or the high-bandwidth request count is 2947 * reached. In DMA mode, only need to queue one request. The 2948 * controller automatically handles multiple packets for 2949 * high-bandwidth transfers. 2950 */ 2951 if (hsotg->params.host_dma || status == 0 || 2952 qh->channel->requests == qh->channel->multi_count) { 2953 qh_ptr = qh_ptr->next; 2954 /* 2955 * Move the QH from the periodic assigned schedule to 2956 * the periodic queued schedule 2957 */ 2958 list_move_tail(&qh->qh_list_entry, 2959 &hsotg->periodic_sched_queued); 2960 2961 /* done queuing high bandwidth */ 2962 hsotg->queuing_high_bandwidth = 0; 2963 } 2964 } 2965 2966 exit: 2967 if (no_queue_space || no_fifo_space || 2968 (!hsotg->params.host_dma && 2969 !list_empty(&hsotg->periodic_sched_assigned))) { 2970 /* 2971 * May need to queue more transactions as the request 2972 * queue or Tx FIFO empties. Enable the periodic Tx 2973 * FIFO empty interrupt. (Always use the half-empty 2974 * level to ensure that new requests are loaded as 2975 * soon as possible.) 2976 */ 2977 gintmsk = dwc2_readl(hsotg, GINTMSK); 2978 if (!(gintmsk & GINTSTS_PTXFEMP)) { 2979 gintmsk |= GINTSTS_PTXFEMP; 2980 dwc2_writel(hsotg, gintmsk, GINTMSK); 2981 } 2982 } else { 2983 /* 2984 * Disable the Tx FIFO empty interrupt since there are 2985 * no more transactions that need to be queued right 2986 * now. This function is called from interrupt 2987 * handlers to queue more transactions as transfer 2988 * states change. 2989 */ 2990 gintmsk = dwc2_readl(hsotg, GINTMSK); 2991 if (gintmsk & GINTSTS_PTXFEMP) { 2992 gintmsk &= ~GINTSTS_PTXFEMP; 2993 dwc2_writel(hsotg, gintmsk, GINTMSK); 2994 } 2995 } 2996 } 2997 2998 /* 2999 * Processes active non-periodic channels and queues transactions for these 3000 * channels to the DWC_otg controller. After queueing transactions, the NP Tx 3001 * FIFO Empty interrupt is enabled if there are more transactions to queue as 3002 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx 3003 * FIFO Empty interrupt is disabled. 3004 * 3005 * Must be called with interrupt disabled and spinlock held 3006 */ 3007 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg) 3008 { 3009 struct list_head *orig_qh_ptr; 3010 struct dwc2_qh *qh; 3011 u32 tx_status; 3012 u32 qspcavail; 3013 u32 fspcavail; 3014 u32 gintmsk; 3015 int status; 3016 int no_queue_space = 0; 3017 int no_fifo_space = 0; 3018 int more_to_do = 0; 3019 3020 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n"); 3021 3022 tx_status = dwc2_readl(hsotg, GNPTXSTS); 3023 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3024 TXSTS_QSPCAVAIL_SHIFT; 3025 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3026 TXSTS_FSPCAVAIL_SHIFT; 3027 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n", 3028 qspcavail); 3029 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n", 3030 fspcavail); 3031 3032 /* 3033 * Keep track of the starting point. Skip over the start-of-list 3034 * entry. 3035 */ 3036 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active) 3037 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 3038 orig_qh_ptr = hsotg->non_periodic_qh_ptr; 3039 3040 /* 3041 * Process once through the active list or until no more space is 3042 * available in the request queue or the Tx FIFO 3043 */ 3044 do { 3045 tx_status = dwc2_readl(hsotg, GNPTXSTS); 3046 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3047 TXSTS_QSPCAVAIL_SHIFT; 3048 if (!hsotg->params.host_dma && qspcavail == 0) { 3049 no_queue_space = 1; 3050 break; 3051 } 3052 3053 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh, 3054 qh_list_entry); 3055 if (!qh->channel) 3056 goto next; 3057 3058 /* Make sure EP's TT buffer is clean before queueing qtds */ 3059 if (qh->tt_buffer_dirty) 3060 goto next; 3061 3062 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3063 TXSTS_FSPCAVAIL_SHIFT; 3064 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 3065 3066 if (status > 0) { 3067 more_to_do = 1; 3068 } else if (status < 0) { 3069 no_fifo_space = 1; 3070 break; 3071 } 3072 next: 3073 /* Advance to next QH, skipping start-of-list entry */ 3074 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 3075 if (hsotg->non_periodic_qh_ptr == 3076 &hsotg->non_periodic_sched_active) 3077 hsotg->non_periodic_qh_ptr = 3078 hsotg->non_periodic_qh_ptr->next; 3079 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr); 3080 3081 if (!hsotg->params.host_dma) { 3082 tx_status = dwc2_readl(hsotg, GNPTXSTS); 3083 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3084 TXSTS_QSPCAVAIL_SHIFT; 3085 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3086 TXSTS_FSPCAVAIL_SHIFT; 3087 dev_vdbg(hsotg->dev, 3088 " NP Tx Req Queue Space Avail (after queue): %d\n", 3089 qspcavail); 3090 dev_vdbg(hsotg->dev, 3091 " NP Tx FIFO Space Avail (after queue): %d\n", 3092 fspcavail); 3093 3094 if (more_to_do || no_queue_space || no_fifo_space) { 3095 /* 3096 * May need to queue more transactions as the request 3097 * queue or Tx FIFO empties. Enable the non-periodic 3098 * Tx FIFO empty interrupt. (Always use the half-empty 3099 * level to ensure that new requests are loaded as 3100 * soon as possible.) 3101 */ 3102 gintmsk = dwc2_readl(hsotg, GINTMSK); 3103 gintmsk |= GINTSTS_NPTXFEMP; 3104 dwc2_writel(hsotg, gintmsk, GINTMSK); 3105 } else { 3106 /* 3107 * Disable the Tx FIFO empty interrupt since there are 3108 * no more transactions that need to be queued right 3109 * now. This function is called from interrupt 3110 * handlers to queue more transactions as transfer 3111 * states change. 3112 */ 3113 gintmsk = dwc2_readl(hsotg, GINTMSK); 3114 gintmsk &= ~GINTSTS_NPTXFEMP; 3115 dwc2_writel(hsotg, gintmsk, GINTMSK); 3116 } 3117 } 3118 } 3119 3120 /** 3121 * dwc2_hcd_queue_transactions() - Processes the currently active host channels 3122 * and queues transactions for these channels to the DWC_otg controller. Called 3123 * from the HCD interrupt handler functions. 3124 * 3125 * @hsotg: The HCD state structure 3126 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic, 3127 * or both) 3128 * 3129 * Must be called with interrupt disabled and spinlock held 3130 */ 3131 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 3132 enum dwc2_transaction_type tr_type) 3133 { 3134 #ifdef DWC2_DEBUG_SOF 3135 dev_vdbg(hsotg->dev, "Queue Transactions\n"); 3136 #endif 3137 /* Process host channels associated with periodic transfers */ 3138 if (tr_type == DWC2_TRANSACTION_PERIODIC || 3139 tr_type == DWC2_TRANSACTION_ALL) 3140 dwc2_process_periodic_channels(hsotg); 3141 3142 /* Process host channels associated with non-periodic transfers */ 3143 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC || 3144 tr_type == DWC2_TRANSACTION_ALL) { 3145 if (!list_empty(&hsotg->non_periodic_sched_active)) { 3146 dwc2_process_non_periodic_channels(hsotg); 3147 } else { 3148 /* 3149 * Ensure NP Tx FIFO empty interrupt is disabled when 3150 * there are no non-periodic transfers to process 3151 */ 3152 u32 gintmsk = dwc2_readl(hsotg, GINTMSK); 3153 3154 gintmsk &= ~GINTSTS_NPTXFEMP; 3155 dwc2_writel(hsotg, gintmsk, GINTMSK); 3156 } 3157 } 3158 } 3159 3160 static void dwc2_conn_id_status_change(struct work_struct *work) 3161 { 3162 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 3163 wf_otg); 3164 u32 count = 0; 3165 u32 gotgctl; 3166 unsigned long flags; 3167 3168 dev_dbg(hsotg->dev, "%s()\n", __func__); 3169 3170 gotgctl = dwc2_readl(hsotg, GOTGCTL); 3171 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl); 3172 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n", 3173 !!(gotgctl & GOTGCTL_CONID_B)); 3174 3175 /* B-Device connector (Device Mode) */ 3176 if (gotgctl & GOTGCTL_CONID_B) { 3177 dwc2_vbus_supply_exit(hsotg); 3178 /* Wait for switch to device mode */ 3179 dev_dbg(hsotg->dev, "connId B\n"); 3180 if (hsotg->bus_suspended) { 3181 dev_info(hsotg->dev, 3182 "Do port resume before switching to device mode\n"); 3183 dwc2_port_resume(hsotg); 3184 } 3185 while (!dwc2_is_device_mode(hsotg)) { 3186 dev_info(hsotg->dev, 3187 "Waiting for Peripheral Mode, Mode=%s\n", 3188 dwc2_is_host_mode(hsotg) ? "Host" : 3189 "Peripheral"); 3190 msleep(20); 3191 /* 3192 * Sometimes the initial GOTGCTRL read is wrong, so 3193 * check it again and jump to host mode if that was 3194 * the case. 3195 */ 3196 gotgctl = dwc2_readl(hsotg, GOTGCTL); 3197 if (!(gotgctl & GOTGCTL_CONID_B)) 3198 goto host; 3199 if (++count > 250) 3200 break; 3201 } 3202 if (count > 250) 3203 dev_err(hsotg->dev, 3204 "Connection id status change timed out\n"); 3205 3206 /* 3207 * Exit Partial Power Down without restoring registers. 3208 * No need to check the return value as registers 3209 * are not being restored. 3210 */ 3211 if (hsotg->in_ppd && hsotg->lx_state == DWC2_L2) 3212 dwc2_exit_partial_power_down(hsotg, 0, false); 3213 3214 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 3215 dwc2_core_init(hsotg, false); 3216 dwc2_enable_global_interrupts(hsotg); 3217 spin_lock_irqsave(&hsotg->lock, flags); 3218 dwc2_hsotg_core_init_disconnected(hsotg, false); 3219 spin_unlock_irqrestore(&hsotg->lock, flags); 3220 /* Enable ACG feature in device mode,if supported */ 3221 dwc2_enable_acg(hsotg); 3222 dwc2_hsotg_core_connect(hsotg); 3223 } else { 3224 host: 3225 /* A-Device connector (Host Mode) */ 3226 dev_dbg(hsotg->dev, "connId A\n"); 3227 while (!dwc2_is_host_mode(hsotg)) { 3228 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n", 3229 dwc2_is_host_mode(hsotg) ? 3230 "Host" : "Peripheral"); 3231 msleep(20); 3232 if (++count > 250) 3233 break; 3234 } 3235 if (count > 250) 3236 dev_err(hsotg->dev, 3237 "Connection id status change timed out\n"); 3238 3239 spin_lock_irqsave(&hsotg->lock, flags); 3240 dwc2_hsotg_disconnect(hsotg); 3241 spin_unlock_irqrestore(&hsotg->lock, flags); 3242 3243 hsotg->op_state = OTG_STATE_A_HOST; 3244 /* Initialize the Core for Host mode */ 3245 dwc2_core_init(hsotg, false); 3246 dwc2_enable_global_interrupts(hsotg); 3247 dwc2_hcd_start(hsotg); 3248 } 3249 } 3250 3251 static void dwc2_wakeup_detected(struct timer_list *t) 3252 { 3253 struct dwc2_hsotg *hsotg = from_timer(hsotg, t, wkp_timer); 3254 u32 hprt0; 3255 3256 dev_dbg(hsotg->dev, "%s()\n", __func__); 3257 3258 /* 3259 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms 3260 * so that OPT tests pass with all PHYs.) 3261 */ 3262 hprt0 = dwc2_read_hprt0(hsotg); 3263 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0); 3264 hprt0 &= ~HPRT0_RES; 3265 dwc2_writel(hsotg, hprt0, HPRT0); 3266 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n", 3267 dwc2_readl(hsotg, HPRT0)); 3268 3269 dwc2_hcd_rem_wakeup(hsotg); 3270 hsotg->bus_suspended = false; 3271 3272 /* Change to L0 state */ 3273 hsotg->lx_state = DWC2_L0; 3274 } 3275 3276 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg) 3277 { 3278 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 3279 3280 return hcd->self.b_hnp_enable; 3281 } 3282 3283 /** 3284 * dwc2_port_suspend() - Put controller in suspend mode for host. 3285 * 3286 * @hsotg: Programming view of the DWC_otg controller 3287 * @windex: The control request wIndex field 3288 * 3289 * Return: non-zero if failed to enter suspend mode for host. 3290 * 3291 * This function is for entering Host mode suspend. 3292 * Must NOT be called with interrupt disabled or spinlock held. 3293 */ 3294 int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) 3295 { 3296 unsigned long flags; 3297 u32 pcgctl; 3298 u32 gotgctl; 3299 int ret = 0; 3300 3301 dev_dbg(hsotg->dev, "%s()\n", __func__); 3302 3303 spin_lock_irqsave(&hsotg->lock, flags); 3304 3305 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) { 3306 gotgctl = dwc2_readl(hsotg, GOTGCTL); 3307 gotgctl |= GOTGCTL_HSTSETHNPEN; 3308 dwc2_writel(hsotg, gotgctl, GOTGCTL); 3309 hsotg->op_state = OTG_STATE_A_SUSPEND; 3310 } 3311 3312 switch (hsotg->params.power_down) { 3313 case DWC2_POWER_DOWN_PARAM_PARTIAL: 3314 ret = dwc2_enter_partial_power_down(hsotg); 3315 if (ret) 3316 dev_err(hsotg->dev, 3317 "enter partial_power_down failed.\n"); 3318 break; 3319 case DWC2_POWER_DOWN_PARAM_HIBERNATION: 3320 /* 3321 * Perform spin unlock and lock because in 3322 * "dwc2_host_enter_hibernation()" function there is a spinlock 3323 * logic which prevents servicing of any IRQ during entering 3324 * hibernation. 3325 */ 3326 spin_unlock_irqrestore(&hsotg->lock, flags); 3327 ret = dwc2_enter_hibernation(hsotg, 1); 3328 if (ret) 3329 dev_err(hsotg->dev, "enter hibernation failed.\n"); 3330 spin_lock_irqsave(&hsotg->lock, flags); 3331 break; 3332 case DWC2_POWER_DOWN_PARAM_NONE: 3333 /* 3334 * If not hibernation nor partial power down are supported, 3335 * clock gating is used to save power. 3336 */ 3337 if (!hsotg->params.no_clock_gating) 3338 dwc2_host_enter_clock_gating(hsotg); 3339 break; 3340 } 3341 3342 /* For HNP the bus must be suspended for at least 200ms */ 3343 if (dwc2_host_is_b_hnp_enabled(hsotg)) { 3344 pcgctl = dwc2_readl(hsotg, PCGCTL); 3345 pcgctl &= ~PCGCTL_STOPPCLK; 3346 dwc2_writel(hsotg, pcgctl, PCGCTL); 3347 3348 spin_unlock_irqrestore(&hsotg->lock, flags); 3349 3350 msleep(200); 3351 } else { 3352 spin_unlock_irqrestore(&hsotg->lock, flags); 3353 } 3354 3355 return ret; 3356 } 3357 3358 /** 3359 * dwc2_port_resume() - Exit controller from suspend mode for host. 3360 * 3361 * @hsotg: Programming view of the DWC_otg controller 3362 * 3363 * Return: non-zero if failed to exit suspend mode for host. 3364 * 3365 * This function is for exiting Host mode suspend. 3366 * Must NOT be called with interrupt disabled or spinlock held. 3367 */ 3368 int dwc2_port_resume(struct dwc2_hsotg *hsotg) 3369 { 3370 unsigned long flags; 3371 int ret = 0; 3372 3373 spin_lock_irqsave(&hsotg->lock, flags); 3374 3375 switch (hsotg->params.power_down) { 3376 case DWC2_POWER_DOWN_PARAM_PARTIAL: 3377 ret = dwc2_exit_partial_power_down(hsotg, 0, true); 3378 if (ret) 3379 dev_err(hsotg->dev, 3380 "exit partial_power_down failed.\n"); 3381 break; 3382 case DWC2_POWER_DOWN_PARAM_HIBERNATION: 3383 /* Exit host hibernation. */ 3384 ret = dwc2_exit_hibernation(hsotg, 0, 0, 1); 3385 if (ret) 3386 dev_err(hsotg->dev, "exit hibernation failed.\n"); 3387 break; 3388 case DWC2_POWER_DOWN_PARAM_NONE: 3389 /* 3390 * If not hibernation nor partial power down are supported, 3391 * port resume is done using the clock gating programming flow. 3392 */ 3393 spin_unlock_irqrestore(&hsotg->lock, flags); 3394 dwc2_host_exit_clock_gating(hsotg, 0); 3395 spin_lock_irqsave(&hsotg->lock, flags); 3396 break; 3397 } 3398 3399 spin_unlock_irqrestore(&hsotg->lock, flags); 3400 3401 return ret; 3402 } 3403 3404 /* Handles hub class-specific requests */ 3405 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, 3406 u16 wvalue, u16 windex, char *buf, u16 wlength) 3407 { 3408 struct usb_hub_descriptor *hub_desc; 3409 int retval = 0; 3410 u32 hprt0; 3411 u32 port_status; 3412 u32 speed; 3413 u32 pcgctl; 3414 u32 pwr; 3415 3416 switch (typereq) { 3417 case ClearHubFeature: 3418 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue); 3419 3420 switch (wvalue) { 3421 case C_HUB_LOCAL_POWER: 3422 case C_HUB_OVER_CURRENT: 3423 /* Nothing required here */ 3424 break; 3425 3426 default: 3427 retval = -EINVAL; 3428 dev_err(hsotg->dev, 3429 "ClearHubFeature request %1xh unknown\n", 3430 wvalue); 3431 } 3432 break; 3433 3434 case ClearPortFeature: 3435 if (wvalue != USB_PORT_FEAT_L1) 3436 if (!windex || windex > 1) 3437 goto error; 3438 switch (wvalue) { 3439 case USB_PORT_FEAT_ENABLE: 3440 dev_dbg(hsotg->dev, 3441 "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); 3442 hprt0 = dwc2_read_hprt0(hsotg); 3443 hprt0 |= HPRT0_ENA; 3444 dwc2_writel(hsotg, hprt0, HPRT0); 3445 break; 3446 3447 case USB_PORT_FEAT_SUSPEND: 3448 dev_dbg(hsotg->dev, 3449 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); 3450 3451 if (hsotg->bus_suspended) 3452 retval = dwc2_port_resume(hsotg); 3453 break; 3454 3455 case USB_PORT_FEAT_POWER: 3456 dev_dbg(hsotg->dev, 3457 "ClearPortFeature USB_PORT_FEAT_POWER\n"); 3458 hprt0 = dwc2_read_hprt0(hsotg); 3459 pwr = hprt0 & HPRT0_PWR; 3460 hprt0 &= ~HPRT0_PWR; 3461 dwc2_writel(hsotg, hprt0, HPRT0); 3462 if (pwr) 3463 dwc2_vbus_supply_exit(hsotg); 3464 break; 3465 3466 case USB_PORT_FEAT_INDICATOR: 3467 dev_dbg(hsotg->dev, 3468 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); 3469 /* Port indicator not supported */ 3470 break; 3471 3472 case USB_PORT_FEAT_C_CONNECTION: 3473 /* 3474 * Clears driver's internal Connect Status Change flag 3475 */ 3476 dev_dbg(hsotg->dev, 3477 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); 3478 hsotg->flags.b.port_connect_status_change = 0; 3479 break; 3480 3481 case USB_PORT_FEAT_C_RESET: 3482 /* Clears driver's internal Port Reset Change flag */ 3483 dev_dbg(hsotg->dev, 3484 "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); 3485 hsotg->flags.b.port_reset_change = 0; 3486 break; 3487 3488 case USB_PORT_FEAT_C_ENABLE: 3489 /* 3490 * Clears the driver's internal Port Enable/Disable 3491 * Change flag 3492 */ 3493 dev_dbg(hsotg->dev, 3494 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); 3495 hsotg->flags.b.port_enable_change = 0; 3496 break; 3497 3498 case USB_PORT_FEAT_C_SUSPEND: 3499 /* 3500 * Clears the driver's internal Port Suspend Change 3501 * flag, which is set when resume signaling on the host 3502 * port is complete 3503 */ 3504 dev_dbg(hsotg->dev, 3505 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); 3506 hsotg->flags.b.port_suspend_change = 0; 3507 break; 3508 3509 case USB_PORT_FEAT_C_PORT_L1: 3510 dev_dbg(hsotg->dev, 3511 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n"); 3512 hsotg->flags.b.port_l1_change = 0; 3513 break; 3514 3515 case USB_PORT_FEAT_C_OVER_CURRENT: 3516 dev_dbg(hsotg->dev, 3517 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); 3518 hsotg->flags.b.port_over_current_change = 0; 3519 break; 3520 3521 default: 3522 retval = -EINVAL; 3523 dev_err(hsotg->dev, 3524 "ClearPortFeature request %1xh unknown or unsupported\n", 3525 wvalue); 3526 } 3527 break; 3528 3529 case GetHubDescriptor: 3530 dev_dbg(hsotg->dev, "GetHubDescriptor\n"); 3531 hub_desc = (struct usb_hub_descriptor *)buf; 3532 hub_desc->bDescLength = 9; 3533 hub_desc->bDescriptorType = USB_DT_HUB; 3534 hub_desc->bNbrPorts = 1; 3535 hub_desc->wHubCharacteristics = 3536 cpu_to_le16(HUB_CHAR_COMMON_LPSM | 3537 HUB_CHAR_INDV_PORT_OCPM); 3538 hub_desc->bPwrOn2PwrGood = 1; 3539 hub_desc->bHubContrCurrent = 0; 3540 hub_desc->u.hs.DeviceRemovable[0] = 0; 3541 hub_desc->u.hs.DeviceRemovable[1] = 0xff; 3542 break; 3543 3544 case GetHubStatus: 3545 dev_dbg(hsotg->dev, "GetHubStatus\n"); 3546 memset(buf, 0, 4); 3547 break; 3548 3549 case GetPortStatus: 3550 dev_vdbg(hsotg->dev, 3551 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex, 3552 hsotg->flags.d32); 3553 if (!windex || windex > 1) 3554 goto error; 3555 3556 port_status = 0; 3557 if (hsotg->flags.b.port_connect_status_change) 3558 port_status |= USB_PORT_STAT_C_CONNECTION << 16; 3559 if (hsotg->flags.b.port_enable_change) 3560 port_status |= USB_PORT_STAT_C_ENABLE << 16; 3561 if (hsotg->flags.b.port_suspend_change) 3562 port_status |= USB_PORT_STAT_C_SUSPEND << 16; 3563 if (hsotg->flags.b.port_l1_change) 3564 port_status |= USB_PORT_STAT_C_L1 << 16; 3565 if (hsotg->flags.b.port_reset_change) 3566 port_status |= USB_PORT_STAT_C_RESET << 16; 3567 if (hsotg->flags.b.port_over_current_change) { 3568 dev_warn(hsotg->dev, "Overcurrent change detected\n"); 3569 port_status |= USB_PORT_STAT_C_OVERCURRENT << 16; 3570 } 3571 3572 if (!hsotg->flags.b.port_connect_status) { 3573 /* 3574 * The port is disconnected, which means the core is 3575 * either in device mode or it soon will be. Just 3576 * return 0's for the remainder of the port status 3577 * since the port register can't be read if the core 3578 * is in device mode. 3579 */ 3580 *(__le32 *)buf = cpu_to_le32(port_status); 3581 break; 3582 } 3583 3584 hprt0 = dwc2_readl(hsotg, HPRT0); 3585 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0); 3586 3587 if (hprt0 & HPRT0_CONNSTS) 3588 port_status |= USB_PORT_STAT_CONNECTION; 3589 if (hprt0 & HPRT0_ENA) 3590 port_status |= USB_PORT_STAT_ENABLE; 3591 if (hprt0 & HPRT0_SUSP) 3592 port_status |= USB_PORT_STAT_SUSPEND; 3593 if (hprt0 & HPRT0_OVRCURRACT) 3594 port_status |= USB_PORT_STAT_OVERCURRENT; 3595 if (hprt0 & HPRT0_RST) 3596 port_status |= USB_PORT_STAT_RESET; 3597 if (hprt0 & HPRT0_PWR) 3598 port_status |= USB_PORT_STAT_POWER; 3599 3600 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 3601 if (speed == HPRT0_SPD_HIGH_SPEED) 3602 port_status |= USB_PORT_STAT_HIGH_SPEED; 3603 else if (speed == HPRT0_SPD_LOW_SPEED) 3604 port_status |= USB_PORT_STAT_LOW_SPEED; 3605 3606 if (hprt0 & HPRT0_TSTCTL_MASK) 3607 port_status |= USB_PORT_STAT_TEST; 3608 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ 3609 3610 if (hsotg->params.dma_desc_fs_enable) { 3611 /* 3612 * Enable descriptor DMA only if a full speed 3613 * device is connected. 3614 */ 3615 if (hsotg->new_connection && 3616 ((port_status & 3617 (USB_PORT_STAT_CONNECTION | 3618 USB_PORT_STAT_HIGH_SPEED | 3619 USB_PORT_STAT_LOW_SPEED)) == 3620 USB_PORT_STAT_CONNECTION)) { 3621 u32 hcfg; 3622 3623 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n"); 3624 hsotg->params.dma_desc_enable = true; 3625 hcfg = dwc2_readl(hsotg, HCFG); 3626 hcfg |= HCFG_DESCDMA; 3627 dwc2_writel(hsotg, hcfg, HCFG); 3628 hsotg->new_connection = false; 3629 } 3630 } 3631 3632 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status); 3633 *(__le32 *)buf = cpu_to_le32(port_status); 3634 break; 3635 3636 case SetHubFeature: 3637 dev_dbg(hsotg->dev, "SetHubFeature\n"); 3638 /* No HUB features supported */ 3639 break; 3640 3641 case SetPortFeature: 3642 dev_dbg(hsotg->dev, "SetPortFeature\n"); 3643 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1)) 3644 goto error; 3645 3646 if (!hsotg->flags.b.port_connect_status) { 3647 /* 3648 * The port is disconnected, which means the core is 3649 * either in device mode or it soon will be. Just 3650 * return without doing anything since the port 3651 * register can't be written if the core is in device 3652 * mode. 3653 */ 3654 break; 3655 } 3656 3657 switch (wvalue) { 3658 case USB_PORT_FEAT_SUSPEND: 3659 dev_dbg(hsotg->dev, 3660 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); 3661 if (windex != hsotg->otg_port) 3662 goto error; 3663 if (!hsotg->bus_suspended) 3664 retval = dwc2_port_suspend(hsotg, windex); 3665 break; 3666 3667 case USB_PORT_FEAT_POWER: 3668 dev_dbg(hsotg->dev, 3669 "SetPortFeature - USB_PORT_FEAT_POWER\n"); 3670 hprt0 = dwc2_read_hprt0(hsotg); 3671 pwr = hprt0 & HPRT0_PWR; 3672 hprt0 |= HPRT0_PWR; 3673 dwc2_writel(hsotg, hprt0, HPRT0); 3674 if (!pwr) 3675 dwc2_vbus_supply_init(hsotg); 3676 break; 3677 3678 case USB_PORT_FEAT_RESET: 3679 dev_dbg(hsotg->dev, 3680 "SetPortFeature - USB_PORT_FEAT_RESET\n"); 3681 3682 hprt0 = dwc2_read_hprt0(hsotg); 3683 3684 if (hsotg->hibernated) { 3685 retval = dwc2_exit_hibernation(hsotg, 0, 1, 1); 3686 if (retval) 3687 dev_err(hsotg->dev, 3688 "exit hibernation failed\n"); 3689 } 3690 3691 if (hsotg->in_ppd) { 3692 retval = dwc2_exit_partial_power_down(hsotg, 1, 3693 true); 3694 if (retval) 3695 dev_err(hsotg->dev, 3696 "exit partial_power_down failed\n"); 3697 } 3698 3699 if (hsotg->params.power_down == 3700 DWC2_POWER_DOWN_PARAM_NONE && hsotg->bus_suspended) 3701 dwc2_host_exit_clock_gating(hsotg, 0); 3702 3703 pcgctl = dwc2_readl(hsotg, PCGCTL); 3704 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK); 3705 dwc2_writel(hsotg, pcgctl, PCGCTL); 3706 /* ??? Original driver does this */ 3707 dwc2_writel(hsotg, 0, PCGCTL); 3708 3709 hprt0 = dwc2_read_hprt0(hsotg); 3710 pwr = hprt0 & HPRT0_PWR; 3711 /* Clear suspend bit if resetting from suspend state */ 3712 hprt0 &= ~HPRT0_SUSP; 3713 3714 /* 3715 * When B-Host the Port reset bit is set in the Start 3716 * HCD Callback function, so that the reset is started 3717 * within 1ms of the HNP success interrupt 3718 */ 3719 if (!dwc2_hcd_is_b_host(hsotg)) { 3720 hprt0 |= HPRT0_PWR | HPRT0_RST; 3721 dev_dbg(hsotg->dev, 3722 "In host mode, hprt0=%08x\n", hprt0); 3723 dwc2_writel(hsotg, hprt0, HPRT0); 3724 if (!pwr) 3725 dwc2_vbus_supply_init(hsotg); 3726 } 3727 3728 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ 3729 msleep(50); 3730 hprt0 &= ~HPRT0_RST; 3731 dwc2_writel(hsotg, hprt0, HPRT0); 3732 hsotg->lx_state = DWC2_L0; /* Now back to On state */ 3733 break; 3734 3735 case USB_PORT_FEAT_INDICATOR: 3736 dev_dbg(hsotg->dev, 3737 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); 3738 /* Not supported */ 3739 break; 3740 3741 case USB_PORT_FEAT_TEST: 3742 hprt0 = dwc2_read_hprt0(hsotg); 3743 dev_dbg(hsotg->dev, 3744 "SetPortFeature - USB_PORT_FEAT_TEST\n"); 3745 hprt0 &= ~HPRT0_TSTCTL_MASK; 3746 hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT; 3747 dwc2_writel(hsotg, hprt0, HPRT0); 3748 break; 3749 3750 default: 3751 retval = -EINVAL; 3752 dev_err(hsotg->dev, 3753 "SetPortFeature %1xh unknown or unsupported\n", 3754 wvalue); 3755 break; 3756 } 3757 break; 3758 3759 default: 3760 error: 3761 retval = -EINVAL; 3762 dev_dbg(hsotg->dev, 3763 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n", 3764 typereq, windex, wvalue); 3765 break; 3766 } 3767 3768 return retval; 3769 } 3770 3771 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port) 3772 { 3773 int retval; 3774 3775 if (port != 1) 3776 return -EINVAL; 3777 3778 retval = (hsotg->flags.b.port_connect_status_change || 3779 hsotg->flags.b.port_reset_change || 3780 hsotg->flags.b.port_enable_change || 3781 hsotg->flags.b.port_suspend_change || 3782 hsotg->flags.b.port_over_current_change); 3783 3784 if (retval) { 3785 dev_dbg(hsotg->dev, 3786 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n"); 3787 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n", 3788 hsotg->flags.b.port_connect_status_change); 3789 dev_dbg(hsotg->dev, " port_reset_change: %d\n", 3790 hsotg->flags.b.port_reset_change); 3791 dev_dbg(hsotg->dev, " port_enable_change: %d\n", 3792 hsotg->flags.b.port_enable_change); 3793 dev_dbg(hsotg->dev, " port_suspend_change: %d\n", 3794 hsotg->flags.b.port_suspend_change); 3795 dev_dbg(hsotg->dev, " port_over_current_change: %d\n", 3796 hsotg->flags.b.port_over_current_change); 3797 } 3798 3799 return retval; 3800 } 3801 3802 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 3803 { 3804 u32 hfnum = dwc2_readl(hsotg, HFNUM); 3805 3806 #ifdef DWC2_DEBUG_SOF 3807 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n", 3808 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT); 3809 #endif 3810 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 3811 } 3812 3813 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us) 3814 { 3815 u32 hprt = dwc2_readl(hsotg, HPRT0); 3816 u32 hfir = dwc2_readl(hsotg, HFIR); 3817 u32 hfnum = dwc2_readl(hsotg, HFNUM); 3818 unsigned int us_per_frame; 3819 unsigned int frame_number; 3820 unsigned int remaining; 3821 unsigned int interval; 3822 unsigned int phy_clks; 3823 3824 /* High speed has 125 us per (micro) frame; others are 1 ms per */ 3825 us_per_frame = (hprt & HPRT0_SPD_MASK) ? 1000 : 125; 3826 3827 /* Extract fields */ 3828 frame_number = (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 3829 remaining = (hfnum & HFNUM_FRREM_MASK) >> HFNUM_FRREM_SHIFT; 3830 interval = (hfir & HFIR_FRINT_MASK) >> HFIR_FRINT_SHIFT; 3831 3832 /* 3833 * Number of phy clocks since the last tick of the frame number after 3834 * "us" has passed. 3835 */ 3836 phy_clks = (interval - remaining) + 3837 DIV_ROUND_UP(interval * us, us_per_frame); 3838 3839 return dwc2_frame_num_inc(frame_number, phy_clks / interval); 3840 } 3841 3842 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg) 3843 { 3844 return hsotg->op_state == OTG_STATE_B_HOST; 3845 } 3846 3847 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg, 3848 int iso_desc_count, 3849 gfp_t mem_flags) 3850 { 3851 struct dwc2_hcd_urb *urb; 3852 3853 urb = kzalloc(struct_size(urb, iso_descs, iso_desc_count), mem_flags); 3854 if (urb) 3855 urb->packet_count = iso_desc_count; 3856 return urb; 3857 } 3858 3859 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg, 3860 struct dwc2_hcd_urb *urb, u8 dev_addr, 3861 u8 ep_num, u8 ep_type, u8 ep_dir, 3862 u16 maxp, u16 maxp_mult) 3863 { 3864 if (dbg_perio() || 3865 ep_type == USB_ENDPOINT_XFER_BULK || 3866 ep_type == USB_ENDPOINT_XFER_CONTROL) 3867 dev_vdbg(hsotg->dev, 3868 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, maxp=%d (%d mult)\n", 3869 dev_addr, ep_num, ep_dir, ep_type, maxp, maxp_mult); 3870 urb->pipe_info.dev_addr = dev_addr; 3871 urb->pipe_info.ep_num = ep_num; 3872 urb->pipe_info.pipe_type = ep_type; 3873 urb->pipe_info.pipe_dir = ep_dir; 3874 urb->pipe_info.maxp = maxp; 3875 urb->pipe_info.maxp_mult = maxp_mult; 3876 } 3877 3878 /* 3879 * NOTE: This function will be removed once the peripheral controller code 3880 * is integrated and the driver is stable 3881 */ 3882 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg) 3883 { 3884 #ifdef DEBUG 3885 struct dwc2_host_chan *chan; 3886 struct dwc2_hcd_urb *urb; 3887 struct dwc2_qtd *qtd; 3888 int num_channels; 3889 u32 np_tx_status; 3890 u32 p_tx_status; 3891 int i; 3892 3893 num_channels = hsotg->params.host_channels; 3894 dev_dbg(hsotg->dev, "\n"); 3895 dev_dbg(hsotg->dev, 3896 "************************************************************\n"); 3897 dev_dbg(hsotg->dev, "HCD State:\n"); 3898 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels); 3899 3900 for (i = 0; i < num_channels; i++) { 3901 chan = hsotg->hc_ptr_array[i]; 3902 dev_dbg(hsotg->dev, " Channel %d:\n", i); 3903 dev_dbg(hsotg->dev, 3904 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 3905 chan->dev_addr, chan->ep_num, chan->ep_is_in); 3906 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed); 3907 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 3908 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 3909 dev_dbg(hsotg->dev, " data_pid_start: %d\n", 3910 chan->data_pid_start); 3911 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count); 3912 dev_dbg(hsotg->dev, " xfer_started: %d\n", 3913 chan->xfer_started); 3914 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 3915 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 3916 (unsigned long)chan->xfer_dma); 3917 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 3918 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count); 3919 dev_dbg(hsotg->dev, " halt_on_queue: %d\n", 3920 chan->halt_on_queue); 3921 dev_dbg(hsotg->dev, " halt_pending: %d\n", 3922 chan->halt_pending); 3923 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 3924 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split); 3925 dev_dbg(hsotg->dev, " complete_split: %d\n", 3926 chan->complete_split); 3927 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr); 3928 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port); 3929 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos); 3930 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests); 3931 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 3932 3933 if (chan->xfer_started) { 3934 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk; 3935 3936 hfnum = dwc2_readl(hsotg, HFNUM); 3937 hcchar = dwc2_readl(hsotg, HCCHAR(i)); 3938 hctsiz = dwc2_readl(hsotg, HCTSIZ(i)); 3939 hcint = dwc2_readl(hsotg, HCINT(i)); 3940 hcintmsk = dwc2_readl(hsotg, HCINTMSK(i)); 3941 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum); 3942 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar); 3943 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz); 3944 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint); 3945 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk); 3946 } 3947 3948 if (!(chan->xfer_started && chan->qh)) 3949 continue; 3950 3951 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) { 3952 if (!qtd->in_process) 3953 break; 3954 urb = qtd->urb; 3955 dev_dbg(hsotg->dev, " URB Info:\n"); 3956 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n", 3957 qtd, urb); 3958 if (urb) { 3959 dev_dbg(hsotg->dev, 3960 " Dev: %d, EP: %d %s\n", 3961 dwc2_hcd_get_dev_addr(&urb->pipe_info), 3962 dwc2_hcd_get_ep_num(&urb->pipe_info), 3963 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 3964 "IN" : "OUT"); 3965 dev_dbg(hsotg->dev, 3966 " Max packet size: %d (%d mult)\n", 3967 dwc2_hcd_get_maxp(&urb->pipe_info), 3968 dwc2_hcd_get_maxp_mult(&urb->pipe_info)); 3969 dev_dbg(hsotg->dev, 3970 " transfer_buffer: %p\n", 3971 urb->buf); 3972 dev_dbg(hsotg->dev, 3973 " transfer_dma: %08lx\n", 3974 (unsigned long)urb->dma); 3975 dev_dbg(hsotg->dev, 3976 " transfer_buffer_length: %d\n", 3977 urb->length); 3978 dev_dbg(hsotg->dev, " actual_length: %d\n", 3979 urb->actual_length); 3980 } 3981 } 3982 } 3983 3984 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n", 3985 hsotg->non_periodic_channels); 3986 dev_dbg(hsotg->dev, " periodic_channels: %d\n", 3987 hsotg->periodic_channels); 3988 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs); 3989 np_tx_status = dwc2_readl(hsotg, GNPTXSTS); 3990 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n", 3991 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 3992 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n", 3993 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 3994 p_tx_status = dwc2_readl(hsotg, HPTXSTS); 3995 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n", 3996 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 3997 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n", 3998 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 3999 dwc2_dump_global_registers(hsotg); 4000 dwc2_dump_host_registers(hsotg); 4001 dev_dbg(hsotg->dev, 4002 "************************************************************\n"); 4003 dev_dbg(hsotg->dev, "\n"); 4004 #endif 4005 } 4006 4007 struct wrapper_priv_data { 4008 struct dwc2_hsotg *hsotg; 4009 }; 4010 4011 /* Gets the dwc2_hsotg from a usb_hcd */ 4012 static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd) 4013 { 4014 struct wrapper_priv_data *p; 4015 4016 p = (struct wrapper_priv_data *)&hcd->hcd_priv; 4017 return p->hsotg; 4018 } 4019 4020 /** 4021 * dwc2_host_get_tt_info() - Get the dwc2_tt associated with context 4022 * 4023 * This will get the dwc2_tt structure (and ttport) associated with the given 4024 * context (which is really just a struct urb pointer). 4025 * 4026 * The first time this is called for a given TT we allocate memory for our 4027 * structure. When everyone is done and has called dwc2_host_put_tt_info() 4028 * then the refcount for the structure will go to 0 and we'll free it. 4029 * 4030 * @hsotg: The HCD state structure for the DWC OTG controller. 4031 * @context: The priv pointer from a struct dwc2_hcd_urb. 4032 * @mem_flags: Flags for allocating memory. 4033 * @ttport: We'll return this device's port number here. That's used to 4034 * reference into the bitmap if we're on a multi_tt hub. 4035 * 4036 * Return: a pointer to a struct dwc2_tt. Don't forget to call 4037 * dwc2_host_put_tt_info()! Returns NULL upon memory alloc failure. 4038 */ 4039 4040 struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context, 4041 gfp_t mem_flags, int *ttport) 4042 { 4043 struct urb *urb = context; 4044 struct dwc2_tt *dwc_tt = NULL; 4045 4046 if (urb->dev->tt) { 4047 *ttport = urb->dev->ttport; 4048 4049 dwc_tt = urb->dev->tt->hcpriv; 4050 if (!dwc_tt) { 4051 size_t bitmap_size; 4052 4053 /* 4054 * For single_tt we need one schedule. For multi_tt 4055 * we need one per port. 4056 */ 4057 bitmap_size = DWC2_ELEMENTS_PER_LS_BITMAP * 4058 sizeof(dwc_tt->periodic_bitmaps[0]); 4059 if (urb->dev->tt->multi) 4060 bitmap_size *= urb->dev->tt->hub->maxchild; 4061 4062 dwc_tt = kzalloc(sizeof(*dwc_tt) + bitmap_size, 4063 mem_flags); 4064 if (!dwc_tt) 4065 return NULL; 4066 4067 dwc_tt->usb_tt = urb->dev->tt; 4068 dwc_tt->usb_tt->hcpriv = dwc_tt; 4069 } 4070 4071 dwc_tt->refcount++; 4072 } 4073 4074 return dwc_tt; 4075 } 4076 4077 /** 4078 * dwc2_host_put_tt_info() - Put the dwc2_tt from dwc2_host_get_tt_info() 4079 * 4080 * Frees resources allocated by dwc2_host_get_tt_info() if all current holders 4081 * of the structure are done. 4082 * 4083 * It's OK to call this with NULL. 4084 * 4085 * @hsotg: The HCD state structure for the DWC OTG controller. 4086 * @dwc_tt: The pointer returned by dwc2_host_get_tt_info. 4087 */ 4088 void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, struct dwc2_tt *dwc_tt) 4089 { 4090 /* Model kfree and make put of NULL a no-op */ 4091 if (!dwc_tt) 4092 return; 4093 4094 WARN_ON(dwc_tt->refcount < 1); 4095 4096 dwc_tt->refcount--; 4097 if (!dwc_tt->refcount) { 4098 dwc_tt->usb_tt->hcpriv = NULL; 4099 kfree(dwc_tt); 4100 } 4101 } 4102 4103 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context) 4104 { 4105 struct urb *urb = context; 4106 4107 return urb->dev->speed; 4108 } 4109 4110 static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw, 4111 struct urb *urb) 4112 { 4113 struct usb_bus *bus = hcd_to_bus(hcd); 4114 4115 if (urb->interval) 4116 bus->bandwidth_allocated += bw / urb->interval; 4117 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 4118 bus->bandwidth_isoc_reqs++; 4119 else 4120 bus->bandwidth_int_reqs++; 4121 } 4122 4123 static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw, 4124 struct urb *urb) 4125 { 4126 struct usb_bus *bus = hcd_to_bus(hcd); 4127 4128 if (urb->interval) 4129 bus->bandwidth_allocated -= bw / urb->interval; 4130 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 4131 bus->bandwidth_isoc_reqs--; 4132 else 4133 bus->bandwidth_int_reqs--; 4134 } 4135 4136 /* 4137 * Sets the final status of an URB and returns it to the upper layer. Any 4138 * required cleanup of the URB is performed. 4139 * 4140 * Must be called with interrupt disabled and spinlock held 4141 */ 4142 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 4143 int status) 4144 { 4145 struct urb *urb; 4146 int i; 4147 4148 if (!qtd) { 4149 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__); 4150 return; 4151 } 4152 4153 if (!qtd->urb) { 4154 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__); 4155 return; 4156 } 4157 4158 urb = qtd->urb->priv; 4159 if (!urb) { 4160 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__); 4161 return; 4162 } 4163 4164 urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb); 4165 4166 if (dbg_urb(urb)) 4167 dev_vdbg(hsotg->dev, 4168 "%s: urb %p device %d ep %d-%s status %d actual %d\n", 4169 __func__, urb, usb_pipedevice(urb->pipe), 4170 usb_pipeendpoint(urb->pipe), 4171 usb_pipein(urb->pipe) ? "IN" : "OUT", status, 4172 urb->actual_length); 4173 4174 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 4175 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb); 4176 for (i = 0; i < urb->number_of_packets; ++i) { 4177 urb->iso_frame_desc[i].actual_length = 4178 dwc2_hcd_urb_get_iso_desc_actual_length( 4179 qtd->urb, i); 4180 urb->iso_frame_desc[i].status = 4181 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i); 4182 } 4183 } 4184 4185 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) { 4186 for (i = 0; i < urb->number_of_packets; i++) 4187 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n", 4188 i, urb->iso_frame_desc[i].status); 4189 } 4190 4191 urb->status = status; 4192 if (!status) { 4193 if ((urb->transfer_flags & URB_SHORT_NOT_OK) && 4194 urb->actual_length < urb->transfer_buffer_length) 4195 urb->status = -EREMOTEIO; 4196 } 4197 4198 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || 4199 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { 4200 struct usb_host_endpoint *ep = urb->ep; 4201 4202 if (ep) 4203 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg), 4204 dwc2_hcd_get_ep_bandwidth(hsotg, ep), 4205 urb); 4206 } 4207 4208 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb); 4209 urb->hcpriv = NULL; 4210 kfree(qtd->urb); 4211 qtd->urb = NULL; 4212 4213 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status); 4214 } 4215 4216 /* 4217 * Work queue function for starting the HCD when A-Cable is connected 4218 */ 4219 static void dwc2_hcd_start_func(struct work_struct *work) 4220 { 4221 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 4222 start_work.work); 4223 4224 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg); 4225 dwc2_host_start(hsotg); 4226 } 4227 4228 /* 4229 * Reset work queue function 4230 */ 4231 static void dwc2_hcd_reset_func(struct work_struct *work) 4232 { 4233 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 4234 reset_work.work); 4235 unsigned long flags; 4236 u32 hprt0; 4237 4238 dev_dbg(hsotg->dev, "USB RESET function called\n"); 4239 4240 spin_lock_irqsave(&hsotg->lock, flags); 4241 4242 hprt0 = dwc2_read_hprt0(hsotg); 4243 hprt0 &= ~HPRT0_RST; 4244 dwc2_writel(hsotg, hprt0, HPRT0); 4245 hsotg->flags.b.port_reset_change = 1; 4246 4247 spin_unlock_irqrestore(&hsotg->lock, flags); 4248 } 4249 4250 static void dwc2_hcd_phy_reset_func(struct work_struct *work) 4251 { 4252 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 4253 phy_reset_work); 4254 int ret; 4255 4256 ret = phy_reset(hsotg->phy); 4257 if (ret) 4258 dev_warn(hsotg->dev, "PHY reset failed\n"); 4259 } 4260 4261 /* 4262 * ========================================================================= 4263 * Linux HC Driver Functions 4264 * ========================================================================= 4265 */ 4266 4267 /* 4268 * Initializes the DWC_otg controller and its root hub and prepares it for host 4269 * mode operation. Activates the root port. Returns 0 on success and a negative 4270 * error code on failure. 4271 */ 4272 static int _dwc2_hcd_start(struct usb_hcd *hcd) 4273 { 4274 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4275 struct usb_bus *bus = hcd_to_bus(hcd); 4276 unsigned long flags; 4277 u32 hprt0; 4278 int ret; 4279 4280 dev_dbg(hsotg->dev, "DWC OTG HCD START\n"); 4281 4282 spin_lock_irqsave(&hsotg->lock, flags); 4283 hsotg->lx_state = DWC2_L0; 4284 hcd->state = HC_STATE_RUNNING; 4285 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4286 4287 if (dwc2_is_device_mode(hsotg)) { 4288 spin_unlock_irqrestore(&hsotg->lock, flags); 4289 return 0; /* why 0 ?? */ 4290 } 4291 4292 dwc2_hcd_reinit(hsotg); 4293 4294 hprt0 = dwc2_read_hprt0(hsotg); 4295 /* Has vbus power been turned on in dwc2_core_host_init ? */ 4296 if (hprt0 & HPRT0_PWR) { 4297 /* Enable external vbus supply before resuming root hub */ 4298 spin_unlock_irqrestore(&hsotg->lock, flags); 4299 ret = dwc2_vbus_supply_init(hsotg); 4300 if (ret) 4301 return ret; 4302 spin_lock_irqsave(&hsotg->lock, flags); 4303 } 4304 4305 /* Initialize and connect root hub if one is not already attached */ 4306 if (bus->root_hub) { 4307 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n"); 4308 /* Inform the HUB driver to resume */ 4309 usb_hcd_resume_root_hub(hcd); 4310 } 4311 4312 spin_unlock_irqrestore(&hsotg->lock, flags); 4313 4314 return 0; 4315 } 4316 4317 /* 4318 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are 4319 * stopped. 4320 */ 4321 static void _dwc2_hcd_stop(struct usb_hcd *hcd) 4322 { 4323 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4324 unsigned long flags; 4325 u32 hprt0; 4326 4327 /* Turn off all host-specific interrupts */ 4328 dwc2_disable_host_interrupts(hsotg); 4329 4330 /* Wait for interrupt processing to finish */ 4331 synchronize_irq(hcd->irq); 4332 4333 spin_lock_irqsave(&hsotg->lock, flags); 4334 hprt0 = dwc2_read_hprt0(hsotg); 4335 /* Ensure hcd is disconnected */ 4336 dwc2_hcd_disconnect(hsotg, true); 4337 dwc2_hcd_stop(hsotg); 4338 hsotg->lx_state = DWC2_L3; 4339 hcd->state = HC_STATE_HALT; 4340 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4341 spin_unlock_irqrestore(&hsotg->lock, flags); 4342 4343 /* keep balanced supply init/exit by checking HPRT0_PWR */ 4344 if (hprt0 & HPRT0_PWR) 4345 dwc2_vbus_supply_exit(hsotg); 4346 4347 usleep_range(1000, 3000); 4348 } 4349 4350 static int _dwc2_hcd_suspend(struct usb_hcd *hcd) 4351 { 4352 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4353 unsigned long flags; 4354 int ret = 0; 4355 4356 spin_lock_irqsave(&hsotg->lock, flags); 4357 4358 if (dwc2_is_device_mode(hsotg)) 4359 goto unlock; 4360 4361 if (hsotg->lx_state != DWC2_L0) 4362 goto unlock; 4363 4364 if (!HCD_HW_ACCESSIBLE(hcd)) 4365 goto unlock; 4366 4367 if (hsotg->op_state == OTG_STATE_B_PERIPHERAL) 4368 goto unlock; 4369 4370 if (hsotg->bus_suspended) 4371 goto skip_power_saving; 4372 4373 if (hsotg->flags.b.port_connect_status == 0) 4374 goto skip_power_saving; 4375 4376 switch (hsotg->params.power_down) { 4377 case DWC2_POWER_DOWN_PARAM_PARTIAL: 4378 /* Enter partial_power_down */ 4379 ret = dwc2_enter_partial_power_down(hsotg); 4380 if (ret) 4381 dev_err(hsotg->dev, 4382 "enter partial_power_down failed\n"); 4383 /* After entering suspend, hardware is not accessible */ 4384 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4385 break; 4386 case DWC2_POWER_DOWN_PARAM_HIBERNATION: 4387 /* Enter hibernation */ 4388 spin_unlock_irqrestore(&hsotg->lock, flags); 4389 ret = dwc2_enter_hibernation(hsotg, 1); 4390 if (ret) 4391 dev_err(hsotg->dev, "enter hibernation failed\n"); 4392 spin_lock_irqsave(&hsotg->lock, flags); 4393 4394 /* After entering suspend, hardware is not accessible */ 4395 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4396 break; 4397 case DWC2_POWER_DOWN_PARAM_NONE: 4398 /* 4399 * If not hibernation nor partial power down are supported, 4400 * clock gating is used to save power. 4401 */ 4402 if (!hsotg->params.no_clock_gating) { 4403 dwc2_host_enter_clock_gating(hsotg); 4404 4405 /* After entering suspend, hardware is not accessible */ 4406 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4407 } 4408 break; 4409 default: 4410 goto skip_power_saving; 4411 } 4412 4413 spin_unlock_irqrestore(&hsotg->lock, flags); 4414 dwc2_vbus_supply_exit(hsotg); 4415 spin_lock_irqsave(&hsotg->lock, flags); 4416 4417 /* Ask phy to be suspended */ 4418 if (!IS_ERR_OR_NULL(hsotg->uphy)) { 4419 spin_unlock_irqrestore(&hsotg->lock, flags); 4420 usb_phy_set_suspend(hsotg->uphy, true); 4421 spin_lock_irqsave(&hsotg->lock, flags); 4422 } 4423 4424 skip_power_saving: 4425 hsotg->lx_state = DWC2_L2; 4426 unlock: 4427 spin_unlock_irqrestore(&hsotg->lock, flags); 4428 4429 return ret; 4430 } 4431 4432 static int _dwc2_hcd_resume(struct usb_hcd *hcd) 4433 { 4434 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4435 unsigned long flags; 4436 u32 hprt0; 4437 int ret = 0; 4438 4439 spin_lock_irqsave(&hsotg->lock, flags); 4440 4441 if (dwc2_is_device_mode(hsotg)) 4442 goto unlock; 4443 4444 if (hsotg->lx_state != DWC2_L2) 4445 goto unlock; 4446 4447 hprt0 = dwc2_read_hprt0(hsotg); 4448 4449 /* 4450 * Added port connection status checking which prevents exiting from 4451 * Partial Power Down mode from _dwc2_hcd_resume() if not in Partial 4452 * Power Down mode. 4453 */ 4454 if (hprt0 & HPRT0_CONNSTS) { 4455 hsotg->lx_state = DWC2_L0; 4456 goto unlock; 4457 } 4458 4459 switch (hsotg->params.power_down) { 4460 case DWC2_POWER_DOWN_PARAM_PARTIAL: 4461 ret = dwc2_exit_partial_power_down(hsotg, 0, true); 4462 if (ret) 4463 dev_err(hsotg->dev, 4464 "exit partial_power_down failed\n"); 4465 /* 4466 * Set HW accessible bit before powering on the controller 4467 * since an interrupt may rise. 4468 */ 4469 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4470 break; 4471 case DWC2_POWER_DOWN_PARAM_HIBERNATION: 4472 ret = dwc2_exit_hibernation(hsotg, 0, 0, 1); 4473 if (ret) 4474 dev_err(hsotg->dev, "exit hibernation failed.\n"); 4475 4476 /* 4477 * Set HW accessible bit before powering on the controller 4478 * since an interrupt may rise. 4479 */ 4480 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4481 break; 4482 case DWC2_POWER_DOWN_PARAM_NONE: 4483 /* 4484 * If not hibernation nor partial power down are supported, 4485 * port resume is done using the clock gating programming flow. 4486 */ 4487 spin_unlock_irqrestore(&hsotg->lock, flags); 4488 dwc2_host_exit_clock_gating(hsotg, 0); 4489 4490 /* 4491 * Initialize the Core for Host mode, as after system resume 4492 * the global interrupts are disabled. 4493 */ 4494 dwc2_core_init(hsotg, false); 4495 dwc2_enable_global_interrupts(hsotg); 4496 dwc2_hcd_reinit(hsotg); 4497 spin_lock_irqsave(&hsotg->lock, flags); 4498 4499 /* 4500 * Set HW accessible bit before powering on the controller 4501 * since an interrupt may rise. 4502 */ 4503 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4504 break; 4505 default: 4506 hsotg->lx_state = DWC2_L0; 4507 goto unlock; 4508 } 4509 4510 /* Change Root port status, as port status change occurred after resume.*/ 4511 hsotg->flags.b.port_suspend_change = 1; 4512 4513 /* 4514 * Enable power if not already done. 4515 * This must not be spinlocked since duration 4516 * of this call is unknown. 4517 */ 4518 if (!IS_ERR_OR_NULL(hsotg->uphy)) { 4519 spin_unlock_irqrestore(&hsotg->lock, flags); 4520 usb_phy_set_suspend(hsotg->uphy, false); 4521 spin_lock_irqsave(&hsotg->lock, flags); 4522 } 4523 4524 /* Enable external vbus supply after resuming the port. */ 4525 spin_unlock_irqrestore(&hsotg->lock, flags); 4526 dwc2_vbus_supply_init(hsotg); 4527 4528 /* Wait for controller to correctly update D+/D- level */ 4529 usleep_range(3000, 5000); 4530 spin_lock_irqsave(&hsotg->lock, flags); 4531 4532 /* 4533 * Clear Port Enable and Port Status changes. 4534 * Enable Port Power. 4535 */ 4536 dwc2_writel(hsotg, HPRT0_PWR | HPRT0_CONNDET | 4537 HPRT0_ENACHG, HPRT0); 4538 4539 /* Wait for controller to detect Port Connect */ 4540 spin_unlock_irqrestore(&hsotg->lock, flags); 4541 usleep_range(5000, 7000); 4542 spin_lock_irqsave(&hsotg->lock, flags); 4543 unlock: 4544 spin_unlock_irqrestore(&hsotg->lock, flags); 4545 4546 return ret; 4547 } 4548 4549 /* Returns the current frame number */ 4550 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd) 4551 { 4552 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4553 4554 return dwc2_hcd_get_frame_number(hsotg); 4555 } 4556 4557 static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb, 4558 char *fn_name) 4559 { 4560 #ifdef VERBOSE_DEBUG 4561 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4562 char *pipetype = NULL; 4563 char *speed = NULL; 4564 4565 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb); 4566 dev_vdbg(hsotg->dev, " Device address: %d\n", 4567 usb_pipedevice(urb->pipe)); 4568 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n", 4569 usb_pipeendpoint(urb->pipe), 4570 usb_pipein(urb->pipe) ? "IN" : "OUT"); 4571 4572 switch (usb_pipetype(urb->pipe)) { 4573 case PIPE_CONTROL: 4574 pipetype = "CONTROL"; 4575 break; 4576 case PIPE_BULK: 4577 pipetype = "BULK"; 4578 break; 4579 case PIPE_INTERRUPT: 4580 pipetype = "INTERRUPT"; 4581 break; 4582 case PIPE_ISOCHRONOUS: 4583 pipetype = "ISOCHRONOUS"; 4584 break; 4585 } 4586 4587 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype, 4588 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ? 4589 "IN" : "OUT"); 4590 4591 switch (urb->dev->speed) { 4592 case USB_SPEED_HIGH: 4593 speed = "HIGH"; 4594 break; 4595 case USB_SPEED_FULL: 4596 speed = "FULL"; 4597 break; 4598 case USB_SPEED_LOW: 4599 speed = "LOW"; 4600 break; 4601 default: 4602 speed = "UNKNOWN"; 4603 break; 4604 } 4605 4606 dev_vdbg(hsotg->dev, " Speed: %s\n", speed); 4607 dev_vdbg(hsotg->dev, " Max packet size: %d (%d mult)\n", 4608 usb_endpoint_maxp(&urb->ep->desc), 4609 usb_endpoint_maxp_mult(&urb->ep->desc)); 4610 4611 dev_vdbg(hsotg->dev, " Data buffer length: %d\n", 4612 urb->transfer_buffer_length); 4613 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n", 4614 urb->transfer_buffer, (unsigned long)urb->transfer_dma); 4615 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n", 4616 urb->setup_packet, (unsigned long)urb->setup_dma); 4617 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval); 4618 4619 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 4620 int i; 4621 4622 for (i = 0; i < urb->number_of_packets; i++) { 4623 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i); 4624 dev_vdbg(hsotg->dev, " offset: %d, length %d\n", 4625 urb->iso_frame_desc[i].offset, 4626 urb->iso_frame_desc[i].length); 4627 } 4628 } 4629 #endif 4630 } 4631 4632 /* 4633 * Starts processing a USB transfer request specified by a USB Request Block 4634 * (URB). mem_flags indicates the type of memory allocation to use while 4635 * processing this URB. 4636 */ 4637 static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, 4638 gfp_t mem_flags) 4639 { 4640 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4641 struct usb_host_endpoint *ep = urb->ep; 4642 struct dwc2_hcd_urb *dwc2_urb; 4643 int i; 4644 int retval; 4645 int alloc_bandwidth = 0; 4646 u8 ep_type = 0; 4647 u32 tflags = 0; 4648 void *buf; 4649 unsigned long flags; 4650 struct dwc2_qh *qh; 4651 bool qh_allocated = false; 4652 struct dwc2_qtd *qtd; 4653 struct dwc2_gregs_backup *gr; 4654 4655 gr = &hsotg->gr_backup; 4656 4657 if (dbg_urb(urb)) { 4658 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n"); 4659 dwc2_dump_urb_info(hcd, urb, "urb_enqueue"); 4660 } 4661 4662 if (hsotg->hibernated) { 4663 if (gr->gotgctl & GOTGCTL_CURMODE_HOST) 4664 retval = dwc2_exit_hibernation(hsotg, 0, 0, 1); 4665 else 4666 retval = dwc2_exit_hibernation(hsotg, 0, 0, 0); 4667 4668 if (retval) 4669 dev_err(hsotg->dev, 4670 "exit hibernation failed.\n"); 4671 } 4672 4673 if (hsotg->in_ppd) { 4674 retval = dwc2_exit_partial_power_down(hsotg, 0, true); 4675 if (retval) 4676 dev_err(hsotg->dev, 4677 "exit partial_power_down failed\n"); 4678 } 4679 4680 if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_NONE && 4681 hsotg->bus_suspended) { 4682 if (dwc2_is_device_mode(hsotg)) 4683 dwc2_gadget_exit_clock_gating(hsotg, 0); 4684 else 4685 dwc2_host_exit_clock_gating(hsotg, 0); 4686 } 4687 4688 if (!ep) 4689 return -EINVAL; 4690 4691 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || 4692 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { 4693 spin_lock_irqsave(&hsotg->lock, flags); 4694 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep)) 4695 alloc_bandwidth = 1; 4696 spin_unlock_irqrestore(&hsotg->lock, flags); 4697 } 4698 4699 switch (usb_pipetype(urb->pipe)) { 4700 case PIPE_CONTROL: 4701 ep_type = USB_ENDPOINT_XFER_CONTROL; 4702 break; 4703 case PIPE_ISOCHRONOUS: 4704 ep_type = USB_ENDPOINT_XFER_ISOC; 4705 break; 4706 case PIPE_BULK: 4707 ep_type = USB_ENDPOINT_XFER_BULK; 4708 break; 4709 case PIPE_INTERRUPT: 4710 ep_type = USB_ENDPOINT_XFER_INT; 4711 break; 4712 } 4713 4714 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets, 4715 mem_flags); 4716 if (!dwc2_urb) 4717 return -ENOMEM; 4718 4719 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe), 4720 usb_pipeendpoint(urb->pipe), ep_type, 4721 usb_pipein(urb->pipe), 4722 usb_endpoint_maxp(&ep->desc), 4723 usb_endpoint_maxp_mult(&ep->desc)); 4724 4725 buf = urb->transfer_buffer; 4726 4727 if (hcd_uses_dma(hcd)) { 4728 if (!buf && (urb->transfer_dma & 3)) { 4729 dev_err(hsotg->dev, 4730 "%s: unaligned transfer with no transfer_buffer", 4731 __func__); 4732 retval = -EINVAL; 4733 goto fail0; 4734 } 4735 } 4736 4737 if (!(urb->transfer_flags & URB_NO_INTERRUPT)) 4738 tflags |= URB_GIVEBACK_ASAP; 4739 if (urb->transfer_flags & URB_ZERO_PACKET) 4740 tflags |= URB_SEND_ZERO_PACKET; 4741 4742 dwc2_urb->priv = urb; 4743 dwc2_urb->buf = buf; 4744 dwc2_urb->dma = urb->transfer_dma; 4745 dwc2_urb->length = urb->transfer_buffer_length; 4746 dwc2_urb->setup_packet = urb->setup_packet; 4747 dwc2_urb->setup_dma = urb->setup_dma; 4748 dwc2_urb->flags = tflags; 4749 dwc2_urb->interval = urb->interval; 4750 dwc2_urb->status = -EINPROGRESS; 4751 4752 for (i = 0; i < urb->number_of_packets; ++i) 4753 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i, 4754 urb->iso_frame_desc[i].offset, 4755 urb->iso_frame_desc[i].length); 4756 4757 urb->hcpriv = dwc2_urb; 4758 qh = (struct dwc2_qh *)ep->hcpriv; 4759 /* Create QH for the endpoint if it doesn't exist */ 4760 if (!qh) { 4761 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags); 4762 if (!qh) { 4763 retval = -ENOMEM; 4764 goto fail0; 4765 } 4766 ep->hcpriv = qh; 4767 qh_allocated = true; 4768 } 4769 4770 qtd = kzalloc(sizeof(*qtd), mem_flags); 4771 if (!qtd) { 4772 retval = -ENOMEM; 4773 goto fail1; 4774 } 4775 4776 spin_lock_irqsave(&hsotg->lock, flags); 4777 retval = usb_hcd_link_urb_to_ep(hcd, urb); 4778 if (retval) 4779 goto fail2; 4780 4781 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd); 4782 if (retval) 4783 goto fail3; 4784 4785 if (alloc_bandwidth) { 4786 dwc2_allocate_bus_bandwidth(hcd, 4787 dwc2_hcd_get_ep_bandwidth(hsotg, ep), 4788 urb); 4789 } 4790 4791 spin_unlock_irqrestore(&hsotg->lock, flags); 4792 4793 return 0; 4794 4795 fail3: 4796 dwc2_urb->priv = NULL; 4797 usb_hcd_unlink_urb_from_ep(hcd, urb); 4798 if (qh_allocated && qh->channel && qh->channel->qh == qh) 4799 qh->channel->qh = NULL; 4800 fail2: 4801 spin_unlock_irqrestore(&hsotg->lock, flags); 4802 urb->hcpriv = NULL; 4803 kfree(qtd); 4804 fail1: 4805 if (qh_allocated) { 4806 struct dwc2_qtd *qtd2, *qtd2_tmp; 4807 4808 ep->hcpriv = NULL; 4809 dwc2_hcd_qh_unlink(hsotg, qh); 4810 /* Free each QTD in the QH's QTD list */ 4811 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list, 4812 qtd_list_entry) 4813 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh); 4814 dwc2_hcd_qh_free(hsotg, qh); 4815 } 4816 fail0: 4817 kfree(dwc2_urb); 4818 4819 return retval; 4820 } 4821 4822 /* 4823 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success. 4824 */ 4825 static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, 4826 int status) 4827 { 4828 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4829 int rc; 4830 unsigned long flags; 4831 4832 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n"); 4833 dwc2_dump_urb_info(hcd, urb, "urb_dequeue"); 4834 4835 spin_lock_irqsave(&hsotg->lock, flags); 4836 4837 rc = usb_hcd_check_unlink_urb(hcd, urb, status); 4838 if (rc) 4839 goto out; 4840 4841 if (!urb->hcpriv) { 4842 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n"); 4843 goto out; 4844 } 4845 4846 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv); 4847 4848 usb_hcd_unlink_urb_from_ep(hcd, urb); 4849 4850 kfree(urb->hcpriv); 4851 urb->hcpriv = NULL; 4852 4853 /* Higher layer software sets URB status */ 4854 spin_unlock(&hsotg->lock); 4855 usb_hcd_giveback_urb(hcd, urb, status); 4856 spin_lock(&hsotg->lock); 4857 4858 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n"); 4859 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status); 4860 out: 4861 spin_unlock_irqrestore(&hsotg->lock, flags); 4862 4863 return rc; 4864 } 4865 4866 /* 4867 * Frees resources in the DWC_otg controller related to a given endpoint. Also 4868 * clears state in the HCD related to the endpoint. Any URBs for the endpoint 4869 * must already be dequeued. 4870 */ 4871 static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd, 4872 struct usb_host_endpoint *ep) 4873 { 4874 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4875 4876 dev_dbg(hsotg->dev, 4877 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n", 4878 ep->desc.bEndpointAddress, ep->hcpriv); 4879 dwc2_hcd_endpoint_disable(hsotg, ep, 250); 4880 } 4881 4882 /* 4883 * Resets endpoint specific parameter values, in current version used to reset 4884 * the data toggle (as a WA). This function can be called from usb_clear_halt 4885 * routine. 4886 */ 4887 static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd, 4888 struct usb_host_endpoint *ep) 4889 { 4890 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4891 unsigned long flags; 4892 4893 dev_dbg(hsotg->dev, 4894 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n", 4895 ep->desc.bEndpointAddress); 4896 4897 spin_lock_irqsave(&hsotg->lock, flags); 4898 dwc2_hcd_endpoint_reset(hsotg, ep); 4899 spin_unlock_irqrestore(&hsotg->lock, flags); 4900 } 4901 4902 /* 4903 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if 4904 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid 4905 * interrupt. 4906 * 4907 * This function is called by the USB core when an interrupt occurs 4908 */ 4909 static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd) 4910 { 4911 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4912 4913 return dwc2_handle_hcd_intr(hsotg); 4914 } 4915 4916 /* 4917 * Creates Status Change bitmap for the root hub and root port. The bitmap is 4918 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1 4919 * is the status change indicator for the single root port. Returns 1 if either 4920 * change indicator is 1, otherwise returns 0. 4921 */ 4922 static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf) 4923 { 4924 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4925 4926 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1; 4927 return buf[0] != 0; 4928 } 4929 4930 /* Handles hub class-specific requests */ 4931 static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue, 4932 u16 windex, char *buf, u16 wlength) 4933 { 4934 int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq, 4935 wvalue, windex, buf, wlength); 4936 return retval; 4937 } 4938 4939 /* Handles hub TT buffer clear completions */ 4940 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd, 4941 struct usb_host_endpoint *ep) 4942 { 4943 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4944 struct dwc2_qh *qh; 4945 unsigned long flags; 4946 4947 qh = ep->hcpriv; 4948 if (!qh) 4949 return; 4950 4951 spin_lock_irqsave(&hsotg->lock, flags); 4952 qh->tt_buffer_dirty = 0; 4953 4954 if (hsotg->flags.b.port_connect_status) 4955 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL); 4956 4957 spin_unlock_irqrestore(&hsotg->lock, flags); 4958 } 4959 4960 /* 4961 * HPRT0_SPD_HIGH_SPEED: high speed 4962 * HPRT0_SPD_FULL_SPEED: full speed 4963 */ 4964 static void dwc2_change_bus_speed(struct usb_hcd *hcd, int speed) 4965 { 4966 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4967 4968 if (hsotg->params.speed == speed) 4969 return; 4970 4971 hsotg->params.speed = speed; 4972 queue_work(hsotg->wq_otg, &hsotg->wf_otg); 4973 } 4974 4975 static void dwc2_free_dev(struct usb_hcd *hcd, struct usb_device *udev) 4976 { 4977 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4978 4979 if (!hsotg->params.change_speed_quirk) 4980 return; 4981 4982 /* 4983 * On removal, set speed to default high-speed. 4984 */ 4985 if (udev->parent && udev->parent->speed > USB_SPEED_UNKNOWN && 4986 udev->parent->speed < USB_SPEED_HIGH) { 4987 dev_info(hsotg->dev, "Set speed to default high-speed\n"); 4988 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED); 4989 } 4990 } 4991 4992 static int dwc2_reset_device(struct usb_hcd *hcd, struct usb_device *udev) 4993 { 4994 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4995 4996 if (!hsotg->params.change_speed_quirk) 4997 return 0; 4998 4999 if (udev->speed == USB_SPEED_HIGH) { 5000 dev_info(hsotg->dev, "Set speed to high-speed\n"); 5001 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED); 5002 } else if ((udev->speed == USB_SPEED_FULL || 5003 udev->speed == USB_SPEED_LOW)) { 5004 /* 5005 * Change speed setting to full-speed if there's 5006 * a full-speed or low-speed device plugged in. 5007 */ 5008 dev_info(hsotg->dev, "Set speed to full-speed\n"); 5009 dwc2_change_bus_speed(hcd, HPRT0_SPD_FULL_SPEED); 5010 } 5011 5012 return 0; 5013 } 5014 5015 static struct hc_driver dwc2_hc_driver = { 5016 .description = "dwc2_hsotg", 5017 .product_desc = "DWC OTG Controller", 5018 .hcd_priv_size = sizeof(struct wrapper_priv_data), 5019 5020 .irq = _dwc2_hcd_irq, 5021 .flags = HCD_MEMORY | HCD_USB2 | HCD_BH, 5022 5023 .start = _dwc2_hcd_start, 5024 .stop = _dwc2_hcd_stop, 5025 .urb_enqueue = _dwc2_hcd_urb_enqueue, 5026 .urb_dequeue = _dwc2_hcd_urb_dequeue, 5027 .endpoint_disable = _dwc2_hcd_endpoint_disable, 5028 .endpoint_reset = _dwc2_hcd_endpoint_reset, 5029 .get_frame_number = _dwc2_hcd_get_frame_number, 5030 5031 .hub_status_data = _dwc2_hcd_hub_status_data, 5032 .hub_control = _dwc2_hcd_hub_control, 5033 .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete, 5034 5035 .bus_suspend = _dwc2_hcd_suspend, 5036 .bus_resume = _dwc2_hcd_resume, 5037 5038 .map_urb_for_dma = dwc2_map_urb_for_dma, 5039 .unmap_urb_for_dma = dwc2_unmap_urb_for_dma, 5040 }; 5041 5042 /* 5043 * Frees secondary storage associated with the dwc2_hsotg structure contained 5044 * in the struct usb_hcd field 5045 */ 5046 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg) 5047 { 5048 u32 ahbcfg; 5049 u32 dctl; 5050 int i; 5051 5052 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n"); 5053 5054 /* Free memory for QH/QTD lists */ 5055 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive); 5056 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_waiting); 5057 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active); 5058 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive); 5059 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready); 5060 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned); 5061 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued); 5062 5063 /* Free memory for the host channels */ 5064 for (i = 0; i < MAX_EPS_CHANNELS; i++) { 5065 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 5066 5067 if (chan) { 5068 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n", 5069 i, chan); 5070 hsotg->hc_ptr_array[i] = NULL; 5071 kfree(chan); 5072 } 5073 } 5074 5075 if (hsotg->params.host_dma) { 5076 if (hsotg->status_buf) { 5077 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE, 5078 hsotg->status_buf, 5079 hsotg->status_buf_dma); 5080 hsotg->status_buf = NULL; 5081 } 5082 } else { 5083 kfree(hsotg->status_buf); 5084 hsotg->status_buf = NULL; 5085 } 5086 5087 ahbcfg = dwc2_readl(hsotg, GAHBCFG); 5088 5089 /* Disable all interrupts */ 5090 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 5091 dwc2_writel(hsotg, ahbcfg, GAHBCFG); 5092 dwc2_writel(hsotg, 0, GINTMSK); 5093 5094 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) { 5095 dctl = dwc2_readl(hsotg, DCTL); 5096 dctl |= DCTL_SFTDISCON; 5097 dwc2_writel(hsotg, dctl, DCTL); 5098 } 5099 5100 if (hsotg->wq_otg) { 5101 if (!cancel_work_sync(&hsotg->wf_otg)) 5102 flush_workqueue(hsotg->wq_otg); 5103 destroy_workqueue(hsotg->wq_otg); 5104 } 5105 5106 cancel_work_sync(&hsotg->phy_reset_work); 5107 5108 del_timer(&hsotg->wkp_timer); 5109 } 5110 5111 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg) 5112 { 5113 /* Turn off all host-specific interrupts */ 5114 dwc2_disable_host_interrupts(hsotg); 5115 5116 dwc2_hcd_free(hsotg); 5117 } 5118 5119 /* 5120 * Initializes the HCD. This function allocates memory for and initializes the 5121 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the 5122 * USB bus with the core and calls the hc_driver->start() function. It returns 5123 * a negative error on failure. 5124 */ 5125 int dwc2_hcd_init(struct dwc2_hsotg *hsotg) 5126 { 5127 struct platform_device *pdev = to_platform_device(hsotg->dev); 5128 struct resource *res; 5129 struct usb_hcd *hcd; 5130 struct dwc2_host_chan *channel; 5131 u32 hcfg; 5132 int i, num_channels; 5133 int retval; 5134 5135 if (usb_disabled()) 5136 return -ENODEV; 5137 5138 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n"); 5139 5140 retval = -ENOMEM; 5141 5142 hcfg = dwc2_readl(hsotg, HCFG); 5143 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg); 5144 5145 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 5146 hsotg->frame_num_array = kcalloc(FRAME_NUM_ARRAY_SIZE, 5147 sizeof(*hsotg->frame_num_array), 5148 GFP_KERNEL); 5149 if (!hsotg->frame_num_array) 5150 goto error1; 5151 hsotg->last_frame_num_array = 5152 kcalloc(FRAME_NUM_ARRAY_SIZE, 5153 sizeof(*hsotg->last_frame_num_array), GFP_KERNEL); 5154 if (!hsotg->last_frame_num_array) 5155 goto error1; 5156 #endif 5157 hsotg->last_frame_num = HFNUM_MAX_FRNUM; 5158 5159 /* Check if the bus driver or platform code has setup a dma_mask */ 5160 if (hsotg->params.host_dma && 5161 !hsotg->dev->dma_mask) { 5162 dev_warn(hsotg->dev, 5163 "dma_mask not set, disabling DMA\n"); 5164 hsotg->params.host_dma = false; 5165 hsotg->params.dma_desc_enable = false; 5166 } 5167 5168 /* Set device flags indicating whether the HCD supports DMA */ 5169 if (hsotg->params.host_dma) { 5170 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) 5171 dev_warn(hsotg->dev, "can't set DMA mask\n"); 5172 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) 5173 dev_warn(hsotg->dev, "can't set coherent DMA mask\n"); 5174 } 5175 5176 if (hsotg->params.change_speed_quirk) { 5177 dwc2_hc_driver.free_dev = dwc2_free_dev; 5178 dwc2_hc_driver.reset_device = dwc2_reset_device; 5179 } 5180 5181 if (hsotg->params.host_dma) 5182 dwc2_hc_driver.flags |= HCD_DMA; 5183 5184 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev)); 5185 if (!hcd) 5186 goto error1; 5187 5188 hcd->has_tt = 1; 5189 5190 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 5191 if (!res) { 5192 retval = -EINVAL; 5193 goto error2; 5194 } 5195 hcd->rsrc_start = res->start; 5196 hcd->rsrc_len = resource_size(res); 5197 5198 ((struct wrapper_priv_data *)&hcd->hcd_priv)->hsotg = hsotg; 5199 hsotg->priv = hcd; 5200 5201 /* 5202 * Disable the global interrupt until all the interrupt handlers are 5203 * installed 5204 */ 5205 dwc2_disable_global_interrupts(hsotg); 5206 5207 /* Initialize the DWC_otg core, and select the Phy type */ 5208 retval = dwc2_core_init(hsotg, true); 5209 if (retval) 5210 goto error2; 5211 5212 /* Create new workqueue and init work */ 5213 retval = -ENOMEM; 5214 hsotg->wq_otg = alloc_ordered_workqueue("dwc2", 0); 5215 if (!hsotg->wq_otg) { 5216 dev_err(hsotg->dev, "Failed to create workqueue\n"); 5217 goto error2; 5218 } 5219 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change); 5220 5221 timer_setup(&hsotg->wkp_timer, dwc2_wakeup_detected, 0); 5222 5223 /* Initialize the non-periodic schedule */ 5224 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive); 5225 INIT_LIST_HEAD(&hsotg->non_periodic_sched_waiting); 5226 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active); 5227 5228 /* Initialize the periodic schedule */ 5229 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive); 5230 INIT_LIST_HEAD(&hsotg->periodic_sched_ready); 5231 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned); 5232 INIT_LIST_HEAD(&hsotg->periodic_sched_queued); 5233 5234 INIT_LIST_HEAD(&hsotg->split_order); 5235 5236 /* 5237 * Create a host channel descriptor for each host channel implemented 5238 * in the controller. Initialize the channel descriptor array. 5239 */ 5240 INIT_LIST_HEAD(&hsotg->free_hc_list); 5241 num_channels = hsotg->params.host_channels; 5242 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array)); 5243 5244 for (i = 0; i < num_channels; i++) { 5245 channel = kzalloc(sizeof(*channel), GFP_KERNEL); 5246 if (!channel) 5247 goto error3; 5248 channel->hc_num = i; 5249 INIT_LIST_HEAD(&channel->split_order_list_entry); 5250 hsotg->hc_ptr_array[i] = channel; 5251 } 5252 5253 /* Initialize work */ 5254 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func); 5255 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func); 5256 INIT_WORK(&hsotg->phy_reset_work, dwc2_hcd_phy_reset_func); 5257 5258 /* 5259 * Allocate space for storing data on status transactions. Normally no 5260 * data is sent, but this space acts as a bit bucket. This must be 5261 * done after usb_add_hcd since that function allocates the DMA buffer 5262 * pool. 5263 */ 5264 if (hsotg->params.host_dma) 5265 hsotg->status_buf = dma_alloc_coherent(hsotg->dev, 5266 DWC2_HCD_STATUS_BUF_SIZE, 5267 &hsotg->status_buf_dma, GFP_KERNEL); 5268 else 5269 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE, 5270 GFP_KERNEL); 5271 5272 if (!hsotg->status_buf) 5273 goto error3; 5274 5275 /* 5276 * Create kmem caches to handle descriptor buffers in descriptor 5277 * DMA mode. 5278 * Alignment must be set to 512 bytes. 5279 */ 5280 if (hsotg->params.dma_desc_enable || 5281 hsotg->params.dma_desc_fs_enable) { 5282 hsotg->desc_gen_cache = kmem_cache_create("dwc2-gen-desc", 5283 sizeof(struct dwc2_dma_desc) * 5284 MAX_DMA_DESC_NUM_GENERIC, 512, SLAB_CACHE_DMA, 5285 NULL); 5286 if (!hsotg->desc_gen_cache) { 5287 dev_err(hsotg->dev, 5288 "unable to create dwc2 generic desc cache\n"); 5289 5290 /* 5291 * Disable descriptor dma mode since it will not be 5292 * usable. 5293 */ 5294 hsotg->params.dma_desc_enable = false; 5295 hsotg->params.dma_desc_fs_enable = false; 5296 } 5297 5298 hsotg->desc_hsisoc_cache = kmem_cache_create("dwc2-hsisoc-desc", 5299 sizeof(struct dwc2_dma_desc) * 5300 MAX_DMA_DESC_NUM_HS_ISOC, 512, 0, NULL); 5301 if (!hsotg->desc_hsisoc_cache) { 5302 dev_err(hsotg->dev, 5303 "unable to create dwc2 hs isoc desc cache\n"); 5304 5305 kmem_cache_destroy(hsotg->desc_gen_cache); 5306 5307 /* 5308 * Disable descriptor dma mode since it will not be 5309 * usable. 5310 */ 5311 hsotg->params.dma_desc_enable = false; 5312 hsotg->params.dma_desc_fs_enable = false; 5313 } 5314 } 5315 5316 if (hsotg->params.host_dma) { 5317 /* 5318 * Create kmem caches to handle non-aligned buffer 5319 * in Buffer DMA mode. 5320 */ 5321 hsotg->unaligned_cache = kmem_cache_create("dwc2-unaligned-dma", 5322 DWC2_KMEM_UNALIGNED_BUF_SIZE, 4, 5323 SLAB_CACHE_DMA, NULL); 5324 if (!hsotg->unaligned_cache) 5325 dev_err(hsotg->dev, 5326 "unable to create dwc2 unaligned cache\n"); 5327 } 5328 5329 hsotg->otg_port = 1; 5330 hsotg->frame_list = NULL; 5331 hsotg->frame_list_dma = 0; 5332 hsotg->periodic_qh_count = 0; 5333 5334 /* Initiate lx_state to L3 disconnected state */ 5335 hsotg->lx_state = DWC2_L3; 5336 5337 hcd->self.otg_port = hsotg->otg_port; 5338 5339 /* Don't support SG list at this point */ 5340 hcd->self.sg_tablesize = 0; 5341 5342 if (!IS_ERR_OR_NULL(hsotg->uphy)) 5343 otg_set_host(hsotg->uphy->otg, &hcd->self); 5344 5345 /* 5346 * Finish generic HCD initialization and start the HCD. This function 5347 * allocates the DMA buffer pool, registers the USB bus, requests the 5348 * IRQ line, and calls hcd_start method. 5349 */ 5350 retval = usb_add_hcd(hcd, hsotg->irq, IRQF_SHARED); 5351 if (retval < 0) 5352 goto error4; 5353 5354 device_wakeup_enable(hcd->self.controller); 5355 5356 dwc2_hcd_dump_state(hsotg); 5357 5358 dwc2_enable_global_interrupts(hsotg); 5359 5360 return 0; 5361 5362 error4: 5363 kmem_cache_destroy(hsotg->unaligned_cache); 5364 kmem_cache_destroy(hsotg->desc_hsisoc_cache); 5365 kmem_cache_destroy(hsotg->desc_gen_cache); 5366 error3: 5367 dwc2_hcd_release(hsotg); 5368 error2: 5369 usb_put_hcd(hcd); 5370 error1: 5371 5372 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 5373 kfree(hsotg->last_frame_num_array); 5374 kfree(hsotg->frame_num_array); 5375 #endif 5376 5377 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval); 5378 return retval; 5379 } 5380 5381 /* 5382 * Removes the HCD. 5383 * Frees memory and resources associated with the HCD and deregisters the bus. 5384 */ 5385 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) 5386 { 5387 struct usb_hcd *hcd; 5388 5389 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n"); 5390 5391 hcd = dwc2_hsotg_to_hcd(hsotg); 5392 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd); 5393 5394 if (!hcd) { 5395 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n", 5396 __func__); 5397 return; 5398 } 5399 5400 if (!IS_ERR_OR_NULL(hsotg->uphy)) 5401 otg_set_host(hsotg->uphy->otg, NULL); 5402 5403 usb_remove_hcd(hcd); 5404 hsotg->priv = NULL; 5405 5406 kmem_cache_destroy(hsotg->unaligned_cache); 5407 kmem_cache_destroy(hsotg->desc_hsisoc_cache); 5408 kmem_cache_destroy(hsotg->desc_gen_cache); 5409 5410 dwc2_hcd_release(hsotg); 5411 usb_put_hcd(hcd); 5412 5413 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 5414 kfree(hsotg->last_frame_num_array); 5415 kfree(hsotg->frame_num_array); 5416 #endif 5417 } 5418 5419 /** 5420 * dwc2_backup_host_registers() - Backup controller host registers. 5421 * When suspending usb bus, registers needs to be backuped 5422 * if controller power is disabled once suspended. 5423 * 5424 * @hsotg: Programming view of the DWC_otg controller 5425 */ 5426 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) 5427 { 5428 struct dwc2_hregs_backup *hr; 5429 int i; 5430 5431 dev_dbg(hsotg->dev, "%s\n", __func__); 5432 5433 /* Backup Host regs */ 5434 hr = &hsotg->hr_backup; 5435 hr->hcfg = dwc2_readl(hsotg, HCFG); 5436 hr->haintmsk = dwc2_readl(hsotg, HAINTMSK); 5437 for (i = 0; i < hsotg->params.host_channels; ++i) 5438 hr->hcintmsk[i] = dwc2_readl(hsotg, HCINTMSK(i)); 5439 5440 hr->hprt0 = dwc2_read_hprt0(hsotg); 5441 hr->hfir = dwc2_readl(hsotg, HFIR); 5442 hr->hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ); 5443 hr->valid = true; 5444 5445 return 0; 5446 } 5447 5448 /** 5449 * dwc2_restore_host_registers() - Restore controller host registers. 5450 * When resuming usb bus, device registers needs to be restored 5451 * if controller power were disabled. 5452 * 5453 * @hsotg: Programming view of the DWC_otg controller 5454 */ 5455 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) 5456 { 5457 struct dwc2_hregs_backup *hr; 5458 int i; 5459 5460 dev_dbg(hsotg->dev, "%s\n", __func__); 5461 5462 /* Restore host regs */ 5463 hr = &hsotg->hr_backup; 5464 if (!hr->valid) { 5465 dev_err(hsotg->dev, "%s: no host registers to restore\n", 5466 __func__); 5467 return -EINVAL; 5468 } 5469 hr->valid = false; 5470 5471 dwc2_writel(hsotg, hr->hcfg, HCFG); 5472 dwc2_writel(hsotg, hr->haintmsk, HAINTMSK); 5473 5474 for (i = 0; i < hsotg->params.host_channels; ++i) 5475 dwc2_writel(hsotg, hr->hcintmsk[i], HCINTMSK(i)); 5476 5477 dwc2_writel(hsotg, hr->hprt0, HPRT0); 5478 dwc2_writel(hsotg, hr->hfir, HFIR); 5479 dwc2_writel(hsotg, hr->hptxfsiz, HPTXFSIZ); 5480 hsotg->frame_number = 0; 5481 5482 return 0; 5483 } 5484 5485 /** 5486 * dwc2_host_enter_hibernation() - Put controller in Hibernation. 5487 * 5488 * @hsotg: Programming view of the DWC_otg controller 5489 */ 5490 int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg) 5491 { 5492 unsigned long flags; 5493 int ret = 0; 5494 u32 hprt0; 5495 u32 pcgcctl; 5496 u32 gusbcfg; 5497 u32 gpwrdn; 5498 5499 dev_dbg(hsotg->dev, "Preparing host for hibernation\n"); 5500 ret = dwc2_backup_global_registers(hsotg); 5501 if (ret) { 5502 dev_err(hsotg->dev, "%s: failed to backup global registers\n", 5503 __func__); 5504 return ret; 5505 } 5506 ret = dwc2_backup_host_registers(hsotg); 5507 if (ret) { 5508 dev_err(hsotg->dev, "%s: failed to backup host registers\n", 5509 __func__); 5510 return ret; 5511 } 5512 5513 /* Enter USB Suspend Mode */ 5514 hprt0 = dwc2_readl(hsotg, HPRT0); 5515 hprt0 |= HPRT0_SUSP; 5516 hprt0 &= ~HPRT0_ENA; 5517 dwc2_writel(hsotg, hprt0, HPRT0); 5518 5519 /* Wait for the HPRT0.PrtSusp register field to be set */ 5520 if (dwc2_hsotg_wait_bit_set(hsotg, HPRT0, HPRT0_SUSP, 5000)) 5521 dev_warn(hsotg->dev, "Suspend wasn't generated\n"); 5522 5523 /* 5524 * We need to disable interrupts to prevent servicing of any IRQ 5525 * during going to hibernation 5526 */ 5527 spin_lock_irqsave(&hsotg->lock, flags); 5528 hsotg->lx_state = DWC2_L2; 5529 5530 gusbcfg = dwc2_readl(hsotg, GUSBCFG); 5531 if (gusbcfg & GUSBCFG_ULPI_UTMI_SEL) { 5532 /* ULPI interface */ 5533 /* Suspend the Phy Clock */ 5534 pcgcctl = dwc2_readl(hsotg, PCGCTL); 5535 pcgcctl |= PCGCTL_STOPPCLK; 5536 dwc2_writel(hsotg, pcgcctl, PCGCTL); 5537 udelay(10); 5538 5539 gpwrdn = dwc2_readl(hsotg, GPWRDN); 5540 gpwrdn |= GPWRDN_PMUACTV; 5541 dwc2_writel(hsotg, gpwrdn, GPWRDN); 5542 udelay(10); 5543 } else { 5544 /* UTMI+ Interface */ 5545 gpwrdn = dwc2_readl(hsotg, GPWRDN); 5546 gpwrdn |= GPWRDN_PMUACTV; 5547 dwc2_writel(hsotg, gpwrdn, GPWRDN); 5548 udelay(10); 5549 5550 pcgcctl = dwc2_readl(hsotg, PCGCTL); 5551 pcgcctl |= PCGCTL_STOPPCLK; 5552 dwc2_writel(hsotg, pcgcctl, PCGCTL); 5553 udelay(10); 5554 } 5555 5556 /* Enable interrupts from wake up logic */ 5557 gpwrdn = dwc2_readl(hsotg, GPWRDN); 5558 gpwrdn |= GPWRDN_PMUINTSEL; 5559 dwc2_writel(hsotg, gpwrdn, GPWRDN); 5560 udelay(10); 5561 5562 /* Unmask host mode interrupts in GPWRDN */ 5563 gpwrdn = dwc2_readl(hsotg, GPWRDN); 5564 gpwrdn |= GPWRDN_DISCONN_DET_MSK; 5565 gpwrdn |= GPWRDN_LNSTSCHG_MSK; 5566 gpwrdn |= GPWRDN_STS_CHGINT_MSK; 5567 dwc2_writel(hsotg, gpwrdn, GPWRDN); 5568 udelay(10); 5569 5570 /* Enable Power Down Clamp */ 5571 gpwrdn = dwc2_readl(hsotg, GPWRDN); 5572 gpwrdn |= GPWRDN_PWRDNCLMP; 5573 dwc2_writel(hsotg, gpwrdn, GPWRDN); 5574 udelay(10); 5575 5576 /* Switch off VDD */ 5577 gpwrdn = dwc2_readl(hsotg, GPWRDN); 5578 gpwrdn |= GPWRDN_PWRDNSWTCH; 5579 dwc2_writel(hsotg, gpwrdn, GPWRDN); 5580 5581 hsotg->hibernated = 1; 5582 hsotg->bus_suspended = 1; 5583 dev_dbg(hsotg->dev, "Host hibernation completed\n"); 5584 spin_unlock_irqrestore(&hsotg->lock, flags); 5585 return ret; 5586 } 5587 5588 /* 5589 * dwc2_host_exit_hibernation() 5590 * 5591 * @hsotg: Programming view of the DWC_otg controller 5592 * @rem_wakeup: indicates whether resume is initiated by Device or Host. 5593 * @param reset: indicates whether resume is initiated by Reset. 5594 * 5595 * Return: non-zero if failed to enter to hibernation. 5596 * 5597 * This function is for exiting from Host mode hibernation by 5598 * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup. 5599 */ 5600 int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup, 5601 int reset) 5602 { 5603 u32 gpwrdn; 5604 u32 hprt0; 5605 int ret = 0; 5606 struct dwc2_gregs_backup *gr; 5607 struct dwc2_hregs_backup *hr; 5608 5609 gr = &hsotg->gr_backup; 5610 hr = &hsotg->hr_backup; 5611 5612 dev_dbg(hsotg->dev, 5613 "%s: called with rem_wakeup = %d reset = %d\n", 5614 __func__, rem_wakeup, reset); 5615 5616 dwc2_hib_restore_common(hsotg, rem_wakeup, 1); 5617 hsotg->hibernated = 0; 5618 5619 /* 5620 * This step is not described in functional spec but if not wait for 5621 * this delay, mismatch interrupts occurred because just after restore 5622 * core is in Device mode(gintsts.curmode == 0) 5623 */ 5624 mdelay(100); 5625 5626 /* Clear all pending interupts */ 5627 dwc2_writel(hsotg, 0xffffffff, GINTSTS); 5628 5629 /* De-assert Restore */ 5630 gpwrdn = dwc2_readl(hsotg, GPWRDN); 5631 gpwrdn &= ~GPWRDN_RESTORE; 5632 dwc2_writel(hsotg, gpwrdn, GPWRDN); 5633 udelay(10); 5634 5635 /* Restore GUSBCFG, HCFG */ 5636 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG); 5637 dwc2_writel(hsotg, hr->hcfg, HCFG); 5638 5639 /* De-assert Wakeup Logic */ 5640 gpwrdn = dwc2_readl(hsotg, GPWRDN); 5641 gpwrdn &= ~GPWRDN_PMUACTV; 5642 dwc2_writel(hsotg, gpwrdn, GPWRDN); 5643 udelay(10); 5644 5645 hprt0 = hr->hprt0; 5646 hprt0 |= HPRT0_PWR; 5647 hprt0 &= ~HPRT0_ENA; 5648 hprt0 &= ~HPRT0_SUSP; 5649 dwc2_writel(hsotg, hprt0, HPRT0); 5650 5651 hprt0 = hr->hprt0; 5652 hprt0 |= HPRT0_PWR; 5653 hprt0 &= ~HPRT0_ENA; 5654 hprt0 &= ~HPRT0_SUSP; 5655 5656 if (reset) { 5657 hprt0 |= HPRT0_RST; 5658 dwc2_writel(hsotg, hprt0, HPRT0); 5659 5660 /* Wait for Resume time and then program HPRT again */ 5661 mdelay(60); 5662 hprt0 &= ~HPRT0_RST; 5663 dwc2_writel(hsotg, hprt0, HPRT0); 5664 } else { 5665 hprt0 |= HPRT0_RES; 5666 dwc2_writel(hsotg, hprt0, HPRT0); 5667 5668 /* Wait for Resume time and then program HPRT again */ 5669 mdelay(100); 5670 hprt0 &= ~HPRT0_RES; 5671 dwc2_writel(hsotg, hprt0, HPRT0); 5672 } 5673 /* Clear all interrupt status */ 5674 hprt0 = dwc2_readl(hsotg, HPRT0); 5675 hprt0 |= HPRT0_CONNDET; 5676 hprt0 |= HPRT0_ENACHG; 5677 hprt0 &= ~HPRT0_ENA; 5678 dwc2_writel(hsotg, hprt0, HPRT0); 5679 5680 hprt0 = dwc2_readl(hsotg, HPRT0); 5681 5682 /* Clear all pending interupts */ 5683 dwc2_writel(hsotg, 0xffffffff, GINTSTS); 5684 5685 /* Restore global registers */ 5686 ret = dwc2_restore_global_registers(hsotg); 5687 if (ret) { 5688 dev_err(hsotg->dev, "%s: failed to restore registers\n", 5689 __func__); 5690 return ret; 5691 } 5692 5693 /* Restore host registers */ 5694 ret = dwc2_restore_host_registers(hsotg); 5695 if (ret) { 5696 dev_err(hsotg->dev, "%s: failed to restore host registers\n", 5697 __func__); 5698 return ret; 5699 } 5700 5701 if (rem_wakeup) { 5702 dwc2_hcd_rem_wakeup(hsotg); 5703 /* 5704 * Change "port_connect_status_change" flag to re-enumerate, 5705 * because after exit from hibernation port connection status 5706 * is not detected. 5707 */ 5708 hsotg->flags.b.port_connect_status_change = 1; 5709 } 5710 5711 hsotg->hibernated = 0; 5712 hsotg->bus_suspended = 0; 5713 hsotg->lx_state = DWC2_L0; 5714 dev_dbg(hsotg->dev, "Host hibernation restore complete\n"); 5715 return ret; 5716 } 5717 5718 bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2) 5719 { 5720 struct usb_device *root_hub = dwc2_hsotg_to_hcd(dwc2)->self.root_hub; 5721 5722 /* If the controller isn't allowed to wakeup then we can power off. */ 5723 if (!device_may_wakeup(dwc2->dev)) 5724 return true; 5725 5726 /* 5727 * We don't want to power off the PHY if something under the 5728 * root hub has wakeup enabled. 5729 */ 5730 if (usb_wakeup_enabled_descendants(root_hub)) 5731 return false; 5732 5733 /* No reason to keep the PHY powered, so allow poweroff */ 5734 return true; 5735 } 5736 5737 /** 5738 * dwc2_host_enter_partial_power_down() - Put controller in partial 5739 * power down. 5740 * 5741 * @hsotg: Programming view of the DWC_otg controller 5742 * 5743 * Return: non-zero if failed to enter host partial power down. 5744 * 5745 * This function is for entering Host mode partial power down. 5746 */ 5747 int dwc2_host_enter_partial_power_down(struct dwc2_hsotg *hsotg) 5748 { 5749 u32 pcgcctl; 5750 u32 hprt0; 5751 int ret = 0; 5752 5753 dev_dbg(hsotg->dev, "Entering host partial power down started.\n"); 5754 5755 /* Put this port in suspend mode. */ 5756 hprt0 = dwc2_read_hprt0(hsotg); 5757 hprt0 |= HPRT0_SUSP; 5758 dwc2_writel(hsotg, hprt0, HPRT0); 5759 udelay(5); 5760 5761 /* Wait for the HPRT0.PrtSusp register field to be set */ 5762 if (dwc2_hsotg_wait_bit_set(hsotg, HPRT0, HPRT0_SUSP, 3000)) 5763 dev_warn(hsotg->dev, "Suspend wasn't generated\n"); 5764 5765 /* Backup all registers */ 5766 ret = dwc2_backup_global_registers(hsotg); 5767 if (ret) { 5768 dev_err(hsotg->dev, "%s: failed to backup global registers\n", 5769 __func__); 5770 return ret; 5771 } 5772 5773 ret = dwc2_backup_host_registers(hsotg); 5774 if (ret) { 5775 dev_err(hsotg->dev, "%s: failed to backup host registers\n", 5776 __func__); 5777 return ret; 5778 } 5779 5780 /* 5781 * Clear any pending interrupts since dwc2 will not be able to 5782 * clear them after entering partial_power_down. 5783 */ 5784 dwc2_writel(hsotg, 0xffffffff, GINTSTS); 5785 5786 /* Put the controller in low power state */ 5787 pcgcctl = dwc2_readl(hsotg, PCGCTL); 5788 5789 pcgcctl |= PCGCTL_PWRCLMP; 5790 dwc2_writel(hsotg, pcgcctl, PCGCTL); 5791 udelay(5); 5792 5793 pcgcctl |= PCGCTL_RSTPDWNMODULE; 5794 dwc2_writel(hsotg, pcgcctl, PCGCTL); 5795 udelay(5); 5796 5797 pcgcctl |= PCGCTL_STOPPCLK; 5798 dwc2_writel(hsotg, pcgcctl, PCGCTL); 5799 5800 /* Set in_ppd flag to 1 as here core enters suspend. */ 5801 hsotg->in_ppd = 1; 5802 hsotg->lx_state = DWC2_L2; 5803 hsotg->bus_suspended = true; 5804 5805 dev_dbg(hsotg->dev, "Entering host partial power down completed.\n"); 5806 5807 return ret; 5808 } 5809 5810 /* 5811 * dwc2_host_exit_partial_power_down() - Exit controller from host partial 5812 * power down. 5813 * 5814 * @hsotg: Programming view of the DWC_otg controller 5815 * @rem_wakeup: indicates whether resume is initiated by Reset. 5816 * @restore: indicates whether need to restore the registers or not. 5817 * 5818 * Return: non-zero if failed to exit host partial power down. 5819 * 5820 * This function is for exiting from Host mode partial power down. 5821 */ 5822 int dwc2_host_exit_partial_power_down(struct dwc2_hsotg *hsotg, 5823 int rem_wakeup, bool restore) 5824 { 5825 u32 pcgcctl; 5826 int ret = 0; 5827 u32 hprt0; 5828 5829 dev_dbg(hsotg->dev, "Exiting host partial power down started.\n"); 5830 5831 pcgcctl = dwc2_readl(hsotg, PCGCTL); 5832 pcgcctl &= ~PCGCTL_STOPPCLK; 5833 dwc2_writel(hsotg, pcgcctl, PCGCTL); 5834 udelay(5); 5835 5836 pcgcctl = dwc2_readl(hsotg, PCGCTL); 5837 pcgcctl &= ~PCGCTL_PWRCLMP; 5838 dwc2_writel(hsotg, pcgcctl, PCGCTL); 5839 udelay(5); 5840 5841 pcgcctl = dwc2_readl(hsotg, PCGCTL); 5842 pcgcctl &= ~PCGCTL_RSTPDWNMODULE; 5843 dwc2_writel(hsotg, pcgcctl, PCGCTL); 5844 5845 udelay(100); 5846 if (restore) { 5847 ret = dwc2_restore_global_registers(hsotg); 5848 if (ret) { 5849 dev_err(hsotg->dev, "%s: failed to restore registers\n", 5850 __func__); 5851 return ret; 5852 } 5853 5854 ret = dwc2_restore_host_registers(hsotg); 5855 if (ret) { 5856 dev_err(hsotg->dev, "%s: failed to restore host registers\n", 5857 __func__); 5858 return ret; 5859 } 5860 } 5861 5862 /* Drive resume signaling and exit suspend mode on the port. */ 5863 hprt0 = dwc2_read_hprt0(hsotg); 5864 hprt0 |= HPRT0_RES; 5865 hprt0 &= ~HPRT0_SUSP; 5866 dwc2_writel(hsotg, hprt0, HPRT0); 5867 udelay(5); 5868 5869 if (!rem_wakeup) { 5870 /* Stop driveing resume signaling on the port. */ 5871 hprt0 = dwc2_read_hprt0(hsotg); 5872 hprt0 &= ~HPRT0_RES; 5873 dwc2_writel(hsotg, hprt0, HPRT0); 5874 5875 hsotg->bus_suspended = false; 5876 } else { 5877 /* Turn on the port power bit. */ 5878 hprt0 = dwc2_read_hprt0(hsotg); 5879 hprt0 |= HPRT0_PWR; 5880 dwc2_writel(hsotg, hprt0, HPRT0); 5881 5882 /* Connect hcd. */ 5883 dwc2_hcd_connect(hsotg); 5884 5885 mod_timer(&hsotg->wkp_timer, 5886 jiffies + msecs_to_jiffies(71)); 5887 } 5888 5889 /* Set lx_state to and in_ppd to 0 as here core exits from suspend. */ 5890 hsotg->in_ppd = 0; 5891 hsotg->lx_state = DWC2_L0; 5892 5893 dev_dbg(hsotg->dev, "Exiting host partial power down completed.\n"); 5894 return ret; 5895 } 5896 5897 /** 5898 * dwc2_host_enter_clock_gating() - Put controller in clock gating. 5899 * 5900 * @hsotg: Programming view of the DWC_otg controller 5901 * 5902 * This function is for entering Host mode clock gating. 5903 */ 5904 void dwc2_host_enter_clock_gating(struct dwc2_hsotg *hsotg) 5905 { 5906 u32 hprt0; 5907 u32 pcgctl; 5908 5909 dev_dbg(hsotg->dev, "Entering host clock gating.\n"); 5910 5911 /* Put this port in suspend mode. */ 5912 hprt0 = dwc2_read_hprt0(hsotg); 5913 hprt0 |= HPRT0_SUSP; 5914 dwc2_writel(hsotg, hprt0, HPRT0); 5915 5916 /* Set the Phy Clock bit as suspend is received. */ 5917 pcgctl = dwc2_readl(hsotg, PCGCTL); 5918 pcgctl |= PCGCTL_STOPPCLK; 5919 dwc2_writel(hsotg, pcgctl, PCGCTL); 5920 udelay(5); 5921 5922 /* Set the Gate hclk as suspend is received. */ 5923 pcgctl = dwc2_readl(hsotg, PCGCTL); 5924 pcgctl |= PCGCTL_GATEHCLK; 5925 dwc2_writel(hsotg, pcgctl, PCGCTL); 5926 udelay(5); 5927 5928 hsotg->bus_suspended = true; 5929 hsotg->lx_state = DWC2_L2; 5930 } 5931 5932 /** 5933 * dwc2_host_exit_clock_gating() - Exit controller from clock gating. 5934 * 5935 * @hsotg: Programming view of the DWC_otg controller 5936 * @rem_wakeup: indicates whether resume is initiated by remote wakeup 5937 * 5938 * This function is for exiting Host mode clock gating. 5939 */ 5940 void dwc2_host_exit_clock_gating(struct dwc2_hsotg *hsotg, int rem_wakeup) 5941 { 5942 u32 hprt0; 5943 u32 pcgctl; 5944 5945 dev_dbg(hsotg->dev, "Exiting host clock gating.\n"); 5946 5947 /* Clear the Gate hclk. */ 5948 pcgctl = dwc2_readl(hsotg, PCGCTL); 5949 pcgctl &= ~PCGCTL_GATEHCLK; 5950 dwc2_writel(hsotg, pcgctl, PCGCTL); 5951 udelay(5); 5952 5953 /* Phy Clock bit. */ 5954 pcgctl = dwc2_readl(hsotg, PCGCTL); 5955 pcgctl &= ~PCGCTL_STOPPCLK; 5956 dwc2_writel(hsotg, pcgctl, PCGCTL); 5957 udelay(5); 5958 5959 /* Drive resume signaling and exit suspend mode on the port. */ 5960 hprt0 = dwc2_read_hprt0(hsotg); 5961 hprt0 |= HPRT0_RES; 5962 hprt0 &= ~HPRT0_SUSP; 5963 dwc2_writel(hsotg, hprt0, HPRT0); 5964 udelay(5); 5965 5966 if (!rem_wakeup) { 5967 /* In case of port resume need to wait for 40 ms */ 5968 msleep(USB_RESUME_TIMEOUT); 5969 5970 /* Stop driveing resume signaling on the port. */ 5971 hprt0 = dwc2_read_hprt0(hsotg); 5972 hprt0 &= ~HPRT0_RES; 5973 dwc2_writel(hsotg, hprt0, HPRT0); 5974 5975 hsotg->bus_suspended = false; 5976 hsotg->lx_state = DWC2_L0; 5977 } else { 5978 mod_timer(&hsotg->wkp_timer, 5979 jiffies + msecs_to_jiffies(71)); 5980 } 5981 } 5982