1197ba5f4SPaul Zimmerman /* 2197ba5f4SPaul Zimmerman * hcd.c - DesignWare HS OTG Controller host-mode routines 3197ba5f4SPaul Zimmerman * 4197ba5f4SPaul Zimmerman * Copyright (C) 2004-2013 Synopsys, Inc. 5197ba5f4SPaul Zimmerman * 6197ba5f4SPaul Zimmerman * Redistribution and use in source and binary forms, with or without 7197ba5f4SPaul Zimmerman * modification, are permitted provided that the following conditions 8197ba5f4SPaul Zimmerman * are met: 9197ba5f4SPaul Zimmerman * 1. Redistributions of source code must retain the above copyright 10197ba5f4SPaul Zimmerman * notice, this list of conditions, and the following disclaimer, 11197ba5f4SPaul Zimmerman * without modification. 12197ba5f4SPaul Zimmerman * 2. Redistributions in binary form must reproduce the above copyright 13197ba5f4SPaul Zimmerman * notice, this list of conditions and the following disclaimer in the 14197ba5f4SPaul Zimmerman * documentation and/or other materials provided with the distribution. 15197ba5f4SPaul Zimmerman * 3. The names of the above-listed copyright holders may not be used 16197ba5f4SPaul Zimmerman * to endorse or promote products derived from this software without 17197ba5f4SPaul Zimmerman * specific prior written permission. 18197ba5f4SPaul Zimmerman * 19197ba5f4SPaul Zimmerman * ALTERNATIVELY, this software may be distributed under the terms of the 20197ba5f4SPaul Zimmerman * GNU General Public License ("GPL") as published by the Free Software 21197ba5f4SPaul Zimmerman * Foundation; either version 2 of the License, or (at your option) any 22197ba5f4SPaul Zimmerman * later version. 23197ba5f4SPaul Zimmerman * 24197ba5f4SPaul Zimmerman * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25197ba5f4SPaul Zimmerman * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26197ba5f4SPaul Zimmerman * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27197ba5f4SPaul Zimmerman * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28197ba5f4SPaul Zimmerman * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29197ba5f4SPaul Zimmerman * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30197ba5f4SPaul Zimmerman * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31197ba5f4SPaul Zimmerman * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32197ba5f4SPaul Zimmerman * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33197ba5f4SPaul Zimmerman * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34197ba5f4SPaul Zimmerman * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35197ba5f4SPaul Zimmerman */ 36197ba5f4SPaul Zimmerman 37197ba5f4SPaul Zimmerman /* 38197ba5f4SPaul Zimmerman * This file contains the core HCD code, and implements the Linux hc_driver 39197ba5f4SPaul Zimmerman * API 40197ba5f4SPaul Zimmerman */ 41197ba5f4SPaul Zimmerman #include <linux/kernel.h> 42197ba5f4SPaul Zimmerman #include <linux/module.h> 43197ba5f4SPaul Zimmerman #include <linux/spinlock.h> 44197ba5f4SPaul Zimmerman #include <linux/interrupt.h> 45197ba5f4SPaul Zimmerman #include <linux/dma-mapping.h> 46197ba5f4SPaul Zimmerman #include <linux/delay.h> 47197ba5f4SPaul Zimmerman #include <linux/io.h> 48197ba5f4SPaul Zimmerman #include <linux/slab.h> 49197ba5f4SPaul Zimmerman #include <linux/usb.h> 50197ba5f4SPaul Zimmerman 51197ba5f4SPaul Zimmerman #include <linux/usb/hcd.h> 52197ba5f4SPaul Zimmerman #include <linux/usb/ch11.h> 53197ba5f4SPaul Zimmerman 54197ba5f4SPaul Zimmerman #include "core.h" 55197ba5f4SPaul Zimmerman #include "hcd.h" 56197ba5f4SPaul Zimmerman 57197ba5f4SPaul Zimmerman /** 58197ba5f4SPaul Zimmerman * dwc2_dump_channel_info() - Prints the state of a host channel 59197ba5f4SPaul Zimmerman * 60197ba5f4SPaul Zimmerman * @hsotg: Programming view of DWC_otg controller 61197ba5f4SPaul Zimmerman * @chan: Pointer to the channel to dump 62197ba5f4SPaul Zimmerman * 63197ba5f4SPaul Zimmerman * Must be called with interrupt disabled and spinlock held 64197ba5f4SPaul Zimmerman * 65197ba5f4SPaul Zimmerman * NOTE: This function will be removed once the peripheral controller code 66197ba5f4SPaul Zimmerman * is integrated and the driver is stable 67197ba5f4SPaul Zimmerman */ 68197ba5f4SPaul Zimmerman static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg, 69197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan) 70197ba5f4SPaul Zimmerman { 71197ba5f4SPaul Zimmerman #ifdef VERBOSE_DEBUG 72197ba5f4SPaul Zimmerman int num_channels = hsotg->core_params->host_channels; 73197ba5f4SPaul Zimmerman struct dwc2_qh *qh; 74197ba5f4SPaul Zimmerman u32 hcchar; 75197ba5f4SPaul Zimmerman u32 hcsplt; 76197ba5f4SPaul Zimmerman u32 hctsiz; 77197ba5f4SPaul Zimmerman u32 hc_dma; 78197ba5f4SPaul Zimmerman int i; 79197ba5f4SPaul Zimmerman 80197ba5f4SPaul Zimmerman if (chan == NULL) 81197ba5f4SPaul Zimmerman return; 82197ba5f4SPaul Zimmerman 83197ba5f4SPaul Zimmerman hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); 84197ba5f4SPaul Zimmerman hcsplt = readl(hsotg->regs + HCSPLT(chan->hc_num)); 85197ba5f4SPaul Zimmerman hctsiz = readl(hsotg->regs + HCTSIZ(chan->hc_num)); 86197ba5f4SPaul Zimmerman hc_dma = readl(hsotg->regs + HCDMA(chan->hc_num)); 87197ba5f4SPaul Zimmerman 88197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan); 89197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", 90197ba5f4SPaul Zimmerman hcchar, hcsplt); 91197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", 92197ba5f4SPaul Zimmerman hctsiz, hc_dma); 93197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 94197ba5f4SPaul Zimmerman chan->dev_addr, chan->ep_num, chan->ep_is_in); 95197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 96197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 97197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start); 98197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started); 99197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 100197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 101197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 102197ba5f4SPaul Zimmerman (unsigned long)chan->xfer_dma); 103197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 104197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 105197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " NP inactive sched:\n"); 106197ba5f4SPaul Zimmerman list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive, 107197ba5f4SPaul Zimmerman qh_list_entry) 108197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " %p\n", qh); 109197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " NP active sched:\n"); 110197ba5f4SPaul Zimmerman list_for_each_entry(qh, &hsotg->non_periodic_sched_active, 111197ba5f4SPaul Zimmerman qh_list_entry) 112197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " %p\n", qh); 113197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " Channels:\n"); 114197ba5f4SPaul Zimmerman for (i = 0; i < num_channels; i++) { 115197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 116197ba5f4SPaul Zimmerman 117197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " %2d: %p\n", i, chan); 118197ba5f4SPaul Zimmerman } 119197ba5f4SPaul Zimmerman #endif /* VERBOSE_DEBUG */ 120197ba5f4SPaul Zimmerman } 121197ba5f4SPaul Zimmerman 122197ba5f4SPaul Zimmerman /* 123197ba5f4SPaul Zimmerman * Processes all the URBs in a single list of QHs. Completes them with 124197ba5f4SPaul Zimmerman * -ETIMEDOUT and frees the QTD. 125197ba5f4SPaul Zimmerman * 126197ba5f4SPaul Zimmerman * Must be called with interrupt disabled and spinlock held 127197ba5f4SPaul Zimmerman */ 128197ba5f4SPaul Zimmerman static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg, 129197ba5f4SPaul Zimmerman struct list_head *qh_list) 130197ba5f4SPaul Zimmerman { 131197ba5f4SPaul Zimmerman struct dwc2_qh *qh, *qh_tmp; 132197ba5f4SPaul Zimmerman struct dwc2_qtd *qtd, *qtd_tmp; 133197ba5f4SPaul Zimmerman 134197ba5f4SPaul Zimmerman list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 135197ba5f4SPaul Zimmerman list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 136197ba5f4SPaul Zimmerman qtd_list_entry) { 137197ba5f4SPaul Zimmerman dwc2_host_complete(hsotg, qtd, -ETIMEDOUT); 138197ba5f4SPaul Zimmerman dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 139197ba5f4SPaul Zimmerman } 140197ba5f4SPaul Zimmerman } 141197ba5f4SPaul Zimmerman } 142197ba5f4SPaul Zimmerman 143197ba5f4SPaul Zimmerman static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg, 144197ba5f4SPaul Zimmerman struct list_head *qh_list) 145197ba5f4SPaul Zimmerman { 146197ba5f4SPaul Zimmerman struct dwc2_qtd *qtd, *qtd_tmp; 147197ba5f4SPaul Zimmerman struct dwc2_qh *qh, *qh_tmp; 148197ba5f4SPaul Zimmerman unsigned long flags; 149197ba5f4SPaul Zimmerman 150197ba5f4SPaul Zimmerman if (!qh_list->next) 151197ba5f4SPaul Zimmerman /* The list hasn't been initialized yet */ 152197ba5f4SPaul Zimmerman return; 153197ba5f4SPaul Zimmerman 154197ba5f4SPaul Zimmerman spin_lock_irqsave(&hsotg->lock, flags); 155197ba5f4SPaul Zimmerman 156197ba5f4SPaul Zimmerman /* Ensure there are no QTDs or URBs left */ 157197ba5f4SPaul Zimmerman dwc2_kill_urbs_in_qh_list(hsotg, qh_list); 158197ba5f4SPaul Zimmerman 159197ba5f4SPaul Zimmerman list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 160197ba5f4SPaul Zimmerman dwc2_hcd_qh_unlink(hsotg, qh); 161197ba5f4SPaul Zimmerman 162197ba5f4SPaul Zimmerman /* Free each QTD in the QH's QTD list */ 163197ba5f4SPaul Zimmerman list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 164197ba5f4SPaul Zimmerman qtd_list_entry) 165197ba5f4SPaul Zimmerman dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 166197ba5f4SPaul Zimmerman 167197ba5f4SPaul Zimmerman spin_unlock_irqrestore(&hsotg->lock, flags); 168197ba5f4SPaul Zimmerman dwc2_hcd_qh_free(hsotg, qh); 169197ba5f4SPaul Zimmerman spin_lock_irqsave(&hsotg->lock, flags); 170197ba5f4SPaul Zimmerman } 171197ba5f4SPaul Zimmerman 172197ba5f4SPaul Zimmerman spin_unlock_irqrestore(&hsotg->lock, flags); 173197ba5f4SPaul Zimmerman } 174197ba5f4SPaul Zimmerman 175197ba5f4SPaul Zimmerman /* 176197ba5f4SPaul Zimmerman * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic 177197ba5f4SPaul Zimmerman * and periodic schedules. The QTD associated with each URB is removed from 178197ba5f4SPaul Zimmerman * the schedule and freed. This function may be called when a disconnect is 179197ba5f4SPaul Zimmerman * detected or when the HCD is being stopped. 180197ba5f4SPaul Zimmerman * 181197ba5f4SPaul Zimmerman * Must be called with interrupt disabled and spinlock held 182197ba5f4SPaul Zimmerman */ 183197ba5f4SPaul Zimmerman static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg) 184197ba5f4SPaul Zimmerman { 185197ba5f4SPaul Zimmerman dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive); 186197ba5f4SPaul Zimmerman dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active); 187197ba5f4SPaul Zimmerman dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive); 188197ba5f4SPaul Zimmerman dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready); 189197ba5f4SPaul Zimmerman dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned); 190197ba5f4SPaul Zimmerman dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued); 191197ba5f4SPaul Zimmerman } 192197ba5f4SPaul Zimmerman 193197ba5f4SPaul Zimmerman /** 194197ba5f4SPaul Zimmerman * dwc2_hcd_start() - Starts the HCD when switching to Host mode 195197ba5f4SPaul Zimmerman * 196197ba5f4SPaul Zimmerman * @hsotg: Pointer to struct dwc2_hsotg 197197ba5f4SPaul Zimmerman */ 198197ba5f4SPaul Zimmerman void dwc2_hcd_start(struct dwc2_hsotg *hsotg) 199197ba5f4SPaul Zimmerman { 200197ba5f4SPaul Zimmerman u32 hprt0; 201197ba5f4SPaul Zimmerman 202197ba5f4SPaul Zimmerman if (hsotg->op_state == OTG_STATE_B_HOST) { 203197ba5f4SPaul Zimmerman /* 204197ba5f4SPaul Zimmerman * Reset the port. During a HNP mode switch the reset 205197ba5f4SPaul Zimmerman * needs to occur within 1ms and have a duration of at 206197ba5f4SPaul Zimmerman * least 50ms. 207197ba5f4SPaul Zimmerman */ 208197ba5f4SPaul Zimmerman hprt0 = dwc2_read_hprt0(hsotg); 209197ba5f4SPaul Zimmerman hprt0 |= HPRT0_RST; 210197ba5f4SPaul Zimmerman writel(hprt0, hsotg->regs + HPRT0); 211197ba5f4SPaul Zimmerman } 212197ba5f4SPaul Zimmerman 213197ba5f4SPaul Zimmerman queue_delayed_work(hsotg->wq_otg, &hsotg->start_work, 214197ba5f4SPaul Zimmerman msecs_to_jiffies(50)); 215197ba5f4SPaul Zimmerman } 216197ba5f4SPaul Zimmerman 217197ba5f4SPaul Zimmerman /* Must be called with interrupt disabled and spinlock held */ 218197ba5f4SPaul Zimmerman static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg) 219197ba5f4SPaul Zimmerman { 220197ba5f4SPaul Zimmerman int num_channels = hsotg->core_params->host_channels; 221197ba5f4SPaul Zimmerman struct dwc2_host_chan *channel; 222197ba5f4SPaul Zimmerman u32 hcchar; 223197ba5f4SPaul Zimmerman int i; 224197ba5f4SPaul Zimmerman 225197ba5f4SPaul Zimmerman if (hsotg->core_params->dma_enable <= 0) { 226197ba5f4SPaul Zimmerman /* Flush out any channel requests in slave mode */ 227197ba5f4SPaul Zimmerman for (i = 0; i < num_channels; i++) { 228197ba5f4SPaul Zimmerman channel = hsotg->hc_ptr_array[i]; 229197ba5f4SPaul Zimmerman if (!list_empty(&channel->hc_list_entry)) 230197ba5f4SPaul Zimmerman continue; 231197ba5f4SPaul Zimmerman hcchar = readl(hsotg->regs + HCCHAR(i)); 232197ba5f4SPaul Zimmerman if (hcchar & HCCHAR_CHENA) { 233197ba5f4SPaul Zimmerman hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR); 234197ba5f4SPaul Zimmerman hcchar |= HCCHAR_CHDIS; 235197ba5f4SPaul Zimmerman writel(hcchar, hsotg->regs + HCCHAR(i)); 236197ba5f4SPaul Zimmerman } 237197ba5f4SPaul Zimmerman } 238197ba5f4SPaul Zimmerman } 239197ba5f4SPaul Zimmerman 240197ba5f4SPaul Zimmerman for (i = 0; i < num_channels; i++) { 241197ba5f4SPaul Zimmerman channel = hsotg->hc_ptr_array[i]; 242197ba5f4SPaul Zimmerman if (!list_empty(&channel->hc_list_entry)) 243197ba5f4SPaul Zimmerman continue; 244197ba5f4SPaul Zimmerman hcchar = readl(hsotg->regs + HCCHAR(i)); 245197ba5f4SPaul Zimmerman if (hcchar & HCCHAR_CHENA) { 246197ba5f4SPaul Zimmerman /* Halt the channel */ 247197ba5f4SPaul Zimmerman hcchar |= HCCHAR_CHDIS; 248197ba5f4SPaul Zimmerman writel(hcchar, hsotg->regs + HCCHAR(i)); 249197ba5f4SPaul Zimmerman } 250197ba5f4SPaul Zimmerman 251197ba5f4SPaul Zimmerman dwc2_hc_cleanup(hsotg, channel); 252197ba5f4SPaul Zimmerman list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list); 253197ba5f4SPaul Zimmerman /* 254197ba5f4SPaul Zimmerman * Added for Descriptor DMA to prevent channel double cleanup in 255197ba5f4SPaul Zimmerman * release_channel_ddma(), which is called from ep_disable when 256197ba5f4SPaul Zimmerman * device disconnects 257197ba5f4SPaul Zimmerman */ 258197ba5f4SPaul Zimmerman channel->qh = NULL; 259197ba5f4SPaul Zimmerman } 260197ba5f4SPaul Zimmerman } 261197ba5f4SPaul Zimmerman 262197ba5f4SPaul Zimmerman /** 263197ba5f4SPaul Zimmerman * dwc2_hcd_disconnect() - Handles disconnect of the HCD 264197ba5f4SPaul Zimmerman * 265197ba5f4SPaul Zimmerman * @hsotg: Pointer to struct dwc2_hsotg 266197ba5f4SPaul Zimmerman * 267197ba5f4SPaul Zimmerman * Must be called with interrupt disabled and spinlock held 268197ba5f4SPaul Zimmerman */ 269197ba5f4SPaul Zimmerman void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg) 270197ba5f4SPaul Zimmerman { 271197ba5f4SPaul Zimmerman u32 intr; 272197ba5f4SPaul Zimmerman 273197ba5f4SPaul Zimmerman /* Set status flags for the hub driver */ 274197ba5f4SPaul Zimmerman hsotg->flags.b.port_connect_status_change = 1; 275197ba5f4SPaul Zimmerman hsotg->flags.b.port_connect_status = 0; 276197ba5f4SPaul Zimmerman 277197ba5f4SPaul Zimmerman /* 278197ba5f4SPaul Zimmerman * Shutdown any transfers in process by clearing the Tx FIFO Empty 279197ba5f4SPaul Zimmerman * interrupt mask and status bits and disabling subsequent host 280197ba5f4SPaul Zimmerman * channel interrupts. 281197ba5f4SPaul Zimmerman */ 282197ba5f4SPaul Zimmerman intr = readl(hsotg->regs + GINTMSK); 283197ba5f4SPaul Zimmerman intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT); 284197ba5f4SPaul Zimmerman writel(intr, hsotg->regs + GINTMSK); 285197ba5f4SPaul Zimmerman intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT; 286197ba5f4SPaul Zimmerman writel(intr, hsotg->regs + GINTSTS); 287197ba5f4SPaul Zimmerman 288197ba5f4SPaul Zimmerman /* 289197ba5f4SPaul Zimmerman * Turn off the vbus power only if the core has transitioned to device 290197ba5f4SPaul Zimmerman * mode. If still in host mode, need to keep power on to detect a 291197ba5f4SPaul Zimmerman * reconnection. 292197ba5f4SPaul Zimmerman */ 293197ba5f4SPaul Zimmerman if (dwc2_is_device_mode(hsotg)) { 294197ba5f4SPaul Zimmerman if (hsotg->op_state != OTG_STATE_A_SUSPEND) { 295197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "Disconnect: PortPower off\n"); 296197ba5f4SPaul Zimmerman writel(0, hsotg->regs + HPRT0); 297197ba5f4SPaul Zimmerman } 298197ba5f4SPaul Zimmerman 299197ba5f4SPaul Zimmerman dwc2_disable_host_interrupts(hsotg); 300197ba5f4SPaul Zimmerman } 301197ba5f4SPaul Zimmerman 302197ba5f4SPaul Zimmerman /* Respond with an error status to all URBs in the schedule */ 303197ba5f4SPaul Zimmerman dwc2_kill_all_urbs(hsotg); 304197ba5f4SPaul Zimmerman 305197ba5f4SPaul Zimmerman if (dwc2_is_host_mode(hsotg)) 306197ba5f4SPaul Zimmerman /* Clean up any host channels that were in use */ 307197ba5f4SPaul Zimmerman dwc2_hcd_cleanup_channels(hsotg); 308197ba5f4SPaul Zimmerman 309197ba5f4SPaul Zimmerman dwc2_host_disconnect(hsotg); 310197ba5f4SPaul Zimmerman } 311197ba5f4SPaul Zimmerman 312197ba5f4SPaul Zimmerman /** 313197ba5f4SPaul Zimmerman * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup 314197ba5f4SPaul Zimmerman * 315197ba5f4SPaul Zimmerman * @hsotg: Pointer to struct dwc2_hsotg 316197ba5f4SPaul Zimmerman */ 317197ba5f4SPaul Zimmerman static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg) 318197ba5f4SPaul Zimmerman { 319197ba5f4SPaul Zimmerman if (hsotg->lx_state == DWC2_L2) 320197ba5f4SPaul Zimmerman hsotg->flags.b.port_suspend_change = 1; 321197ba5f4SPaul Zimmerman else 322197ba5f4SPaul Zimmerman hsotg->flags.b.port_l1_change = 1; 323197ba5f4SPaul Zimmerman } 324197ba5f4SPaul Zimmerman 325197ba5f4SPaul Zimmerman /** 326197ba5f4SPaul Zimmerman * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner 327197ba5f4SPaul Zimmerman * 328197ba5f4SPaul Zimmerman * @hsotg: Pointer to struct dwc2_hsotg 329197ba5f4SPaul Zimmerman * 330197ba5f4SPaul Zimmerman * Must be called with interrupt disabled and spinlock held 331197ba5f4SPaul Zimmerman */ 332197ba5f4SPaul Zimmerman void dwc2_hcd_stop(struct dwc2_hsotg *hsotg) 333197ba5f4SPaul Zimmerman { 334197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n"); 335197ba5f4SPaul Zimmerman 336197ba5f4SPaul Zimmerman /* 337197ba5f4SPaul Zimmerman * The root hub should be disconnected before this function is called. 338197ba5f4SPaul Zimmerman * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue) 339197ba5f4SPaul Zimmerman * and the QH lists (via ..._hcd_endpoint_disable). 340197ba5f4SPaul Zimmerman */ 341197ba5f4SPaul Zimmerman 342197ba5f4SPaul Zimmerman /* Turn off all host-specific interrupts */ 343197ba5f4SPaul Zimmerman dwc2_disable_host_interrupts(hsotg); 344197ba5f4SPaul Zimmerman 345197ba5f4SPaul Zimmerman /* Turn off the vbus power */ 346197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "PortPower off\n"); 347197ba5f4SPaul Zimmerman writel(0, hsotg->regs + HPRT0); 348197ba5f4SPaul Zimmerman } 349197ba5f4SPaul Zimmerman 350197ba5f4SPaul Zimmerman static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, 351197ba5f4SPaul Zimmerman struct dwc2_hcd_urb *urb, void **ep_handle, 352197ba5f4SPaul Zimmerman gfp_t mem_flags) 353197ba5f4SPaul Zimmerman { 354197ba5f4SPaul Zimmerman struct dwc2_qtd *qtd; 355197ba5f4SPaul Zimmerman unsigned long flags; 356197ba5f4SPaul Zimmerman u32 intr_mask; 357197ba5f4SPaul Zimmerman int retval; 358197ba5f4SPaul Zimmerman int dev_speed; 359197ba5f4SPaul Zimmerman 360197ba5f4SPaul Zimmerman if (!hsotg->flags.b.port_connect_status) { 361197ba5f4SPaul Zimmerman /* No longer connected */ 362197ba5f4SPaul Zimmerman dev_err(hsotg->dev, "Not connected\n"); 363197ba5f4SPaul Zimmerman return -ENODEV; 364197ba5f4SPaul Zimmerman } 365197ba5f4SPaul Zimmerman 366197ba5f4SPaul Zimmerman dev_speed = dwc2_host_get_speed(hsotg, urb->priv); 367197ba5f4SPaul Zimmerman 368197ba5f4SPaul Zimmerman /* Some configurations cannot support LS traffic on a FS root port */ 369197ba5f4SPaul Zimmerman if ((dev_speed == USB_SPEED_LOW) && 370197ba5f4SPaul Zimmerman (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) && 371197ba5f4SPaul Zimmerman (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) { 372197ba5f4SPaul Zimmerman u32 hprt0 = readl(hsotg->regs + HPRT0); 373197ba5f4SPaul Zimmerman u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 374197ba5f4SPaul Zimmerman 375197ba5f4SPaul Zimmerman if (prtspd == HPRT0_SPD_FULL_SPEED) 376197ba5f4SPaul Zimmerman return -ENODEV; 377197ba5f4SPaul Zimmerman } 378197ba5f4SPaul Zimmerman 379197ba5f4SPaul Zimmerman qtd = kzalloc(sizeof(*qtd), mem_flags); 380197ba5f4SPaul Zimmerman if (!qtd) 381197ba5f4SPaul Zimmerman return -ENOMEM; 382197ba5f4SPaul Zimmerman 383197ba5f4SPaul Zimmerman dwc2_hcd_qtd_init(qtd, urb); 384197ba5f4SPaul Zimmerman retval = dwc2_hcd_qtd_add(hsotg, qtd, (struct dwc2_qh **)ep_handle, 385197ba5f4SPaul Zimmerman mem_flags); 386197ba5f4SPaul Zimmerman if (retval) { 387197ba5f4SPaul Zimmerman dev_err(hsotg->dev, 388197ba5f4SPaul Zimmerman "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n", 389197ba5f4SPaul Zimmerman retval); 390197ba5f4SPaul Zimmerman kfree(qtd); 391197ba5f4SPaul Zimmerman return retval; 392197ba5f4SPaul Zimmerman } 393197ba5f4SPaul Zimmerman 394197ba5f4SPaul Zimmerman intr_mask = readl(hsotg->regs + GINTMSK); 395197ba5f4SPaul Zimmerman if (!(intr_mask & GINTSTS_SOF)) { 396197ba5f4SPaul Zimmerman enum dwc2_transaction_type tr_type; 397197ba5f4SPaul Zimmerman 398197ba5f4SPaul Zimmerman if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK && 399197ba5f4SPaul Zimmerman !(qtd->urb->flags & URB_GIVEBACK_ASAP)) 400197ba5f4SPaul Zimmerman /* 401197ba5f4SPaul Zimmerman * Do not schedule SG transactions until qtd has 402197ba5f4SPaul Zimmerman * URB_GIVEBACK_ASAP set 403197ba5f4SPaul Zimmerman */ 404197ba5f4SPaul Zimmerman return 0; 405197ba5f4SPaul Zimmerman 406197ba5f4SPaul Zimmerman spin_lock_irqsave(&hsotg->lock, flags); 407197ba5f4SPaul Zimmerman tr_type = dwc2_hcd_select_transactions(hsotg); 408197ba5f4SPaul Zimmerman if (tr_type != DWC2_TRANSACTION_NONE) 409197ba5f4SPaul Zimmerman dwc2_hcd_queue_transactions(hsotg, tr_type); 410197ba5f4SPaul Zimmerman spin_unlock_irqrestore(&hsotg->lock, flags); 411197ba5f4SPaul Zimmerman } 412197ba5f4SPaul Zimmerman 413197ba5f4SPaul Zimmerman return 0; 414197ba5f4SPaul Zimmerman } 415197ba5f4SPaul Zimmerman 416197ba5f4SPaul Zimmerman /* Must be called with interrupt disabled and spinlock held */ 417197ba5f4SPaul Zimmerman static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg, 418197ba5f4SPaul Zimmerman struct dwc2_hcd_urb *urb) 419197ba5f4SPaul Zimmerman { 420197ba5f4SPaul Zimmerman struct dwc2_qh *qh; 421197ba5f4SPaul Zimmerman struct dwc2_qtd *urb_qtd; 422197ba5f4SPaul Zimmerman 423197ba5f4SPaul Zimmerman urb_qtd = urb->qtd; 424197ba5f4SPaul Zimmerman if (!urb_qtd) { 425197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n"); 426197ba5f4SPaul Zimmerman return -EINVAL; 427197ba5f4SPaul Zimmerman } 428197ba5f4SPaul Zimmerman 429197ba5f4SPaul Zimmerman qh = urb_qtd->qh; 430197ba5f4SPaul Zimmerman if (!qh) { 431197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n"); 432197ba5f4SPaul Zimmerman return -EINVAL; 433197ba5f4SPaul Zimmerman } 434197ba5f4SPaul Zimmerman 435197ba5f4SPaul Zimmerman urb->priv = NULL; 436197ba5f4SPaul Zimmerman 437197ba5f4SPaul Zimmerman if (urb_qtd->in_process && qh->channel) { 438197ba5f4SPaul Zimmerman dwc2_dump_channel_info(hsotg, qh->channel); 439197ba5f4SPaul Zimmerman 440197ba5f4SPaul Zimmerman /* The QTD is in process (it has been assigned to a channel) */ 441197ba5f4SPaul Zimmerman if (hsotg->flags.b.port_connect_status) 442197ba5f4SPaul Zimmerman /* 443197ba5f4SPaul Zimmerman * If still connected (i.e. in host mode), halt the 444197ba5f4SPaul Zimmerman * channel so it can be used for other transfers. If 445197ba5f4SPaul Zimmerman * no longer connected, the host registers can't be 446197ba5f4SPaul Zimmerman * written to halt the channel since the core is in 447197ba5f4SPaul Zimmerman * device mode. 448197ba5f4SPaul Zimmerman */ 449197ba5f4SPaul Zimmerman dwc2_hc_halt(hsotg, qh->channel, 450197ba5f4SPaul Zimmerman DWC2_HC_XFER_URB_DEQUEUE); 451197ba5f4SPaul Zimmerman } 452197ba5f4SPaul Zimmerman 453197ba5f4SPaul Zimmerman /* 454197ba5f4SPaul Zimmerman * Free the QTD and clean up the associated QH. Leave the QH in the 455197ba5f4SPaul Zimmerman * schedule if it has any remaining QTDs. 456197ba5f4SPaul Zimmerman */ 457197ba5f4SPaul Zimmerman if (hsotg->core_params->dma_desc_enable <= 0) { 458197ba5f4SPaul Zimmerman u8 in_process = urb_qtd->in_process; 459197ba5f4SPaul Zimmerman 460197ba5f4SPaul Zimmerman dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 461197ba5f4SPaul Zimmerman if (in_process) { 462197ba5f4SPaul Zimmerman dwc2_hcd_qh_deactivate(hsotg, qh, 0); 463197ba5f4SPaul Zimmerman qh->channel = NULL; 464197ba5f4SPaul Zimmerman } else if (list_empty(&qh->qtd_list)) { 465197ba5f4SPaul Zimmerman dwc2_hcd_qh_unlink(hsotg, qh); 466197ba5f4SPaul Zimmerman } 467197ba5f4SPaul Zimmerman } else { 468197ba5f4SPaul Zimmerman dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 469197ba5f4SPaul Zimmerman } 470197ba5f4SPaul Zimmerman 471197ba5f4SPaul Zimmerman return 0; 472197ba5f4SPaul Zimmerman } 473197ba5f4SPaul Zimmerman 474197ba5f4SPaul Zimmerman /* Must NOT be called with interrupt disabled or spinlock held */ 475197ba5f4SPaul Zimmerman static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg, 476197ba5f4SPaul Zimmerman struct usb_host_endpoint *ep, int retry) 477197ba5f4SPaul Zimmerman { 478197ba5f4SPaul Zimmerman struct dwc2_qtd *qtd, *qtd_tmp; 479197ba5f4SPaul Zimmerman struct dwc2_qh *qh; 480197ba5f4SPaul Zimmerman unsigned long flags; 481197ba5f4SPaul Zimmerman int rc; 482197ba5f4SPaul Zimmerman 483197ba5f4SPaul Zimmerman spin_lock_irqsave(&hsotg->lock, flags); 484197ba5f4SPaul Zimmerman 485197ba5f4SPaul Zimmerman qh = ep->hcpriv; 486197ba5f4SPaul Zimmerman if (!qh) { 487197ba5f4SPaul Zimmerman rc = -EINVAL; 488197ba5f4SPaul Zimmerman goto err; 489197ba5f4SPaul Zimmerman } 490197ba5f4SPaul Zimmerman 491197ba5f4SPaul Zimmerman while (!list_empty(&qh->qtd_list) && retry--) { 492197ba5f4SPaul Zimmerman if (retry == 0) { 493197ba5f4SPaul Zimmerman dev_err(hsotg->dev, 494197ba5f4SPaul Zimmerman "## timeout in dwc2_hcd_endpoint_disable() ##\n"); 495197ba5f4SPaul Zimmerman rc = -EBUSY; 496197ba5f4SPaul Zimmerman goto err; 497197ba5f4SPaul Zimmerman } 498197ba5f4SPaul Zimmerman 499197ba5f4SPaul Zimmerman spin_unlock_irqrestore(&hsotg->lock, flags); 500197ba5f4SPaul Zimmerman usleep_range(20000, 40000); 501197ba5f4SPaul Zimmerman spin_lock_irqsave(&hsotg->lock, flags); 502197ba5f4SPaul Zimmerman qh = ep->hcpriv; 503197ba5f4SPaul Zimmerman if (!qh) { 504197ba5f4SPaul Zimmerman rc = -EINVAL; 505197ba5f4SPaul Zimmerman goto err; 506197ba5f4SPaul Zimmerman } 507197ba5f4SPaul Zimmerman } 508197ba5f4SPaul Zimmerman 509197ba5f4SPaul Zimmerman dwc2_hcd_qh_unlink(hsotg, qh); 510197ba5f4SPaul Zimmerman 511197ba5f4SPaul Zimmerman /* Free each QTD in the QH's QTD list */ 512197ba5f4SPaul Zimmerman list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) 513197ba5f4SPaul Zimmerman dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 514197ba5f4SPaul Zimmerman 515197ba5f4SPaul Zimmerman ep->hcpriv = NULL; 516197ba5f4SPaul Zimmerman spin_unlock_irqrestore(&hsotg->lock, flags); 517197ba5f4SPaul Zimmerman dwc2_hcd_qh_free(hsotg, qh); 518197ba5f4SPaul Zimmerman 519197ba5f4SPaul Zimmerman return 0; 520197ba5f4SPaul Zimmerman 521197ba5f4SPaul Zimmerman err: 522197ba5f4SPaul Zimmerman ep->hcpriv = NULL; 523197ba5f4SPaul Zimmerman spin_unlock_irqrestore(&hsotg->lock, flags); 524197ba5f4SPaul Zimmerman 525197ba5f4SPaul Zimmerman return rc; 526197ba5f4SPaul Zimmerman } 527197ba5f4SPaul Zimmerman 528197ba5f4SPaul Zimmerman /* Must be called with interrupt disabled and spinlock held */ 529197ba5f4SPaul Zimmerman static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg, 530197ba5f4SPaul Zimmerman struct usb_host_endpoint *ep) 531197ba5f4SPaul Zimmerman { 532197ba5f4SPaul Zimmerman struct dwc2_qh *qh = ep->hcpriv; 533197ba5f4SPaul Zimmerman 534197ba5f4SPaul Zimmerman if (!qh) 535197ba5f4SPaul Zimmerman return -EINVAL; 536197ba5f4SPaul Zimmerman 537197ba5f4SPaul Zimmerman qh->data_toggle = DWC2_HC_PID_DATA0; 538197ba5f4SPaul Zimmerman 539197ba5f4SPaul Zimmerman return 0; 540197ba5f4SPaul Zimmerman } 541197ba5f4SPaul Zimmerman 542197ba5f4SPaul Zimmerman /* 543197ba5f4SPaul Zimmerman * Initializes dynamic portions of the DWC_otg HCD state 544197ba5f4SPaul Zimmerman * 545197ba5f4SPaul Zimmerman * Must be called with interrupt disabled and spinlock held 546197ba5f4SPaul Zimmerman */ 547197ba5f4SPaul Zimmerman static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg) 548197ba5f4SPaul Zimmerman { 549197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan, *chan_tmp; 550197ba5f4SPaul Zimmerman int num_channels; 551197ba5f4SPaul Zimmerman int i; 552197ba5f4SPaul Zimmerman 553197ba5f4SPaul Zimmerman hsotg->flags.d32 = 0; 554197ba5f4SPaul Zimmerman hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active; 555197ba5f4SPaul Zimmerman 556197ba5f4SPaul Zimmerman if (hsotg->core_params->uframe_sched > 0) { 557197ba5f4SPaul Zimmerman hsotg->available_host_channels = 558197ba5f4SPaul Zimmerman hsotg->core_params->host_channels; 559197ba5f4SPaul Zimmerman } else { 560197ba5f4SPaul Zimmerman hsotg->non_periodic_channels = 0; 561197ba5f4SPaul Zimmerman hsotg->periodic_channels = 0; 562197ba5f4SPaul Zimmerman } 563197ba5f4SPaul Zimmerman 564197ba5f4SPaul Zimmerman /* 565197ba5f4SPaul Zimmerman * Put all channels in the free channel list and clean up channel 566197ba5f4SPaul Zimmerman * states 567197ba5f4SPaul Zimmerman */ 568197ba5f4SPaul Zimmerman list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list, 569197ba5f4SPaul Zimmerman hc_list_entry) 570197ba5f4SPaul Zimmerman list_del_init(&chan->hc_list_entry); 571197ba5f4SPaul Zimmerman 572197ba5f4SPaul Zimmerman num_channels = hsotg->core_params->host_channels; 573197ba5f4SPaul Zimmerman for (i = 0; i < num_channels; i++) { 574197ba5f4SPaul Zimmerman chan = hsotg->hc_ptr_array[i]; 575197ba5f4SPaul Zimmerman list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list); 576197ba5f4SPaul Zimmerman dwc2_hc_cleanup(hsotg, chan); 577197ba5f4SPaul Zimmerman } 578197ba5f4SPaul Zimmerman 579197ba5f4SPaul Zimmerman /* Initialize the DWC core for host mode operation */ 580197ba5f4SPaul Zimmerman dwc2_core_host_init(hsotg); 581197ba5f4SPaul Zimmerman } 582197ba5f4SPaul Zimmerman 583197ba5f4SPaul Zimmerman static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg, 584197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan, 585197ba5f4SPaul Zimmerman struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 586197ba5f4SPaul Zimmerman { 587197ba5f4SPaul Zimmerman int hub_addr, hub_port; 588197ba5f4SPaul Zimmerman 589197ba5f4SPaul Zimmerman chan->do_split = 1; 590197ba5f4SPaul Zimmerman chan->xact_pos = qtd->isoc_split_pos; 591197ba5f4SPaul Zimmerman chan->complete_split = qtd->complete_split; 592197ba5f4SPaul Zimmerman dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port); 593197ba5f4SPaul Zimmerman chan->hub_addr = (u8)hub_addr; 594197ba5f4SPaul Zimmerman chan->hub_port = (u8)hub_port; 595197ba5f4SPaul Zimmerman } 596197ba5f4SPaul Zimmerman 597197ba5f4SPaul Zimmerman static void *dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg, 598197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan, 599197ba5f4SPaul Zimmerman struct dwc2_qtd *qtd, void *bufptr) 600197ba5f4SPaul Zimmerman { 601197ba5f4SPaul Zimmerman struct dwc2_hcd_urb *urb = qtd->urb; 602197ba5f4SPaul Zimmerman struct dwc2_hcd_iso_packet_desc *frame_desc; 603197ba5f4SPaul Zimmerman 604197ba5f4SPaul Zimmerman switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) { 605197ba5f4SPaul Zimmerman case USB_ENDPOINT_XFER_CONTROL: 606197ba5f4SPaul Zimmerman chan->ep_type = USB_ENDPOINT_XFER_CONTROL; 607197ba5f4SPaul Zimmerman 608197ba5f4SPaul Zimmerman switch (qtd->control_phase) { 609197ba5f4SPaul Zimmerman case DWC2_CONTROL_SETUP: 610197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " Control setup transaction\n"); 611197ba5f4SPaul Zimmerman chan->do_ping = 0; 612197ba5f4SPaul Zimmerman chan->ep_is_in = 0; 613197ba5f4SPaul Zimmerman chan->data_pid_start = DWC2_HC_PID_SETUP; 614197ba5f4SPaul Zimmerman if (hsotg->core_params->dma_enable > 0) 615197ba5f4SPaul Zimmerman chan->xfer_dma = urb->setup_dma; 616197ba5f4SPaul Zimmerman else 617197ba5f4SPaul Zimmerman chan->xfer_buf = urb->setup_packet; 618197ba5f4SPaul Zimmerman chan->xfer_len = 8; 619197ba5f4SPaul Zimmerman bufptr = NULL; 620197ba5f4SPaul Zimmerman break; 621197ba5f4SPaul Zimmerman 622197ba5f4SPaul Zimmerman case DWC2_CONTROL_DATA: 623197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " Control data transaction\n"); 624197ba5f4SPaul Zimmerman chan->data_pid_start = qtd->data_toggle; 625197ba5f4SPaul Zimmerman break; 626197ba5f4SPaul Zimmerman 627197ba5f4SPaul Zimmerman case DWC2_CONTROL_STATUS: 628197ba5f4SPaul Zimmerman /* 629197ba5f4SPaul Zimmerman * Direction is opposite of data direction or IN if no 630197ba5f4SPaul Zimmerman * data 631197ba5f4SPaul Zimmerman */ 632197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " Control status transaction\n"); 633197ba5f4SPaul Zimmerman if (urb->length == 0) 634197ba5f4SPaul Zimmerman chan->ep_is_in = 1; 635197ba5f4SPaul Zimmerman else 636197ba5f4SPaul Zimmerman chan->ep_is_in = 637197ba5f4SPaul Zimmerman dwc2_hcd_is_pipe_out(&urb->pipe_info); 638197ba5f4SPaul Zimmerman if (chan->ep_is_in) 639197ba5f4SPaul Zimmerman chan->do_ping = 0; 640197ba5f4SPaul Zimmerman chan->data_pid_start = DWC2_HC_PID_DATA1; 641197ba5f4SPaul Zimmerman chan->xfer_len = 0; 642197ba5f4SPaul Zimmerman if (hsotg->core_params->dma_enable > 0) 643197ba5f4SPaul Zimmerman chan->xfer_dma = hsotg->status_buf_dma; 644197ba5f4SPaul Zimmerman else 645197ba5f4SPaul Zimmerman chan->xfer_buf = hsotg->status_buf; 646197ba5f4SPaul Zimmerman bufptr = NULL; 647197ba5f4SPaul Zimmerman break; 648197ba5f4SPaul Zimmerman } 649197ba5f4SPaul Zimmerman break; 650197ba5f4SPaul Zimmerman 651197ba5f4SPaul Zimmerman case USB_ENDPOINT_XFER_BULK: 652197ba5f4SPaul Zimmerman chan->ep_type = USB_ENDPOINT_XFER_BULK; 653197ba5f4SPaul Zimmerman break; 654197ba5f4SPaul Zimmerman 655197ba5f4SPaul Zimmerman case USB_ENDPOINT_XFER_INT: 656197ba5f4SPaul Zimmerman chan->ep_type = USB_ENDPOINT_XFER_INT; 657197ba5f4SPaul Zimmerman break; 658197ba5f4SPaul Zimmerman 659197ba5f4SPaul Zimmerman case USB_ENDPOINT_XFER_ISOC: 660197ba5f4SPaul Zimmerman chan->ep_type = USB_ENDPOINT_XFER_ISOC; 661197ba5f4SPaul Zimmerman if (hsotg->core_params->dma_desc_enable > 0) 662197ba5f4SPaul Zimmerman break; 663197ba5f4SPaul Zimmerman 664197ba5f4SPaul Zimmerman frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; 665197ba5f4SPaul Zimmerman frame_desc->status = 0; 666197ba5f4SPaul Zimmerman 667197ba5f4SPaul Zimmerman if (hsotg->core_params->dma_enable > 0) { 668197ba5f4SPaul Zimmerman chan->xfer_dma = urb->dma; 669197ba5f4SPaul Zimmerman chan->xfer_dma += frame_desc->offset + 670197ba5f4SPaul Zimmerman qtd->isoc_split_offset; 671197ba5f4SPaul Zimmerman } else { 672197ba5f4SPaul Zimmerman chan->xfer_buf = urb->buf; 673197ba5f4SPaul Zimmerman chan->xfer_buf += frame_desc->offset + 674197ba5f4SPaul Zimmerman qtd->isoc_split_offset; 675197ba5f4SPaul Zimmerman } 676197ba5f4SPaul Zimmerman 677197ba5f4SPaul Zimmerman chan->xfer_len = frame_desc->length - qtd->isoc_split_offset; 678197ba5f4SPaul Zimmerman 679197ba5f4SPaul Zimmerman /* For non-dword aligned buffers */ 680197ba5f4SPaul Zimmerman if (hsotg->core_params->dma_enable > 0 && 681197ba5f4SPaul Zimmerman (chan->xfer_dma & 0x3)) 682197ba5f4SPaul Zimmerman bufptr = (u8 *)urb->buf + frame_desc->offset + 683197ba5f4SPaul Zimmerman qtd->isoc_split_offset; 684197ba5f4SPaul Zimmerman else 685197ba5f4SPaul Zimmerman bufptr = NULL; 686197ba5f4SPaul Zimmerman 687197ba5f4SPaul Zimmerman if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) { 688197ba5f4SPaul Zimmerman if (chan->xfer_len <= 188) 689197ba5f4SPaul Zimmerman chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL; 690197ba5f4SPaul Zimmerman else 691197ba5f4SPaul Zimmerman chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN; 692197ba5f4SPaul Zimmerman } 693197ba5f4SPaul Zimmerman break; 694197ba5f4SPaul Zimmerman } 695197ba5f4SPaul Zimmerman 696197ba5f4SPaul Zimmerman return bufptr; 697197ba5f4SPaul Zimmerman } 698197ba5f4SPaul Zimmerman 699197ba5f4SPaul Zimmerman static int dwc2_hc_setup_align_buf(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 700197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan, void *bufptr) 701197ba5f4SPaul Zimmerman { 702197ba5f4SPaul Zimmerman u32 buf_size; 703197ba5f4SPaul Zimmerman 704197ba5f4SPaul Zimmerman if (chan->ep_type != USB_ENDPOINT_XFER_ISOC) 705197ba5f4SPaul Zimmerman buf_size = hsotg->core_params->max_transfer_size; 706197ba5f4SPaul Zimmerman else 707197ba5f4SPaul Zimmerman buf_size = 4096; 708197ba5f4SPaul Zimmerman 709197ba5f4SPaul Zimmerman if (!qh->dw_align_buf) { 710197ba5f4SPaul Zimmerman qh->dw_align_buf = dma_alloc_coherent(hsotg->dev, buf_size, 711197ba5f4SPaul Zimmerman &qh->dw_align_buf_dma, 712197ba5f4SPaul Zimmerman GFP_ATOMIC); 713197ba5f4SPaul Zimmerman if (!qh->dw_align_buf) 714197ba5f4SPaul Zimmerman return -ENOMEM; 715197ba5f4SPaul Zimmerman } 716197ba5f4SPaul Zimmerman 717197ba5f4SPaul Zimmerman if (!chan->ep_is_in && chan->xfer_len) { 718197ba5f4SPaul Zimmerman dma_sync_single_for_cpu(hsotg->dev, chan->xfer_dma, buf_size, 719197ba5f4SPaul Zimmerman DMA_TO_DEVICE); 720197ba5f4SPaul Zimmerman memcpy(qh->dw_align_buf, bufptr, chan->xfer_len); 721197ba5f4SPaul Zimmerman dma_sync_single_for_device(hsotg->dev, chan->xfer_dma, buf_size, 722197ba5f4SPaul Zimmerman DMA_TO_DEVICE); 723197ba5f4SPaul Zimmerman } 724197ba5f4SPaul Zimmerman 725197ba5f4SPaul Zimmerman chan->align_buf = qh->dw_align_buf_dma; 726197ba5f4SPaul Zimmerman return 0; 727197ba5f4SPaul Zimmerman } 728197ba5f4SPaul Zimmerman 729197ba5f4SPaul Zimmerman /** 730197ba5f4SPaul Zimmerman * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host 731197ba5f4SPaul Zimmerman * channel and initializes the host channel to perform the transactions. The 732197ba5f4SPaul Zimmerman * host channel is removed from the free list. 733197ba5f4SPaul Zimmerman * 734197ba5f4SPaul Zimmerman * @hsotg: The HCD state structure 735197ba5f4SPaul Zimmerman * @qh: Transactions from the first QTD for this QH are selected and assigned 736197ba5f4SPaul Zimmerman * to a free host channel 737197ba5f4SPaul Zimmerman */ 738197ba5f4SPaul Zimmerman static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 739197ba5f4SPaul Zimmerman { 740197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan; 741197ba5f4SPaul Zimmerman struct dwc2_hcd_urb *urb; 742197ba5f4SPaul Zimmerman struct dwc2_qtd *qtd; 743197ba5f4SPaul Zimmerman void *bufptr = NULL; 744197ba5f4SPaul Zimmerman 745197ba5f4SPaul Zimmerman if (dbg_qh(qh)) 746197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh); 747197ba5f4SPaul Zimmerman 748197ba5f4SPaul Zimmerman if (list_empty(&qh->qtd_list)) { 749197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "No QTDs in QH list\n"); 750197ba5f4SPaul Zimmerman return -ENOMEM; 751197ba5f4SPaul Zimmerman } 752197ba5f4SPaul Zimmerman 753197ba5f4SPaul Zimmerman if (list_empty(&hsotg->free_hc_list)) { 754197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "No free channel to assign\n"); 755197ba5f4SPaul Zimmerman return -ENOMEM; 756197ba5f4SPaul Zimmerman } 757197ba5f4SPaul Zimmerman 758197ba5f4SPaul Zimmerman chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan, 759197ba5f4SPaul Zimmerman hc_list_entry); 760197ba5f4SPaul Zimmerman 761197ba5f4SPaul Zimmerman /* Remove host channel from free list */ 762197ba5f4SPaul Zimmerman list_del_init(&chan->hc_list_entry); 763197ba5f4SPaul Zimmerman 764197ba5f4SPaul Zimmerman qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry); 765197ba5f4SPaul Zimmerman urb = qtd->urb; 766197ba5f4SPaul Zimmerman qh->channel = chan; 767197ba5f4SPaul Zimmerman qtd->in_process = 1; 768197ba5f4SPaul Zimmerman 769197ba5f4SPaul Zimmerman /* 770197ba5f4SPaul Zimmerman * Use usb_pipedevice to determine device address. This address is 771197ba5f4SPaul Zimmerman * 0 before the SET_ADDRESS command and the correct address afterward. 772197ba5f4SPaul Zimmerman */ 773197ba5f4SPaul Zimmerman chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info); 774197ba5f4SPaul Zimmerman chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info); 775197ba5f4SPaul Zimmerman chan->speed = qh->dev_speed; 776197ba5f4SPaul Zimmerman chan->max_packet = dwc2_max_packet(qh->maxp); 777197ba5f4SPaul Zimmerman 778197ba5f4SPaul Zimmerman chan->xfer_started = 0; 779197ba5f4SPaul Zimmerman chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS; 780197ba5f4SPaul Zimmerman chan->error_state = (qtd->error_count > 0); 781197ba5f4SPaul Zimmerman chan->halt_on_queue = 0; 782197ba5f4SPaul Zimmerman chan->halt_pending = 0; 783197ba5f4SPaul Zimmerman chan->requests = 0; 784197ba5f4SPaul Zimmerman 785197ba5f4SPaul Zimmerman /* 786197ba5f4SPaul Zimmerman * The following values may be modified in the transfer type section 787197ba5f4SPaul Zimmerman * below. The xfer_len value may be reduced when the transfer is 788197ba5f4SPaul Zimmerman * started to accommodate the max widths of the XferSize and PktCnt 789197ba5f4SPaul Zimmerman * fields in the HCTSIZn register. 790197ba5f4SPaul Zimmerman */ 791197ba5f4SPaul Zimmerman 792197ba5f4SPaul Zimmerman chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0); 793197ba5f4SPaul Zimmerman if (chan->ep_is_in) 794197ba5f4SPaul Zimmerman chan->do_ping = 0; 795197ba5f4SPaul Zimmerman else 796197ba5f4SPaul Zimmerman chan->do_ping = qh->ping_state; 797197ba5f4SPaul Zimmerman 798197ba5f4SPaul Zimmerman chan->data_pid_start = qh->data_toggle; 799197ba5f4SPaul Zimmerman chan->multi_count = 1; 800197ba5f4SPaul Zimmerman 801197ba5f4SPaul Zimmerman if (urb->actual_length > urb->length && 802197ba5f4SPaul Zimmerman !dwc2_hcd_is_pipe_in(&urb->pipe_info)) 803197ba5f4SPaul Zimmerman urb->actual_length = urb->length; 804197ba5f4SPaul Zimmerman 805197ba5f4SPaul Zimmerman if (hsotg->core_params->dma_enable > 0) { 806197ba5f4SPaul Zimmerman chan->xfer_dma = urb->dma + urb->actual_length; 807197ba5f4SPaul Zimmerman 808197ba5f4SPaul Zimmerman /* For non-dword aligned case */ 809197ba5f4SPaul Zimmerman if (hsotg->core_params->dma_desc_enable <= 0 && 810197ba5f4SPaul Zimmerman (chan->xfer_dma & 0x3)) 811197ba5f4SPaul Zimmerman bufptr = (u8 *)urb->buf + urb->actual_length; 812197ba5f4SPaul Zimmerman } else { 813197ba5f4SPaul Zimmerman chan->xfer_buf = (u8 *)urb->buf + urb->actual_length; 814197ba5f4SPaul Zimmerman } 815197ba5f4SPaul Zimmerman 816197ba5f4SPaul Zimmerman chan->xfer_len = urb->length - urb->actual_length; 817197ba5f4SPaul Zimmerman chan->xfer_count = 0; 818197ba5f4SPaul Zimmerman 819197ba5f4SPaul Zimmerman /* Set the split attributes if required */ 820197ba5f4SPaul Zimmerman if (qh->do_split) 821197ba5f4SPaul Zimmerman dwc2_hc_init_split(hsotg, chan, qtd, urb); 822197ba5f4SPaul Zimmerman else 823197ba5f4SPaul Zimmerman chan->do_split = 0; 824197ba5f4SPaul Zimmerman 825197ba5f4SPaul Zimmerman /* Set the transfer attributes */ 826197ba5f4SPaul Zimmerman bufptr = dwc2_hc_init_xfer(hsotg, chan, qtd, bufptr); 827197ba5f4SPaul Zimmerman 828197ba5f4SPaul Zimmerman /* Non DWORD-aligned buffer case */ 829197ba5f4SPaul Zimmerman if (bufptr) { 830197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, "Non-aligned buffer\n"); 831197ba5f4SPaul Zimmerman if (dwc2_hc_setup_align_buf(hsotg, qh, chan, bufptr)) { 832197ba5f4SPaul Zimmerman dev_err(hsotg->dev, 833197ba5f4SPaul Zimmerman "%s: Failed to allocate memory to handle non-dword aligned buffer\n", 834197ba5f4SPaul Zimmerman __func__); 835197ba5f4SPaul Zimmerman /* Add channel back to free list */ 836197ba5f4SPaul Zimmerman chan->align_buf = 0; 837197ba5f4SPaul Zimmerman chan->multi_count = 0; 838197ba5f4SPaul Zimmerman list_add_tail(&chan->hc_list_entry, 839197ba5f4SPaul Zimmerman &hsotg->free_hc_list); 840197ba5f4SPaul Zimmerman qtd->in_process = 0; 841197ba5f4SPaul Zimmerman qh->channel = NULL; 842197ba5f4SPaul Zimmerman return -ENOMEM; 843197ba5f4SPaul Zimmerman } 844197ba5f4SPaul Zimmerman } else { 845197ba5f4SPaul Zimmerman chan->align_buf = 0; 846197ba5f4SPaul Zimmerman } 847197ba5f4SPaul Zimmerman 848197ba5f4SPaul Zimmerman if (chan->ep_type == USB_ENDPOINT_XFER_INT || 849197ba5f4SPaul Zimmerman chan->ep_type == USB_ENDPOINT_XFER_ISOC) 850197ba5f4SPaul Zimmerman /* 851197ba5f4SPaul Zimmerman * This value may be modified when the transfer is started 852197ba5f4SPaul Zimmerman * to reflect the actual transfer length 853197ba5f4SPaul Zimmerman */ 854197ba5f4SPaul Zimmerman chan->multi_count = dwc2_hb_mult(qh->maxp); 855197ba5f4SPaul Zimmerman 856197ba5f4SPaul Zimmerman if (hsotg->core_params->dma_desc_enable > 0) 857197ba5f4SPaul Zimmerman chan->desc_list_addr = qh->desc_list_dma; 858197ba5f4SPaul Zimmerman 859197ba5f4SPaul Zimmerman dwc2_hc_init(hsotg, chan); 860197ba5f4SPaul Zimmerman chan->qh = qh; 861197ba5f4SPaul Zimmerman 862197ba5f4SPaul Zimmerman return 0; 863197ba5f4SPaul Zimmerman } 864197ba5f4SPaul Zimmerman 865197ba5f4SPaul Zimmerman /** 866197ba5f4SPaul Zimmerman * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer 867197ba5f4SPaul Zimmerman * schedule and assigns them to available host channels. Called from the HCD 868197ba5f4SPaul Zimmerman * interrupt handler functions. 869197ba5f4SPaul Zimmerman * 870197ba5f4SPaul Zimmerman * @hsotg: The HCD state structure 871197ba5f4SPaul Zimmerman * 872197ba5f4SPaul Zimmerman * Return: The types of new transactions that were assigned to host channels 873197ba5f4SPaul Zimmerman */ 874197ba5f4SPaul Zimmerman enum dwc2_transaction_type dwc2_hcd_select_transactions( 875197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg) 876197ba5f4SPaul Zimmerman { 877197ba5f4SPaul Zimmerman enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE; 878197ba5f4SPaul Zimmerman struct list_head *qh_ptr; 879197ba5f4SPaul Zimmerman struct dwc2_qh *qh; 880197ba5f4SPaul Zimmerman int num_channels; 881197ba5f4SPaul Zimmerman 882197ba5f4SPaul Zimmerman #ifdef DWC2_DEBUG_SOF 883197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " Select Transactions\n"); 884197ba5f4SPaul Zimmerman #endif 885197ba5f4SPaul Zimmerman 886197ba5f4SPaul Zimmerman /* Process entries in the periodic ready list */ 887197ba5f4SPaul Zimmerman qh_ptr = hsotg->periodic_sched_ready.next; 888197ba5f4SPaul Zimmerman while (qh_ptr != &hsotg->periodic_sched_ready) { 889197ba5f4SPaul Zimmerman if (list_empty(&hsotg->free_hc_list)) 890197ba5f4SPaul Zimmerman break; 891197ba5f4SPaul Zimmerman if (hsotg->core_params->uframe_sched > 0) { 892197ba5f4SPaul Zimmerman if (hsotg->available_host_channels <= 1) 893197ba5f4SPaul Zimmerman break; 894197ba5f4SPaul Zimmerman hsotg->available_host_channels--; 895197ba5f4SPaul Zimmerman } 896197ba5f4SPaul Zimmerman qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 897197ba5f4SPaul Zimmerman if (dwc2_assign_and_init_hc(hsotg, qh)) 898197ba5f4SPaul Zimmerman break; 899197ba5f4SPaul Zimmerman 900197ba5f4SPaul Zimmerman /* 901197ba5f4SPaul Zimmerman * Move the QH from the periodic ready schedule to the 902197ba5f4SPaul Zimmerman * periodic assigned schedule 903197ba5f4SPaul Zimmerman */ 904197ba5f4SPaul Zimmerman qh_ptr = qh_ptr->next; 905197ba5f4SPaul Zimmerman list_move(&qh->qh_list_entry, &hsotg->periodic_sched_assigned); 906197ba5f4SPaul Zimmerman ret_val = DWC2_TRANSACTION_PERIODIC; 907197ba5f4SPaul Zimmerman } 908197ba5f4SPaul Zimmerman 909197ba5f4SPaul Zimmerman /* 910197ba5f4SPaul Zimmerman * Process entries in the inactive portion of the non-periodic 911197ba5f4SPaul Zimmerman * schedule. Some free host channels may not be used if they are 912197ba5f4SPaul Zimmerman * reserved for periodic transfers. 913197ba5f4SPaul Zimmerman */ 914197ba5f4SPaul Zimmerman num_channels = hsotg->core_params->host_channels; 915197ba5f4SPaul Zimmerman qh_ptr = hsotg->non_periodic_sched_inactive.next; 916197ba5f4SPaul Zimmerman while (qh_ptr != &hsotg->non_periodic_sched_inactive) { 917197ba5f4SPaul Zimmerman if (hsotg->core_params->uframe_sched <= 0 && 918197ba5f4SPaul Zimmerman hsotg->non_periodic_channels >= num_channels - 919197ba5f4SPaul Zimmerman hsotg->periodic_channels) 920197ba5f4SPaul Zimmerman break; 921197ba5f4SPaul Zimmerman if (list_empty(&hsotg->free_hc_list)) 922197ba5f4SPaul Zimmerman break; 923197ba5f4SPaul Zimmerman qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 924197ba5f4SPaul Zimmerman if (hsotg->core_params->uframe_sched > 0) { 925197ba5f4SPaul Zimmerman if (hsotg->available_host_channels < 1) 926197ba5f4SPaul Zimmerman break; 927197ba5f4SPaul Zimmerman hsotg->available_host_channels--; 928197ba5f4SPaul Zimmerman } 929197ba5f4SPaul Zimmerman 930197ba5f4SPaul Zimmerman if (dwc2_assign_and_init_hc(hsotg, qh)) 931197ba5f4SPaul Zimmerman break; 932197ba5f4SPaul Zimmerman 933197ba5f4SPaul Zimmerman /* 934197ba5f4SPaul Zimmerman * Move the QH from the non-periodic inactive schedule to the 935197ba5f4SPaul Zimmerman * non-periodic active schedule 936197ba5f4SPaul Zimmerman */ 937197ba5f4SPaul Zimmerman qh_ptr = qh_ptr->next; 938197ba5f4SPaul Zimmerman list_move(&qh->qh_list_entry, 939197ba5f4SPaul Zimmerman &hsotg->non_periodic_sched_active); 940197ba5f4SPaul Zimmerman 941197ba5f4SPaul Zimmerman if (ret_val == DWC2_TRANSACTION_NONE) 942197ba5f4SPaul Zimmerman ret_val = DWC2_TRANSACTION_NON_PERIODIC; 943197ba5f4SPaul Zimmerman else 944197ba5f4SPaul Zimmerman ret_val = DWC2_TRANSACTION_ALL; 945197ba5f4SPaul Zimmerman 946197ba5f4SPaul Zimmerman if (hsotg->core_params->uframe_sched <= 0) 947197ba5f4SPaul Zimmerman hsotg->non_periodic_channels++; 948197ba5f4SPaul Zimmerman } 949197ba5f4SPaul Zimmerman 950197ba5f4SPaul Zimmerman return ret_val; 951197ba5f4SPaul Zimmerman } 952197ba5f4SPaul Zimmerman 953197ba5f4SPaul Zimmerman /** 954197ba5f4SPaul Zimmerman * dwc2_queue_transaction() - Attempts to queue a single transaction request for 955197ba5f4SPaul Zimmerman * a host channel associated with either a periodic or non-periodic transfer 956197ba5f4SPaul Zimmerman * 957197ba5f4SPaul Zimmerman * @hsotg: The HCD state structure 958197ba5f4SPaul Zimmerman * @chan: Host channel descriptor associated with either a periodic or 959197ba5f4SPaul Zimmerman * non-periodic transfer 960197ba5f4SPaul Zimmerman * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO 961197ba5f4SPaul Zimmerman * for periodic transfers or the non-periodic Tx FIFO 962197ba5f4SPaul Zimmerman * for non-periodic transfers 963197ba5f4SPaul Zimmerman * 964197ba5f4SPaul Zimmerman * Return: 1 if a request is queued and more requests may be needed to 965197ba5f4SPaul Zimmerman * complete the transfer, 0 if no more requests are required for this 966197ba5f4SPaul Zimmerman * transfer, -1 if there is insufficient space in the Tx FIFO 967197ba5f4SPaul Zimmerman * 968197ba5f4SPaul Zimmerman * This function assumes that there is space available in the appropriate 969197ba5f4SPaul Zimmerman * request queue. For an OUT transfer or SETUP transaction in Slave mode, 970197ba5f4SPaul Zimmerman * it checks whether space is available in the appropriate Tx FIFO. 971197ba5f4SPaul Zimmerman * 972197ba5f4SPaul Zimmerman * Must be called with interrupt disabled and spinlock held 973197ba5f4SPaul Zimmerman */ 974197ba5f4SPaul Zimmerman static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg, 975197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan, 976197ba5f4SPaul Zimmerman u16 fifo_dwords_avail) 977197ba5f4SPaul Zimmerman { 978197ba5f4SPaul Zimmerman int retval = 0; 979197ba5f4SPaul Zimmerman 980197ba5f4SPaul Zimmerman if (hsotg->core_params->dma_enable > 0) { 981197ba5f4SPaul Zimmerman if (hsotg->core_params->dma_desc_enable > 0) { 982197ba5f4SPaul Zimmerman if (!chan->xfer_started || 983197ba5f4SPaul Zimmerman chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 984197ba5f4SPaul Zimmerman dwc2_hcd_start_xfer_ddma(hsotg, chan->qh); 985197ba5f4SPaul Zimmerman chan->qh->ping_state = 0; 986197ba5f4SPaul Zimmerman } 987197ba5f4SPaul Zimmerman } else if (!chan->xfer_started) { 988197ba5f4SPaul Zimmerman dwc2_hc_start_transfer(hsotg, chan); 989197ba5f4SPaul Zimmerman chan->qh->ping_state = 0; 990197ba5f4SPaul Zimmerman } 991197ba5f4SPaul Zimmerman } else if (chan->halt_pending) { 992197ba5f4SPaul Zimmerman /* Don't queue a request if the channel has been halted */ 993197ba5f4SPaul Zimmerman } else if (chan->halt_on_queue) { 994197ba5f4SPaul Zimmerman dwc2_hc_halt(hsotg, chan, chan->halt_status); 995197ba5f4SPaul Zimmerman } else if (chan->do_ping) { 996197ba5f4SPaul Zimmerman if (!chan->xfer_started) 997197ba5f4SPaul Zimmerman dwc2_hc_start_transfer(hsotg, chan); 998197ba5f4SPaul Zimmerman } else if (!chan->ep_is_in || 999197ba5f4SPaul Zimmerman chan->data_pid_start == DWC2_HC_PID_SETUP) { 1000197ba5f4SPaul Zimmerman if ((fifo_dwords_avail * 4) >= chan->max_packet) { 1001197ba5f4SPaul Zimmerman if (!chan->xfer_started) { 1002197ba5f4SPaul Zimmerman dwc2_hc_start_transfer(hsotg, chan); 1003197ba5f4SPaul Zimmerman retval = 1; 1004197ba5f4SPaul Zimmerman } else { 1005197ba5f4SPaul Zimmerman retval = dwc2_hc_continue_transfer(hsotg, chan); 1006197ba5f4SPaul Zimmerman } 1007197ba5f4SPaul Zimmerman } else { 1008197ba5f4SPaul Zimmerman retval = -1; 1009197ba5f4SPaul Zimmerman } 1010197ba5f4SPaul Zimmerman } else { 1011197ba5f4SPaul Zimmerman if (!chan->xfer_started) { 1012197ba5f4SPaul Zimmerman dwc2_hc_start_transfer(hsotg, chan); 1013197ba5f4SPaul Zimmerman retval = 1; 1014197ba5f4SPaul Zimmerman } else { 1015197ba5f4SPaul Zimmerman retval = dwc2_hc_continue_transfer(hsotg, chan); 1016197ba5f4SPaul Zimmerman } 1017197ba5f4SPaul Zimmerman } 1018197ba5f4SPaul Zimmerman 1019197ba5f4SPaul Zimmerman return retval; 1020197ba5f4SPaul Zimmerman } 1021197ba5f4SPaul Zimmerman 1022197ba5f4SPaul Zimmerman /* 1023197ba5f4SPaul Zimmerman * Processes periodic channels for the next frame and queues transactions for 1024197ba5f4SPaul Zimmerman * these channels to the DWC_otg controller. After queueing transactions, the 1025197ba5f4SPaul Zimmerman * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions 1026197ba5f4SPaul Zimmerman * to queue as Periodic Tx FIFO or request queue space becomes available. 1027197ba5f4SPaul Zimmerman * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. 1028197ba5f4SPaul Zimmerman * 1029197ba5f4SPaul Zimmerman * Must be called with interrupt disabled and spinlock held 1030197ba5f4SPaul Zimmerman */ 1031197ba5f4SPaul Zimmerman static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) 1032197ba5f4SPaul Zimmerman { 1033197ba5f4SPaul Zimmerman struct list_head *qh_ptr; 1034197ba5f4SPaul Zimmerman struct dwc2_qh *qh; 1035197ba5f4SPaul Zimmerman u32 tx_status; 1036197ba5f4SPaul Zimmerman u32 fspcavail; 1037197ba5f4SPaul Zimmerman u32 gintmsk; 1038197ba5f4SPaul Zimmerman int status; 1039197ba5f4SPaul Zimmerman int no_queue_space = 0; 1040197ba5f4SPaul Zimmerman int no_fifo_space = 0; 1041197ba5f4SPaul Zimmerman u32 qspcavail; 1042197ba5f4SPaul Zimmerman 1043197ba5f4SPaul Zimmerman if (dbg_perio()) 1044197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, "Queue periodic transactions\n"); 1045197ba5f4SPaul Zimmerman 1046197ba5f4SPaul Zimmerman tx_status = readl(hsotg->regs + HPTXSTS); 1047197ba5f4SPaul Zimmerman qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1048197ba5f4SPaul Zimmerman TXSTS_QSPCAVAIL_SHIFT; 1049197ba5f4SPaul Zimmerman fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1050197ba5f4SPaul Zimmerman TXSTS_FSPCAVAIL_SHIFT; 1051197ba5f4SPaul Zimmerman 1052197ba5f4SPaul Zimmerman if (dbg_perio()) { 1053197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n", 1054197ba5f4SPaul Zimmerman qspcavail); 1055197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n", 1056197ba5f4SPaul Zimmerman fspcavail); 1057197ba5f4SPaul Zimmerman } 1058197ba5f4SPaul Zimmerman 1059197ba5f4SPaul Zimmerman qh_ptr = hsotg->periodic_sched_assigned.next; 1060197ba5f4SPaul Zimmerman while (qh_ptr != &hsotg->periodic_sched_assigned) { 1061197ba5f4SPaul Zimmerman tx_status = readl(hsotg->regs + HPTXSTS); 1062197ba5f4SPaul Zimmerman qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1063197ba5f4SPaul Zimmerman TXSTS_QSPCAVAIL_SHIFT; 1064197ba5f4SPaul Zimmerman if (qspcavail == 0) { 1065197ba5f4SPaul Zimmerman no_queue_space = 1; 1066197ba5f4SPaul Zimmerman break; 1067197ba5f4SPaul Zimmerman } 1068197ba5f4SPaul Zimmerman 1069197ba5f4SPaul Zimmerman qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 1070197ba5f4SPaul Zimmerman if (!qh->channel) { 1071197ba5f4SPaul Zimmerman qh_ptr = qh_ptr->next; 1072197ba5f4SPaul Zimmerman continue; 1073197ba5f4SPaul Zimmerman } 1074197ba5f4SPaul Zimmerman 1075197ba5f4SPaul Zimmerman /* Make sure EP's TT buffer is clean before queueing qtds */ 1076197ba5f4SPaul Zimmerman if (qh->tt_buffer_dirty) { 1077197ba5f4SPaul Zimmerman qh_ptr = qh_ptr->next; 1078197ba5f4SPaul Zimmerman continue; 1079197ba5f4SPaul Zimmerman } 1080197ba5f4SPaul Zimmerman 1081197ba5f4SPaul Zimmerman /* 1082197ba5f4SPaul Zimmerman * Set a flag if we're queuing high-bandwidth in slave mode. 1083197ba5f4SPaul Zimmerman * The flag prevents any halts to get into the request queue in 1084197ba5f4SPaul Zimmerman * the middle of multiple high-bandwidth packets getting queued. 1085197ba5f4SPaul Zimmerman */ 1086197ba5f4SPaul Zimmerman if (hsotg->core_params->dma_enable <= 0 && 1087197ba5f4SPaul Zimmerman qh->channel->multi_count > 1) 1088197ba5f4SPaul Zimmerman hsotg->queuing_high_bandwidth = 1; 1089197ba5f4SPaul Zimmerman 1090197ba5f4SPaul Zimmerman fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1091197ba5f4SPaul Zimmerman TXSTS_FSPCAVAIL_SHIFT; 1092197ba5f4SPaul Zimmerman status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 1093197ba5f4SPaul Zimmerman if (status < 0) { 1094197ba5f4SPaul Zimmerman no_fifo_space = 1; 1095197ba5f4SPaul Zimmerman break; 1096197ba5f4SPaul Zimmerman } 1097197ba5f4SPaul Zimmerman 1098197ba5f4SPaul Zimmerman /* 1099197ba5f4SPaul Zimmerman * In Slave mode, stay on the current transfer until there is 1100197ba5f4SPaul Zimmerman * nothing more to do or the high-bandwidth request count is 1101197ba5f4SPaul Zimmerman * reached. In DMA mode, only need to queue one request. The 1102197ba5f4SPaul Zimmerman * controller automatically handles multiple packets for 1103197ba5f4SPaul Zimmerman * high-bandwidth transfers. 1104197ba5f4SPaul Zimmerman */ 1105197ba5f4SPaul Zimmerman if (hsotg->core_params->dma_enable > 0 || status == 0 || 1106197ba5f4SPaul Zimmerman qh->channel->requests == qh->channel->multi_count) { 1107197ba5f4SPaul Zimmerman qh_ptr = qh_ptr->next; 1108197ba5f4SPaul Zimmerman /* 1109197ba5f4SPaul Zimmerman * Move the QH from the periodic assigned schedule to 1110197ba5f4SPaul Zimmerman * the periodic queued schedule 1111197ba5f4SPaul Zimmerman */ 1112197ba5f4SPaul Zimmerman list_move(&qh->qh_list_entry, 1113197ba5f4SPaul Zimmerman &hsotg->periodic_sched_queued); 1114197ba5f4SPaul Zimmerman 1115197ba5f4SPaul Zimmerman /* done queuing high bandwidth */ 1116197ba5f4SPaul Zimmerman hsotg->queuing_high_bandwidth = 0; 1117197ba5f4SPaul Zimmerman } 1118197ba5f4SPaul Zimmerman } 1119197ba5f4SPaul Zimmerman 1120197ba5f4SPaul Zimmerman if (hsotg->core_params->dma_enable <= 0) { 1121197ba5f4SPaul Zimmerman tx_status = readl(hsotg->regs + HPTXSTS); 1122197ba5f4SPaul Zimmerman qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1123197ba5f4SPaul Zimmerman TXSTS_QSPCAVAIL_SHIFT; 1124197ba5f4SPaul Zimmerman fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1125197ba5f4SPaul Zimmerman TXSTS_FSPCAVAIL_SHIFT; 1126197ba5f4SPaul Zimmerman if (dbg_perio()) { 1127197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, 1128197ba5f4SPaul Zimmerman " P Tx Req Queue Space Avail (after queue): %d\n", 1129197ba5f4SPaul Zimmerman qspcavail); 1130197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, 1131197ba5f4SPaul Zimmerman " P Tx FIFO Space Avail (after queue): %d\n", 1132197ba5f4SPaul Zimmerman fspcavail); 1133197ba5f4SPaul Zimmerman } 1134197ba5f4SPaul Zimmerman 1135197ba5f4SPaul Zimmerman if (!list_empty(&hsotg->periodic_sched_assigned) || 1136197ba5f4SPaul Zimmerman no_queue_space || no_fifo_space) { 1137197ba5f4SPaul Zimmerman /* 1138197ba5f4SPaul Zimmerman * May need to queue more transactions as the request 1139197ba5f4SPaul Zimmerman * queue or Tx FIFO empties. Enable the periodic Tx 1140197ba5f4SPaul Zimmerman * FIFO empty interrupt. (Always use the half-empty 1141197ba5f4SPaul Zimmerman * level to ensure that new requests are loaded as 1142197ba5f4SPaul Zimmerman * soon as possible.) 1143197ba5f4SPaul Zimmerman */ 1144197ba5f4SPaul Zimmerman gintmsk = readl(hsotg->regs + GINTMSK); 1145197ba5f4SPaul Zimmerman gintmsk |= GINTSTS_PTXFEMP; 1146197ba5f4SPaul Zimmerman writel(gintmsk, hsotg->regs + GINTMSK); 1147197ba5f4SPaul Zimmerman } else { 1148197ba5f4SPaul Zimmerman /* 1149197ba5f4SPaul Zimmerman * Disable the Tx FIFO empty interrupt since there are 1150197ba5f4SPaul Zimmerman * no more transactions that need to be queued right 1151197ba5f4SPaul Zimmerman * now. This function is called from interrupt 1152197ba5f4SPaul Zimmerman * handlers to queue more transactions as transfer 1153197ba5f4SPaul Zimmerman * states change. 1154197ba5f4SPaul Zimmerman */ 1155197ba5f4SPaul Zimmerman gintmsk = readl(hsotg->regs + GINTMSK); 1156197ba5f4SPaul Zimmerman gintmsk &= ~GINTSTS_PTXFEMP; 1157197ba5f4SPaul Zimmerman writel(gintmsk, hsotg->regs + GINTMSK); 1158197ba5f4SPaul Zimmerman } 1159197ba5f4SPaul Zimmerman } 1160197ba5f4SPaul Zimmerman } 1161197ba5f4SPaul Zimmerman 1162197ba5f4SPaul Zimmerman /* 1163197ba5f4SPaul Zimmerman * Processes active non-periodic channels and queues transactions for these 1164197ba5f4SPaul Zimmerman * channels to the DWC_otg controller. After queueing transactions, the NP Tx 1165197ba5f4SPaul Zimmerman * FIFO Empty interrupt is enabled if there are more transactions to queue as 1166197ba5f4SPaul Zimmerman * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx 1167197ba5f4SPaul Zimmerman * FIFO Empty interrupt is disabled. 1168197ba5f4SPaul Zimmerman * 1169197ba5f4SPaul Zimmerman * Must be called with interrupt disabled and spinlock held 1170197ba5f4SPaul Zimmerman */ 1171197ba5f4SPaul Zimmerman static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg) 1172197ba5f4SPaul Zimmerman { 1173197ba5f4SPaul Zimmerman struct list_head *orig_qh_ptr; 1174197ba5f4SPaul Zimmerman struct dwc2_qh *qh; 1175197ba5f4SPaul Zimmerman u32 tx_status; 1176197ba5f4SPaul Zimmerman u32 qspcavail; 1177197ba5f4SPaul Zimmerman u32 fspcavail; 1178197ba5f4SPaul Zimmerman u32 gintmsk; 1179197ba5f4SPaul Zimmerman int status; 1180197ba5f4SPaul Zimmerman int no_queue_space = 0; 1181197ba5f4SPaul Zimmerman int no_fifo_space = 0; 1182197ba5f4SPaul Zimmerman int more_to_do = 0; 1183197ba5f4SPaul Zimmerman 1184197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n"); 1185197ba5f4SPaul Zimmerman 1186197ba5f4SPaul Zimmerman tx_status = readl(hsotg->regs + GNPTXSTS); 1187197ba5f4SPaul Zimmerman qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1188197ba5f4SPaul Zimmerman TXSTS_QSPCAVAIL_SHIFT; 1189197ba5f4SPaul Zimmerman fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1190197ba5f4SPaul Zimmerman TXSTS_FSPCAVAIL_SHIFT; 1191197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n", 1192197ba5f4SPaul Zimmerman qspcavail); 1193197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n", 1194197ba5f4SPaul Zimmerman fspcavail); 1195197ba5f4SPaul Zimmerman 1196197ba5f4SPaul Zimmerman /* 1197197ba5f4SPaul Zimmerman * Keep track of the starting point. Skip over the start-of-list 1198197ba5f4SPaul Zimmerman * entry. 1199197ba5f4SPaul Zimmerman */ 1200197ba5f4SPaul Zimmerman if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active) 1201197ba5f4SPaul Zimmerman hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 1202197ba5f4SPaul Zimmerman orig_qh_ptr = hsotg->non_periodic_qh_ptr; 1203197ba5f4SPaul Zimmerman 1204197ba5f4SPaul Zimmerman /* 1205197ba5f4SPaul Zimmerman * Process once through the active list or until no more space is 1206197ba5f4SPaul Zimmerman * available in the request queue or the Tx FIFO 1207197ba5f4SPaul Zimmerman */ 1208197ba5f4SPaul Zimmerman do { 1209197ba5f4SPaul Zimmerman tx_status = readl(hsotg->regs + GNPTXSTS); 1210197ba5f4SPaul Zimmerman qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1211197ba5f4SPaul Zimmerman TXSTS_QSPCAVAIL_SHIFT; 1212197ba5f4SPaul Zimmerman if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) { 1213197ba5f4SPaul Zimmerman no_queue_space = 1; 1214197ba5f4SPaul Zimmerman break; 1215197ba5f4SPaul Zimmerman } 1216197ba5f4SPaul Zimmerman 1217197ba5f4SPaul Zimmerman qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh, 1218197ba5f4SPaul Zimmerman qh_list_entry); 1219197ba5f4SPaul Zimmerman if (!qh->channel) 1220197ba5f4SPaul Zimmerman goto next; 1221197ba5f4SPaul Zimmerman 1222197ba5f4SPaul Zimmerman /* Make sure EP's TT buffer is clean before queueing qtds */ 1223197ba5f4SPaul Zimmerman if (qh->tt_buffer_dirty) 1224197ba5f4SPaul Zimmerman goto next; 1225197ba5f4SPaul Zimmerman 1226197ba5f4SPaul Zimmerman fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1227197ba5f4SPaul Zimmerman TXSTS_FSPCAVAIL_SHIFT; 1228197ba5f4SPaul Zimmerman status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 1229197ba5f4SPaul Zimmerman 1230197ba5f4SPaul Zimmerman if (status > 0) { 1231197ba5f4SPaul Zimmerman more_to_do = 1; 1232197ba5f4SPaul Zimmerman } else if (status < 0) { 1233197ba5f4SPaul Zimmerman no_fifo_space = 1; 1234197ba5f4SPaul Zimmerman break; 1235197ba5f4SPaul Zimmerman } 1236197ba5f4SPaul Zimmerman next: 1237197ba5f4SPaul Zimmerman /* Advance to next QH, skipping start-of-list entry */ 1238197ba5f4SPaul Zimmerman hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 1239197ba5f4SPaul Zimmerman if (hsotg->non_periodic_qh_ptr == 1240197ba5f4SPaul Zimmerman &hsotg->non_periodic_sched_active) 1241197ba5f4SPaul Zimmerman hsotg->non_periodic_qh_ptr = 1242197ba5f4SPaul Zimmerman hsotg->non_periodic_qh_ptr->next; 1243197ba5f4SPaul Zimmerman } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr); 1244197ba5f4SPaul Zimmerman 1245197ba5f4SPaul Zimmerman if (hsotg->core_params->dma_enable <= 0) { 1246197ba5f4SPaul Zimmerman tx_status = readl(hsotg->regs + GNPTXSTS); 1247197ba5f4SPaul Zimmerman qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1248197ba5f4SPaul Zimmerman TXSTS_QSPCAVAIL_SHIFT; 1249197ba5f4SPaul Zimmerman fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1250197ba5f4SPaul Zimmerman TXSTS_FSPCAVAIL_SHIFT; 1251197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, 1252197ba5f4SPaul Zimmerman " NP Tx Req Queue Space Avail (after queue): %d\n", 1253197ba5f4SPaul Zimmerman qspcavail); 1254197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, 1255197ba5f4SPaul Zimmerman " NP Tx FIFO Space Avail (after queue): %d\n", 1256197ba5f4SPaul Zimmerman fspcavail); 1257197ba5f4SPaul Zimmerman 1258197ba5f4SPaul Zimmerman if (more_to_do || no_queue_space || no_fifo_space) { 1259197ba5f4SPaul Zimmerman /* 1260197ba5f4SPaul Zimmerman * May need to queue more transactions as the request 1261197ba5f4SPaul Zimmerman * queue or Tx FIFO empties. Enable the non-periodic 1262197ba5f4SPaul Zimmerman * Tx FIFO empty interrupt. (Always use the half-empty 1263197ba5f4SPaul Zimmerman * level to ensure that new requests are loaded as 1264197ba5f4SPaul Zimmerman * soon as possible.) 1265197ba5f4SPaul Zimmerman */ 1266197ba5f4SPaul Zimmerman gintmsk = readl(hsotg->regs + GINTMSK); 1267197ba5f4SPaul Zimmerman gintmsk |= GINTSTS_NPTXFEMP; 1268197ba5f4SPaul Zimmerman writel(gintmsk, hsotg->regs + GINTMSK); 1269197ba5f4SPaul Zimmerman } else { 1270197ba5f4SPaul Zimmerman /* 1271197ba5f4SPaul Zimmerman * Disable the Tx FIFO empty interrupt since there are 1272197ba5f4SPaul Zimmerman * no more transactions that need to be queued right 1273197ba5f4SPaul Zimmerman * now. This function is called from interrupt 1274197ba5f4SPaul Zimmerman * handlers to queue more transactions as transfer 1275197ba5f4SPaul Zimmerman * states change. 1276197ba5f4SPaul Zimmerman */ 1277197ba5f4SPaul Zimmerman gintmsk = readl(hsotg->regs + GINTMSK); 1278197ba5f4SPaul Zimmerman gintmsk &= ~GINTSTS_NPTXFEMP; 1279197ba5f4SPaul Zimmerman writel(gintmsk, hsotg->regs + GINTMSK); 1280197ba5f4SPaul Zimmerman } 1281197ba5f4SPaul Zimmerman } 1282197ba5f4SPaul Zimmerman } 1283197ba5f4SPaul Zimmerman 1284197ba5f4SPaul Zimmerman /** 1285197ba5f4SPaul Zimmerman * dwc2_hcd_queue_transactions() - Processes the currently active host channels 1286197ba5f4SPaul Zimmerman * and queues transactions for these channels to the DWC_otg controller. Called 1287197ba5f4SPaul Zimmerman * from the HCD interrupt handler functions. 1288197ba5f4SPaul Zimmerman * 1289197ba5f4SPaul Zimmerman * @hsotg: The HCD state structure 1290197ba5f4SPaul Zimmerman * @tr_type: The type(s) of transactions to queue (non-periodic, periodic, 1291197ba5f4SPaul Zimmerman * or both) 1292197ba5f4SPaul Zimmerman * 1293197ba5f4SPaul Zimmerman * Must be called with interrupt disabled and spinlock held 1294197ba5f4SPaul Zimmerman */ 1295197ba5f4SPaul Zimmerman void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 1296197ba5f4SPaul Zimmerman enum dwc2_transaction_type tr_type) 1297197ba5f4SPaul Zimmerman { 1298197ba5f4SPaul Zimmerman #ifdef DWC2_DEBUG_SOF 1299197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, "Queue Transactions\n"); 1300197ba5f4SPaul Zimmerman #endif 1301197ba5f4SPaul Zimmerman /* Process host channels associated with periodic transfers */ 1302197ba5f4SPaul Zimmerman if ((tr_type == DWC2_TRANSACTION_PERIODIC || 1303197ba5f4SPaul Zimmerman tr_type == DWC2_TRANSACTION_ALL) && 1304197ba5f4SPaul Zimmerman !list_empty(&hsotg->periodic_sched_assigned)) 1305197ba5f4SPaul Zimmerman dwc2_process_periodic_channels(hsotg); 1306197ba5f4SPaul Zimmerman 1307197ba5f4SPaul Zimmerman /* Process host channels associated with non-periodic transfers */ 1308197ba5f4SPaul Zimmerman if (tr_type == DWC2_TRANSACTION_NON_PERIODIC || 1309197ba5f4SPaul Zimmerman tr_type == DWC2_TRANSACTION_ALL) { 1310197ba5f4SPaul Zimmerman if (!list_empty(&hsotg->non_periodic_sched_active)) { 1311197ba5f4SPaul Zimmerman dwc2_process_non_periodic_channels(hsotg); 1312197ba5f4SPaul Zimmerman } else { 1313197ba5f4SPaul Zimmerman /* 1314197ba5f4SPaul Zimmerman * Ensure NP Tx FIFO empty interrupt is disabled when 1315197ba5f4SPaul Zimmerman * there are no non-periodic transfers to process 1316197ba5f4SPaul Zimmerman */ 1317197ba5f4SPaul Zimmerman u32 gintmsk = readl(hsotg->regs + GINTMSK); 1318197ba5f4SPaul Zimmerman 1319197ba5f4SPaul Zimmerman gintmsk &= ~GINTSTS_NPTXFEMP; 1320197ba5f4SPaul Zimmerman writel(gintmsk, hsotg->regs + GINTMSK); 1321197ba5f4SPaul Zimmerman } 1322197ba5f4SPaul Zimmerman } 1323197ba5f4SPaul Zimmerman } 1324197ba5f4SPaul Zimmerman 1325197ba5f4SPaul Zimmerman static void dwc2_conn_id_status_change(struct work_struct *work) 1326197ba5f4SPaul Zimmerman { 1327197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 1328197ba5f4SPaul Zimmerman wf_otg); 1329197ba5f4SPaul Zimmerman u32 count = 0; 1330197ba5f4SPaul Zimmerman u32 gotgctl; 1331197ba5f4SPaul Zimmerman 1332197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "%s()\n", __func__); 1333197ba5f4SPaul Zimmerman 1334197ba5f4SPaul Zimmerman gotgctl = readl(hsotg->regs + GOTGCTL); 1335197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl); 1336197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n", 1337197ba5f4SPaul Zimmerman !!(gotgctl & GOTGCTL_CONID_B)); 1338197ba5f4SPaul Zimmerman 1339197ba5f4SPaul Zimmerman /* B-Device connector (Device Mode) */ 1340197ba5f4SPaul Zimmerman if (gotgctl & GOTGCTL_CONID_B) { 1341197ba5f4SPaul Zimmerman /* Wait for switch to device mode */ 1342197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "connId B\n"); 1343197ba5f4SPaul Zimmerman while (!dwc2_is_device_mode(hsotg)) { 1344197ba5f4SPaul Zimmerman dev_info(hsotg->dev, 1345197ba5f4SPaul Zimmerman "Waiting for Peripheral Mode, Mode=%s\n", 1346197ba5f4SPaul Zimmerman dwc2_is_host_mode(hsotg) ? "Host" : 1347197ba5f4SPaul Zimmerman "Peripheral"); 1348197ba5f4SPaul Zimmerman usleep_range(20000, 40000); 1349197ba5f4SPaul Zimmerman if (++count > 250) 1350197ba5f4SPaul Zimmerman break; 1351197ba5f4SPaul Zimmerman } 1352197ba5f4SPaul Zimmerman if (count > 250) 1353197ba5f4SPaul Zimmerman dev_err(hsotg->dev, 1354197ba5f4SPaul Zimmerman "Connection id status change timed out\n"); 1355197ba5f4SPaul Zimmerman hsotg->op_state = OTG_STATE_B_PERIPHERAL; 1356197ba5f4SPaul Zimmerman dwc2_core_init(hsotg, false, -1); 1357197ba5f4SPaul Zimmerman dwc2_enable_global_interrupts(hsotg); 1358197ba5f4SPaul Zimmerman } else { 1359197ba5f4SPaul Zimmerman /* A-Device connector (Host Mode) */ 1360197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "connId A\n"); 1361197ba5f4SPaul Zimmerman while (!dwc2_is_host_mode(hsotg)) { 1362197ba5f4SPaul Zimmerman dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n", 1363197ba5f4SPaul Zimmerman dwc2_is_host_mode(hsotg) ? 1364197ba5f4SPaul Zimmerman "Host" : "Peripheral"); 1365197ba5f4SPaul Zimmerman usleep_range(20000, 40000); 1366197ba5f4SPaul Zimmerman if (++count > 250) 1367197ba5f4SPaul Zimmerman break; 1368197ba5f4SPaul Zimmerman } 1369197ba5f4SPaul Zimmerman if (count > 250) 1370197ba5f4SPaul Zimmerman dev_err(hsotg->dev, 1371197ba5f4SPaul Zimmerman "Connection id status change timed out\n"); 1372197ba5f4SPaul Zimmerman hsotg->op_state = OTG_STATE_A_HOST; 1373197ba5f4SPaul Zimmerman 1374197ba5f4SPaul Zimmerman /* Initialize the Core for Host mode */ 1375197ba5f4SPaul Zimmerman dwc2_core_init(hsotg, false, -1); 1376197ba5f4SPaul Zimmerman dwc2_enable_global_interrupts(hsotg); 1377197ba5f4SPaul Zimmerman dwc2_hcd_start(hsotg); 1378197ba5f4SPaul Zimmerman } 1379197ba5f4SPaul Zimmerman } 1380197ba5f4SPaul Zimmerman 1381197ba5f4SPaul Zimmerman static void dwc2_wakeup_detected(unsigned long data) 1382197ba5f4SPaul Zimmerman { 1383197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data; 1384197ba5f4SPaul Zimmerman u32 hprt0; 1385197ba5f4SPaul Zimmerman 1386197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "%s()\n", __func__); 1387197ba5f4SPaul Zimmerman 1388197ba5f4SPaul Zimmerman /* 1389197ba5f4SPaul Zimmerman * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms 1390197ba5f4SPaul Zimmerman * so that OPT tests pass with all PHYs.) 1391197ba5f4SPaul Zimmerman */ 1392197ba5f4SPaul Zimmerman hprt0 = dwc2_read_hprt0(hsotg); 1393197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0); 1394197ba5f4SPaul Zimmerman hprt0 &= ~HPRT0_RES; 1395197ba5f4SPaul Zimmerman writel(hprt0, hsotg->regs + HPRT0); 1396197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n", 1397197ba5f4SPaul Zimmerman readl(hsotg->regs + HPRT0)); 1398197ba5f4SPaul Zimmerman 1399197ba5f4SPaul Zimmerman dwc2_hcd_rem_wakeup(hsotg); 1400197ba5f4SPaul Zimmerman 1401197ba5f4SPaul Zimmerman /* Change to L0 state */ 1402197ba5f4SPaul Zimmerman hsotg->lx_state = DWC2_L0; 1403197ba5f4SPaul Zimmerman } 1404197ba5f4SPaul Zimmerman 1405197ba5f4SPaul Zimmerman static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg) 1406197ba5f4SPaul Zimmerman { 1407197ba5f4SPaul Zimmerman struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 1408197ba5f4SPaul Zimmerman 1409197ba5f4SPaul Zimmerman return hcd->self.b_hnp_enable; 1410197ba5f4SPaul Zimmerman } 1411197ba5f4SPaul Zimmerman 1412197ba5f4SPaul Zimmerman /* Must NOT be called with interrupt disabled or spinlock held */ 1413197ba5f4SPaul Zimmerman static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) 1414197ba5f4SPaul Zimmerman { 1415197ba5f4SPaul Zimmerman unsigned long flags; 1416197ba5f4SPaul Zimmerman u32 hprt0; 1417197ba5f4SPaul Zimmerman u32 pcgctl; 1418197ba5f4SPaul Zimmerman u32 gotgctl; 1419197ba5f4SPaul Zimmerman 1420197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "%s()\n", __func__); 1421197ba5f4SPaul Zimmerman 1422197ba5f4SPaul Zimmerman spin_lock_irqsave(&hsotg->lock, flags); 1423197ba5f4SPaul Zimmerman 1424197ba5f4SPaul Zimmerman if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) { 1425197ba5f4SPaul Zimmerman gotgctl = readl(hsotg->regs + GOTGCTL); 1426197ba5f4SPaul Zimmerman gotgctl |= GOTGCTL_HSTSETHNPEN; 1427197ba5f4SPaul Zimmerman writel(gotgctl, hsotg->regs + GOTGCTL); 1428197ba5f4SPaul Zimmerman hsotg->op_state = OTG_STATE_A_SUSPEND; 1429197ba5f4SPaul Zimmerman } 1430197ba5f4SPaul Zimmerman 1431197ba5f4SPaul Zimmerman hprt0 = dwc2_read_hprt0(hsotg); 1432197ba5f4SPaul Zimmerman hprt0 |= HPRT0_SUSP; 1433197ba5f4SPaul Zimmerman writel(hprt0, hsotg->regs + HPRT0); 1434197ba5f4SPaul Zimmerman 1435197ba5f4SPaul Zimmerman /* Update lx_state */ 1436197ba5f4SPaul Zimmerman hsotg->lx_state = DWC2_L2; 1437197ba5f4SPaul Zimmerman 1438197ba5f4SPaul Zimmerman /* Suspend the Phy Clock */ 1439197ba5f4SPaul Zimmerman pcgctl = readl(hsotg->regs + PCGCTL); 1440197ba5f4SPaul Zimmerman pcgctl |= PCGCTL_STOPPCLK; 1441197ba5f4SPaul Zimmerman writel(pcgctl, hsotg->regs + PCGCTL); 1442197ba5f4SPaul Zimmerman udelay(10); 1443197ba5f4SPaul Zimmerman 1444197ba5f4SPaul Zimmerman /* For HNP the bus must be suspended for at least 200ms */ 1445197ba5f4SPaul Zimmerman if (dwc2_host_is_b_hnp_enabled(hsotg)) { 1446197ba5f4SPaul Zimmerman pcgctl = readl(hsotg->regs + PCGCTL); 1447197ba5f4SPaul Zimmerman pcgctl &= ~PCGCTL_STOPPCLK; 1448197ba5f4SPaul Zimmerman writel(pcgctl, hsotg->regs + PCGCTL); 1449197ba5f4SPaul Zimmerman 1450197ba5f4SPaul Zimmerman spin_unlock_irqrestore(&hsotg->lock, flags); 1451197ba5f4SPaul Zimmerman 1452197ba5f4SPaul Zimmerman usleep_range(200000, 250000); 1453197ba5f4SPaul Zimmerman } else { 1454197ba5f4SPaul Zimmerman spin_unlock_irqrestore(&hsotg->lock, flags); 1455197ba5f4SPaul Zimmerman } 1456197ba5f4SPaul Zimmerman } 1457197ba5f4SPaul Zimmerman 1458197ba5f4SPaul Zimmerman /* Handles hub class-specific requests */ 1459197ba5f4SPaul Zimmerman static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, 1460197ba5f4SPaul Zimmerman u16 wvalue, u16 windex, char *buf, u16 wlength) 1461197ba5f4SPaul Zimmerman { 1462197ba5f4SPaul Zimmerman struct usb_hub_descriptor *hub_desc; 1463197ba5f4SPaul Zimmerman int retval = 0; 1464197ba5f4SPaul Zimmerman u32 hprt0; 1465197ba5f4SPaul Zimmerman u32 port_status; 1466197ba5f4SPaul Zimmerman u32 speed; 1467197ba5f4SPaul Zimmerman u32 pcgctl; 1468197ba5f4SPaul Zimmerman 1469197ba5f4SPaul Zimmerman switch (typereq) { 1470197ba5f4SPaul Zimmerman case ClearHubFeature: 1471197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue); 1472197ba5f4SPaul Zimmerman 1473197ba5f4SPaul Zimmerman switch (wvalue) { 1474197ba5f4SPaul Zimmerman case C_HUB_LOCAL_POWER: 1475197ba5f4SPaul Zimmerman case C_HUB_OVER_CURRENT: 1476197ba5f4SPaul Zimmerman /* Nothing required here */ 1477197ba5f4SPaul Zimmerman break; 1478197ba5f4SPaul Zimmerman 1479197ba5f4SPaul Zimmerman default: 1480197ba5f4SPaul Zimmerman retval = -EINVAL; 1481197ba5f4SPaul Zimmerman dev_err(hsotg->dev, 1482197ba5f4SPaul Zimmerman "ClearHubFeature request %1xh unknown\n", 1483197ba5f4SPaul Zimmerman wvalue); 1484197ba5f4SPaul Zimmerman } 1485197ba5f4SPaul Zimmerman break; 1486197ba5f4SPaul Zimmerman 1487197ba5f4SPaul Zimmerman case ClearPortFeature: 1488197ba5f4SPaul Zimmerman if (wvalue != USB_PORT_FEAT_L1) 1489197ba5f4SPaul Zimmerman if (!windex || windex > 1) 1490197ba5f4SPaul Zimmerman goto error; 1491197ba5f4SPaul Zimmerman switch (wvalue) { 1492197ba5f4SPaul Zimmerman case USB_PORT_FEAT_ENABLE: 1493197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 1494197ba5f4SPaul Zimmerman "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); 1495197ba5f4SPaul Zimmerman hprt0 = dwc2_read_hprt0(hsotg); 1496197ba5f4SPaul Zimmerman hprt0 |= HPRT0_ENA; 1497197ba5f4SPaul Zimmerman writel(hprt0, hsotg->regs + HPRT0); 1498197ba5f4SPaul Zimmerman break; 1499197ba5f4SPaul Zimmerman 1500197ba5f4SPaul Zimmerman case USB_PORT_FEAT_SUSPEND: 1501197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 1502197ba5f4SPaul Zimmerman "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); 1503197ba5f4SPaul Zimmerman writel(0, hsotg->regs + PCGCTL); 1504197ba5f4SPaul Zimmerman usleep_range(20000, 40000); 1505197ba5f4SPaul Zimmerman 1506197ba5f4SPaul Zimmerman hprt0 = dwc2_read_hprt0(hsotg); 1507197ba5f4SPaul Zimmerman hprt0 |= HPRT0_RES; 1508197ba5f4SPaul Zimmerman writel(hprt0, hsotg->regs + HPRT0); 1509197ba5f4SPaul Zimmerman hprt0 &= ~HPRT0_SUSP; 1510197ba5f4SPaul Zimmerman usleep_range(100000, 150000); 1511197ba5f4SPaul Zimmerman 1512197ba5f4SPaul Zimmerman hprt0 &= ~HPRT0_RES; 1513197ba5f4SPaul Zimmerman writel(hprt0, hsotg->regs + HPRT0); 1514197ba5f4SPaul Zimmerman break; 1515197ba5f4SPaul Zimmerman 1516197ba5f4SPaul Zimmerman case USB_PORT_FEAT_POWER: 1517197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 1518197ba5f4SPaul Zimmerman "ClearPortFeature USB_PORT_FEAT_POWER\n"); 1519197ba5f4SPaul Zimmerman hprt0 = dwc2_read_hprt0(hsotg); 1520197ba5f4SPaul Zimmerman hprt0 &= ~HPRT0_PWR; 1521197ba5f4SPaul Zimmerman writel(hprt0, hsotg->regs + HPRT0); 1522197ba5f4SPaul Zimmerman break; 1523197ba5f4SPaul Zimmerman 1524197ba5f4SPaul Zimmerman case USB_PORT_FEAT_INDICATOR: 1525197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 1526197ba5f4SPaul Zimmerman "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); 1527197ba5f4SPaul Zimmerman /* Port indicator not supported */ 1528197ba5f4SPaul Zimmerman break; 1529197ba5f4SPaul Zimmerman 1530197ba5f4SPaul Zimmerman case USB_PORT_FEAT_C_CONNECTION: 1531197ba5f4SPaul Zimmerman /* 1532197ba5f4SPaul Zimmerman * Clears driver's internal Connect Status Change flag 1533197ba5f4SPaul Zimmerman */ 1534197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 1535197ba5f4SPaul Zimmerman "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); 1536197ba5f4SPaul Zimmerman hsotg->flags.b.port_connect_status_change = 0; 1537197ba5f4SPaul Zimmerman break; 1538197ba5f4SPaul Zimmerman 1539197ba5f4SPaul Zimmerman case USB_PORT_FEAT_C_RESET: 1540197ba5f4SPaul Zimmerman /* Clears driver's internal Port Reset Change flag */ 1541197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 1542197ba5f4SPaul Zimmerman "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); 1543197ba5f4SPaul Zimmerman hsotg->flags.b.port_reset_change = 0; 1544197ba5f4SPaul Zimmerman break; 1545197ba5f4SPaul Zimmerman 1546197ba5f4SPaul Zimmerman case USB_PORT_FEAT_C_ENABLE: 1547197ba5f4SPaul Zimmerman /* 1548197ba5f4SPaul Zimmerman * Clears the driver's internal Port Enable/Disable 1549197ba5f4SPaul Zimmerman * Change flag 1550197ba5f4SPaul Zimmerman */ 1551197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 1552197ba5f4SPaul Zimmerman "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); 1553197ba5f4SPaul Zimmerman hsotg->flags.b.port_enable_change = 0; 1554197ba5f4SPaul Zimmerman break; 1555197ba5f4SPaul Zimmerman 1556197ba5f4SPaul Zimmerman case USB_PORT_FEAT_C_SUSPEND: 1557197ba5f4SPaul Zimmerman /* 1558197ba5f4SPaul Zimmerman * Clears the driver's internal Port Suspend Change 1559197ba5f4SPaul Zimmerman * flag, which is set when resume signaling on the host 1560197ba5f4SPaul Zimmerman * port is complete 1561197ba5f4SPaul Zimmerman */ 1562197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 1563197ba5f4SPaul Zimmerman "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); 1564197ba5f4SPaul Zimmerman hsotg->flags.b.port_suspend_change = 0; 1565197ba5f4SPaul Zimmerman break; 1566197ba5f4SPaul Zimmerman 1567197ba5f4SPaul Zimmerman case USB_PORT_FEAT_C_PORT_L1: 1568197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 1569197ba5f4SPaul Zimmerman "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n"); 1570197ba5f4SPaul Zimmerman hsotg->flags.b.port_l1_change = 0; 1571197ba5f4SPaul Zimmerman break; 1572197ba5f4SPaul Zimmerman 1573197ba5f4SPaul Zimmerman case USB_PORT_FEAT_C_OVER_CURRENT: 1574197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 1575197ba5f4SPaul Zimmerman "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); 1576197ba5f4SPaul Zimmerman hsotg->flags.b.port_over_current_change = 0; 1577197ba5f4SPaul Zimmerman break; 1578197ba5f4SPaul Zimmerman 1579197ba5f4SPaul Zimmerman default: 1580197ba5f4SPaul Zimmerman retval = -EINVAL; 1581197ba5f4SPaul Zimmerman dev_err(hsotg->dev, 1582197ba5f4SPaul Zimmerman "ClearPortFeature request %1xh unknown or unsupported\n", 1583197ba5f4SPaul Zimmerman wvalue); 1584197ba5f4SPaul Zimmerman } 1585197ba5f4SPaul Zimmerman break; 1586197ba5f4SPaul Zimmerman 1587197ba5f4SPaul Zimmerman case GetHubDescriptor: 1588197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "GetHubDescriptor\n"); 1589197ba5f4SPaul Zimmerman hub_desc = (struct usb_hub_descriptor *)buf; 1590197ba5f4SPaul Zimmerman hub_desc->bDescLength = 9; 1591197ba5f4SPaul Zimmerman hub_desc->bDescriptorType = 0x29; 1592197ba5f4SPaul Zimmerman hub_desc->bNbrPorts = 1; 1593197ba5f4SPaul Zimmerman hub_desc->wHubCharacteristics = cpu_to_le16(0x08); 1594197ba5f4SPaul Zimmerman hub_desc->bPwrOn2PwrGood = 1; 1595197ba5f4SPaul Zimmerman hub_desc->bHubContrCurrent = 0; 1596197ba5f4SPaul Zimmerman hub_desc->u.hs.DeviceRemovable[0] = 0; 1597197ba5f4SPaul Zimmerman hub_desc->u.hs.DeviceRemovable[1] = 0xff; 1598197ba5f4SPaul Zimmerman break; 1599197ba5f4SPaul Zimmerman 1600197ba5f4SPaul Zimmerman case GetHubStatus: 1601197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "GetHubStatus\n"); 1602197ba5f4SPaul Zimmerman memset(buf, 0, 4); 1603197ba5f4SPaul Zimmerman break; 1604197ba5f4SPaul Zimmerman 1605197ba5f4SPaul Zimmerman case GetPortStatus: 1606197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, 1607197ba5f4SPaul Zimmerman "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex, 1608197ba5f4SPaul Zimmerman hsotg->flags.d32); 1609197ba5f4SPaul Zimmerman if (!windex || windex > 1) 1610197ba5f4SPaul Zimmerman goto error; 1611197ba5f4SPaul Zimmerman 1612197ba5f4SPaul Zimmerman port_status = 0; 1613197ba5f4SPaul Zimmerman if (hsotg->flags.b.port_connect_status_change) 1614197ba5f4SPaul Zimmerman port_status |= USB_PORT_STAT_C_CONNECTION << 16; 1615197ba5f4SPaul Zimmerman if (hsotg->flags.b.port_enable_change) 1616197ba5f4SPaul Zimmerman port_status |= USB_PORT_STAT_C_ENABLE << 16; 1617197ba5f4SPaul Zimmerman if (hsotg->flags.b.port_suspend_change) 1618197ba5f4SPaul Zimmerman port_status |= USB_PORT_STAT_C_SUSPEND << 16; 1619197ba5f4SPaul Zimmerman if (hsotg->flags.b.port_l1_change) 1620197ba5f4SPaul Zimmerman port_status |= USB_PORT_STAT_C_L1 << 16; 1621197ba5f4SPaul Zimmerman if (hsotg->flags.b.port_reset_change) 1622197ba5f4SPaul Zimmerman port_status |= USB_PORT_STAT_C_RESET << 16; 1623197ba5f4SPaul Zimmerman if (hsotg->flags.b.port_over_current_change) { 1624197ba5f4SPaul Zimmerman dev_warn(hsotg->dev, "Overcurrent change detected\n"); 1625197ba5f4SPaul Zimmerman port_status |= USB_PORT_STAT_C_OVERCURRENT << 16; 1626197ba5f4SPaul Zimmerman } 1627197ba5f4SPaul Zimmerman 1628197ba5f4SPaul Zimmerman if (!hsotg->flags.b.port_connect_status) { 1629197ba5f4SPaul Zimmerman /* 1630197ba5f4SPaul Zimmerman * The port is disconnected, which means the core is 1631197ba5f4SPaul Zimmerman * either in device mode or it soon will be. Just 1632197ba5f4SPaul Zimmerman * return 0's for the remainder of the port status 1633197ba5f4SPaul Zimmerman * since the port register can't be read if the core 1634197ba5f4SPaul Zimmerman * is in device mode. 1635197ba5f4SPaul Zimmerman */ 1636197ba5f4SPaul Zimmerman *(__le32 *)buf = cpu_to_le32(port_status); 1637197ba5f4SPaul Zimmerman break; 1638197ba5f4SPaul Zimmerman } 1639197ba5f4SPaul Zimmerman 1640197ba5f4SPaul Zimmerman hprt0 = readl(hsotg->regs + HPRT0); 1641197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0); 1642197ba5f4SPaul Zimmerman 1643197ba5f4SPaul Zimmerman if (hprt0 & HPRT0_CONNSTS) 1644197ba5f4SPaul Zimmerman port_status |= USB_PORT_STAT_CONNECTION; 1645197ba5f4SPaul Zimmerman if (hprt0 & HPRT0_ENA) 1646197ba5f4SPaul Zimmerman port_status |= USB_PORT_STAT_ENABLE; 1647197ba5f4SPaul Zimmerman if (hprt0 & HPRT0_SUSP) 1648197ba5f4SPaul Zimmerman port_status |= USB_PORT_STAT_SUSPEND; 1649197ba5f4SPaul Zimmerman if (hprt0 & HPRT0_OVRCURRACT) 1650197ba5f4SPaul Zimmerman port_status |= USB_PORT_STAT_OVERCURRENT; 1651197ba5f4SPaul Zimmerman if (hprt0 & HPRT0_RST) 1652197ba5f4SPaul Zimmerman port_status |= USB_PORT_STAT_RESET; 1653197ba5f4SPaul Zimmerman if (hprt0 & HPRT0_PWR) 1654197ba5f4SPaul Zimmerman port_status |= USB_PORT_STAT_POWER; 1655197ba5f4SPaul Zimmerman 1656197ba5f4SPaul Zimmerman speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 1657197ba5f4SPaul Zimmerman if (speed == HPRT0_SPD_HIGH_SPEED) 1658197ba5f4SPaul Zimmerman port_status |= USB_PORT_STAT_HIGH_SPEED; 1659197ba5f4SPaul Zimmerman else if (speed == HPRT0_SPD_LOW_SPEED) 1660197ba5f4SPaul Zimmerman port_status |= USB_PORT_STAT_LOW_SPEED; 1661197ba5f4SPaul Zimmerman 1662197ba5f4SPaul Zimmerman if (hprt0 & HPRT0_TSTCTL_MASK) 1663197ba5f4SPaul Zimmerman port_status |= USB_PORT_STAT_TEST; 1664197ba5f4SPaul Zimmerman /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ 1665197ba5f4SPaul Zimmerman 1666197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status); 1667197ba5f4SPaul Zimmerman *(__le32 *)buf = cpu_to_le32(port_status); 1668197ba5f4SPaul Zimmerman break; 1669197ba5f4SPaul Zimmerman 1670197ba5f4SPaul Zimmerman case SetHubFeature: 1671197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "SetHubFeature\n"); 1672197ba5f4SPaul Zimmerman /* No HUB features supported */ 1673197ba5f4SPaul Zimmerman break; 1674197ba5f4SPaul Zimmerman 1675197ba5f4SPaul Zimmerman case SetPortFeature: 1676197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "SetPortFeature\n"); 1677197ba5f4SPaul Zimmerman if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1)) 1678197ba5f4SPaul Zimmerman goto error; 1679197ba5f4SPaul Zimmerman 1680197ba5f4SPaul Zimmerman if (!hsotg->flags.b.port_connect_status) { 1681197ba5f4SPaul Zimmerman /* 1682197ba5f4SPaul Zimmerman * The port is disconnected, which means the core is 1683197ba5f4SPaul Zimmerman * either in device mode or it soon will be. Just 1684197ba5f4SPaul Zimmerman * return without doing anything since the port 1685197ba5f4SPaul Zimmerman * register can't be written if the core is in device 1686197ba5f4SPaul Zimmerman * mode. 1687197ba5f4SPaul Zimmerman */ 1688197ba5f4SPaul Zimmerman break; 1689197ba5f4SPaul Zimmerman } 1690197ba5f4SPaul Zimmerman 1691197ba5f4SPaul Zimmerman switch (wvalue) { 1692197ba5f4SPaul Zimmerman case USB_PORT_FEAT_SUSPEND: 1693197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 1694197ba5f4SPaul Zimmerman "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); 1695197ba5f4SPaul Zimmerman if (windex != hsotg->otg_port) 1696197ba5f4SPaul Zimmerman goto error; 1697197ba5f4SPaul Zimmerman dwc2_port_suspend(hsotg, windex); 1698197ba5f4SPaul Zimmerman break; 1699197ba5f4SPaul Zimmerman 1700197ba5f4SPaul Zimmerman case USB_PORT_FEAT_POWER: 1701197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 1702197ba5f4SPaul Zimmerman "SetPortFeature - USB_PORT_FEAT_POWER\n"); 1703197ba5f4SPaul Zimmerman hprt0 = dwc2_read_hprt0(hsotg); 1704197ba5f4SPaul Zimmerman hprt0 |= HPRT0_PWR; 1705197ba5f4SPaul Zimmerman writel(hprt0, hsotg->regs + HPRT0); 1706197ba5f4SPaul Zimmerman break; 1707197ba5f4SPaul Zimmerman 1708197ba5f4SPaul Zimmerman case USB_PORT_FEAT_RESET: 1709197ba5f4SPaul Zimmerman hprt0 = dwc2_read_hprt0(hsotg); 1710197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 1711197ba5f4SPaul Zimmerman "SetPortFeature - USB_PORT_FEAT_RESET\n"); 1712197ba5f4SPaul Zimmerman pcgctl = readl(hsotg->regs + PCGCTL); 1713197ba5f4SPaul Zimmerman pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK); 1714197ba5f4SPaul Zimmerman writel(pcgctl, hsotg->regs + PCGCTL); 1715197ba5f4SPaul Zimmerman /* ??? Original driver does this */ 1716197ba5f4SPaul Zimmerman writel(0, hsotg->regs + PCGCTL); 1717197ba5f4SPaul Zimmerman 1718197ba5f4SPaul Zimmerman hprt0 = dwc2_read_hprt0(hsotg); 1719197ba5f4SPaul Zimmerman /* Clear suspend bit if resetting from suspend state */ 1720197ba5f4SPaul Zimmerman hprt0 &= ~HPRT0_SUSP; 1721197ba5f4SPaul Zimmerman 1722197ba5f4SPaul Zimmerman /* 1723197ba5f4SPaul Zimmerman * When B-Host the Port reset bit is set in the Start 1724197ba5f4SPaul Zimmerman * HCD Callback function, so that the reset is started 1725197ba5f4SPaul Zimmerman * within 1ms of the HNP success interrupt 1726197ba5f4SPaul Zimmerman */ 1727197ba5f4SPaul Zimmerman if (!dwc2_hcd_is_b_host(hsotg)) { 1728197ba5f4SPaul Zimmerman hprt0 |= HPRT0_PWR | HPRT0_RST; 1729197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 1730197ba5f4SPaul Zimmerman "In host mode, hprt0=%08x\n", hprt0); 1731197ba5f4SPaul Zimmerman writel(hprt0, hsotg->regs + HPRT0); 1732197ba5f4SPaul Zimmerman } 1733197ba5f4SPaul Zimmerman 1734197ba5f4SPaul Zimmerman /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ 1735197ba5f4SPaul Zimmerman usleep_range(50000, 70000); 1736197ba5f4SPaul Zimmerman hprt0 &= ~HPRT0_RST; 1737197ba5f4SPaul Zimmerman writel(hprt0, hsotg->regs + HPRT0); 1738197ba5f4SPaul Zimmerman hsotg->lx_state = DWC2_L0; /* Now back to On state */ 1739197ba5f4SPaul Zimmerman break; 1740197ba5f4SPaul Zimmerman 1741197ba5f4SPaul Zimmerman case USB_PORT_FEAT_INDICATOR: 1742197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 1743197ba5f4SPaul Zimmerman "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); 1744197ba5f4SPaul Zimmerman /* Not supported */ 1745197ba5f4SPaul Zimmerman break; 1746197ba5f4SPaul Zimmerman 1747197ba5f4SPaul Zimmerman default: 1748197ba5f4SPaul Zimmerman retval = -EINVAL; 1749197ba5f4SPaul Zimmerman dev_err(hsotg->dev, 1750197ba5f4SPaul Zimmerman "SetPortFeature %1xh unknown or unsupported\n", 1751197ba5f4SPaul Zimmerman wvalue); 1752197ba5f4SPaul Zimmerman break; 1753197ba5f4SPaul Zimmerman } 1754197ba5f4SPaul Zimmerman break; 1755197ba5f4SPaul Zimmerman 1756197ba5f4SPaul Zimmerman default: 1757197ba5f4SPaul Zimmerman error: 1758197ba5f4SPaul Zimmerman retval = -EINVAL; 1759197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 1760197ba5f4SPaul Zimmerman "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n", 1761197ba5f4SPaul Zimmerman typereq, windex, wvalue); 1762197ba5f4SPaul Zimmerman break; 1763197ba5f4SPaul Zimmerman } 1764197ba5f4SPaul Zimmerman 1765197ba5f4SPaul Zimmerman return retval; 1766197ba5f4SPaul Zimmerman } 1767197ba5f4SPaul Zimmerman 1768197ba5f4SPaul Zimmerman static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port) 1769197ba5f4SPaul Zimmerman { 1770197ba5f4SPaul Zimmerman int retval; 1771197ba5f4SPaul Zimmerman 1772197ba5f4SPaul Zimmerman if (port != 1) 1773197ba5f4SPaul Zimmerman return -EINVAL; 1774197ba5f4SPaul Zimmerman 1775197ba5f4SPaul Zimmerman retval = (hsotg->flags.b.port_connect_status_change || 1776197ba5f4SPaul Zimmerman hsotg->flags.b.port_reset_change || 1777197ba5f4SPaul Zimmerman hsotg->flags.b.port_enable_change || 1778197ba5f4SPaul Zimmerman hsotg->flags.b.port_suspend_change || 1779197ba5f4SPaul Zimmerman hsotg->flags.b.port_over_current_change); 1780197ba5f4SPaul Zimmerman 1781197ba5f4SPaul Zimmerman if (retval) { 1782197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 1783197ba5f4SPaul Zimmerman "DWC OTG HCD HUB STATUS DATA: Root port status changed\n"); 1784197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " port_connect_status_change: %d\n", 1785197ba5f4SPaul Zimmerman hsotg->flags.b.port_connect_status_change); 1786197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " port_reset_change: %d\n", 1787197ba5f4SPaul Zimmerman hsotg->flags.b.port_reset_change); 1788197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " port_enable_change: %d\n", 1789197ba5f4SPaul Zimmerman hsotg->flags.b.port_enable_change); 1790197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " port_suspend_change: %d\n", 1791197ba5f4SPaul Zimmerman hsotg->flags.b.port_suspend_change); 1792197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " port_over_current_change: %d\n", 1793197ba5f4SPaul Zimmerman hsotg->flags.b.port_over_current_change); 1794197ba5f4SPaul Zimmerman } 1795197ba5f4SPaul Zimmerman 1796197ba5f4SPaul Zimmerman return retval; 1797197ba5f4SPaul Zimmerman } 1798197ba5f4SPaul Zimmerman 1799197ba5f4SPaul Zimmerman int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1800197ba5f4SPaul Zimmerman { 1801197ba5f4SPaul Zimmerman u32 hfnum = readl(hsotg->regs + HFNUM); 1802197ba5f4SPaul Zimmerman 1803197ba5f4SPaul Zimmerman #ifdef DWC2_DEBUG_SOF 1804197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n", 1805197ba5f4SPaul Zimmerman (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT); 1806197ba5f4SPaul Zimmerman #endif 1807197ba5f4SPaul Zimmerman return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 1808197ba5f4SPaul Zimmerman } 1809197ba5f4SPaul Zimmerman 1810197ba5f4SPaul Zimmerman int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg) 1811197ba5f4SPaul Zimmerman { 1812197ba5f4SPaul Zimmerman return hsotg->op_state == OTG_STATE_B_HOST; 1813197ba5f4SPaul Zimmerman } 1814197ba5f4SPaul Zimmerman 1815197ba5f4SPaul Zimmerman static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg, 1816197ba5f4SPaul Zimmerman int iso_desc_count, 1817197ba5f4SPaul Zimmerman gfp_t mem_flags) 1818197ba5f4SPaul Zimmerman { 1819197ba5f4SPaul Zimmerman struct dwc2_hcd_urb *urb; 1820197ba5f4SPaul Zimmerman u32 size = sizeof(*urb) + iso_desc_count * 1821197ba5f4SPaul Zimmerman sizeof(struct dwc2_hcd_iso_packet_desc); 1822197ba5f4SPaul Zimmerman 1823197ba5f4SPaul Zimmerman urb = kzalloc(size, mem_flags); 1824197ba5f4SPaul Zimmerman if (urb) 1825197ba5f4SPaul Zimmerman urb->packet_count = iso_desc_count; 1826197ba5f4SPaul Zimmerman return urb; 1827197ba5f4SPaul Zimmerman } 1828197ba5f4SPaul Zimmerman 1829197ba5f4SPaul Zimmerman static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg, 1830197ba5f4SPaul Zimmerman struct dwc2_hcd_urb *urb, u8 dev_addr, 1831197ba5f4SPaul Zimmerman u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps) 1832197ba5f4SPaul Zimmerman { 1833197ba5f4SPaul Zimmerman if (dbg_perio() || 1834197ba5f4SPaul Zimmerman ep_type == USB_ENDPOINT_XFER_BULK || 1835197ba5f4SPaul Zimmerman ep_type == USB_ENDPOINT_XFER_CONTROL) 1836197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, 1837197ba5f4SPaul Zimmerman "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n", 1838197ba5f4SPaul Zimmerman dev_addr, ep_num, ep_dir, ep_type, mps); 1839197ba5f4SPaul Zimmerman urb->pipe_info.dev_addr = dev_addr; 1840197ba5f4SPaul Zimmerman urb->pipe_info.ep_num = ep_num; 1841197ba5f4SPaul Zimmerman urb->pipe_info.pipe_type = ep_type; 1842197ba5f4SPaul Zimmerman urb->pipe_info.pipe_dir = ep_dir; 1843197ba5f4SPaul Zimmerman urb->pipe_info.mps = mps; 1844197ba5f4SPaul Zimmerman } 1845197ba5f4SPaul Zimmerman 1846197ba5f4SPaul Zimmerman /* 1847197ba5f4SPaul Zimmerman * NOTE: This function will be removed once the peripheral controller code 1848197ba5f4SPaul Zimmerman * is integrated and the driver is stable 1849197ba5f4SPaul Zimmerman */ 1850197ba5f4SPaul Zimmerman void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg) 1851197ba5f4SPaul Zimmerman { 1852197ba5f4SPaul Zimmerman #ifdef DEBUG 1853197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan; 1854197ba5f4SPaul Zimmerman struct dwc2_hcd_urb *urb; 1855197ba5f4SPaul Zimmerman struct dwc2_qtd *qtd; 1856197ba5f4SPaul Zimmerman int num_channels; 1857197ba5f4SPaul Zimmerman u32 np_tx_status; 1858197ba5f4SPaul Zimmerman u32 p_tx_status; 1859197ba5f4SPaul Zimmerman int i; 1860197ba5f4SPaul Zimmerman 1861197ba5f4SPaul Zimmerman num_channels = hsotg->core_params->host_channels; 1862197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "\n"); 1863197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 1864197ba5f4SPaul Zimmerman "************************************************************\n"); 1865197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "HCD State:\n"); 1866197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels); 1867197ba5f4SPaul Zimmerman 1868197ba5f4SPaul Zimmerman for (i = 0; i < num_channels; i++) { 1869197ba5f4SPaul Zimmerman chan = hsotg->hc_ptr_array[i]; 1870197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " Channel %d:\n", i); 1871197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 1872197ba5f4SPaul Zimmerman " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 1873197ba5f4SPaul Zimmerman chan->dev_addr, chan->ep_num, chan->ep_is_in); 1874197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " speed: %d\n", chan->speed); 1875197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 1876197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 1877197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " data_pid_start: %d\n", 1878197ba5f4SPaul Zimmerman chan->data_pid_start); 1879197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count); 1880197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " xfer_started: %d\n", 1881197ba5f4SPaul Zimmerman chan->xfer_started); 1882197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 1883197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 1884197ba5f4SPaul Zimmerman (unsigned long)chan->xfer_dma); 1885197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 1886197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count); 1887197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " halt_on_queue: %d\n", 1888197ba5f4SPaul Zimmerman chan->halt_on_queue); 1889197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " halt_pending: %d\n", 1890197ba5f4SPaul Zimmerman chan->halt_pending); 1891197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 1892197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split); 1893197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " complete_split: %d\n", 1894197ba5f4SPaul Zimmerman chan->complete_split); 1895197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr); 1896197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port); 1897197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos); 1898197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " requests: %d\n", chan->requests); 1899197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 1900197ba5f4SPaul Zimmerman 1901197ba5f4SPaul Zimmerman if (chan->xfer_started) { 1902197ba5f4SPaul Zimmerman u32 hfnum, hcchar, hctsiz, hcint, hcintmsk; 1903197ba5f4SPaul Zimmerman 1904197ba5f4SPaul Zimmerman hfnum = readl(hsotg->regs + HFNUM); 1905197ba5f4SPaul Zimmerman hcchar = readl(hsotg->regs + HCCHAR(i)); 1906197ba5f4SPaul Zimmerman hctsiz = readl(hsotg->regs + HCTSIZ(i)); 1907197ba5f4SPaul Zimmerman hcint = readl(hsotg->regs + HCINT(i)); 1908197ba5f4SPaul Zimmerman hcintmsk = readl(hsotg->regs + HCINTMSK(i)); 1909197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum); 1910197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar); 1911197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz); 1912197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint); 1913197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk); 1914197ba5f4SPaul Zimmerman } 1915197ba5f4SPaul Zimmerman 1916197ba5f4SPaul Zimmerman if (!(chan->xfer_started && chan->qh)) 1917197ba5f4SPaul Zimmerman continue; 1918197ba5f4SPaul Zimmerman 1919197ba5f4SPaul Zimmerman list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) { 1920197ba5f4SPaul Zimmerman if (!qtd->in_process) 1921197ba5f4SPaul Zimmerman break; 1922197ba5f4SPaul Zimmerman urb = qtd->urb; 1923197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " URB Info:\n"); 1924197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n", 1925197ba5f4SPaul Zimmerman qtd, urb); 1926197ba5f4SPaul Zimmerman if (urb) { 1927197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 1928197ba5f4SPaul Zimmerman " Dev: %d, EP: %d %s\n", 1929197ba5f4SPaul Zimmerman dwc2_hcd_get_dev_addr(&urb->pipe_info), 1930197ba5f4SPaul Zimmerman dwc2_hcd_get_ep_num(&urb->pipe_info), 1931197ba5f4SPaul Zimmerman dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 1932197ba5f4SPaul Zimmerman "IN" : "OUT"); 1933197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 1934197ba5f4SPaul Zimmerman " Max packet size: %d\n", 1935197ba5f4SPaul Zimmerman dwc2_hcd_get_mps(&urb->pipe_info)); 1936197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 1937197ba5f4SPaul Zimmerman " transfer_buffer: %p\n", 1938197ba5f4SPaul Zimmerman urb->buf); 1939197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 1940197ba5f4SPaul Zimmerman " transfer_dma: %08lx\n", 1941197ba5f4SPaul Zimmerman (unsigned long)urb->dma); 1942197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 1943197ba5f4SPaul Zimmerman " transfer_buffer_length: %d\n", 1944197ba5f4SPaul Zimmerman urb->length); 1945197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " actual_length: %d\n", 1946197ba5f4SPaul Zimmerman urb->actual_length); 1947197ba5f4SPaul Zimmerman } 1948197ba5f4SPaul Zimmerman } 1949197ba5f4SPaul Zimmerman } 1950197ba5f4SPaul Zimmerman 1951197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " non_periodic_channels: %d\n", 1952197ba5f4SPaul Zimmerman hsotg->non_periodic_channels); 1953197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " periodic_channels: %d\n", 1954197ba5f4SPaul Zimmerman hsotg->periodic_channels); 1955197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs); 1956197ba5f4SPaul Zimmerman np_tx_status = readl(hsotg->regs + GNPTXSTS); 1957197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n", 1958197ba5f4SPaul Zimmerman (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 1959197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n", 1960197ba5f4SPaul Zimmerman (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 1961197ba5f4SPaul Zimmerman p_tx_status = readl(hsotg->regs + HPTXSTS); 1962197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n", 1963197ba5f4SPaul Zimmerman (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 1964197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n", 1965197ba5f4SPaul Zimmerman (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 1966197ba5f4SPaul Zimmerman dwc2_hcd_dump_frrem(hsotg); 1967197ba5f4SPaul Zimmerman dwc2_dump_global_registers(hsotg); 1968197ba5f4SPaul Zimmerman dwc2_dump_host_registers(hsotg); 1969197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 1970197ba5f4SPaul Zimmerman "************************************************************\n"); 1971197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "\n"); 1972197ba5f4SPaul Zimmerman #endif 1973197ba5f4SPaul Zimmerman } 1974197ba5f4SPaul Zimmerman 1975197ba5f4SPaul Zimmerman /* 1976197ba5f4SPaul Zimmerman * NOTE: This function will be removed once the peripheral controller code 1977197ba5f4SPaul Zimmerman * is integrated and the driver is stable 1978197ba5f4SPaul Zimmerman */ 1979197ba5f4SPaul Zimmerman void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg) 1980197ba5f4SPaul Zimmerman { 1981197ba5f4SPaul Zimmerman #ifdef DWC2_DUMP_FRREM 1982197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "Frame remaining at SOF:\n"); 1983197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1984197ba5f4SPaul Zimmerman hsotg->frrem_samples, hsotg->frrem_accum, 1985197ba5f4SPaul Zimmerman hsotg->frrem_samples > 0 ? 1986197ba5f4SPaul Zimmerman hsotg->frrem_accum / hsotg->frrem_samples : 0); 1987197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "\n"); 1988197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n"); 1989197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1990197ba5f4SPaul Zimmerman hsotg->hfnum_7_samples, 1991197ba5f4SPaul Zimmerman hsotg->hfnum_7_frrem_accum, 1992197ba5f4SPaul Zimmerman hsotg->hfnum_7_samples > 0 ? 1993197ba5f4SPaul Zimmerman hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0); 1994197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n"); 1995197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 1996197ba5f4SPaul Zimmerman hsotg->hfnum_0_samples, 1997197ba5f4SPaul Zimmerman hsotg->hfnum_0_frrem_accum, 1998197ba5f4SPaul Zimmerman hsotg->hfnum_0_samples > 0 ? 1999197ba5f4SPaul Zimmerman hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0); 2000197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n"); 2001197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2002197ba5f4SPaul Zimmerman hsotg->hfnum_other_samples, 2003197ba5f4SPaul Zimmerman hsotg->hfnum_other_frrem_accum, 2004197ba5f4SPaul Zimmerman hsotg->hfnum_other_samples > 0 ? 2005197ba5f4SPaul Zimmerman hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples : 2006197ba5f4SPaul Zimmerman 0); 2007197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "\n"); 2008197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n"); 2009197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2010197ba5f4SPaul Zimmerman hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a, 2011197ba5f4SPaul Zimmerman hsotg->hfnum_7_samples_a > 0 ? 2012197ba5f4SPaul Zimmerman hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0); 2013197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n"); 2014197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2015197ba5f4SPaul Zimmerman hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a, 2016197ba5f4SPaul Zimmerman hsotg->hfnum_0_samples_a > 0 ? 2017197ba5f4SPaul Zimmerman hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0); 2018197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n"); 2019197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2020197ba5f4SPaul Zimmerman hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a, 2021197ba5f4SPaul Zimmerman hsotg->hfnum_other_samples_a > 0 ? 2022197ba5f4SPaul Zimmerman hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a 2023197ba5f4SPaul Zimmerman : 0); 2024197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "\n"); 2025197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n"); 2026197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2027197ba5f4SPaul Zimmerman hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b, 2028197ba5f4SPaul Zimmerman hsotg->hfnum_7_samples_b > 0 ? 2029197ba5f4SPaul Zimmerman hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0); 2030197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n"); 2031197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2032197ba5f4SPaul Zimmerman hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b, 2033197ba5f4SPaul Zimmerman (hsotg->hfnum_0_samples_b > 0) ? 2034197ba5f4SPaul Zimmerman hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0); 2035197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n"); 2036197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2037197ba5f4SPaul Zimmerman hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b, 2038197ba5f4SPaul Zimmerman (hsotg->hfnum_other_samples_b > 0) ? 2039197ba5f4SPaul Zimmerman hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b 2040197ba5f4SPaul Zimmerman : 0); 2041197ba5f4SPaul Zimmerman #endif 2042197ba5f4SPaul Zimmerman } 2043197ba5f4SPaul Zimmerman 2044197ba5f4SPaul Zimmerman struct wrapper_priv_data { 2045197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg; 2046197ba5f4SPaul Zimmerman }; 2047197ba5f4SPaul Zimmerman 2048197ba5f4SPaul Zimmerman /* Gets the dwc2_hsotg from a usb_hcd */ 2049197ba5f4SPaul Zimmerman static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd) 2050197ba5f4SPaul Zimmerman { 2051197ba5f4SPaul Zimmerman struct wrapper_priv_data *p; 2052197ba5f4SPaul Zimmerman 2053197ba5f4SPaul Zimmerman p = (struct wrapper_priv_data *) &hcd->hcd_priv; 2054197ba5f4SPaul Zimmerman return p->hsotg; 2055197ba5f4SPaul Zimmerman } 2056197ba5f4SPaul Zimmerman 2057197ba5f4SPaul Zimmerman static int _dwc2_hcd_start(struct usb_hcd *hcd); 2058197ba5f4SPaul Zimmerman 2059197ba5f4SPaul Zimmerman void dwc2_host_start(struct dwc2_hsotg *hsotg) 2060197ba5f4SPaul Zimmerman { 2061197ba5f4SPaul Zimmerman struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 2062197ba5f4SPaul Zimmerman 2063197ba5f4SPaul Zimmerman hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg); 2064197ba5f4SPaul Zimmerman _dwc2_hcd_start(hcd); 2065197ba5f4SPaul Zimmerman } 2066197ba5f4SPaul Zimmerman 2067197ba5f4SPaul Zimmerman void dwc2_host_disconnect(struct dwc2_hsotg *hsotg) 2068197ba5f4SPaul Zimmerman { 2069197ba5f4SPaul Zimmerman struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 2070197ba5f4SPaul Zimmerman 2071197ba5f4SPaul Zimmerman hcd->self.is_b_host = 0; 2072197ba5f4SPaul Zimmerman } 2073197ba5f4SPaul Zimmerman 2074197ba5f4SPaul Zimmerman void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr, 2075197ba5f4SPaul Zimmerman int *hub_port) 2076197ba5f4SPaul Zimmerman { 2077197ba5f4SPaul Zimmerman struct urb *urb = context; 2078197ba5f4SPaul Zimmerman 2079197ba5f4SPaul Zimmerman if (urb->dev->tt) 2080197ba5f4SPaul Zimmerman *hub_addr = urb->dev->tt->hub->devnum; 2081197ba5f4SPaul Zimmerman else 2082197ba5f4SPaul Zimmerman *hub_addr = 0; 2083197ba5f4SPaul Zimmerman *hub_port = urb->dev->ttport; 2084197ba5f4SPaul Zimmerman } 2085197ba5f4SPaul Zimmerman 2086197ba5f4SPaul Zimmerman int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context) 2087197ba5f4SPaul Zimmerman { 2088197ba5f4SPaul Zimmerman struct urb *urb = context; 2089197ba5f4SPaul Zimmerman 2090197ba5f4SPaul Zimmerman return urb->dev->speed; 2091197ba5f4SPaul Zimmerman } 2092197ba5f4SPaul Zimmerman 2093197ba5f4SPaul Zimmerman static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw, 2094197ba5f4SPaul Zimmerman struct urb *urb) 2095197ba5f4SPaul Zimmerman { 2096197ba5f4SPaul Zimmerman struct usb_bus *bus = hcd_to_bus(hcd); 2097197ba5f4SPaul Zimmerman 2098197ba5f4SPaul Zimmerman if (urb->interval) 2099197ba5f4SPaul Zimmerman bus->bandwidth_allocated += bw / urb->interval; 2100197ba5f4SPaul Zimmerman if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 2101197ba5f4SPaul Zimmerman bus->bandwidth_isoc_reqs++; 2102197ba5f4SPaul Zimmerman else 2103197ba5f4SPaul Zimmerman bus->bandwidth_int_reqs++; 2104197ba5f4SPaul Zimmerman } 2105197ba5f4SPaul Zimmerman 2106197ba5f4SPaul Zimmerman static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw, 2107197ba5f4SPaul Zimmerman struct urb *urb) 2108197ba5f4SPaul Zimmerman { 2109197ba5f4SPaul Zimmerman struct usb_bus *bus = hcd_to_bus(hcd); 2110197ba5f4SPaul Zimmerman 2111197ba5f4SPaul Zimmerman if (urb->interval) 2112197ba5f4SPaul Zimmerman bus->bandwidth_allocated -= bw / urb->interval; 2113197ba5f4SPaul Zimmerman if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 2114197ba5f4SPaul Zimmerman bus->bandwidth_isoc_reqs--; 2115197ba5f4SPaul Zimmerman else 2116197ba5f4SPaul Zimmerman bus->bandwidth_int_reqs--; 2117197ba5f4SPaul Zimmerman } 2118197ba5f4SPaul Zimmerman 2119197ba5f4SPaul Zimmerman /* 2120197ba5f4SPaul Zimmerman * Sets the final status of an URB and returns it to the upper layer. Any 2121197ba5f4SPaul Zimmerman * required cleanup of the URB is performed. 2122197ba5f4SPaul Zimmerman * 2123197ba5f4SPaul Zimmerman * Must be called with interrupt disabled and spinlock held 2124197ba5f4SPaul Zimmerman */ 2125197ba5f4SPaul Zimmerman void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 2126197ba5f4SPaul Zimmerman int status) 2127197ba5f4SPaul Zimmerman { 2128197ba5f4SPaul Zimmerman struct urb *urb; 2129197ba5f4SPaul Zimmerman int i; 2130197ba5f4SPaul Zimmerman 2131197ba5f4SPaul Zimmerman if (!qtd) { 2132197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__); 2133197ba5f4SPaul Zimmerman return; 2134197ba5f4SPaul Zimmerman } 2135197ba5f4SPaul Zimmerman 2136197ba5f4SPaul Zimmerman if (!qtd->urb) { 2137197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__); 2138197ba5f4SPaul Zimmerman return; 2139197ba5f4SPaul Zimmerman } 2140197ba5f4SPaul Zimmerman 2141197ba5f4SPaul Zimmerman urb = qtd->urb->priv; 2142197ba5f4SPaul Zimmerman if (!urb) { 2143197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__); 2144197ba5f4SPaul Zimmerman return; 2145197ba5f4SPaul Zimmerman } 2146197ba5f4SPaul Zimmerman 2147197ba5f4SPaul Zimmerman urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb); 2148197ba5f4SPaul Zimmerman 2149197ba5f4SPaul Zimmerman if (dbg_urb(urb)) 2150197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, 2151197ba5f4SPaul Zimmerman "%s: urb %p device %d ep %d-%s status %d actual %d\n", 2152197ba5f4SPaul Zimmerman __func__, urb, usb_pipedevice(urb->pipe), 2153197ba5f4SPaul Zimmerman usb_pipeendpoint(urb->pipe), 2154197ba5f4SPaul Zimmerman usb_pipein(urb->pipe) ? "IN" : "OUT", status, 2155197ba5f4SPaul Zimmerman urb->actual_length); 2156197ba5f4SPaul Zimmerman 2157197ba5f4SPaul Zimmerman if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) { 2158197ba5f4SPaul Zimmerman for (i = 0; i < urb->number_of_packets; i++) 2159197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n", 2160197ba5f4SPaul Zimmerman i, urb->iso_frame_desc[i].status); 2161197ba5f4SPaul Zimmerman } 2162197ba5f4SPaul Zimmerman 2163197ba5f4SPaul Zimmerman if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 2164197ba5f4SPaul Zimmerman urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb); 2165197ba5f4SPaul Zimmerman for (i = 0; i < urb->number_of_packets; ++i) { 2166197ba5f4SPaul Zimmerman urb->iso_frame_desc[i].actual_length = 2167197ba5f4SPaul Zimmerman dwc2_hcd_urb_get_iso_desc_actual_length( 2168197ba5f4SPaul Zimmerman qtd->urb, i); 2169197ba5f4SPaul Zimmerman urb->iso_frame_desc[i].status = 2170197ba5f4SPaul Zimmerman dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i); 2171197ba5f4SPaul Zimmerman } 2172197ba5f4SPaul Zimmerman } 2173197ba5f4SPaul Zimmerman 2174197ba5f4SPaul Zimmerman urb->status = status; 2175197ba5f4SPaul Zimmerman if (!status) { 2176197ba5f4SPaul Zimmerman if ((urb->transfer_flags & URB_SHORT_NOT_OK) && 2177197ba5f4SPaul Zimmerman urb->actual_length < urb->transfer_buffer_length) 2178197ba5f4SPaul Zimmerman urb->status = -EREMOTEIO; 2179197ba5f4SPaul Zimmerman } 2180197ba5f4SPaul Zimmerman 2181197ba5f4SPaul Zimmerman if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || 2182197ba5f4SPaul Zimmerman usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { 2183197ba5f4SPaul Zimmerman struct usb_host_endpoint *ep = urb->ep; 2184197ba5f4SPaul Zimmerman 2185197ba5f4SPaul Zimmerman if (ep) 2186197ba5f4SPaul Zimmerman dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg), 2187197ba5f4SPaul Zimmerman dwc2_hcd_get_ep_bandwidth(hsotg, ep), 2188197ba5f4SPaul Zimmerman urb); 2189197ba5f4SPaul Zimmerman } 2190197ba5f4SPaul Zimmerman 2191197ba5f4SPaul Zimmerman usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb); 2192197ba5f4SPaul Zimmerman urb->hcpriv = NULL; 2193197ba5f4SPaul Zimmerman kfree(qtd->urb); 2194197ba5f4SPaul Zimmerman qtd->urb = NULL; 2195197ba5f4SPaul Zimmerman 2196197ba5f4SPaul Zimmerman spin_unlock(&hsotg->lock); 2197197ba5f4SPaul Zimmerman usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status); 2198197ba5f4SPaul Zimmerman spin_lock(&hsotg->lock); 2199197ba5f4SPaul Zimmerman } 2200197ba5f4SPaul Zimmerman 2201197ba5f4SPaul Zimmerman /* 2202197ba5f4SPaul Zimmerman * Work queue function for starting the HCD when A-Cable is connected 2203197ba5f4SPaul Zimmerman */ 2204197ba5f4SPaul Zimmerman static void dwc2_hcd_start_func(struct work_struct *work) 2205197ba5f4SPaul Zimmerman { 2206197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 2207197ba5f4SPaul Zimmerman start_work.work); 2208197ba5f4SPaul Zimmerman 2209197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg); 2210197ba5f4SPaul Zimmerman dwc2_host_start(hsotg); 2211197ba5f4SPaul Zimmerman } 2212197ba5f4SPaul Zimmerman 2213197ba5f4SPaul Zimmerman /* 2214197ba5f4SPaul Zimmerman * Reset work queue function 2215197ba5f4SPaul Zimmerman */ 2216197ba5f4SPaul Zimmerman static void dwc2_hcd_reset_func(struct work_struct *work) 2217197ba5f4SPaul Zimmerman { 2218197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 2219197ba5f4SPaul Zimmerman reset_work.work); 2220197ba5f4SPaul Zimmerman u32 hprt0; 2221197ba5f4SPaul Zimmerman 2222197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "USB RESET function called\n"); 2223197ba5f4SPaul Zimmerman hprt0 = dwc2_read_hprt0(hsotg); 2224197ba5f4SPaul Zimmerman hprt0 &= ~HPRT0_RST; 2225197ba5f4SPaul Zimmerman writel(hprt0, hsotg->regs + HPRT0); 2226197ba5f4SPaul Zimmerman hsotg->flags.b.port_reset_change = 1; 2227197ba5f4SPaul Zimmerman } 2228197ba5f4SPaul Zimmerman 2229197ba5f4SPaul Zimmerman /* 2230197ba5f4SPaul Zimmerman * ========================================================================= 2231197ba5f4SPaul Zimmerman * Linux HC Driver Functions 2232197ba5f4SPaul Zimmerman * ========================================================================= 2233197ba5f4SPaul Zimmerman */ 2234197ba5f4SPaul Zimmerman 2235197ba5f4SPaul Zimmerman /* 2236197ba5f4SPaul Zimmerman * Initializes the DWC_otg controller and its root hub and prepares it for host 2237197ba5f4SPaul Zimmerman * mode operation. Activates the root port. Returns 0 on success and a negative 2238197ba5f4SPaul Zimmerman * error code on failure. 2239197ba5f4SPaul Zimmerman */ 2240197ba5f4SPaul Zimmerman static int _dwc2_hcd_start(struct usb_hcd *hcd) 2241197ba5f4SPaul Zimmerman { 2242197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2243197ba5f4SPaul Zimmerman struct usb_bus *bus = hcd_to_bus(hcd); 2244197ba5f4SPaul Zimmerman unsigned long flags; 2245197ba5f4SPaul Zimmerman 2246197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "DWC OTG HCD START\n"); 2247197ba5f4SPaul Zimmerman 2248197ba5f4SPaul Zimmerman spin_lock_irqsave(&hsotg->lock, flags); 2249197ba5f4SPaul Zimmerman 2250197ba5f4SPaul Zimmerman hcd->state = HC_STATE_RUNNING; 2251197ba5f4SPaul Zimmerman 2252197ba5f4SPaul Zimmerman if (dwc2_is_device_mode(hsotg)) { 2253197ba5f4SPaul Zimmerman spin_unlock_irqrestore(&hsotg->lock, flags); 2254197ba5f4SPaul Zimmerman return 0; /* why 0 ?? */ 2255197ba5f4SPaul Zimmerman } 2256197ba5f4SPaul Zimmerman 2257197ba5f4SPaul Zimmerman dwc2_hcd_reinit(hsotg); 2258197ba5f4SPaul Zimmerman 2259197ba5f4SPaul Zimmerman /* Initialize and connect root hub if one is not already attached */ 2260197ba5f4SPaul Zimmerman if (bus->root_hub) { 2261197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n"); 2262197ba5f4SPaul Zimmerman /* Inform the HUB driver to resume */ 2263197ba5f4SPaul Zimmerman usb_hcd_resume_root_hub(hcd); 2264197ba5f4SPaul Zimmerman } 2265197ba5f4SPaul Zimmerman 2266197ba5f4SPaul Zimmerman spin_unlock_irqrestore(&hsotg->lock, flags); 2267197ba5f4SPaul Zimmerman return 0; 2268197ba5f4SPaul Zimmerman } 2269197ba5f4SPaul Zimmerman 2270197ba5f4SPaul Zimmerman /* 2271197ba5f4SPaul Zimmerman * Halts the DWC_otg host mode operations in a clean manner. USB transfers are 2272197ba5f4SPaul Zimmerman * stopped. 2273197ba5f4SPaul Zimmerman */ 2274197ba5f4SPaul Zimmerman static void _dwc2_hcd_stop(struct usb_hcd *hcd) 2275197ba5f4SPaul Zimmerman { 2276197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2277197ba5f4SPaul Zimmerman unsigned long flags; 2278197ba5f4SPaul Zimmerman 2279197ba5f4SPaul Zimmerman spin_lock_irqsave(&hsotg->lock, flags); 2280197ba5f4SPaul Zimmerman dwc2_hcd_stop(hsotg); 2281197ba5f4SPaul Zimmerman spin_unlock_irqrestore(&hsotg->lock, flags); 2282197ba5f4SPaul Zimmerman 2283197ba5f4SPaul Zimmerman usleep_range(1000, 3000); 2284197ba5f4SPaul Zimmerman } 2285197ba5f4SPaul Zimmerman 2286197ba5f4SPaul Zimmerman /* Returns the current frame number */ 2287197ba5f4SPaul Zimmerman static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd) 2288197ba5f4SPaul Zimmerman { 2289197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2290197ba5f4SPaul Zimmerman 2291197ba5f4SPaul Zimmerman return dwc2_hcd_get_frame_number(hsotg); 2292197ba5f4SPaul Zimmerman } 2293197ba5f4SPaul Zimmerman 2294197ba5f4SPaul Zimmerman static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb, 2295197ba5f4SPaul Zimmerman char *fn_name) 2296197ba5f4SPaul Zimmerman { 2297197ba5f4SPaul Zimmerman #ifdef VERBOSE_DEBUG 2298197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2299197ba5f4SPaul Zimmerman char *pipetype; 2300197ba5f4SPaul Zimmerman char *speed; 2301197ba5f4SPaul Zimmerman 2302197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb); 2303197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " Device address: %d\n", 2304197ba5f4SPaul Zimmerman usb_pipedevice(urb->pipe)); 2305197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n", 2306197ba5f4SPaul Zimmerman usb_pipeendpoint(urb->pipe), 2307197ba5f4SPaul Zimmerman usb_pipein(urb->pipe) ? "IN" : "OUT"); 2308197ba5f4SPaul Zimmerman 2309197ba5f4SPaul Zimmerman switch (usb_pipetype(urb->pipe)) { 2310197ba5f4SPaul Zimmerman case PIPE_CONTROL: 2311197ba5f4SPaul Zimmerman pipetype = "CONTROL"; 2312197ba5f4SPaul Zimmerman break; 2313197ba5f4SPaul Zimmerman case PIPE_BULK: 2314197ba5f4SPaul Zimmerman pipetype = "BULK"; 2315197ba5f4SPaul Zimmerman break; 2316197ba5f4SPaul Zimmerman case PIPE_INTERRUPT: 2317197ba5f4SPaul Zimmerman pipetype = "INTERRUPT"; 2318197ba5f4SPaul Zimmerman break; 2319197ba5f4SPaul Zimmerman case PIPE_ISOCHRONOUS: 2320197ba5f4SPaul Zimmerman pipetype = "ISOCHRONOUS"; 2321197ba5f4SPaul Zimmerman break; 2322197ba5f4SPaul Zimmerman default: 2323197ba5f4SPaul Zimmerman pipetype = "UNKNOWN"; 2324197ba5f4SPaul Zimmerman break; 2325197ba5f4SPaul Zimmerman } 2326197ba5f4SPaul Zimmerman 2327197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype, 2328197ba5f4SPaul Zimmerman usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ? 2329197ba5f4SPaul Zimmerman "IN" : "OUT"); 2330197ba5f4SPaul Zimmerman 2331197ba5f4SPaul Zimmerman switch (urb->dev->speed) { 2332197ba5f4SPaul Zimmerman case USB_SPEED_HIGH: 2333197ba5f4SPaul Zimmerman speed = "HIGH"; 2334197ba5f4SPaul Zimmerman break; 2335197ba5f4SPaul Zimmerman case USB_SPEED_FULL: 2336197ba5f4SPaul Zimmerman speed = "FULL"; 2337197ba5f4SPaul Zimmerman break; 2338197ba5f4SPaul Zimmerman case USB_SPEED_LOW: 2339197ba5f4SPaul Zimmerman speed = "LOW"; 2340197ba5f4SPaul Zimmerman break; 2341197ba5f4SPaul Zimmerman default: 2342197ba5f4SPaul Zimmerman speed = "UNKNOWN"; 2343197ba5f4SPaul Zimmerman break; 2344197ba5f4SPaul Zimmerman } 2345197ba5f4SPaul Zimmerman 2346197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " Speed: %s\n", speed); 2347197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " Max packet size: %d\n", 2348197ba5f4SPaul Zimmerman usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))); 2349197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " Data buffer length: %d\n", 2350197ba5f4SPaul Zimmerman urb->transfer_buffer_length); 2351197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n", 2352197ba5f4SPaul Zimmerman urb->transfer_buffer, (unsigned long)urb->transfer_dma); 2353197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n", 2354197ba5f4SPaul Zimmerman urb->setup_packet, (unsigned long)urb->setup_dma); 2355197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval); 2356197ba5f4SPaul Zimmerman 2357197ba5f4SPaul Zimmerman if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 2358197ba5f4SPaul Zimmerman int i; 2359197ba5f4SPaul Zimmerman 2360197ba5f4SPaul Zimmerman for (i = 0; i < urb->number_of_packets; i++) { 2361197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i); 2362197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " offset: %d, length %d\n", 2363197ba5f4SPaul Zimmerman urb->iso_frame_desc[i].offset, 2364197ba5f4SPaul Zimmerman urb->iso_frame_desc[i].length); 2365197ba5f4SPaul Zimmerman } 2366197ba5f4SPaul Zimmerman } 2367197ba5f4SPaul Zimmerman #endif 2368197ba5f4SPaul Zimmerman } 2369197ba5f4SPaul Zimmerman 2370197ba5f4SPaul Zimmerman /* 2371197ba5f4SPaul Zimmerman * Starts processing a USB transfer request specified by a USB Request Block 2372197ba5f4SPaul Zimmerman * (URB). mem_flags indicates the type of memory allocation to use while 2373197ba5f4SPaul Zimmerman * processing this URB. 2374197ba5f4SPaul Zimmerman */ 2375197ba5f4SPaul Zimmerman static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, 2376197ba5f4SPaul Zimmerman gfp_t mem_flags) 2377197ba5f4SPaul Zimmerman { 2378197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2379197ba5f4SPaul Zimmerman struct usb_host_endpoint *ep = urb->ep; 2380197ba5f4SPaul Zimmerman struct dwc2_hcd_urb *dwc2_urb; 2381197ba5f4SPaul Zimmerman int i; 2382197ba5f4SPaul Zimmerman int retval; 2383197ba5f4SPaul Zimmerman int alloc_bandwidth = 0; 2384197ba5f4SPaul Zimmerman u8 ep_type = 0; 2385197ba5f4SPaul Zimmerman u32 tflags = 0; 2386197ba5f4SPaul Zimmerman void *buf; 2387197ba5f4SPaul Zimmerman unsigned long flags; 2388197ba5f4SPaul Zimmerman 2389197ba5f4SPaul Zimmerman if (dbg_urb(urb)) { 2390197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n"); 2391197ba5f4SPaul Zimmerman dwc2_dump_urb_info(hcd, urb, "urb_enqueue"); 2392197ba5f4SPaul Zimmerman } 2393197ba5f4SPaul Zimmerman 2394197ba5f4SPaul Zimmerman if (ep == NULL) 2395197ba5f4SPaul Zimmerman return -EINVAL; 2396197ba5f4SPaul Zimmerman 2397197ba5f4SPaul Zimmerman if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || 2398197ba5f4SPaul Zimmerman usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { 2399197ba5f4SPaul Zimmerman spin_lock_irqsave(&hsotg->lock, flags); 2400197ba5f4SPaul Zimmerman if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep)) 2401197ba5f4SPaul Zimmerman alloc_bandwidth = 1; 2402197ba5f4SPaul Zimmerman spin_unlock_irqrestore(&hsotg->lock, flags); 2403197ba5f4SPaul Zimmerman } 2404197ba5f4SPaul Zimmerman 2405197ba5f4SPaul Zimmerman switch (usb_pipetype(urb->pipe)) { 2406197ba5f4SPaul Zimmerman case PIPE_CONTROL: 2407197ba5f4SPaul Zimmerman ep_type = USB_ENDPOINT_XFER_CONTROL; 2408197ba5f4SPaul Zimmerman break; 2409197ba5f4SPaul Zimmerman case PIPE_ISOCHRONOUS: 2410197ba5f4SPaul Zimmerman ep_type = USB_ENDPOINT_XFER_ISOC; 2411197ba5f4SPaul Zimmerman break; 2412197ba5f4SPaul Zimmerman case PIPE_BULK: 2413197ba5f4SPaul Zimmerman ep_type = USB_ENDPOINT_XFER_BULK; 2414197ba5f4SPaul Zimmerman break; 2415197ba5f4SPaul Zimmerman case PIPE_INTERRUPT: 2416197ba5f4SPaul Zimmerman ep_type = USB_ENDPOINT_XFER_INT; 2417197ba5f4SPaul Zimmerman break; 2418197ba5f4SPaul Zimmerman default: 2419197ba5f4SPaul Zimmerman dev_warn(hsotg->dev, "Wrong ep type\n"); 2420197ba5f4SPaul Zimmerman } 2421197ba5f4SPaul Zimmerman 2422197ba5f4SPaul Zimmerman dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets, 2423197ba5f4SPaul Zimmerman mem_flags); 2424197ba5f4SPaul Zimmerman if (!dwc2_urb) 2425197ba5f4SPaul Zimmerman return -ENOMEM; 2426197ba5f4SPaul Zimmerman 2427197ba5f4SPaul Zimmerman dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe), 2428197ba5f4SPaul Zimmerman usb_pipeendpoint(urb->pipe), ep_type, 2429197ba5f4SPaul Zimmerman usb_pipein(urb->pipe), 2430197ba5f4SPaul Zimmerman usb_maxpacket(urb->dev, urb->pipe, 2431197ba5f4SPaul Zimmerman !(usb_pipein(urb->pipe)))); 2432197ba5f4SPaul Zimmerman 2433197ba5f4SPaul Zimmerman buf = urb->transfer_buffer; 2434197ba5f4SPaul Zimmerman 2435197ba5f4SPaul Zimmerman if (hcd->self.uses_dma) { 2436197ba5f4SPaul Zimmerman if (!buf && (urb->transfer_dma & 3)) { 2437197ba5f4SPaul Zimmerman dev_err(hsotg->dev, 2438197ba5f4SPaul Zimmerman "%s: unaligned transfer with no transfer_buffer", 2439197ba5f4SPaul Zimmerman __func__); 2440197ba5f4SPaul Zimmerman retval = -EINVAL; 2441197ba5f4SPaul Zimmerman goto fail1; 2442197ba5f4SPaul Zimmerman } 2443197ba5f4SPaul Zimmerman } 2444197ba5f4SPaul Zimmerman 2445197ba5f4SPaul Zimmerman if (!(urb->transfer_flags & URB_NO_INTERRUPT)) 2446197ba5f4SPaul Zimmerman tflags |= URB_GIVEBACK_ASAP; 2447197ba5f4SPaul Zimmerman if (urb->transfer_flags & URB_ZERO_PACKET) 2448197ba5f4SPaul Zimmerman tflags |= URB_SEND_ZERO_PACKET; 2449197ba5f4SPaul Zimmerman 2450197ba5f4SPaul Zimmerman dwc2_urb->priv = urb; 2451197ba5f4SPaul Zimmerman dwc2_urb->buf = buf; 2452197ba5f4SPaul Zimmerman dwc2_urb->dma = urb->transfer_dma; 2453197ba5f4SPaul Zimmerman dwc2_urb->length = urb->transfer_buffer_length; 2454197ba5f4SPaul Zimmerman dwc2_urb->setup_packet = urb->setup_packet; 2455197ba5f4SPaul Zimmerman dwc2_urb->setup_dma = urb->setup_dma; 2456197ba5f4SPaul Zimmerman dwc2_urb->flags = tflags; 2457197ba5f4SPaul Zimmerman dwc2_urb->interval = urb->interval; 2458197ba5f4SPaul Zimmerman dwc2_urb->status = -EINPROGRESS; 2459197ba5f4SPaul Zimmerman 2460197ba5f4SPaul Zimmerman for (i = 0; i < urb->number_of_packets; ++i) 2461197ba5f4SPaul Zimmerman dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i, 2462197ba5f4SPaul Zimmerman urb->iso_frame_desc[i].offset, 2463197ba5f4SPaul Zimmerman urb->iso_frame_desc[i].length); 2464197ba5f4SPaul Zimmerman 2465197ba5f4SPaul Zimmerman urb->hcpriv = dwc2_urb; 2466197ba5f4SPaul Zimmerman 2467197ba5f4SPaul Zimmerman spin_lock_irqsave(&hsotg->lock, flags); 2468197ba5f4SPaul Zimmerman retval = usb_hcd_link_urb_to_ep(hcd, urb); 2469197ba5f4SPaul Zimmerman spin_unlock_irqrestore(&hsotg->lock, flags); 2470197ba5f4SPaul Zimmerman if (retval) 2471197ba5f4SPaul Zimmerman goto fail1; 2472197ba5f4SPaul Zimmerman 2473197ba5f4SPaul Zimmerman retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, &ep->hcpriv, mem_flags); 2474197ba5f4SPaul Zimmerman if (retval) 2475197ba5f4SPaul Zimmerman goto fail2; 2476197ba5f4SPaul Zimmerman 2477197ba5f4SPaul Zimmerman if (alloc_bandwidth) { 2478197ba5f4SPaul Zimmerman spin_lock_irqsave(&hsotg->lock, flags); 2479197ba5f4SPaul Zimmerman dwc2_allocate_bus_bandwidth(hcd, 2480197ba5f4SPaul Zimmerman dwc2_hcd_get_ep_bandwidth(hsotg, ep), 2481197ba5f4SPaul Zimmerman urb); 2482197ba5f4SPaul Zimmerman spin_unlock_irqrestore(&hsotg->lock, flags); 2483197ba5f4SPaul Zimmerman } 2484197ba5f4SPaul Zimmerman 2485197ba5f4SPaul Zimmerman return 0; 2486197ba5f4SPaul Zimmerman 2487197ba5f4SPaul Zimmerman fail2: 2488197ba5f4SPaul Zimmerman spin_lock_irqsave(&hsotg->lock, flags); 2489197ba5f4SPaul Zimmerman dwc2_urb->priv = NULL; 2490197ba5f4SPaul Zimmerman usb_hcd_unlink_urb_from_ep(hcd, urb); 2491197ba5f4SPaul Zimmerman spin_unlock_irqrestore(&hsotg->lock, flags); 2492197ba5f4SPaul Zimmerman fail1: 2493197ba5f4SPaul Zimmerman urb->hcpriv = NULL; 2494197ba5f4SPaul Zimmerman kfree(dwc2_urb); 2495197ba5f4SPaul Zimmerman 2496197ba5f4SPaul Zimmerman return retval; 2497197ba5f4SPaul Zimmerman } 2498197ba5f4SPaul Zimmerman 2499197ba5f4SPaul Zimmerman /* 2500197ba5f4SPaul Zimmerman * Aborts/cancels a USB transfer request. Always returns 0 to indicate success. 2501197ba5f4SPaul Zimmerman */ 2502197ba5f4SPaul Zimmerman static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, 2503197ba5f4SPaul Zimmerman int status) 2504197ba5f4SPaul Zimmerman { 2505197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2506197ba5f4SPaul Zimmerman int rc; 2507197ba5f4SPaul Zimmerman unsigned long flags; 2508197ba5f4SPaul Zimmerman 2509197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n"); 2510197ba5f4SPaul Zimmerman dwc2_dump_urb_info(hcd, urb, "urb_dequeue"); 2511197ba5f4SPaul Zimmerman 2512197ba5f4SPaul Zimmerman spin_lock_irqsave(&hsotg->lock, flags); 2513197ba5f4SPaul Zimmerman 2514197ba5f4SPaul Zimmerman rc = usb_hcd_check_unlink_urb(hcd, urb, status); 2515197ba5f4SPaul Zimmerman if (rc) 2516197ba5f4SPaul Zimmerman goto out; 2517197ba5f4SPaul Zimmerman 2518197ba5f4SPaul Zimmerman if (!urb->hcpriv) { 2519197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n"); 2520197ba5f4SPaul Zimmerman goto out; 2521197ba5f4SPaul Zimmerman } 2522197ba5f4SPaul Zimmerman 2523197ba5f4SPaul Zimmerman rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv); 2524197ba5f4SPaul Zimmerman 2525197ba5f4SPaul Zimmerman usb_hcd_unlink_urb_from_ep(hcd, urb); 2526197ba5f4SPaul Zimmerman 2527197ba5f4SPaul Zimmerman kfree(urb->hcpriv); 2528197ba5f4SPaul Zimmerman urb->hcpriv = NULL; 2529197ba5f4SPaul Zimmerman 2530197ba5f4SPaul Zimmerman /* Higher layer software sets URB status */ 2531197ba5f4SPaul Zimmerman spin_unlock(&hsotg->lock); 2532197ba5f4SPaul Zimmerman usb_hcd_giveback_urb(hcd, urb, status); 2533197ba5f4SPaul Zimmerman spin_lock(&hsotg->lock); 2534197ba5f4SPaul Zimmerman 2535197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n"); 2536197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status); 2537197ba5f4SPaul Zimmerman out: 2538197ba5f4SPaul Zimmerman spin_unlock_irqrestore(&hsotg->lock, flags); 2539197ba5f4SPaul Zimmerman 2540197ba5f4SPaul Zimmerman return rc; 2541197ba5f4SPaul Zimmerman } 2542197ba5f4SPaul Zimmerman 2543197ba5f4SPaul Zimmerman /* 2544197ba5f4SPaul Zimmerman * Frees resources in the DWC_otg controller related to a given endpoint. Also 2545197ba5f4SPaul Zimmerman * clears state in the HCD related to the endpoint. Any URBs for the endpoint 2546197ba5f4SPaul Zimmerman * must already be dequeued. 2547197ba5f4SPaul Zimmerman */ 2548197ba5f4SPaul Zimmerman static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd, 2549197ba5f4SPaul Zimmerman struct usb_host_endpoint *ep) 2550197ba5f4SPaul Zimmerman { 2551197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2552197ba5f4SPaul Zimmerman 2553197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 2554197ba5f4SPaul Zimmerman "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n", 2555197ba5f4SPaul Zimmerman ep->desc.bEndpointAddress, ep->hcpriv); 2556197ba5f4SPaul Zimmerman dwc2_hcd_endpoint_disable(hsotg, ep, 250); 2557197ba5f4SPaul Zimmerman } 2558197ba5f4SPaul Zimmerman 2559197ba5f4SPaul Zimmerman /* 2560197ba5f4SPaul Zimmerman * Resets endpoint specific parameter values, in current version used to reset 2561197ba5f4SPaul Zimmerman * the data toggle (as a WA). This function can be called from usb_clear_halt 2562197ba5f4SPaul Zimmerman * routine. 2563197ba5f4SPaul Zimmerman */ 2564197ba5f4SPaul Zimmerman static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd, 2565197ba5f4SPaul Zimmerman struct usb_host_endpoint *ep) 2566197ba5f4SPaul Zimmerman { 2567197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2568197ba5f4SPaul Zimmerman int is_control = usb_endpoint_xfer_control(&ep->desc); 2569197ba5f4SPaul Zimmerman int is_out = usb_endpoint_dir_out(&ep->desc); 2570197ba5f4SPaul Zimmerman int epnum = usb_endpoint_num(&ep->desc); 2571197ba5f4SPaul Zimmerman struct usb_device *udev; 2572197ba5f4SPaul Zimmerman unsigned long flags; 2573197ba5f4SPaul Zimmerman 2574197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 2575197ba5f4SPaul Zimmerman "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n", 2576197ba5f4SPaul Zimmerman ep->desc.bEndpointAddress); 2577197ba5f4SPaul Zimmerman 2578197ba5f4SPaul Zimmerman udev = to_usb_device(hsotg->dev); 2579197ba5f4SPaul Zimmerman 2580197ba5f4SPaul Zimmerman spin_lock_irqsave(&hsotg->lock, flags); 2581197ba5f4SPaul Zimmerman 2582197ba5f4SPaul Zimmerman usb_settoggle(udev, epnum, is_out, 0); 2583197ba5f4SPaul Zimmerman if (is_control) 2584197ba5f4SPaul Zimmerman usb_settoggle(udev, epnum, !is_out, 0); 2585197ba5f4SPaul Zimmerman dwc2_hcd_endpoint_reset(hsotg, ep); 2586197ba5f4SPaul Zimmerman 2587197ba5f4SPaul Zimmerman spin_unlock_irqrestore(&hsotg->lock, flags); 2588197ba5f4SPaul Zimmerman } 2589197ba5f4SPaul Zimmerman 2590197ba5f4SPaul Zimmerman /* 2591197ba5f4SPaul Zimmerman * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if 2592197ba5f4SPaul Zimmerman * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid 2593197ba5f4SPaul Zimmerman * interrupt. 2594197ba5f4SPaul Zimmerman * 2595197ba5f4SPaul Zimmerman * This function is called by the USB core when an interrupt occurs 2596197ba5f4SPaul Zimmerman */ 2597197ba5f4SPaul Zimmerman static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd) 2598197ba5f4SPaul Zimmerman { 2599197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2600197ba5f4SPaul Zimmerman 2601197ba5f4SPaul Zimmerman return dwc2_handle_hcd_intr(hsotg); 2602197ba5f4SPaul Zimmerman } 2603197ba5f4SPaul Zimmerman 2604197ba5f4SPaul Zimmerman /* 2605197ba5f4SPaul Zimmerman * Creates Status Change bitmap for the root hub and root port. The bitmap is 2606197ba5f4SPaul Zimmerman * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1 2607197ba5f4SPaul Zimmerman * is the status change indicator for the single root port. Returns 1 if either 2608197ba5f4SPaul Zimmerman * change indicator is 1, otherwise returns 0. 2609197ba5f4SPaul Zimmerman */ 2610197ba5f4SPaul Zimmerman static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf) 2611197ba5f4SPaul Zimmerman { 2612197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2613197ba5f4SPaul Zimmerman 2614197ba5f4SPaul Zimmerman buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1; 2615197ba5f4SPaul Zimmerman return buf[0] != 0; 2616197ba5f4SPaul Zimmerman } 2617197ba5f4SPaul Zimmerman 2618197ba5f4SPaul Zimmerman /* Handles hub class-specific requests */ 2619197ba5f4SPaul Zimmerman static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue, 2620197ba5f4SPaul Zimmerman u16 windex, char *buf, u16 wlength) 2621197ba5f4SPaul Zimmerman { 2622197ba5f4SPaul Zimmerman int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq, 2623197ba5f4SPaul Zimmerman wvalue, windex, buf, wlength); 2624197ba5f4SPaul Zimmerman return retval; 2625197ba5f4SPaul Zimmerman } 2626197ba5f4SPaul Zimmerman 2627197ba5f4SPaul Zimmerman /* Handles hub TT buffer clear completions */ 2628197ba5f4SPaul Zimmerman static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd, 2629197ba5f4SPaul Zimmerman struct usb_host_endpoint *ep) 2630197ba5f4SPaul Zimmerman { 2631197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2632197ba5f4SPaul Zimmerman struct dwc2_qh *qh; 2633197ba5f4SPaul Zimmerman unsigned long flags; 2634197ba5f4SPaul Zimmerman 2635197ba5f4SPaul Zimmerman qh = ep->hcpriv; 2636197ba5f4SPaul Zimmerman if (!qh) 2637197ba5f4SPaul Zimmerman return; 2638197ba5f4SPaul Zimmerman 2639197ba5f4SPaul Zimmerman spin_lock_irqsave(&hsotg->lock, flags); 2640197ba5f4SPaul Zimmerman qh->tt_buffer_dirty = 0; 2641197ba5f4SPaul Zimmerman 2642197ba5f4SPaul Zimmerman if (hsotg->flags.b.port_connect_status) 2643197ba5f4SPaul Zimmerman dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL); 2644197ba5f4SPaul Zimmerman 2645197ba5f4SPaul Zimmerman spin_unlock_irqrestore(&hsotg->lock, flags); 2646197ba5f4SPaul Zimmerman } 2647197ba5f4SPaul Zimmerman 2648197ba5f4SPaul Zimmerman static struct hc_driver dwc2_hc_driver = { 2649197ba5f4SPaul Zimmerman .description = "dwc2_hsotg", 2650197ba5f4SPaul Zimmerman .product_desc = "DWC OTG Controller", 2651197ba5f4SPaul Zimmerman .hcd_priv_size = sizeof(struct wrapper_priv_data), 2652197ba5f4SPaul Zimmerman 2653197ba5f4SPaul Zimmerman .irq = _dwc2_hcd_irq, 2654197ba5f4SPaul Zimmerman .flags = HCD_MEMORY | HCD_USB2, 2655197ba5f4SPaul Zimmerman 2656197ba5f4SPaul Zimmerman .start = _dwc2_hcd_start, 2657197ba5f4SPaul Zimmerman .stop = _dwc2_hcd_stop, 2658197ba5f4SPaul Zimmerman .urb_enqueue = _dwc2_hcd_urb_enqueue, 2659197ba5f4SPaul Zimmerman .urb_dequeue = _dwc2_hcd_urb_dequeue, 2660197ba5f4SPaul Zimmerman .endpoint_disable = _dwc2_hcd_endpoint_disable, 2661197ba5f4SPaul Zimmerman .endpoint_reset = _dwc2_hcd_endpoint_reset, 2662197ba5f4SPaul Zimmerman .get_frame_number = _dwc2_hcd_get_frame_number, 2663197ba5f4SPaul Zimmerman 2664197ba5f4SPaul Zimmerman .hub_status_data = _dwc2_hcd_hub_status_data, 2665197ba5f4SPaul Zimmerman .hub_control = _dwc2_hcd_hub_control, 2666197ba5f4SPaul Zimmerman .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete, 2667197ba5f4SPaul Zimmerman }; 2668197ba5f4SPaul Zimmerman 2669197ba5f4SPaul Zimmerman /* 2670197ba5f4SPaul Zimmerman * Frees secondary storage associated with the dwc2_hsotg structure contained 2671197ba5f4SPaul Zimmerman * in the struct usb_hcd field 2672197ba5f4SPaul Zimmerman */ 2673197ba5f4SPaul Zimmerman static void dwc2_hcd_free(struct dwc2_hsotg *hsotg) 2674197ba5f4SPaul Zimmerman { 2675197ba5f4SPaul Zimmerman u32 ahbcfg; 2676197ba5f4SPaul Zimmerman u32 dctl; 2677197ba5f4SPaul Zimmerman int i; 2678197ba5f4SPaul Zimmerman 2679197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n"); 2680197ba5f4SPaul Zimmerman 2681197ba5f4SPaul Zimmerman /* Free memory for QH/QTD lists */ 2682197ba5f4SPaul Zimmerman dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive); 2683197ba5f4SPaul Zimmerman dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active); 2684197ba5f4SPaul Zimmerman dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive); 2685197ba5f4SPaul Zimmerman dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready); 2686197ba5f4SPaul Zimmerman dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned); 2687197ba5f4SPaul Zimmerman dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued); 2688197ba5f4SPaul Zimmerman 2689197ba5f4SPaul Zimmerman /* Free memory for the host channels */ 2690197ba5f4SPaul Zimmerman for (i = 0; i < MAX_EPS_CHANNELS; i++) { 2691197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 2692197ba5f4SPaul Zimmerman 2693197ba5f4SPaul Zimmerman if (chan != NULL) { 2694197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n", 2695197ba5f4SPaul Zimmerman i, chan); 2696197ba5f4SPaul Zimmerman hsotg->hc_ptr_array[i] = NULL; 2697197ba5f4SPaul Zimmerman kfree(chan); 2698197ba5f4SPaul Zimmerman } 2699197ba5f4SPaul Zimmerman } 2700197ba5f4SPaul Zimmerman 2701197ba5f4SPaul Zimmerman if (hsotg->core_params->dma_enable > 0) { 2702197ba5f4SPaul Zimmerman if (hsotg->status_buf) { 2703197ba5f4SPaul Zimmerman dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE, 2704197ba5f4SPaul Zimmerman hsotg->status_buf, 2705197ba5f4SPaul Zimmerman hsotg->status_buf_dma); 2706197ba5f4SPaul Zimmerman hsotg->status_buf = NULL; 2707197ba5f4SPaul Zimmerman } 2708197ba5f4SPaul Zimmerman } else { 2709197ba5f4SPaul Zimmerman kfree(hsotg->status_buf); 2710197ba5f4SPaul Zimmerman hsotg->status_buf = NULL; 2711197ba5f4SPaul Zimmerman } 2712197ba5f4SPaul Zimmerman 2713197ba5f4SPaul Zimmerman ahbcfg = readl(hsotg->regs + GAHBCFG); 2714197ba5f4SPaul Zimmerman 2715197ba5f4SPaul Zimmerman /* Disable all interrupts */ 2716197ba5f4SPaul Zimmerman ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 2717197ba5f4SPaul Zimmerman writel(ahbcfg, hsotg->regs + GAHBCFG); 2718197ba5f4SPaul Zimmerman writel(0, hsotg->regs + GINTMSK); 2719197ba5f4SPaul Zimmerman 2720197ba5f4SPaul Zimmerman if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) { 2721197ba5f4SPaul Zimmerman dctl = readl(hsotg->regs + DCTL); 2722197ba5f4SPaul Zimmerman dctl |= DCTL_SFTDISCON; 2723197ba5f4SPaul Zimmerman writel(dctl, hsotg->regs + DCTL); 2724197ba5f4SPaul Zimmerman } 2725197ba5f4SPaul Zimmerman 2726197ba5f4SPaul Zimmerman if (hsotg->wq_otg) { 2727197ba5f4SPaul Zimmerman if (!cancel_work_sync(&hsotg->wf_otg)) 2728197ba5f4SPaul Zimmerman flush_workqueue(hsotg->wq_otg); 2729197ba5f4SPaul Zimmerman destroy_workqueue(hsotg->wq_otg); 2730197ba5f4SPaul Zimmerman } 2731197ba5f4SPaul Zimmerman 2732197ba5f4SPaul Zimmerman kfree(hsotg->core_params); 2733197ba5f4SPaul Zimmerman hsotg->core_params = NULL; 2734197ba5f4SPaul Zimmerman del_timer(&hsotg->wkp_timer); 2735197ba5f4SPaul Zimmerman } 2736197ba5f4SPaul Zimmerman 2737197ba5f4SPaul Zimmerman static void dwc2_hcd_release(struct dwc2_hsotg *hsotg) 2738197ba5f4SPaul Zimmerman { 2739197ba5f4SPaul Zimmerman /* Turn off all host-specific interrupts */ 2740197ba5f4SPaul Zimmerman dwc2_disable_host_interrupts(hsotg); 2741197ba5f4SPaul Zimmerman 2742197ba5f4SPaul Zimmerman dwc2_hcd_free(hsotg); 2743197ba5f4SPaul Zimmerman } 2744197ba5f4SPaul Zimmerman 2745197ba5f4SPaul Zimmerman /* 2746197ba5f4SPaul Zimmerman * Sets all parameters to the given value. 2747197ba5f4SPaul Zimmerman * 2748197ba5f4SPaul Zimmerman * Assumes that the dwc2_core_params struct contains only integers. 2749197ba5f4SPaul Zimmerman */ 2750197ba5f4SPaul Zimmerman void dwc2_set_all_params(struct dwc2_core_params *params, int value) 2751197ba5f4SPaul Zimmerman { 2752197ba5f4SPaul Zimmerman int *p = (int *)params; 2753197ba5f4SPaul Zimmerman size_t size = sizeof(*params) / sizeof(*p); 2754197ba5f4SPaul Zimmerman int i; 2755197ba5f4SPaul Zimmerman 2756197ba5f4SPaul Zimmerman for (i = 0; i < size; i++) 2757197ba5f4SPaul Zimmerman p[i] = value; 2758197ba5f4SPaul Zimmerman } 2759197ba5f4SPaul Zimmerman EXPORT_SYMBOL_GPL(dwc2_set_all_params); 2760197ba5f4SPaul Zimmerman 2761197ba5f4SPaul Zimmerman /* 2762197ba5f4SPaul Zimmerman * Initializes the HCD. This function allocates memory for and initializes the 2763197ba5f4SPaul Zimmerman * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the 2764197ba5f4SPaul Zimmerman * USB bus with the core and calls the hc_driver->start() function. It returns 2765197ba5f4SPaul Zimmerman * a negative error on failure. 2766197ba5f4SPaul Zimmerman */ 2767197ba5f4SPaul Zimmerman int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq, 2768197ba5f4SPaul Zimmerman const struct dwc2_core_params *params) 2769197ba5f4SPaul Zimmerman { 2770197ba5f4SPaul Zimmerman struct usb_hcd *hcd; 2771197ba5f4SPaul Zimmerman struct dwc2_host_chan *channel; 2772197ba5f4SPaul Zimmerman u32 hcfg; 2773197ba5f4SPaul Zimmerman int i, num_channels; 2774197ba5f4SPaul Zimmerman int retval; 2775197ba5f4SPaul Zimmerman 2776197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n"); 2777197ba5f4SPaul Zimmerman 2778197ba5f4SPaul Zimmerman /* Detect config values from hardware */ 2779197ba5f4SPaul Zimmerman retval = dwc2_get_hwparams(hsotg); 2780197ba5f4SPaul Zimmerman 2781197ba5f4SPaul Zimmerman if (retval) 2782197ba5f4SPaul Zimmerman return retval; 2783197ba5f4SPaul Zimmerman 2784197ba5f4SPaul Zimmerman retval = -ENOMEM; 2785197ba5f4SPaul Zimmerman 2786197ba5f4SPaul Zimmerman hcfg = readl(hsotg->regs + HCFG); 2787197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg); 2788197ba5f4SPaul Zimmerman 2789197ba5f4SPaul Zimmerman #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 2790197ba5f4SPaul Zimmerman hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) * 2791197ba5f4SPaul Zimmerman FRAME_NUM_ARRAY_SIZE, GFP_KERNEL); 2792197ba5f4SPaul Zimmerman if (!hsotg->frame_num_array) 2793197ba5f4SPaul Zimmerman goto error1; 2794197ba5f4SPaul Zimmerman hsotg->last_frame_num_array = kzalloc( 2795197ba5f4SPaul Zimmerman sizeof(*hsotg->last_frame_num_array) * 2796197ba5f4SPaul Zimmerman FRAME_NUM_ARRAY_SIZE, GFP_KERNEL); 2797197ba5f4SPaul Zimmerman if (!hsotg->last_frame_num_array) 2798197ba5f4SPaul Zimmerman goto error1; 2799197ba5f4SPaul Zimmerman hsotg->last_frame_num = HFNUM_MAX_FRNUM; 2800197ba5f4SPaul Zimmerman #endif 2801197ba5f4SPaul Zimmerman 2802197ba5f4SPaul Zimmerman hsotg->core_params = kzalloc(sizeof(*hsotg->core_params), GFP_KERNEL); 2803197ba5f4SPaul Zimmerman if (!hsotg->core_params) 2804197ba5f4SPaul Zimmerman goto error1; 2805197ba5f4SPaul Zimmerman 2806197ba5f4SPaul Zimmerman dwc2_set_all_params(hsotg->core_params, -1); 2807197ba5f4SPaul Zimmerman 2808197ba5f4SPaul Zimmerman /* Validate parameter values */ 2809197ba5f4SPaul Zimmerman dwc2_set_parameters(hsotg, params); 2810197ba5f4SPaul Zimmerman 2811197ba5f4SPaul Zimmerman /* Check if the bus driver or platform code has setup a dma_mask */ 2812197ba5f4SPaul Zimmerman if (hsotg->core_params->dma_enable > 0 && 2813197ba5f4SPaul Zimmerman hsotg->dev->dma_mask == NULL) { 2814197ba5f4SPaul Zimmerman dev_warn(hsotg->dev, 2815197ba5f4SPaul Zimmerman "dma_mask not set, disabling DMA\n"); 2816197ba5f4SPaul Zimmerman hsotg->core_params->dma_enable = 0; 2817197ba5f4SPaul Zimmerman hsotg->core_params->dma_desc_enable = 0; 2818197ba5f4SPaul Zimmerman } 2819197ba5f4SPaul Zimmerman 2820197ba5f4SPaul Zimmerman /* Set device flags indicating whether the HCD supports DMA */ 2821197ba5f4SPaul Zimmerman if (hsotg->core_params->dma_enable > 0) { 2822197ba5f4SPaul Zimmerman if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) 2823197ba5f4SPaul Zimmerman dev_warn(hsotg->dev, "can't set DMA mask\n"); 2824197ba5f4SPaul Zimmerman if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) 2825197ba5f4SPaul Zimmerman dev_warn(hsotg->dev, "can't set coherent DMA mask\n"); 2826197ba5f4SPaul Zimmerman } 2827197ba5f4SPaul Zimmerman 2828197ba5f4SPaul Zimmerman hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev)); 2829197ba5f4SPaul Zimmerman if (!hcd) 2830197ba5f4SPaul Zimmerman goto error1; 2831197ba5f4SPaul Zimmerman 2832197ba5f4SPaul Zimmerman if (hsotg->core_params->dma_enable <= 0) 2833197ba5f4SPaul Zimmerman hcd->self.uses_dma = 0; 2834197ba5f4SPaul Zimmerman 2835197ba5f4SPaul Zimmerman hcd->has_tt = 1; 2836197ba5f4SPaul Zimmerman 2837197ba5f4SPaul Zimmerman spin_lock_init(&hsotg->lock); 2838197ba5f4SPaul Zimmerman ((struct wrapper_priv_data *) &hcd->hcd_priv)->hsotg = hsotg; 2839197ba5f4SPaul Zimmerman hsotg->priv = hcd; 2840197ba5f4SPaul Zimmerman 2841197ba5f4SPaul Zimmerman /* 2842197ba5f4SPaul Zimmerman * Disable the global interrupt until all the interrupt handlers are 2843197ba5f4SPaul Zimmerman * installed 2844197ba5f4SPaul Zimmerman */ 2845197ba5f4SPaul Zimmerman dwc2_disable_global_interrupts(hsotg); 2846197ba5f4SPaul Zimmerman 2847197ba5f4SPaul Zimmerman /* Initialize the DWC_otg core, and select the Phy type */ 2848197ba5f4SPaul Zimmerman retval = dwc2_core_init(hsotg, true, irq); 2849197ba5f4SPaul Zimmerman if (retval) 2850197ba5f4SPaul Zimmerman goto error2; 2851197ba5f4SPaul Zimmerman 2852197ba5f4SPaul Zimmerman /* Create new workqueue and init work */ 2853197ba5f4SPaul Zimmerman retval = -ENOMEM; 2854197ba5f4SPaul Zimmerman hsotg->wq_otg = create_singlethread_workqueue("dwc2"); 2855197ba5f4SPaul Zimmerman if (!hsotg->wq_otg) { 2856197ba5f4SPaul Zimmerman dev_err(hsotg->dev, "Failed to create workqueue\n"); 2857197ba5f4SPaul Zimmerman goto error2; 2858197ba5f4SPaul Zimmerman } 2859197ba5f4SPaul Zimmerman INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change); 2860197ba5f4SPaul Zimmerman 2861197ba5f4SPaul Zimmerman setup_timer(&hsotg->wkp_timer, dwc2_wakeup_detected, 2862197ba5f4SPaul Zimmerman (unsigned long)hsotg); 2863197ba5f4SPaul Zimmerman 2864197ba5f4SPaul Zimmerman /* Initialize the non-periodic schedule */ 2865197ba5f4SPaul Zimmerman INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive); 2866197ba5f4SPaul Zimmerman INIT_LIST_HEAD(&hsotg->non_periodic_sched_active); 2867197ba5f4SPaul Zimmerman 2868197ba5f4SPaul Zimmerman /* Initialize the periodic schedule */ 2869197ba5f4SPaul Zimmerman INIT_LIST_HEAD(&hsotg->periodic_sched_inactive); 2870197ba5f4SPaul Zimmerman INIT_LIST_HEAD(&hsotg->periodic_sched_ready); 2871197ba5f4SPaul Zimmerman INIT_LIST_HEAD(&hsotg->periodic_sched_assigned); 2872197ba5f4SPaul Zimmerman INIT_LIST_HEAD(&hsotg->periodic_sched_queued); 2873197ba5f4SPaul Zimmerman 2874197ba5f4SPaul Zimmerman /* 2875197ba5f4SPaul Zimmerman * Create a host channel descriptor for each host channel implemented 2876197ba5f4SPaul Zimmerman * in the controller. Initialize the channel descriptor array. 2877197ba5f4SPaul Zimmerman */ 2878197ba5f4SPaul Zimmerman INIT_LIST_HEAD(&hsotg->free_hc_list); 2879197ba5f4SPaul Zimmerman num_channels = hsotg->core_params->host_channels; 2880197ba5f4SPaul Zimmerman memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array)); 2881197ba5f4SPaul Zimmerman 2882197ba5f4SPaul Zimmerman for (i = 0; i < num_channels; i++) { 2883197ba5f4SPaul Zimmerman channel = kzalloc(sizeof(*channel), GFP_KERNEL); 2884197ba5f4SPaul Zimmerman if (channel == NULL) 2885197ba5f4SPaul Zimmerman goto error3; 2886197ba5f4SPaul Zimmerman channel->hc_num = i; 2887197ba5f4SPaul Zimmerman hsotg->hc_ptr_array[i] = channel; 2888197ba5f4SPaul Zimmerman } 2889197ba5f4SPaul Zimmerman 2890197ba5f4SPaul Zimmerman if (hsotg->core_params->uframe_sched > 0) 2891197ba5f4SPaul Zimmerman dwc2_hcd_init_usecs(hsotg); 2892197ba5f4SPaul Zimmerman 2893197ba5f4SPaul Zimmerman /* Initialize hsotg start work */ 2894197ba5f4SPaul Zimmerman INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func); 2895197ba5f4SPaul Zimmerman 2896197ba5f4SPaul Zimmerman /* Initialize port reset work */ 2897197ba5f4SPaul Zimmerman INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func); 2898197ba5f4SPaul Zimmerman 2899197ba5f4SPaul Zimmerman /* 2900197ba5f4SPaul Zimmerman * Allocate space for storing data on status transactions. Normally no 2901197ba5f4SPaul Zimmerman * data is sent, but this space acts as a bit bucket. This must be 2902197ba5f4SPaul Zimmerman * done after usb_add_hcd since that function allocates the DMA buffer 2903197ba5f4SPaul Zimmerman * pool. 2904197ba5f4SPaul Zimmerman */ 2905197ba5f4SPaul Zimmerman if (hsotg->core_params->dma_enable > 0) 2906197ba5f4SPaul Zimmerman hsotg->status_buf = dma_alloc_coherent(hsotg->dev, 2907197ba5f4SPaul Zimmerman DWC2_HCD_STATUS_BUF_SIZE, 2908197ba5f4SPaul Zimmerman &hsotg->status_buf_dma, GFP_KERNEL); 2909197ba5f4SPaul Zimmerman else 2910197ba5f4SPaul Zimmerman hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE, 2911197ba5f4SPaul Zimmerman GFP_KERNEL); 2912197ba5f4SPaul Zimmerman 2913197ba5f4SPaul Zimmerman if (!hsotg->status_buf) 2914197ba5f4SPaul Zimmerman goto error3; 2915197ba5f4SPaul Zimmerman 2916197ba5f4SPaul Zimmerman hsotg->otg_port = 1; 2917197ba5f4SPaul Zimmerman hsotg->frame_list = NULL; 2918197ba5f4SPaul Zimmerman hsotg->frame_list_dma = 0; 2919197ba5f4SPaul Zimmerman hsotg->periodic_qh_count = 0; 2920197ba5f4SPaul Zimmerman 2921197ba5f4SPaul Zimmerman /* Initiate lx_state to L3 disconnected state */ 2922197ba5f4SPaul Zimmerman hsotg->lx_state = DWC2_L3; 2923197ba5f4SPaul Zimmerman 2924197ba5f4SPaul Zimmerman hcd->self.otg_port = hsotg->otg_port; 2925197ba5f4SPaul Zimmerman 2926197ba5f4SPaul Zimmerman /* Don't support SG list at this point */ 2927197ba5f4SPaul Zimmerman hcd->self.sg_tablesize = 0; 2928197ba5f4SPaul Zimmerman 2929197ba5f4SPaul Zimmerman /* 2930197ba5f4SPaul Zimmerman * Finish generic HCD initialization and start the HCD. This function 2931197ba5f4SPaul Zimmerman * allocates the DMA buffer pool, registers the USB bus, requests the 2932197ba5f4SPaul Zimmerman * IRQ line, and calls hcd_start method. 2933197ba5f4SPaul Zimmerman */ 2934197ba5f4SPaul Zimmerman retval = usb_add_hcd(hcd, irq, IRQF_SHARED); 2935197ba5f4SPaul Zimmerman if (retval < 0) 2936197ba5f4SPaul Zimmerman goto error3; 2937197ba5f4SPaul Zimmerman 2938*ec513b16SLinus Torvalds device_wakeup_enable(hcd->self.controller); 2939*ec513b16SLinus Torvalds 2940197ba5f4SPaul Zimmerman dwc2_hcd_dump_state(hsotg); 2941197ba5f4SPaul Zimmerman 2942197ba5f4SPaul Zimmerman dwc2_enable_global_interrupts(hsotg); 2943197ba5f4SPaul Zimmerman 2944197ba5f4SPaul Zimmerman return 0; 2945197ba5f4SPaul Zimmerman 2946197ba5f4SPaul Zimmerman error3: 2947197ba5f4SPaul Zimmerman dwc2_hcd_release(hsotg); 2948197ba5f4SPaul Zimmerman error2: 2949197ba5f4SPaul Zimmerman usb_put_hcd(hcd); 2950197ba5f4SPaul Zimmerman error1: 2951197ba5f4SPaul Zimmerman kfree(hsotg->core_params); 2952197ba5f4SPaul Zimmerman 2953197ba5f4SPaul Zimmerman #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 2954197ba5f4SPaul Zimmerman kfree(hsotg->last_frame_num_array); 2955197ba5f4SPaul Zimmerman kfree(hsotg->frame_num_array); 2956197ba5f4SPaul Zimmerman #endif 2957197ba5f4SPaul Zimmerman 2958197ba5f4SPaul Zimmerman dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval); 2959197ba5f4SPaul Zimmerman return retval; 2960197ba5f4SPaul Zimmerman } 2961197ba5f4SPaul Zimmerman EXPORT_SYMBOL_GPL(dwc2_hcd_init); 2962197ba5f4SPaul Zimmerman 2963197ba5f4SPaul Zimmerman /* 2964197ba5f4SPaul Zimmerman * Removes the HCD. 2965197ba5f4SPaul Zimmerman * Frees memory and resources associated with the HCD and deregisters the bus. 2966197ba5f4SPaul Zimmerman */ 2967197ba5f4SPaul Zimmerman void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) 2968197ba5f4SPaul Zimmerman { 2969197ba5f4SPaul Zimmerman struct usb_hcd *hcd; 2970197ba5f4SPaul Zimmerman 2971197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n"); 2972197ba5f4SPaul Zimmerman 2973197ba5f4SPaul Zimmerman hcd = dwc2_hsotg_to_hcd(hsotg); 2974197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd); 2975197ba5f4SPaul Zimmerman 2976197ba5f4SPaul Zimmerman if (!hcd) { 2977197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n", 2978197ba5f4SPaul Zimmerman __func__); 2979197ba5f4SPaul Zimmerman return; 2980197ba5f4SPaul Zimmerman } 2981197ba5f4SPaul Zimmerman 2982197ba5f4SPaul Zimmerman usb_remove_hcd(hcd); 2983197ba5f4SPaul Zimmerman hsotg->priv = NULL; 2984197ba5f4SPaul Zimmerman dwc2_hcd_release(hsotg); 2985197ba5f4SPaul Zimmerman usb_put_hcd(hcd); 2986197ba5f4SPaul Zimmerman 2987197ba5f4SPaul Zimmerman #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 2988197ba5f4SPaul Zimmerman kfree(hsotg->last_frame_num_array); 2989197ba5f4SPaul Zimmerman kfree(hsotg->frame_num_array); 2990197ba5f4SPaul Zimmerman #endif 2991197ba5f4SPaul Zimmerman } 2992197ba5f4SPaul Zimmerman EXPORT_SYMBOL_GPL(dwc2_hcd_remove); 2993