1197ba5f4SPaul Zimmerman /* 2197ba5f4SPaul Zimmerman * hcd.c - DesignWare HS OTG Controller host-mode routines 3197ba5f4SPaul Zimmerman * 4197ba5f4SPaul Zimmerman * Copyright (C) 2004-2013 Synopsys, Inc. 5197ba5f4SPaul Zimmerman * 6197ba5f4SPaul Zimmerman * Redistribution and use in source and binary forms, with or without 7197ba5f4SPaul Zimmerman * modification, are permitted provided that the following conditions 8197ba5f4SPaul Zimmerman * are met: 9197ba5f4SPaul Zimmerman * 1. Redistributions of source code must retain the above copyright 10197ba5f4SPaul Zimmerman * notice, this list of conditions, and the following disclaimer, 11197ba5f4SPaul Zimmerman * without modification. 12197ba5f4SPaul Zimmerman * 2. Redistributions in binary form must reproduce the above copyright 13197ba5f4SPaul Zimmerman * notice, this list of conditions and the following disclaimer in the 14197ba5f4SPaul Zimmerman * documentation and/or other materials provided with the distribution. 15197ba5f4SPaul Zimmerman * 3. The names of the above-listed copyright holders may not be used 16197ba5f4SPaul Zimmerman * to endorse or promote products derived from this software without 17197ba5f4SPaul Zimmerman * specific prior written permission. 18197ba5f4SPaul Zimmerman * 19197ba5f4SPaul Zimmerman * ALTERNATIVELY, this software may be distributed under the terms of the 20197ba5f4SPaul Zimmerman * GNU General Public License ("GPL") as published by the Free Software 21197ba5f4SPaul Zimmerman * Foundation; either version 2 of the License, or (at your option) any 22197ba5f4SPaul Zimmerman * later version. 23197ba5f4SPaul Zimmerman * 24197ba5f4SPaul Zimmerman * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25197ba5f4SPaul Zimmerman * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26197ba5f4SPaul Zimmerman * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27197ba5f4SPaul Zimmerman * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28197ba5f4SPaul Zimmerman * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29197ba5f4SPaul Zimmerman * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30197ba5f4SPaul Zimmerman * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31197ba5f4SPaul Zimmerman * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32197ba5f4SPaul Zimmerman * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33197ba5f4SPaul Zimmerman * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34197ba5f4SPaul Zimmerman * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35197ba5f4SPaul Zimmerman */ 36197ba5f4SPaul Zimmerman 37197ba5f4SPaul Zimmerman /* 38197ba5f4SPaul Zimmerman * This file contains the core HCD code, and implements the Linux hc_driver 39197ba5f4SPaul Zimmerman * API 40197ba5f4SPaul Zimmerman */ 41197ba5f4SPaul Zimmerman #include <linux/kernel.h> 42197ba5f4SPaul Zimmerman #include <linux/module.h> 43197ba5f4SPaul Zimmerman #include <linux/spinlock.h> 44197ba5f4SPaul Zimmerman #include <linux/interrupt.h> 45197ba5f4SPaul Zimmerman #include <linux/dma-mapping.h> 46197ba5f4SPaul Zimmerman #include <linux/delay.h> 47197ba5f4SPaul Zimmerman #include <linux/io.h> 48197ba5f4SPaul Zimmerman #include <linux/slab.h> 49197ba5f4SPaul Zimmerman #include <linux/usb.h> 50197ba5f4SPaul Zimmerman 51197ba5f4SPaul Zimmerman #include <linux/usb/hcd.h> 52197ba5f4SPaul Zimmerman #include <linux/usb/ch11.h> 53197ba5f4SPaul Zimmerman 54197ba5f4SPaul Zimmerman #include "core.h" 55197ba5f4SPaul Zimmerman #include "hcd.h" 56197ba5f4SPaul Zimmerman 57*9156a7efSChen Yu static void dwc2_port_resume(struct dwc2_hsotg *hsotg); 58*9156a7efSChen Yu 59b02038faSJohn Youn /* 60b02038faSJohn Youn * ========================================================================= 61b02038faSJohn Youn * Host Core Layer Functions 62b02038faSJohn Youn * ========================================================================= 63b02038faSJohn Youn */ 64b02038faSJohn Youn 65b02038faSJohn Youn /** 66b02038faSJohn Youn * dwc2_enable_common_interrupts() - Initializes the commmon interrupts, 67b02038faSJohn Youn * used in both device and host modes 68b02038faSJohn Youn * 69b02038faSJohn Youn * @hsotg: Programming view of the DWC_otg controller 70b02038faSJohn Youn */ 71b02038faSJohn Youn static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg) 72b02038faSJohn Youn { 73b02038faSJohn Youn u32 intmsk; 74b02038faSJohn Youn 75b02038faSJohn Youn /* Clear any pending OTG Interrupts */ 76b02038faSJohn Youn dwc2_writel(0xffffffff, hsotg->regs + GOTGINT); 77b02038faSJohn Youn 78b02038faSJohn Youn /* Clear any pending interrupts */ 79b02038faSJohn Youn dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); 80b02038faSJohn Youn 81b02038faSJohn Youn /* Enable the interrupts in the GINTMSK */ 82b02038faSJohn Youn intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT; 83b02038faSJohn Youn 8495832c00SJohn Youn if (!hsotg->params.host_dma) 85b02038faSJohn Youn intmsk |= GINTSTS_RXFLVL; 8695832c00SJohn Youn if (!hsotg->params.external_id_pin_ctl) 87b02038faSJohn Youn intmsk |= GINTSTS_CONIDSTSCHNG; 88b02038faSJohn Youn 89b02038faSJohn Youn intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP | 90b02038faSJohn Youn GINTSTS_SESSREQINT; 91b02038faSJohn Youn 92b02038faSJohn Youn dwc2_writel(intmsk, hsotg->regs + GINTMSK); 93b02038faSJohn Youn } 94b02038faSJohn Youn 95b02038faSJohn Youn /* 96b02038faSJohn Youn * Initializes the FSLSPClkSel field of the HCFG register depending on the 97b02038faSJohn Youn * PHY type 98b02038faSJohn Youn */ 99b02038faSJohn Youn static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg) 100b02038faSJohn Youn { 101b02038faSJohn Youn u32 hcfg, val; 102b02038faSJohn Youn 103b02038faSJohn Youn if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && 104b02038faSJohn Youn hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && 10595832c00SJohn Youn hsotg->params.ulpi_fs_ls) || 106bea8e86cSJohn Youn hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) { 107b02038faSJohn Youn /* Full speed PHY */ 108b02038faSJohn Youn val = HCFG_FSLSPCLKSEL_48_MHZ; 109b02038faSJohn Youn } else { 110b02038faSJohn Youn /* High speed PHY running at full speed or high speed */ 111b02038faSJohn Youn val = HCFG_FSLSPCLKSEL_30_60_MHZ; 112b02038faSJohn Youn } 113b02038faSJohn Youn 114b02038faSJohn Youn dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val); 115b02038faSJohn Youn hcfg = dwc2_readl(hsotg->regs + HCFG); 116b02038faSJohn Youn hcfg &= ~HCFG_FSLSPCLKSEL_MASK; 117b02038faSJohn Youn hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT; 118b02038faSJohn Youn dwc2_writel(hcfg, hsotg->regs + HCFG); 119b02038faSJohn Youn } 120b02038faSJohn Youn 121b02038faSJohn Youn static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 122b02038faSJohn Youn { 123b02038faSJohn Youn u32 usbcfg, i2cctl; 124b02038faSJohn Youn int retval = 0; 125b02038faSJohn Youn 126b02038faSJohn Youn /* 127b02038faSJohn Youn * core_init() is now called on every switch so only call the 128b02038faSJohn Youn * following for the first time through 129b02038faSJohn Youn */ 130b02038faSJohn Youn if (select_phy) { 131b02038faSJohn Youn dev_dbg(hsotg->dev, "FS PHY selected\n"); 132b02038faSJohn Youn 133b02038faSJohn Youn usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 134b02038faSJohn Youn if (!(usbcfg & GUSBCFG_PHYSEL)) { 135b02038faSJohn Youn usbcfg |= GUSBCFG_PHYSEL; 136b02038faSJohn Youn dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 137b02038faSJohn Youn 138b02038faSJohn Youn /* Reset after a PHY select */ 139b02038faSJohn Youn retval = dwc2_core_reset_and_force_dr_mode(hsotg); 140b02038faSJohn Youn 141b02038faSJohn Youn if (retval) { 142b02038faSJohn Youn dev_err(hsotg->dev, 143b02038faSJohn Youn "%s: Reset failed, aborting", __func__); 144b02038faSJohn Youn return retval; 145b02038faSJohn Youn } 146b02038faSJohn Youn } 147b02038faSJohn Youn } 148b02038faSJohn Youn 149b02038faSJohn Youn /* 150b02038faSJohn Youn * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also 151b02038faSJohn Youn * do this on HNP Dev/Host mode switches (done in dev_init and 152b02038faSJohn Youn * host_init). 153b02038faSJohn Youn */ 154b02038faSJohn Youn if (dwc2_is_host_mode(hsotg)) 155b02038faSJohn Youn dwc2_init_fs_ls_pclk_sel(hsotg); 156b02038faSJohn Youn 15795832c00SJohn Youn if (hsotg->params.i2c_enable) { 158b02038faSJohn Youn dev_dbg(hsotg->dev, "FS PHY enabling I2C\n"); 159b02038faSJohn Youn 160b02038faSJohn Youn /* Program GUSBCFG.OtgUtmiFsSel to I2C */ 161b02038faSJohn Youn usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 162b02038faSJohn Youn usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL; 163b02038faSJohn Youn dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 164b02038faSJohn Youn 165b02038faSJohn Youn /* Program GI2CCTL.I2CEn */ 166b02038faSJohn Youn i2cctl = dwc2_readl(hsotg->regs + GI2CCTL); 167b02038faSJohn Youn i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK; 168b02038faSJohn Youn i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT; 169b02038faSJohn Youn i2cctl &= ~GI2CCTL_I2CEN; 170b02038faSJohn Youn dwc2_writel(i2cctl, hsotg->regs + GI2CCTL); 171b02038faSJohn Youn i2cctl |= GI2CCTL_I2CEN; 172b02038faSJohn Youn dwc2_writel(i2cctl, hsotg->regs + GI2CCTL); 173b02038faSJohn Youn } 174b02038faSJohn Youn 175b02038faSJohn Youn return retval; 176b02038faSJohn Youn } 177b02038faSJohn Youn 178b02038faSJohn Youn static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 179b02038faSJohn Youn { 180b02038faSJohn Youn u32 usbcfg, usbcfg_old; 181b02038faSJohn Youn int retval = 0; 182b02038faSJohn Youn 183b02038faSJohn Youn if (!select_phy) 184b02038faSJohn Youn return 0; 185b02038faSJohn Youn 186b02038faSJohn Youn usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 187b02038faSJohn Youn usbcfg_old = usbcfg; 188b02038faSJohn Youn 189b02038faSJohn Youn /* 190b02038faSJohn Youn * HS PHY parameters. These parameters are preserved during soft reset 191b02038faSJohn Youn * so only program the first time. Do a soft reset immediately after 192b02038faSJohn Youn * setting phyif. 193b02038faSJohn Youn */ 194bea8e86cSJohn Youn switch (hsotg->params.phy_type) { 195b02038faSJohn Youn case DWC2_PHY_TYPE_PARAM_ULPI: 196b02038faSJohn Youn /* ULPI interface */ 197b02038faSJohn Youn dev_dbg(hsotg->dev, "HS ULPI PHY selected\n"); 198b02038faSJohn Youn usbcfg |= GUSBCFG_ULPI_UTMI_SEL; 199b02038faSJohn Youn usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL); 20095832c00SJohn Youn if (hsotg->params.phy_ulpi_ddr) 201b02038faSJohn Youn usbcfg |= GUSBCFG_DDRSEL; 202b02038faSJohn Youn break; 203b02038faSJohn Youn case DWC2_PHY_TYPE_PARAM_UTMI: 204b02038faSJohn Youn /* UTMI+ interface */ 205b02038faSJohn Youn dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n"); 206b02038faSJohn Youn usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16); 207bea8e86cSJohn Youn if (hsotg->params.phy_utmi_width == 16) 208b02038faSJohn Youn usbcfg |= GUSBCFG_PHYIF16; 209b02038faSJohn Youn break; 210b02038faSJohn Youn default: 211b02038faSJohn Youn dev_err(hsotg->dev, "FS PHY selected at HS!\n"); 212b02038faSJohn Youn break; 213b02038faSJohn Youn } 214b02038faSJohn Youn 215b02038faSJohn Youn if (usbcfg != usbcfg_old) { 216b02038faSJohn Youn dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 217b02038faSJohn Youn 218b02038faSJohn Youn /* Reset after setting the PHY parameters */ 219b02038faSJohn Youn retval = dwc2_core_reset_and_force_dr_mode(hsotg); 220b02038faSJohn Youn if (retval) { 221b02038faSJohn Youn dev_err(hsotg->dev, 222b02038faSJohn Youn "%s: Reset failed, aborting", __func__); 223b02038faSJohn Youn return retval; 224b02038faSJohn Youn } 225b02038faSJohn Youn } 226b02038faSJohn Youn 227b02038faSJohn Youn return retval; 228b02038faSJohn Youn } 229b02038faSJohn Youn 230b02038faSJohn Youn static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 231b02038faSJohn Youn { 232b02038faSJohn Youn u32 usbcfg; 233b02038faSJohn Youn int retval = 0; 234b02038faSJohn Youn 23538e9002bSVardan Mikayelyan if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL || 23638e9002bSVardan Mikayelyan hsotg->params.speed == DWC2_SPEED_PARAM_LOW) && 237bea8e86cSJohn Youn hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) { 23838e9002bSVardan Mikayelyan /* If FS/LS mode with FS/LS PHY */ 239b02038faSJohn Youn retval = dwc2_fs_phy_init(hsotg, select_phy); 240b02038faSJohn Youn if (retval) 241b02038faSJohn Youn return retval; 242b02038faSJohn Youn } else { 243b02038faSJohn Youn /* High speed PHY */ 244b02038faSJohn Youn retval = dwc2_hs_phy_init(hsotg, select_phy); 245b02038faSJohn Youn if (retval) 246b02038faSJohn Youn return retval; 247b02038faSJohn Youn } 248b02038faSJohn Youn 249b02038faSJohn Youn if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && 250b02038faSJohn Youn hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && 25195832c00SJohn Youn hsotg->params.ulpi_fs_ls) { 252b02038faSJohn Youn dev_dbg(hsotg->dev, "Setting ULPI FSLS\n"); 253b02038faSJohn Youn usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 254b02038faSJohn Youn usbcfg |= GUSBCFG_ULPI_FS_LS; 255b02038faSJohn Youn usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M; 256b02038faSJohn Youn dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 257b02038faSJohn Youn } else { 258b02038faSJohn Youn usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 259b02038faSJohn Youn usbcfg &= ~GUSBCFG_ULPI_FS_LS; 260b02038faSJohn Youn usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M; 261b02038faSJohn Youn dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 262b02038faSJohn Youn } 263b02038faSJohn Youn 264b02038faSJohn Youn return retval; 265b02038faSJohn Youn } 266b02038faSJohn Youn 267b02038faSJohn Youn static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg) 268b02038faSJohn Youn { 269b02038faSJohn Youn u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 270b02038faSJohn Youn 271b02038faSJohn Youn switch (hsotg->hw_params.arch) { 272b02038faSJohn Youn case GHWCFG2_EXT_DMA_ARCH: 273b02038faSJohn Youn dev_err(hsotg->dev, "External DMA Mode not supported\n"); 274b02038faSJohn Youn return -EINVAL; 275b02038faSJohn Youn 276b02038faSJohn Youn case GHWCFG2_INT_DMA_ARCH: 277b02038faSJohn Youn dev_dbg(hsotg->dev, "Internal DMA Mode\n"); 278bea8e86cSJohn Youn if (hsotg->params.ahbcfg != -1) { 279b02038faSJohn Youn ahbcfg &= GAHBCFG_CTRL_MASK; 280bea8e86cSJohn Youn ahbcfg |= hsotg->params.ahbcfg & 281b02038faSJohn Youn ~GAHBCFG_CTRL_MASK; 282b02038faSJohn Youn } 283b02038faSJohn Youn break; 284b02038faSJohn Youn 285b02038faSJohn Youn case GHWCFG2_SLAVE_ONLY_ARCH: 286b02038faSJohn Youn default: 287b02038faSJohn Youn dev_dbg(hsotg->dev, "Slave Only Mode\n"); 288b02038faSJohn Youn break; 289b02038faSJohn Youn } 290b02038faSJohn Youn 291e7839f99SJohn Youn dev_dbg(hsotg->dev, "host_dma:%d dma_desc_enable:%d\n", 292e7839f99SJohn Youn hsotg->params.host_dma, 293bea8e86cSJohn Youn hsotg->params.dma_desc_enable); 294b02038faSJohn Youn 29595832c00SJohn Youn if (hsotg->params.host_dma) { 29695832c00SJohn Youn if (hsotg->params.dma_desc_enable) 297b02038faSJohn Youn dev_dbg(hsotg->dev, "Using Descriptor DMA mode\n"); 298b02038faSJohn Youn else 299b02038faSJohn Youn dev_dbg(hsotg->dev, "Using Buffer DMA mode\n"); 300b02038faSJohn Youn } else { 301b02038faSJohn Youn dev_dbg(hsotg->dev, "Using Slave mode\n"); 30295832c00SJohn Youn hsotg->params.dma_desc_enable = false; 303b02038faSJohn Youn } 304b02038faSJohn Youn 30595832c00SJohn Youn if (hsotg->params.host_dma) 306b02038faSJohn Youn ahbcfg |= GAHBCFG_DMA_EN; 307b02038faSJohn Youn 308b02038faSJohn Youn dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); 309b02038faSJohn Youn 310b02038faSJohn Youn return 0; 311b02038faSJohn Youn } 312b02038faSJohn Youn 313b02038faSJohn Youn static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg) 314b02038faSJohn Youn { 315b02038faSJohn Youn u32 usbcfg; 316b02038faSJohn Youn 317b02038faSJohn Youn usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 318b02038faSJohn Youn usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP); 319b02038faSJohn Youn 320b02038faSJohn Youn switch (hsotg->hw_params.op_mode) { 321b02038faSJohn Youn case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 322bea8e86cSJohn Youn if (hsotg->params.otg_cap == 323b02038faSJohn Youn DWC2_CAP_PARAM_HNP_SRP_CAPABLE) 324b02038faSJohn Youn usbcfg |= GUSBCFG_HNPCAP; 325bea8e86cSJohn Youn if (hsotg->params.otg_cap != 326b02038faSJohn Youn DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE) 327b02038faSJohn Youn usbcfg |= GUSBCFG_SRPCAP; 328b02038faSJohn Youn break; 329b02038faSJohn Youn 330b02038faSJohn Youn case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 331b02038faSJohn Youn case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 332b02038faSJohn Youn case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 333bea8e86cSJohn Youn if (hsotg->params.otg_cap != 334b02038faSJohn Youn DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE) 335b02038faSJohn Youn usbcfg |= GUSBCFG_SRPCAP; 336b02038faSJohn Youn break; 337b02038faSJohn Youn 338b02038faSJohn Youn case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE: 339b02038faSJohn Youn case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE: 340b02038faSJohn Youn case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST: 341b02038faSJohn Youn default: 342b02038faSJohn Youn break; 343b02038faSJohn Youn } 344b02038faSJohn Youn 345b02038faSJohn Youn dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 346b02038faSJohn Youn } 347b02038faSJohn Youn 348b02038faSJohn Youn /** 349b02038faSJohn Youn * dwc2_enable_host_interrupts() - Enables the Host mode interrupts 350b02038faSJohn Youn * 351b02038faSJohn Youn * @hsotg: Programming view of DWC_otg controller 352b02038faSJohn Youn */ 353b02038faSJohn Youn static void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg) 354b02038faSJohn Youn { 355b02038faSJohn Youn u32 intmsk; 356b02038faSJohn Youn 357b02038faSJohn Youn dev_dbg(hsotg->dev, "%s()\n", __func__); 358b02038faSJohn Youn 359b02038faSJohn Youn /* Disable all interrupts */ 360b02038faSJohn Youn dwc2_writel(0, hsotg->regs + GINTMSK); 361b02038faSJohn Youn dwc2_writel(0, hsotg->regs + HAINTMSK); 362b02038faSJohn Youn 363b02038faSJohn Youn /* Enable the common interrupts */ 364b02038faSJohn Youn dwc2_enable_common_interrupts(hsotg); 365b02038faSJohn Youn 366b02038faSJohn Youn /* Enable host mode interrupts without disturbing common interrupts */ 367b02038faSJohn Youn intmsk = dwc2_readl(hsotg->regs + GINTMSK); 368b02038faSJohn Youn intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT; 369b02038faSJohn Youn dwc2_writel(intmsk, hsotg->regs + GINTMSK); 370b02038faSJohn Youn } 371b02038faSJohn Youn 372b02038faSJohn Youn /** 373b02038faSJohn Youn * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts 374b02038faSJohn Youn * 375b02038faSJohn Youn * @hsotg: Programming view of DWC_otg controller 376b02038faSJohn Youn */ 377b02038faSJohn Youn static void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg) 378b02038faSJohn Youn { 379b02038faSJohn Youn u32 intmsk = dwc2_readl(hsotg->regs + GINTMSK); 380b02038faSJohn Youn 381b02038faSJohn Youn /* Disable host mode interrupts without disturbing common interrupts */ 382b02038faSJohn Youn intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT | 383b02038faSJohn Youn GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT); 384b02038faSJohn Youn dwc2_writel(intmsk, hsotg->regs + GINTMSK); 385b02038faSJohn Youn } 386b02038faSJohn Youn 387b02038faSJohn Youn /* 388b02038faSJohn Youn * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size 389b02038faSJohn Youn * For system that have a total fifo depth that is smaller than the default 390b02038faSJohn Youn * RX + TX fifo size. 391b02038faSJohn Youn * 392b02038faSJohn Youn * @hsotg: Programming view of DWC_otg controller 393b02038faSJohn Youn */ 394b02038faSJohn Youn static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg) 395b02038faSJohn Youn { 396bea8e86cSJohn Youn struct dwc2_core_params *params = &hsotg->params; 397b02038faSJohn Youn struct dwc2_hw_params *hw = &hsotg->hw_params; 398b02038faSJohn Youn u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size; 399b02038faSJohn Youn 400b02038faSJohn Youn total_fifo_size = hw->total_fifo_size; 401b02038faSJohn Youn rxfsiz = params->host_rx_fifo_size; 402b02038faSJohn Youn nptxfsiz = params->host_nperio_tx_fifo_size; 403b02038faSJohn Youn ptxfsiz = params->host_perio_tx_fifo_size; 404b02038faSJohn Youn 405b02038faSJohn Youn /* 406b02038faSJohn Youn * Will use Method 2 defined in the DWC2 spec: minimum FIFO depth 407b02038faSJohn Youn * allocation with support for high bandwidth endpoints. Synopsys 408b02038faSJohn Youn * defines MPS(Max Packet size) for a periodic EP=1024, and for 409b02038faSJohn Youn * non-periodic as 512. 410b02038faSJohn Youn */ 411b02038faSJohn Youn if (total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)) { 412b02038faSJohn Youn /* 413b02038faSJohn Youn * For Buffer DMA mode/Scatter Gather DMA mode 414b02038faSJohn Youn * 2 * ((Largest Packet size / 4) + 1 + 1) + n 415b02038faSJohn Youn * with n = number of host channel. 416b02038faSJohn Youn * 2 * ((1024/4) + 2) = 516 417b02038faSJohn Youn */ 418b02038faSJohn Youn rxfsiz = 516 + hw->host_channels; 419b02038faSJohn Youn 420b02038faSJohn Youn /* 421b02038faSJohn Youn * min non-periodic tx fifo depth 422b02038faSJohn Youn * 2 * (largest non-periodic USB packet used / 4) 423b02038faSJohn Youn * 2 * (512/4) = 256 424b02038faSJohn Youn */ 425b02038faSJohn Youn nptxfsiz = 256; 426b02038faSJohn Youn 427b02038faSJohn Youn /* 428b02038faSJohn Youn * min periodic tx fifo depth 429b02038faSJohn Youn * (largest packet size*MC)/4 430b02038faSJohn Youn * (1024 * 3)/4 = 768 431b02038faSJohn Youn */ 432b02038faSJohn Youn ptxfsiz = 768; 433b02038faSJohn Youn 434b02038faSJohn Youn params->host_rx_fifo_size = rxfsiz; 435b02038faSJohn Youn params->host_nperio_tx_fifo_size = nptxfsiz; 436b02038faSJohn Youn params->host_perio_tx_fifo_size = ptxfsiz; 437b02038faSJohn Youn } 438b02038faSJohn Youn 439b02038faSJohn Youn /* 440b02038faSJohn Youn * If the summation of RX, NPTX and PTX fifo sizes is still 441b02038faSJohn Youn * bigger than the total_fifo_size, then we have a problem. 442b02038faSJohn Youn * 443b02038faSJohn Youn * We won't be able to allocate as many endpoints. Right now, 444b02038faSJohn Youn * we're just printing an error message, but ideally this FIFO 445b02038faSJohn Youn * allocation algorithm would be improved in the future. 446b02038faSJohn Youn * 447b02038faSJohn Youn * FIXME improve this FIFO allocation algorithm. 448b02038faSJohn Youn */ 449b02038faSJohn Youn if (unlikely(total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz))) 450b02038faSJohn Youn dev_err(hsotg->dev, "invalid fifo sizes\n"); 451b02038faSJohn Youn } 452b02038faSJohn Youn 453b02038faSJohn Youn static void dwc2_config_fifos(struct dwc2_hsotg *hsotg) 454b02038faSJohn Youn { 455bea8e86cSJohn Youn struct dwc2_core_params *params = &hsotg->params; 456b02038faSJohn Youn u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz; 457b02038faSJohn Youn 458b02038faSJohn Youn if (!params->enable_dynamic_fifo) 459b02038faSJohn Youn return; 460b02038faSJohn Youn 461b02038faSJohn Youn dwc2_calculate_dynamic_fifo(hsotg); 462b02038faSJohn Youn 463b02038faSJohn Youn /* Rx FIFO */ 464b02038faSJohn Youn grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); 465b02038faSJohn Youn dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz); 466b02038faSJohn Youn grxfsiz &= ~GRXFSIZ_DEPTH_MASK; 467b02038faSJohn Youn grxfsiz |= params->host_rx_fifo_size << 468b02038faSJohn Youn GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK; 469b02038faSJohn Youn dwc2_writel(grxfsiz, hsotg->regs + GRXFSIZ); 470b02038faSJohn Youn dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", 471b02038faSJohn Youn dwc2_readl(hsotg->regs + GRXFSIZ)); 472b02038faSJohn Youn 473b02038faSJohn Youn /* Non-periodic Tx FIFO */ 474b02038faSJohn Youn dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n", 475b02038faSJohn Youn dwc2_readl(hsotg->regs + GNPTXFSIZ)); 476b02038faSJohn Youn nptxfsiz = params->host_nperio_tx_fifo_size << 477b02038faSJohn Youn FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; 478b02038faSJohn Youn nptxfsiz |= params->host_rx_fifo_size << 479b02038faSJohn Youn FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; 480b02038faSJohn Youn dwc2_writel(nptxfsiz, hsotg->regs + GNPTXFSIZ); 481b02038faSJohn Youn dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n", 482b02038faSJohn Youn dwc2_readl(hsotg->regs + GNPTXFSIZ)); 483b02038faSJohn Youn 484b02038faSJohn Youn /* Periodic Tx FIFO */ 485b02038faSJohn Youn dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n", 486b02038faSJohn Youn dwc2_readl(hsotg->regs + HPTXFSIZ)); 487b02038faSJohn Youn hptxfsiz = params->host_perio_tx_fifo_size << 488b02038faSJohn Youn FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; 489b02038faSJohn Youn hptxfsiz |= (params->host_rx_fifo_size + 490b02038faSJohn Youn params->host_nperio_tx_fifo_size) << 491b02038faSJohn Youn FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; 492b02038faSJohn Youn dwc2_writel(hptxfsiz, hsotg->regs + HPTXFSIZ); 493b02038faSJohn Youn dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n", 494b02038faSJohn Youn dwc2_readl(hsotg->regs + HPTXFSIZ)); 495b02038faSJohn Youn 49695832c00SJohn Youn if (hsotg->params.en_multiple_tx_fifo && 497b02038faSJohn Youn hsotg->hw_params.snpsid <= DWC2_CORE_REV_2_94a) { 498b02038faSJohn Youn /* 499b02038faSJohn Youn * Global DFIFOCFG calculation for Host mode - 500b02038faSJohn Youn * include RxFIFO, NPTXFIFO and HPTXFIFO 501b02038faSJohn Youn */ 502b02038faSJohn Youn dfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG); 503b02038faSJohn Youn dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK; 504b02038faSJohn Youn dfifocfg |= (params->host_rx_fifo_size + 505b02038faSJohn Youn params->host_nperio_tx_fifo_size + 506b02038faSJohn Youn params->host_perio_tx_fifo_size) << 507b02038faSJohn Youn GDFIFOCFG_EPINFOBASE_SHIFT & 508b02038faSJohn Youn GDFIFOCFG_EPINFOBASE_MASK; 509b02038faSJohn Youn dwc2_writel(dfifocfg, hsotg->regs + GDFIFOCFG); 510b02038faSJohn Youn } 511b02038faSJohn Youn } 512b02038faSJohn Youn 513b02038faSJohn Youn /** 514b02038faSJohn Youn * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for 515b02038faSJohn Youn * the HFIR register according to PHY type and speed 516b02038faSJohn Youn * 517b02038faSJohn Youn * @hsotg: Programming view of DWC_otg controller 518b02038faSJohn Youn * 519b02038faSJohn Youn * NOTE: The caller can modify the value of the HFIR register only after the 520b02038faSJohn Youn * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort) 521b02038faSJohn Youn * has been set 522b02038faSJohn Youn */ 523b02038faSJohn Youn u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg) 524b02038faSJohn Youn { 525b02038faSJohn Youn u32 usbcfg; 526b02038faSJohn Youn u32 hprt0; 527b02038faSJohn Youn int clock = 60; /* default value */ 528b02038faSJohn Youn 529b02038faSJohn Youn usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 530b02038faSJohn Youn hprt0 = dwc2_readl(hsotg->regs + HPRT0); 531b02038faSJohn Youn 532b02038faSJohn Youn if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) && 533b02038faSJohn Youn !(usbcfg & GUSBCFG_PHYIF16)) 534b02038faSJohn Youn clock = 60; 535b02038faSJohn Youn if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type == 536b02038faSJohn Youn GHWCFG2_FS_PHY_TYPE_SHARED_ULPI) 537b02038faSJohn Youn clock = 48; 538b02038faSJohn Youn if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 539b02038faSJohn Youn !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16)) 540b02038faSJohn Youn clock = 30; 541b02038faSJohn Youn if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 542b02038faSJohn Youn !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16)) 543b02038faSJohn Youn clock = 60; 544b02038faSJohn Youn if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 545b02038faSJohn Youn !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16)) 546b02038faSJohn Youn clock = 48; 547b02038faSJohn Youn if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) && 548b02038faSJohn Youn hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI) 549b02038faSJohn Youn clock = 48; 550b02038faSJohn Youn if ((usbcfg & GUSBCFG_PHYSEL) && 551b02038faSJohn Youn hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) 552b02038faSJohn Youn clock = 48; 553b02038faSJohn Youn 554b02038faSJohn Youn if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED) 555b02038faSJohn Youn /* High speed case */ 556b02038faSJohn Youn return 125 * clock - 1; 557b02038faSJohn Youn 558b02038faSJohn Youn /* FS/LS case */ 559b02038faSJohn Youn return 1000 * clock - 1; 560b02038faSJohn Youn } 561b02038faSJohn Youn 562b02038faSJohn Youn /** 563b02038faSJohn Youn * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination 564b02038faSJohn Youn * buffer 565b02038faSJohn Youn * 566b02038faSJohn Youn * @core_if: Programming view of DWC_otg controller 567b02038faSJohn Youn * @dest: Destination buffer for the packet 568b02038faSJohn Youn * @bytes: Number of bytes to copy to the destination 569b02038faSJohn Youn */ 570b02038faSJohn Youn void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes) 571b02038faSJohn Youn { 572b02038faSJohn Youn u32 __iomem *fifo = hsotg->regs + HCFIFO(0); 573b02038faSJohn Youn u32 *data_buf = (u32 *)dest; 574b02038faSJohn Youn int word_count = (bytes + 3) / 4; 575b02038faSJohn Youn int i; 576b02038faSJohn Youn 577b02038faSJohn Youn /* 578b02038faSJohn Youn * Todo: Account for the case where dest is not dword aligned. This 579b02038faSJohn Youn * requires reading data from the FIFO into a u32 temp buffer, then 580b02038faSJohn Youn * moving it into the data buffer. 581b02038faSJohn Youn */ 582b02038faSJohn Youn 583b02038faSJohn Youn dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes); 584b02038faSJohn Youn 585b02038faSJohn Youn for (i = 0; i < word_count; i++, data_buf++) 586b02038faSJohn Youn *data_buf = dwc2_readl(fifo); 587b02038faSJohn Youn } 588b02038faSJohn Youn 589197ba5f4SPaul Zimmerman /** 590197ba5f4SPaul Zimmerman * dwc2_dump_channel_info() - Prints the state of a host channel 591197ba5f4SPaul Zimmerman * 592197ba5f4SPaul Zimmerman * @hsotg: Programming view of DWC_otg controller 593197ba5f4SPaul Zimmerman * @chan: Pointer to the channel to dump 594197ba5f4SPaul Zimmerman * 595197ba5f4SPaul Zimmerman * Must be called with interrupt disabled and spinlock held 596197ba5f4SPaul Zimmerman * 597197ba5f4SPaul Zimmerman * NOTE: This function will be removed once the peripheral controller code 598197ba5f4SPaul Zimmerman * is integrated and the driver is stable 599197ba5f4SPaul Zimmerman */ 600197ba5f4SPaul Zimmerman static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg, 601197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan) 602197ba5f4SPaul Zimmerman { 603197ba5f4SPaul Zimmerman #ifdef VERBOSE_DEBUG 604bea8e86cSJohn Youn int num_channels = hsotg->params.host_channels; 605197ba5f4SPaul Zimmerman struct dwc2_qh *qh; 606197ba5f4SPaul Zimmerman u32 hcchar; 607197ba5f4SPaul Zimmerman u32 hcsplt; 608197ba5f4SPaul Zimmerman u32 hctsiz; 609197ba5f4SPaul Zimmerman u32 hc_dma; 610197ba5f4SPaul Zimmerman int i; 611197ba5f4SPaul Zimmerman 612b02038faSJohn Youn if (!chan) 613197ba5f4SPaul Zimmerman return; 614197ba5f4SPaul Zimmerman 61595c8bc36SAntti Seppälä hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 61695c8bc36SAntti Seppälä hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num)); 61795c8bc36SAntti Seppälä hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chan->hc_num)); 61895c8bc36SAntti Seppälä hc_dma = dwc2_readl(hsotg->regs + HCDMA(chan->hc_num)); 619197ba5f4SPaul Zimmerman 620197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan); 621197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", 622197ba5f4SPaul Zimmerman hcchar, hcsplt); 623197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", 624197ba5f4SPaul Zimmerman hctsiz, hc_dma); 625197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 626197ba5f4SPaul Zimmerman chan->dev_addr, chan->ep_num, chan->ep_is_in); 627197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 628197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 629197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start); 630197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started); 631197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 632197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 633197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 634197ba5f4SPaul Zimmerman (unsigned long)chan->xfer_dma); 635197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 636197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 637197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " NP inactive sched:\n"); 638197ba5f4SPaul Zimmerman list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive, 639197ba5f4SPaul Zimmerman qh_list_entry) 640197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " %p\n", qh); 641197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " NP active sched:\n"); 642197ba5f4SPaul Zimmerman list_for_each_entry(qh, &hsotg->non_periodic_sched_active, 643197ba5f4SPaul Zimmerman qh_list_entry) 644197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " %p\n", qh); 645197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " Channels:\n"); 646197ba5f4SPaul Zimmerman for (i = 0; i < num_channels; i++) { 647197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 648197ba5f4SPaul Zimmerman 649197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " %2d: %p\n", i, chan); 650197ba5f4SPaul Zimmerman } 651197ba5f4SPaul Zimmerman #endif /* VERBOSE_DEBUG */ 652197ba5f4SPaul Zimmerman } 653197ba5f4SPaul Zimmerman 6544411bebaSRazmik Karapetyan static int _dwc2_hcd_start(struct usb_hcd *hcd); 6554411bebaSRazmik Karapetyan 6564411bebaSRazmik Karapetyan static void dwc2_host_start(struct dwc2_hsotg *hsotg) 6574411bebaSRazmik Karapetyan { 6584411bebaSRazmik Karapetyan struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 6594411bebaSRazmik Karapetyan 6604411bebaSRazmik Karapetyan hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg); 6614411bebaSRazmik Karapetyan _dwc2_hcd_start(hcd); 6624411bebaSRazmik Karapetyan } 6634411bebaSRazmik Karapetyan 6644411bebaSRazmik Karapetyan static void dwc2_host_disconnect(struct dwc2_hsotg *hsotg) 6654411bebaSRazmik Karapetyan { 6664411bebaSRazmik Karapetyan struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 6674411bebaSRazmik Karapetyan 6684411bebaSRazmik Karapetyan hcd->self.is_b_host = 0; 6694411bebaSRazmik Karapetyan } 6704411bebaSRazmik Karapetyan 6714411bebaSRazmik Karapetyan static void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, 6724411bebaSRazmik Karapetyan int *hub_addr, int *hub_port) 6734411bebaSRazmik Karapetyan { 6744411bebaSRazmik Karapetyan struct urb *urb = context; 6754411bebaSRazmik Karapetyan 6764411bebaSRazmik Karapetyan if (urb->dev->tt) 6774411bebaSRazmik Karapetyan *hub_addr = urb->dev->tt->hub->devnum; 6784411bebaSRazmik Karapetyan else 6794411bebaSRazmik Karapetyan *hub_addr = 0; 6804411bebaSRazmik Karapetyan *hub_port = urb->dev->ttport; 6814411bebaSRazmik Karapetyan } 6824411bebaSRazmik Karapetyan 683197ba5f4SPaul Zimmerman /* 684b02038faSJohn Youn * ========================================================================= 685b02038faSJohn Youn * Low Level Host Channel Access Functions 686b02038faSJohn Youn * ========================================================================= 687b02038faSJohn Youn */ 688b02038faSJohn Youn 689b02038faSJohn Youn static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg, 690b02038faSJohn Youn struct dwc2_host_chan *chan) 691b02038faSJohn Youn { 692b02038faSJohn Youn u32 hcintmsk = HCINTMSK_CHHLTD; 693b02038faSJohn Youn 694b02038faSJohn Youn switch (chan->ep_type) { 695b02038faSJohn Youn case USB_ENDPOINT_XFER_CONTROL: 696b02038faSJohn Youn case USB_ENDPOINT_XFER_BULK: 697b02038faSJohn Youn dev_vdbg(hsotg->dev, "control/bulk\n"); 698b02038faSJohn Youn hcintmsk |= HCINTMSK_XFERCOMPL; 699b02038faSJohn Youn hcintmsk |= HCINTMSK_STALL; 700b02038faSJohn Youn hcintmsk |= HCINTMSK_XACTERR; 701b02038faSJohn Youn hcintmsk |= HCINTMSK_DATATGLERR; 702b02038faSJohn Youn if (chan->ep_is_in) { 703b02038faSJohn Youn hcintmsk |= HCINTMSK_BBLERR; 704b02038faSJohn Youn } else { 705b02038faSJohn Youn hcintmsk |= HCINTMSK_NAK; 706b02038faSJohn Youn hcintmsk |= HCINTMSK_NYET; 707b02038faSJohn Youn if (chan->do_ping) 708b02038faSJohn Youn hcintmsk |= HCINTMSK_ACK; 709b02038faSJohn Youn } 710b02038faSJohn Youn 711b02038faSJohn Youn if (chan->do_split) { 712b02038faSJohn Youn hcintmsk |= HCINTMSK_NAK; 713b02038faSJohn Youn if (chan->complete_split) 714b02038faSJohn Youn hcintmsk |= HCINTMSK_NYET; 715b02038faSJohn Youn else 716b02038faSJohn Youn hcintmsk |= HCINTMSK_ACK; 717b02038faSJohn Youn } 718b02038faSJohn Youn 719b02038faSJohn Youn if (chan->error_state) 720b02038faSJohn Youn hcintmsk |= HCINTMSK_ACK; 721b02038faSJohn Youn break; 722b02038faSJohn Youn 723b02038faSJohn Youn case USB_ENDPOINT_XFER_INT: 724b02038faSJohn Youn if (dbg_perio()) 725b02038faSJohn Youn dev_vdbg(hsotg->dev, "intr\n"); 726b02038faSJohn Youn hcintmsk |= HCINTMSK_XFERCOMPL; 727b02038faSJohn Youn hcintmsk |= HCINTMSK_NAK; 728b02038faSJohn Youn hcintmsk |= HCINTMSK_STALL; 729b02038faSJohn Youn hcintmsk |= HCINTMSK_XACTERR; 730b02038faSJohn Youn hcintmsk |= HCINTMSK_DATATGLERR; 731b02038faSJohn Youn hcintmsk |= HCINTMSK_FRMOVRUN; 732b02038faSJohn Youn 733b02038faSJohn Youn if (chan->ep_is_in) 734b02038faSJohn Youn hcintmsk |= HCINTMSK_BBLERR; 735b02038faSJohn Youn if (chan->error_state) 736b02038faSJohn Youn hcintmsk |= HCINTMSK_ACK; 737b02038faSJohn Youn if (chan->do_split) { 738b02038faSJohn Youn if (chan->complete_split) 739b02038faSJohn Youn hcintmsk |= HCINTMSK_NYET; 740b02038faSJohn Youn else 741b02038faSJohn Youn hcintmsk |= HCINTMSK_ACK; 742b02038faSJohn Youn } 743b02038faSJohn Youn break; 744b02038faSJohn Youn 745b02038faSJohn Youn case USB_ENDPOINT_XFER_ISOC: 746b02038faSJohn Youn if (dbg_perio()) 747b02038faSJohn Youn dev_vdbg(hsotg->dev, "isoc\n"); 748b02038faSJohn Youn hcintmsk |= HCINTMSK_XFERCOMPL; 749b02038faSJohn Youn hcintmsk |= HCINTMSK_FRMOVRUN; 750b02038faSJohn Youn hcintmsk |= HCINTMSK_ACK; 751b02038faSJohn Youn 752b02038faSJohn Youn if (chan->ep_is_in) { 753b02038faSJohn Youn hcintmsk |= HCINTMSK_XACTERR; 754b02038faSJohn Youn hcintmsk |= HCINTMSK_BBLERR; 755b02038faSJohn Youn } 756b02038faSJohn Youn break; 757b02038faSJohn Youn default: 758b02038faSJohn Youn dev_err(hsotg->dev, "## Unknown EP type ##\n"); 759b02038faSJohn Youn break; 760b02038faSJohn Youn } 761b02038faSJohn Youn 762b02038faSJohn Youn dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); 763b02038faSJohn Youn if (dbg_hc(chan)) 764b02038faSJohn Youn dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); 765b02038faSJohn Youn } 766b02038faSJohn Youn 767b02038faSJohn Youn static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg, 768b02038faSJohn Youn struct dwc2_host_chan *chan) 769b02038faSJohn Youn { 770b02038faSJohn Youn u32 hcintmsk = HCINTMSK_CHHLTD; 771b02038faSJohn Youn 772b02038faSJohn Youn /* 773b02038faSJohn Youn * For Descriptor DMA mode core halts the channel on AHB error. 774b02038faSJohn Youn * Interrupt is not required. 775b02038faSJohn Youn */ 77695832c00SJohn Youn if (!hsotg->params.dma_desc_enable) { 777b02038faSJohn Youn if (dbg_hc(chan)) 778b02038faSJohn Youn dev_vdbg(hsotg->dev, "desc DMA disabled\n"); 779b02038faSJohn Youn hcintmsk |= HCINTMSK_AHBERR; 780b02038faSJohn Youn } else { 781b02038faSJohn Youn if (dbg_hc(chan)) 782b02038faSJohn Youn dev_vdbg(hsotg->dev, "desc DMA enabled\n"); 783b02038faSJohn Youn if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 784b02038faSJohn Youn hcintmsk |= HCINTMSK_XFERCOMPL; 785b02038faSJohn Youn } 786b02038faSJohn Youn 787b02038faSJohn Youn if (chan->error_state && !chan->do_split && 788b02038faSJohn Youn chan->ep_type != USB_ENDPOINT_XFER_ISOC) { 789b02038faSJohn Youn if (dbg_hc(chan)) 790b02038faSJohn Youn dev_vdbg(hsotg->dev, "setting ACK\n"); 791b02038faSJohn Youn hcintmsk |= HCINTMSK_ACK; 792b02038faSJohn Youn if (chan->ep_is_in) { 793b02038faSJohn Youn hcintmsk |= HCINTMSK_DATATGLERR; 794b02038faSJohn Youn if (chan->ep_type != USB_ENDPOINT_XFER_INT) 795b02038faSJohn Youn hcintmsk |= HCINTMSK_NAK; 796b02038faSJohn Youn } 797b02038faSJohn Youn } 798b02038faSJohn Youn 799b02038faSJohn Youn dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); 800b02038faSJohn Youn if (dbg_hc(chan)) 801b02038faSJohn Youn dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); 802b02038faSJohn Youn } 803b02038faSJohn Youn 804b02038faSJohn Youn static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg, 805b02038faSJohn Youn struct dwc2_host_chan *chan) 806b02038faSJohn Youn { 807b02038faSJohn Youn u32 intmsk; 808b02038faSJohn Youn 80995832c00SJohn Youn if (hsotg->params.host_dma) { 810b02038faSJohn Youn if (dbg_hc(chan)) 811b02038faSJohn Youn dev_vdbg(hsotg->dev, "DMA enabled\n"); 812b02038faSJohn Youn dwc2_hc_enable_dma_ints(hsotg, chan); 813b02038faSJohn Youn } else { 814b02038faSJohn Youn if (dbg_hc(chan)) 815b02038faSJohn Youn dev_vdbg(hsotg->dev, "DMA disabled\n"); 816b02038faSJohn Youn dwc2_hc_enable_slave_ints(hsotg, chan); 817b02038faSJohn Youn } 818b02038faSJohn Youn 819b02038faSJohn Youn /* Enable the top level host channel interrupt */ 820b02038faSJohn Youn intmsk = dwc2_readl(hsotg->regs + HAINTMSK); 821b02038faSJohn Youn intmsk |= 1 << chan->hc_num; 822b02038faSJohn Youn dwc2_writel(intmsk, hsotg->regs + HAINTMSK); 823b02038faSJohn Youn if (dbg_hc(chan)) 824b02038faSJohn Youn dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk); 825b02038faSJohn Youn 826b02038faSJohn Youn /* Make sure host channel interrupts are enabled */ 827b02038faSJohn Youn intmsk = dwc2_readl(hsotg->regs + GINTMSK); 828b02038faSJohn Youn intmsk |= GINTSTS_HCHINT; 829b02038faSJohn Youn dwc2_writel(intmsk, hsotg->regs + GINTMSK); 830b02038faSJohn Youn if (dbg_hc(chan)) 831b02038faSJohn Youn dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk); 832b02038faSJohn Youn } 833b02038faSJohn Youn 834b02038faSJohn Youn /** 835b02038faSJohn Youn * dwc2_hc_init() - Prepares a host channel for transferring packets to/from 836b02038faSJohn Youn * a specific endpoint 837b02038faSJohn Youn * 838b02038faSJohn Youn * @hsotg: Programming view of DWC_otg controller 839b02038faSJohn Youn * @chan: Information needed to initialize the host channel 840b02038faSJohn Youn * 841b02038faSJohn Youn * The HCCHARn register is set up with the characteristics specified in chan. 842b02038faSJohn Youn * Host channel interrupts that may need to be serviced while this transfer is 843b02038faSJohn Youn * in progress are enabled. 844b02038faSJohn Youn */ 845b02038faSJohn Youn static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) 846b02038faSJohn Youn { 847b02038faSJohn Youn u8 hc_num = chan->hc_num; 848b02038faSJohn Youn u32 hcintmsk; 849b02038faSJohn Youn u32 hcchar; 850b02038faSJohn Youn u32 hcsplt = 0; 851b02038faSJohn Youn 852b02038faSJohn Youn if (dbg_hc(chan)) 853b02038faSJohn Youn dev_vdbg(hsotg->dev, "%s()\n", __func__); 854b02038faSJohn Youn 855b02038faSJohn Youn /* Clear old interrupt conditions for this host channel */ 856b02038faSJohn Youn hcintmsk = 0xffffffff; 857b02038faSJohn Youn hcintmsk &= ~HCINTMSK_RESERVED14_31; 858b02038faSJohn Youn dwc2_writel(hcintmsk, hsotg->regs + HCINT(hc_num)); 859b02038faSJohn Youn 860b02038faSJohn Youn /* Enable channel interrupts required for this transfer */ 861b02038faSJohn Youn dwc2_hc_enable_ints(hsotg, chan); 862b02038faSJohn Youn 863b02038faSJohn Youn /* 864b02038faSJohn Youn * Program the HCCHARn register with the endpoint characteristics for 865b02038faSJohn Youn * the current transfer 866b02038faSJohn Youn */ 867b02038faSJohn Youn hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK; 868b02038faSJohn Youn hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK; 869b02038faSJohn Youn if (chan->ep_is_in) 870b02038faSJohn Youn hcchar |= HCCHAR_EPDIR; 871b02038faSJohn Youn if (chan->speed == USB_SPEED_LOW) 872b02038faSJohn Youn hcchar |= HCCHAR_LSPDDEV; 873b02038faSJohn Youn hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK; 874b02038faSJohn Youn hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK; 875b02038faSJohn Youn dwc2_writel(hcchar, hsotg->regs + HCCHAR(hc_num)); 876b02038faSJohn Youn if (dbg_hc(chan)) { 877b02038faSJohn Youn dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n", 878b02038faSJohn Youn hc_num, hcchar); 879b02038faSJohn Youn 880b02038faSJohn Youn dev_vdbg(hsotg->dev, "%s: Channel %d\n", 881b02038faSJohn Youn __func__, hc_num); 882b02038faSJohn Youn dev_vdbg(hsotg->dev, " Dev Addr: %d\n", 883b02038faSJohn Youn chan->dev_addr); 884b02038faSJohn Youn dev_vdbg(hsotg->dev, " Ep Num: %d\n", 885b02038faSJohn Youn chan->ep_num); 886b02038faSJohn Youn dev_vdbg(hsotg->dev, " Is In: %d\n", 887b02038faSJohn Youn chan->ep_is_in); 888b02038faSJohn Youn dev_vdbg(hsotg->dev, " Is Low Speed: %d\n", 889b02038faSJohn Youn chan->speed == USB_SPEED_LOW); 890b02038faSJohn Youn dev_vdbg(hsotg->dev, " Ep Type: %d\n", 891b02038faSJohn Youn chan->ep_type); 892b02038faSJohn Youn dev_vdbg(hsotg->dev, " Max Pkt: %d\n", 893b02038faSJohn Youn chan->max_packet); 894b02038faSJohn Youn } 895b02038faSJohn Youn 896b02038faSJohn Youn /* Program the HCSPLT register for SPLITs */ 897b02038faSJohn Youn if (chan->do_split) { 898b02038faSJohn Youn if (dbg_hc(chan)) 899b02038faSJohn Youn dev_vdbg(hsotg->dev, 900b02038faSJohn Youn "Programming HC %d with split --> %s\n", 901b02038faSJohn Youn hc_num, 902b02038faSJohn Youn chan->complete_split ? "CSPLIT" : "SSPLIT"); 903b02038faSJohn Youn if (chan->complete_split) 904b02038faSJohn Youn hcsplt |= HCSPLT_COMPSPLT; 905b02038faSJohn Youn hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT & 906b02038faSJohn Youn HCSPLT_XACTPOS_MASK; 907b02038faSJohn Youn hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT & 908b02038faSJohn Youn HCSPLT_HUBADDR_MASK; 909b02038faSJohn Youn hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT & 910b02038faSJohn Youn HCSPLT_PRTADDR_MASK; 911b02038faSJohn Youn if (dbg_hc(chan)) { 912b02038faSJohn Youn dev_vdbg(hsotg->dev, " comp split %d\n", 913b02038faSJohn Youn chan->complete_split); 914b02038faSJohn Youn dev_vdbg(hsotg->dev, " xact pos %d\n", 915b02038faSJohn Youn chan->xact_pos); 916b02038faSJohn Youn dev_vdbg(hsotg->dev, " hub addr %d\n", 917b02038faSJohn Youn chan->hub_addr); 918b02038faSJohn Youn dev_vdbg(hsotg->dev, " hub port %d\n", 919b02038faSJohn Youn chan->hub_port); 920b02038faSJohn Youn dev_vdbg(hsotg->dev, " is_in %d\n", 921b02038faSJohn Youn chan->ep_is_in); 922b02038faSJohn Youn dev_vdbg(hsotg->dev, " Max Pkt %d\n", 923b02038faSJohn Youn chan->max_packet); 924b02038faSJohn Youn dev_vdbg(hsotg->dev, " xferlen %d\n", 925b02038faSJohn Youn chan->xfer_len); 926b02038faSJohn Youn } 927b02038faSJohn Youn } 928b02038faSJohn Youn 929b02038faSJohn Youn dwc2_writel(hcsplt, hsotg->regs + HCSPLT(hc_num)); 930b02038faSJohn Youn } 931b02038faSJohn Youn 932b02038faSJohn Youn /** 933b02038faSJohn Youn * dwc2_hc_halt() - Attempts to halt a host channel 934b02038faSJohn Youn * 935b02038faSJohn Youn * @hsotg: Controller register interface 936b02038faSJohn Youn * @chan: Host channel to halt 937b02038faSJohn Youn * @halt_status: Reason for halting the channel 938b02038faSJohn Youn * 939b02038faSJohn Youn * This function should only be called in Slave mode or to abort a transfer in 940b02038faSJohn Youn * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the 941b02038faSJohn Youn * controller halts the channel when the transfer is complete or a condition 942b02038faSJohn Youn * occurs that requires application intervention. 943b02038faSJohn Youn * 944b02038faSJohn Youn * In slave mode, checks for a free request queue entry, then sets the Channel 945b02038faSJohn Youn * Enable and Channel Disable bits of the Host Channel Characteristics 946b02038faSJohn Youn * register of the specified channel to intiate the halt. If there is no free 947b02038faSJohn Youn * request queue entry, sets only the Channel Disable bit of the HCCHARn 948b02038faSJohn Youn * register to flush requests for this channel. In the latter case, sets a 949b02038faSJohn Youn * flag to indicate that the host channel needs to be halted when a request 950b02038faSJohn Youn * queue slot is open. 951b02038faSJohn Youn * 952b02038faSJohn Youn * In DMA mode, always sets the Channel Enable and Channel Disable bits of the 953b02038faSJohn Youn * HCCHARn register. The controller ensures there is space in the request 954b02038faSJohn Youn * queue before submitting the halt request. 955b02038faSJohn Youn * 956b02038faSJohn Youn * Some time may elapse before the core flushes any posted requests for this 957b02038faSJohn Youn * host channel and halts. The Channel Halted interrupt handler completes the 958b02038faSJohn Youn * deactivation of the host channel. 959b02038faSJohn Youn */ 960b02038faSJohn Youn void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 961b02038faSJohn Youn enum dwc2_halt_status halt_status) 962b02038faSJohn Youn { 963b02038faSJohn Youn u32 nptxsts, hptxsts, hcchar; 964b02038faSJohn Youn 965b02038faSJohn Youn if (dbg_hc(chan)) 966b02038faSJohn Youn dev_vdbg(hsotg->dev, "%s()\n", __func__); 967b02038faSJohn Youn if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS) 968b02038faSJohn Youn dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status); 969b02038faSJohn Youn 970b02038faSJohn Youn if (halt_status == DWC2_HC_XFER_URB_DEQUEUE || 971b02038faSJohn Youn halt_status == DWC2_HC_XFER_AHB_ERR) { 972b02038faSJohn Youn /* 973b02038faSJohn Youn * Disable all channel interrupts except Ch Halted. The QTD 974b02038faSJohn Youn * and QH state associated with this transfer has been cleared 975b02038faSJohn Youn * (in the case of URB_DEQUEUE), so the channel needs to be 976b02038faSJohn Youn * shut down carefully to prevent crashes. 977b02038faSJohn Youn */ 978b02038faSJohn Youn u32 hcintmsk = HCINTMSK_CHHLTD; 979b02038faSJohn Youn 980b02038faSJohn Youn dev_vdbg(hsotg->dev, "dequeue/error\n"); 981b02038faSJohn Youn dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); 982b02038faSJohn Youn 983b02038faSJohn Youn /* 984b02038faSJohn Youn * Make sure no other interrupts besides halt are currently 985b02038faSJohn Youn * pending. Handling another interrupt could cause a crash due 986b02038faSJohn Youn * to the QTD and QH state. 987b02038faSJohn Youn */ 988b02038faSJohn Youn dwc2_writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num)); 989b02038faSJohn Youn 990b02038faSJohn Youn /* 991b02038faSJohn Youn * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR 992b02038faSJohn Youn * even if the channel was already halted for some other 993b02038faSJohn Youn * reason 994b02038faSJohn Youn */ 995b02038faSJohn Youn chan->halt_status = halt_status; 996b02038faSJohn Youn 997b02038faSJohn Youn hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 998b02038faSJohn Youn if (!(hcchar & HCCHAR_CHENA)) { 999b02038faSJohn Youn /* 1000b02038faSJohn Youn * The channel is either already halted or it hasn't 1001b02038faSJohn Youn * started yet. In DMA mode, the transfer may halt if 1002b02038faSJohn Youn * it finishes normally or a condition occurs that 1003b02038faSJohn Youn * requires driver intervention. Don't want to halt 1004b02038faSJohn Youn * the channel again. In either Slave or DMA mode, 1005b02038faSJohn Youn * it's possible that the transfer has been assigned 1006b02038faSJohn Youn * to a channel, but not started yet when an URB is 1007b02038faSJohn Youn * dequeued. Don't want to halt a channel that hasn't 1008b02038faSJohn Youn * started yet. 1009b02038faSJohn Youn */ 1010b02038faSJohn Youn return; 1011b02038faSJohn Youn } 1012b02038faSJohn Youn } 1013b02038faSJohn Youn if (chan->halt_pending) { 1014b02038faSJohn Youn /* 1015b02038faSJohn Youn * A halt has already been issued for this channel. This might 1016b02038faSJohn Youn * happen when a transfer is aborted by a higher level in 1017b02038faSJohn Youn * the stack. 1018b02038faSJohn Youn */ 1019b02038faSJohn Youn dev_vdbg(hsotg->dev, 1020b02038faSJohn Youn "*** %s: Channel %d, chan->halt_pending already set ***\n", 1021b02038faSJohn Youn __func__, chan->hc_num); 1022b02038faSJohn Youn return; 1023b02038faSJohn Youn } 1024b02038faSJohn Youn 1025b02038faSJohn Youn hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1026b02038faSJohn Youn 1027b02038faSJohn Youn /* No need to set the bit in DDMA for disabling the channel */ 1028b02038faSJohn Youn /* TODO check it everywhere channel is disabled */ 102995832c00SJohn Youn if (!hsotg->params.dma_desc_enable) { 1030b02038faSJohn Youn if (dbg_hc(chan)) 1031b02038faSJohn Youn dev_vdbg(hsotg->dev, "desc DMA disabled\n"); 1032b02038faSJohn Youn hcchar |= HCCHAR_CHENA; 1033b02038faSJohn Youn } else { 1034b02038faSJohn Youn if (dbg_hc(chan)) 1035b02038faSJohn Youn dev_dbg(hsotg->dev, "desc DMA enabled\n"); 1036b02038faSJohn Youn } 1037b02038faSJohn Youn hcchar |= HCCHAR_CHDIS; 1038b02038faSJohn Youn 103995832c00SJohn Youn if (!hsotg->params.host_dma) { 1040b02038faSJohn Youn if (dbg_hc(chan)) 1041b02038faSJohn Youn dev_vdbg(hsotg->dev, "DMA not enabled\n"); 1042b02038faSJohn Youn hcchar |= HCCHAR_CHENA; 1043b02038faSJohn Youn 1044b02038faSJohn Youn /* Check for space in the request queue to issue the halt */ 1045b02038faSJohn Youn if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL || 1046b02038faSJohn Youn chan->ep_type == USB_ENDPOINT_XFER_BULK) { 1047b02038faSJohn Youn dev_vdbg(hsotg->dev, "control/bulk\n"); 1048b02038faSJohn Youn nptxsts = dwc2_readl(hsotg->regs + GNPTXSTS); 1049b02038faSJohn Youn if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) { 1050b02038faSJohn Youn dev_vdbg(hsotg->dev, "Disabling channel\n"); 1051b02038faSJohn Youn hcchar &= ~HCCHAR_CHENA; 1052b02038faSJohn Youn } 1053b02038faSJohn Youn } else { 1054b02038faSJohn Youn if (dbg_perio()) 1055b02038faSJohn Youn dev_vdbg(hsotg->dev, "isoc/intr\n"); 1056b02038faSJohn Youn hptxsts = dwc2_readl(hsotg->regs + HPTXSTS); 1057b02038faSJohn Youn if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 || 1058b02038faSJohn Youn hsotg->queuing_high_bandwidth) { 1059b02038faSJohn Youn if (dbg_perio()) 1060b02038faSJohn Youn dev_vdbg(hsotg->dev, "Disabling channel\n"); 1061b02038faSJohn Youn hcchar &= ~HCCHAR_CHENA; 1062b02038faSJohn Youn } 1063b02038faSJohn Youn } 1064b02038faSJohn Youn } else { 1065b02038faSJohn Youn if (dbg_hc(chan)) 1066b02038faSJohn Youn dev_vdbg(hsotg->dev, "DMA enabled\n"); 1067b02038faSJohn Youn } 1068b02038faSJohn Youn 1069b02038faSJohn Youn dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1070b02038faSJohn Youn chan->halt_status = halt_status; 1071b02038faSJohn Youn 1072b02038faSJohn Youn if (hcchar & HCCHAR_CHENA) { 1073b02038faSJohn Youn if (dbg_hc(chan)) 1074b02038faSJohn Youn dev_vdbg(hsotg->dev, "Channel enabled\n"); 1075b02038faSJohn Youn chan->halt_pending = 1; 1076b02038faSJohn Youn chan->halt_on_queue = 0; 1077b02038faSJohn Youn } else { 1078b02038faSJohn Youn if (dbg_hc(chan)) 1079b02038faSJohn Youn dev_vdbg(hsotg->dev, "Channel disabled\n"); 1080b02038faSJohn Youn chan->halt_on_queue = 1; 1081b02038faSJohn Youn } 1082b02038faSJohn Youn 1083b02038faSJohn Youn if (dbg_hc(chan)) { 1084b02038faSJohn Youn dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1085b02038faSJohn Youn chan->hc_num); 1086b02038faSJohn Youn dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n", 1087b02038faSJohn Youn hcchar); 1088b02038faSJohn Youn dev_vdbg(hsotg->dev, " halt_pending: %d\n", 1089b02038faSJohn Youn chan->halt_pending); 1090b02038faSJohn Youn dev_vdbg(hsotg->dev, " halt_on_queue: %d\n", 1091b02038faSJohn Youn chan->halt_on_queue); 1092b02038faSJohn Youn dev_vdbg(hsotg->dev, " halt_status: %d\n", 1093b02038faSJohn Youn chan->halt_status); 1094b02038faSJohn Youn } 1095b02038faSJohn Youn } 1096b02038faSJohn Youn 1097b02038faSJohn Youn /** 1098b02038faSJohn Youn * dwc2_hc_cleanup() - Clears the transfer state for a host channel 1099b02038faSJohn Youn * 1100b02038faSJohn Youn * @hsotg: Programming view of DWC_otg controller 1101b02038faSJohn Youn * @chan: Identifies the host channel to clean up 1102b02038faSJohn Youn * 1103b02038faSJohn Youn * This function is normally called after a transfer is done and the host 1104b02038faSJohn Youn * channel is being released 1105b02038faSJohn Youn */ 1106b02038faSJohn Youn void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) 1107b02038faSJohn Youn { 1108b02038faSJohn Youn u32 hcintmsk; 1109b02038faSJohn Youn 1110b02038faSJohn Youn chan->xfer_started = 0; 1111b02038faSJohn Youn 1112b02038faSJohn Youn list_del_init(&chan->split_order_list_entry); 1113b02038faSJohn Youn 1114b02038faSJohn Youn /* 1115b02038faSJohn Youn * Clear channel interrupt enables and any unhandled channel interrupt 1116b02038faSJohn Youn * conditions 1117b02038faSJohn Youn */ 1118b02038faSJohn Youn dwc2_writel(0, hsotg->regs + HCINTMSK(chan->hc_num)); 1119b02038faSJohn Youn hcintmsk = 0xffffffff; 1120b02038faSJohn Youn hcintmsk &= ~HCINTMSK_RESERVED14_31; 1121b02038faSJohn Youn dwc2_writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num)); 1122b02038faSJohn Youn } 1123b02038faSJohn Youn 1124b02038faSJohn Youn /** 1125b02038faSJohn Youn * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in 1126b02038faSJohn Youn * which frame a periodic transfer should occur 1127b02038faSJohn Youn * 1128b02038faSJohn Youn * @hsotg: Programming view of DWC_otg controller 1129b02038faSJohn Youn * @chan: Identifies the host channel to set up and its properties 1130b02038faSJohn Youn * @hcchar: Current value of the HCCHAR register for the specified host channel 1131b02038faSJohn Youn * 1132b02038faSJohn Youn * This function has no effect on non-periodic transfers 1133b02038faSJohn Youn */ 1134b02038faSJohn Youn static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg, 1135b02038faSJohn Youn struct dwc2_host_chan *chan, u32 *hcchar) 1136b02038faSJohn Youn { 1137b02038faSJohn Youn if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1138b02038faSJohn Youn chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1139b02038faSJohn Youn int host_speed; 1140b02038faSJohn Youn int xfer_ns; 1141b02038faSJohn Youn int xfer_us; 1142b02038faSJohn Youn int bytes_in_fifo; 1143b02038faSJohn Youn u16 fifo_space; 1144b02038faSJohn Youn u16 frame_number; 1145b02038faSJohn Youn u16 wire_frame; 1146b02038faSJohn Youn 1147b02038faSJohn Youn /* 1148b02038faSJohn Youn * Try to figure out if we're an even or odd frame. If we set 1149b02038faSJohn Youn * even and the current frame number is even the the transfer 1150b02038faSJohn Youn * will happen immediately. Similar if both are odd. If one is 1151b02038faSJohn Youn * even and the other is odd then the transfer will happen when 1152b02038faSJohn Youn * the frame number ticks. 1153b02038faSJohn Youn * 1154b02038faSJohn Youn * There's a bit of a balancing act to get this right. 1155b02038faSJohn Youn * Sometimes we may want to send data in the current frame (AK 1156b02038faSJohn Youn * right away). We might want to do this if the frame number 1157b02038faSJohn Youn * _just_ ticked, but we might also want to do this in order 1158b02038faSJohn Youn * to continue a split transaction that happened late in a 1159b02038faSJohn Youn * microframe (so we didn't know to queue the next transfer 1160b02038faSJohn Youn * until the frame number had ticked). The problem is that we 1161b02038faSJohn Youn * need a lot of knowledge to know if there's actually still 1162b02038faSJohn Youn * time to send things or if it would be better to wait until 1163b02038faSJohn Youn * the next frame. 1164b02038faSJohn Youn * 1165b02038faSJohn Youn * We can look at how much time is left in the current frame 1166b02038faSJohn Youn * and make a guess about whether we'll have time to transfer. 1167b02038faSJohn Youn * We'll do that. 1168b02038faSJohn Youn */ 1169b02038faSJohn Youn 1170b02038faSJohn Youn /* Get speed host is running at */ 1171b02038faSJohn Youn host_speed = (chan->speed != USB_SPEED_HIGH && 1172b02038faSJohn Youn !chan->do_split) ? chan->speed : USB_SPEED_HIGH; 1173b02038faSJohn Youn 1174b02038faSJohn Youn /* See how many bytes are in the periodic FIFO right now */ 1175b02038faSJohn Youn fifo_space = (dwc2_readl(hsotg->regs + HPTXSTS) & 1176b02038faSJohn Youn TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT; 1177b02038faSJohn Youn bytes_in_fifo = sizeof(u32) * 1178bea8e86cSJohn Youn (hsotg->params.host_perio_tx_fifo_size - 1179b02038faSJohn Youn fifo_space); 1180b02038faSJohn Youn 1181b02038faSJohn Youn /* 1182b02038faSJohn Youn * Roughly estimate bus time for everything in the periodic 1183b02038faSJohn Youn * queue + our new transfer. This is "rough" because we're 1184b02038faSJohn Youn * using a function that makes takes into account IN/OUT 1185b02038faSJohn Youn * and INT/ISO and we're just slamming in one value for all 1186b02038faSJohn Youn * transfers. This should be an over-estimate and that should 1187b02038faSJohn Youn * be OK, but we can probably tighten it. 1188b02038faSJohn Youn */ 1189b02038faSJohn Youn xfer_ns = usb_calc_bus_time(host_speed, false, false, 1190b02038faSJohn Youn chan->xfer_len + bytes_in_fifo); 1191b02038faSJohn Youn xfer_us = NS_TO_US(xfer_ns); 1192b02038faSJohn Youn 1193b02038faSJohn Youn /* See what frame number we'll be at by the time we finish */ 1194b02038faSJohn Youn frame_number = dwc2_hcd_get_future_frame_number(hsotg, xfer_us); 1195b02038faSJohn Youn 1196b02038faSJohn Youn /* This is when we were scheduled to be on the wire */ 1197b02038faSJohn Youn wire_frame = dwc2_frame_num_inc(chan->qh->next_active_frame, 1); 1198b02038faSJohn Youn 1199b02038faSJohn Youn /* 1200b02038faSJohn Youn * If we'd finish _after_ the frame we're scheduled in then 1201b02038faSJohn Youn * it's hopeless. Just schedule right away and hope for the 1202b02038faSJohn Youn * best. Note that it _might_ be wise to call back into the 1203b02038faSJohn Youn * scheduler to pick a better frame, but this is better than 1204b02038faSJohn Youn * nothing. 1205b02038faSJohn Youn */ 1206b02038faSJohn Youn if (dwc2_frame_num_gt(frame_number, wire_frame)) { 1207b02038faSJohn Youn dwc2_sch_vdbg(hsotg, 1208b02038faSJohn Youn "QH=%p EO MISS fr=%04x=>%04x (%+d)\n", 1209b02038faSJohn Youn chan->qh, wire_frame, frame_number, 1210b02038faSJohn Youn dwc2_frame_num_dec(frame_number, 1211b02038faSJohn Youn wire_frame)); 1212b02038faSJohn Youn wire_frame = frame_number; 1213b02038faSJohn Youn 1214b02038faSJohn Youn /* 1215b02038faSJohn Youn * We picked a different frame number; communicate this 1216b02038faSJohn Youn * back to the scheduler so it doesn't try to schedule 1217b02038faSJohn Youn * another in the same frame. 1218b02038faSJohn Youn * 1219b02038faSJohn Youn * Remember that next_active_frame is 1 before the wire 1220b02038faSJohn Youn * frame. 1221b02038faSJohn Youn */ 1222b02038faSJohn Youn chan->qh->next_active_frame = 1223b02038faSJohn Youn dwc2_frame_num_dec(frame_number, 1); 1224b02038faSJohn Youn } 1225b02038faSJohn Youn 1226b02038faSJohn Youn if (wire_frame & 1) 1227b02038faSJohn Youn *hcchar |= HCCHAR_ODDFRM; 1228b02038faSJohn Youn else 1229b02038faSJohn Youn *hcchar &= ~HCCHAR_ODDFRM; 1230b02038faSJohn Youn } 1231b02038faSJohn Youn } 1232b02038faSJohn Youn 1233b02038faSJohn Youn static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan) 1234b02038faSJohn Youn { 1235b02038faSJohn Youn /* Set up the initial PID for the transfer */ 1236b02038faSJohn Youn if (chan->speed == USB_SPEED_HIGH) { 1237b02038faSJohn Youn if (chan->ep_is_in) { 1238b02038faSJohn Youn if (chan->multi_count == 1) 1239b02038faSJohn Youn chan->data_pid_start = DWC2_HC_PID_DATA0; 1240b02038faSJohn Youn else if (chan->multi_count == 2) 1241b02038faSJohn Youn chan->data_pid_start = DWC2_HC_PID_DATA1; 1242b02038faSJohn Youn else 1243b02038faSJohn Youn chan->data_pid_start = DWC2_HC_PID_DATA2; 1244b02038faSJohn Youn } else { 1245b02038faSJohn Youn if (chan->multi_count == 1) 1246b02038faSJohn Youn chan->data_pid_start = DWC2_HC_PID_DATA0; 1247b02038faSJohn Youn else 1248b02038faSJohn Youn chan->data_pid_start = DWC2_HC_PID_MDATA; 1249b02038faSJohn Youn } 1250b02038faSJohn Youn } else { 1251b02038faSJohn Youn chan->data_pid_start = DWC2_HC_PID_DATA0; 1252b02038faSJohn Youn } 1253b02038faSJohn Youn } 1254b02038faSJohn Youn 1255b02038faSJohn Youn /** 1256b02038faSJohn Youn * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with 1257b02038faSJohn Youn * the Host Channel 1258b02038faSJohn Youn * 1259b02038faSJohn Youn * @hsotg: Programming view of DWC_otg controller 1260b02038faSJohn Youn * @chan: Information needed to initialize the host channel 1261b02038faSJohn Youn * 1262b02038faSJohn Youn * This function should only be called in Slave mode. For a channel associated 1263b02038faSJohn Youn * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel 1264b02038faSJohn Youn * associated with a periodic EP, the periodic Tx FIFO is written. 1265b02038faSJohn Youn * 1266b02038faSJohn Youn * Upon return the xfer_buf and xfer_count fields in chan are incremented by 1267b02038faSJohn Youn * the number of bytes written to the Tx FIFO. 1268b02038faSJohn Youn */ 1269b02038faSJohn Youn static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg, 1270b02038faSJohn Youn struct dwc2_host_chan *chan) 1271b02038faSJohn Youn { 1272b02038faSJohn Youn u32 i; 1273b02038faSJohn Youn u32 remaining_count; 1274b02038faSJohn Youn u32 byte_count; 1275b02038faSJohn Youn u32 dword_count; 1276b02038faSJohn Youn u32 __iomem *data_fifo; 1277b02038faSJohn Youn u32 *data_buf = (u32 *)chan->xfer_buf; 1278b02038faSJohn Youn 1279b02038faSJohn Youn if (dbg_hc(chan)) 1280b02038faSJohn Youn dev_vdbg(hsotg->dev, "%s()\n", __func__); 1281b02038faSJohn Youn 1282b02038faSJohn Youn data_fifo = (u32 __iomem *)(hsotg->regs + HCFIFO(chan->hc_num)); 1283b02038faSJohn Youn 1284b02038faSJohn Youn remaining_count = chan->xfer_len - chan->xfer_count; 1285b02038faSJohn Youn if (remaining_count > chan->max_packet) 1286b02038faSJohn Youn byte_count = chan->max_packet; 1287b02038faSJohn Youn else 1288b02038faSJohn Youn byte_count = remaining_count; 1289b02038faSJohn Youn 1290b02038faSJohn Youn dword_count = (byte_count + 3) / 4; 1291b02038faSJohn Youn 1292b02038faSJohn Youn if (((unsigned long)data_buf & 0x3) == 0) { 1293b02038faSJohn Youn /* xfer_buf is DWORD aligned */ 1294b02038faSJohn Youn for (i = 0; i < dword_count; i++, data_buf++) 1295b02038faSJohn Youn dwc2_writel(*data_buf, data_fifo); 1296b02038faSJohn Youn } else { 1297b02038faSJohn Youn /* xfer_buf is not DWORD aligned */ 1298b02038faSJohn Youn for (i = 0; i < dword_count; i++, data_buf++) { 1299b02038faSJohn Youn u32 data = data_buf[0] | data_buf[1] << 8 | 1300b02038faSJohn Youn data_buf[2] << 16 | data_buf[3] << 24; 1301b02038faSJohn Youn dwc2_writel(data, data_fifo); 1302b02038faSJohn Youn } 1303b02038faSJohn Youn } 1304b02038faSJohn Youn 1305b02038faSJohn Youn chan->xfer_count += byte_count; 1306b02038faSJohn Youn chan->xfer_buf += byte_count; 1307b02038faSJohn Youn } 1308b02038faSJohn Youn 1309b02038faSJohn Youn /** 1310b02038faSJohn Youn * dwc2_hc_do_ping() - Starts a PING transfer 1311b02038faSJohn Youn * 1312b02038faSJohn Youn * @hsotg: Programming view of DWC_otg controller 1313b02038faSJohn Youn * @chan: Information needed to initialize the host channel 1314b02038faSJohn Youn * 1315b02038faSJohn Youn * This function should only be called in Slave mode. The Do Ping bit is set in 1316b02038faSJohn Youn * the HCTSIZ register, then the channel is enabled. 1317b02038faSJohn Youn */ 1318b02038faSJohn Youn static void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, 1319b02038faSJohn Youn struct dwc2_host_chan *chan) 1320b02038faSJohn Youn { 1321b02038faSJohn Youn u32 hcchar; 1322b02038faSJohn Youn u32 hctsiz; 1323b02038faSJohn Youn 1324b02038faSJohn Youn if (dbg_hc(chan)) 1325b02038faSJohn Youn dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1326b02038faSJohn Youn chan->hc_num); 1327b02038faSJohn Youn 1328b02038faSJohn Youn hctsiz = TSIZ_DOPNG; 1329b02038faSJohn Youn hctsiz |= 1 << TSIZ_PKTCNT_SHIFT; 1330b02038faSJohn Youn dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); 1331b02038faSJohn Youn 1332b02038faSJohn Youn hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1333b02038faSJohn Youn hcchar |= HCCHAR_CHENA; 1334b02038faSJohn Youn hcchar &= ~HCCHAR_CHDIS; 1335b02038faSJohn Youn dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1336b02038faSJohn Youn } 1337b02038faSJohn Youn 1338b02038faSJohn Youn /** 1339b02038faSJohn Youn * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host 1340b02038faSJohn Youn * channel and starts the transfer 1341b02038faSJohn Youn * 1342b02038faSJohn Youn * @hsotg: Programming view of DWC_otg controller 1343b02038faSJohn Youn * @chan: Information needed to initialize the host channel. The xfer_len value 1344b02038faSJohn Youn * may be reduced to accommodate the max widths of the XferSize and 1345b02038faSJohn Youn * PktCnt fields in the HCTSIZn register. The multi_count value may be 1346b02038faSJohn Youn * changed to reflect the final xfer_len value. 1347b02038faSJohn Youn * 1348b02038faSJohn Youn * This function may be called in either Slave mode or DMA mode. In Slave mode, 1349b02038faSJohn Youn * the caller must ensure that there is sufficient space in the request queue 1350b02038faSJohn Youn * and Tx Data FIFO. 1351b02038faSJohn Youn * 1352b02038faSJohn Youn * For an OUT transfer in Slave mode, it loads a data packet into the 1353b02038faSJohn Youn * appropriate FIFO. If necessary, additional data packets are loaded in the 1354b02038faSJohn Youn * Host ISR. 1355b02038faSJohn Youn * 1356b02038faSJohn Youn * For an IN transfer in Slave mode, a data packet is requested. The data 1357b02038faSJohn Youn * packets are unloaded from the Rx FIFO in the Host ISR. If necessary, 1358b02038faSJohn Youn * additional data packets are requested in the Host ISR. 1359b02038faSJohn Youn * 1360b02038faSJohn Youn * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ 1361b02038faSJohn Youn * register along with a packet count of 1 and the channel is enabled. This 1362b02038faSJohn Youn * causes a single PING transaction to occur. Other fields in HCTSIZ are 1363b02038faSJohn Youn * simply set to 0 since no data transfer occurs in this case. 1364b02038faSJohn Youn * 1365b02038faSJohn Youn * For a PING transfer in DMA mode, the HCTSIZ register is initialized with 1366b02038faSJohn Youn * all the information required to perform the subsequent data transfer. In 1367b02038faSJohn Youn * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the 1368b02038faSJohn Youn * controller performs the entire PING protocol, then starts the data 1369b02038faSJohn Youn * transfer. 1370b02038faSJohn Youn */ 1371b02038faSJohn Youn static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 1372b02038faSJohn Youn struct dwc2_host_chan *chan) 1373b02038faSJohn Youn { 1374bea8e86cSJohn Youn u32 max_hc_xfer_size = hsotg->params.max_transfer_size; 1375bea8e86cSJohn Youn u16 max_hc_pkt_count = hsotg->params.max_packet_count; 1376b02038faSJohn Youn u32 hcchar; 1377b02038faSJohn Youn u32 hctsiz = 0; 1378b02038faSJohn Youn u16 num_packets; 1379b02038faSJohn Youn u32 ec_mc; 1380b02038faSJohn Youn 1381b02038faSJohn Youn if (dbg_hc(chan)) 1382b02038faSJohn Youn dev_vdbg(hsotg->dev, "%s()\n", __func__); 1383b02038faSJohn Youn 1384b02038faSJohn Youn if (chan->do_ping) { 138595832c00SJohn Youn if (!hsotg->params.host_dma) { 1386b02038faSJohn Youn if (dbg_hc(chan)) 1387b02038faSJohn Youn dev_vdbg(hsotg->dev, "ping, no DMA\n"); 1388b02038faSJohn Youn dwc2_hc_do_ping(hsotg, chan); 1389b02038faSJohn Youn chan->xfer_started = 1; 1390b02038faSJohn Youn return; 1391b02038faSJohn Youn } 1392b02038faSJohn Youn 1393b02038faSJohn Youn if (dbg_hc(chan)) 1394b02038faSJohn Youn dev_vdbg(hsotg->dev, "ping, DMA\n"); 1395b02038faSJohn Youn 1396b02038faSJohn Youn hctsiz |= TSIZ_DOPNG; 1397b02038faSJohn Youn } 1398b02038faSJohn Youn 1399b02038faSJohn Youn if (chan->do_split) { 1400b02038faSJohn Youn if (dbg_hc(chan)) 1401b02038faSJohn Youn dev_vdbg(hsotg->dev, "split\n"); 1402b02038faSJohn Youn num_packets = 1; 1403b02038faSJohn Youn 1404b02038faSJohn Youn if (chan->complete_split && !chan->ep_is_in) 1405b02038faSJohn Youn /* 1406b02038faSJohn Youn * For CSPLIT OUT Transfer, set the size to 0 so the 1407b02038faSJohn Youn * core doesn't expect any data written to the FIFO 1408b02038faSJohn Youn */ 1409b02038faSJohn Youn chan->xfer_len = 0; 1410b02038faSJohn Youn else if (chan->ep_is_in || chan->xfer_len > chan->max_packet) 1411b02038faSJohn Youn chan->xfer_len = chan->max_packet; 1412b02038faSJohn Youn else if (!chan->ep_is_in && chan->xfer_len > 188) 1413b02038faSJohn Youn chan->xfer_len = 188; 1414b02038faSJohn Youn 1415b02038faSJohn Youn hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT & 1416b02038faSJohn Youn TSIZ_XFERSIZE_MASK; 1417b02038faSJohn Youn 1418b02038faSJohn Youn /* For split set ec_mc for immediate retries */ 1419b02038faSJohn Youn if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1420b02038faSJohn Youn chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1421b02038faSJohn Youn ec_mc = 3; 1422b02038faSJohn Youn else 1423b02038faSJohn Youn ec_mc = 1; 1424b02038faSJohn Youn } else { 1425b02038faSJohn Youn if (dbg_hc(chan)) 1426b02038faSJohn Youn dev_vdbg(hsotg->dev, "no split\n"); 1427b02038faSJohn Youn /* 1428b02038faSJohn Youn * Ensure that the transfer length and packet count will fit 1429b02038faSJohn Youn * in the widths allocated for them in the HCTSIZn register 1430b02038faSJohn Youn */ 1431b02038faSJohn Youn if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1432b02038faSJohn Youn chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1433b02038faSJohn Youn /* 1434b02038faSJohn Youn * Make sure the transfer size is no larger than one 1435b02038faSJohn Youn * (micro)frame's worth of data. (A check was done 1436b02038faSJohn Youn * when the periodic transfer was accepted to ensure 1437b02038faSJohn Youn * that a (micro)frame's worth of data can be 1438b02038faSJohn Youn * programmed into a channel.) 1439b02038faSJohn Youn */ 1440b02038faSJohn Youn u32 max_periodic_len = 1441b02038faSJohn Youn chan->multi_count * chan->max_packet; 1442b02038faSJohn Youn 1443b02038faSJohn Youn if (chan->xfer_len > max_periodic_len) 1444b02038faSJohn Youn chan->xfer_len = max_periodic_len; 1445b02038faSJohn Youn } else if (chan->xfer_len > max_hc_xfer_size) { 1446b02038faSJohn Youn /* 1447b02038faSJohn Youn * Make sure that xfer_len is a multiple of max packet 1448b02038faSJohn Youn * size 1449b02038faSJohn Youn */ 1450b02038faSJohn Youn chan->xfer_len = 1451b02038faSJohn Youn max_hc_xfer_size - chan->max_packet + 1; 1452b02038faSJohn Youn } 1453b02038faSJohn Youn 1454b02038faSJohn Youn if (chan->xfer_len > 0) { 1455b02038faSJohn Youn num_packets = (chan->xfer_len + chan->max_packet - 1) / 1456b02038faSJohn Youn chan->max_packet; 1457b02038faSJohn Youn if (num_packets > max_hc_pkt_count) { 1458b02038faSJohn Youn num_packets = max_hc_pkt_count; 1459b02038faSJohn Youn chan->xfer_len = num_packets * chan->max_packet; 1460b02038faSJohn Youn } 1461b02038faSJohn Youn } else { 1462b02038faSJohn Youn /* Need 1 packet for transfer length of 0 */ 1463b02038faSJohn Youn num_packets = 1; 1464b02038faSJohn Youn } 1465b02038faSJohn Youn 1466b02038faSJohn Youn if (chan->ep_is_in) 1467b02038faSJohn Youn /* 1468b02038faSJohn Youn * Always program an integral # of max packets for IN 1469b02038faSJohn Youn * transfers 1470b02038faSJohn Youn */ 1471b02038faSJohn Youn chan->xfer_len = num_packets * chan->max_packet; 1472b02038faSJohn Youn 1473b02038faSJohn Youn if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1474b02038faSJohn Youn chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1475b02038faSJohn Youn /* 1476b02038faSJohn Youn * Make sure that the multi_count field matches the 1477b02038faSJohn Youn * actual transfer length 1478b02038faSJohn Youn */ 1479b02038faSJohn Youn chan->multi_count = num_packets; 1480b02038faSJohn Youn 1481b02038faSJohn Youn if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1482b02038faSJohn Youn dwc2_set_pid_isoc(chan); 1483b02038faSJohn Youn 1484b02038faSJohn Youn hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT & 1485b02038faSJohn Youn TSIZ_XFERSIZE_MASK; 1486b02038faSJohn Youn 1487b02038faSJohn Youn /* The ec_mc gets the multi_count for non-split */ 1488b02038faSJohn Youn ec_mc = chan->multi_count; 1489b02038faSJohn Youn } 1490b02038faSJohn Youn 1491b02038faSJohn Youn chan->start_pkt_count = num_packets; 1492b02038faSJohn Youn hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK; 1493b02038faSJohn Youn hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & 1494b02038faSJohn Youn TSIZ_SC_MC_PID_MASK; 1495b02038faSJohn Youn dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); 1496b02038faSJohn Youn if (dbg_hc(chan)) { 1497b02038faSJohn Youn dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n", 1498b02038faSJohn Youn hctsiz, chan->hc_num); 1499b02038faSJohn Youn 1500b02038faSJohn Youn dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1501b02038faSJohn Youn chan->hc_num); 1502b02038faSJohn Youn dev_vdbg(hsotg->dev, " Xfer Size: %d\n", 1503b02038faSJohn Youn (hctsiz & TSIZ_XFERSIZE_MASK) >> 1504b02038faSJohn Youn TSIZ_XFERSIZE_SHIFT); 1505b02038faSJohn Youn dev_vdbg(hsotg->dev, " Num Pkts: %d\n", 1506b02038faSJohn Youn (hctsiz & TSIZ_PKTCNT_MASK) >> 1507b02038faSJohn Youn TSIZ_PKTCNT_SHIFT); 1508b02038faSJohn Youn dev_vdbg(hsotg->dev, " Start PID: %d\n", 1509b02038faSJohn Youn (hctsiz & TSIZ_SC_MC_PID_MASK) >> 1510b02038faSJohn Youn TSIZ_SC_MC_PID_SHIFT); 1511b02038faSJohn Youn } 1512b02038faSJohn Youn 151395832c00SJohn Youn if (hsotg->params.host_dma) { 1514b02038faSJohn Youn dwc2_writel((u32)chan->xfer_dma, 1515b02038faSJohn Youn hsotg->regs + HCDMA(chan->hc_num)); 1516b02038faSJohn Youn if (dbg_hc(chan)) 1517b02038faSJohn Youn dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n", 1518b02038faSJohn Youn (unsigned long)chan->xfer_dma, chan->hc_num); 1519b02038faSJohn Youn } 1520b02038faSJohn Youn 1521b02038faSJohn Youn /* Start the split */ 1522b02038faSJohn Youn if (chan->do_split) { 1523b02038faSJohn Youn u32 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num)); 1524b02038faSJohn Youn 1525b02038faSJohn Youn hcsplt |= HCSPLT_SPLTENA; 1526b02038faSJohn Youn dwc2_writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num)); 1527b02038faSJohn Youn } 1528b02038faSJohn Youn 1529b02038faSJohn Youn hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1530b02038faSJohn Youn hcchar &= ~HCCHAR_MULTICNT_MASK; 1531b02038faSJohn Youn hcchar |= (ec_mc << HCCHAR_MULTICNT_SHIFT) & HCCHAR_MULTICNT_MASK; 1532b02038faSJohn Youn dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); 1533b02038faSJohn Youn 1534b02038faSJohn Youn if (hcchar & HCCHAR_CHDIS) 1535b02038faSJohn Youn dev_warn(hsotg->dev, 1536b02038faSJohn Youn "%s: chdis set, channel %d, hcchar 0x%08x\n", 1537b02038faSJohn Youn __func__, chan->hc_num, hcchar); 1538b02038faSJohn Youn 1539b02038faSJohn Youn /* Set host channel enable after all other setup is complete */ 1540b02038faSJohn Youn hcchar |= HCCHAR_CHENA; 1541b02038faSJohn Youn hcchar &= ~HCCHAR_CHDIS; 1542b02038faSJohn Youn 1543b02038faSJohn Youn if (dbg_hc(chan)) 1544b02038faSJohn Youn dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", 1545b02038faSJohn Youn (hcchar & HCCHAR_MULTICNT_MASK) >> 1546b02038faSJohn Youn HCCHAR_MULTICNT_SHIFT); 1547b02038faSJohn Youn 1548b02038faSJohn Youn dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1549b02038faSJohn Youn if (dbg_hc(chan)) 1550b02038faSJohn Youn dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, 1551b02038faSJohn Youn chan->hc_num); 1552b02038faSJohn Youn 1553b02038faSJohn Youn chan->xfer_started = 1; 1554b02038faSJohn Youn chan->requests++; 1555b02038faSJohn Youn 155695832c00SJohn Youn if (!hsotg->params.host_dma && 1557b02038faSJohn Youn !chan->ep_is_in && chan->xfer_len > 0) 1558b02038faSJohn Youn /* Load OUT packet into the appropriate Tx FIFO */ 1559b02038faSJohn Youn dwc2_hc_write_packet(hsotg, chan); 1560b02038faSJohn Youn } 1561b02038faSJohn Youn 1562b02038faSJohn Youn /** 1563b02038faSJohn Youn * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a 1564b02038faSJohn Youn * host channel and starts the transfer in Descriptor DMA mode 1565b02038faSJohn Youn * 1566b02038faSJohn Youn * @hsotg: Programming view of DWC_otg controller 1567b02038faSJohn Youn * @chan: Information needed to initialize the host channel 1568b02038faSJohn Youn * 1569b02038faSJohn Youn * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set. 1570b02038faSJohn Youn * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field 1571b02038faSJohn Youn * with micro-frame bitmap. 1572b02038faSJohn Youn * 1573b02038faSJohn Youn * Initializes HCDMA register with descriptor list address and CTD value then 1574b02038faSJohn Youn * starts the transfer via enabling the channel. 1575b02038faSJohn Youn */ 1576b02038faSJohn Youn void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 1577b02038faSJohn Youn struct dwc2_host_chan *chan) 1578b02038faSJohn Youn { 1579b02038faSJohn Youn u32 hcchar; 1580b02038faSJohn Youn u32 hctsiz = 0; 1581b02038faSJohn Youn 1582b02038faSJohn Youn if (chan->do_ping) 1583b02038faSJohn Youn hctsiz |= TSIZ_DOPNG; 1584b02038faSJohn Youn 1585b02038faSJohn Youn if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1586b02038faSJohn Youn dwc2_set_pid_isoc(chan); 1587b02038faSJohn Youn 1588b02038faSJohn Youn /* Packet Count and Xfer Size are not used in Descriptor DMA mode */ 1589b02038faSJohn Youn hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & 1590b02038faSJohn Youn TSIZ_SC_MC_PID_MASK; 1591b02038faSJohn Youn 1592b02038faSJohn Youn /* 0 - 1 descriptor, 1 - 2 descriptors, etc */ 1593b02038faSJohn Youn hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK; 1594b02038faSJohn Youn 1595b02038faSJohn Youn /* Non-zero only for high-speed interrupt endpoints */ 1596b02038faSJohn Youn hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK; 1597b02038faSJohn Youn 1598b02038faSJohn Youn if (dbg_hc(chan)) { 1599b02038faSJohn Youn dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1600b02038faSJohn Youn chan->hc_num); 1601b02038faSJohn Youn dev_vdbg(hsotg->dev, " Start PID: %d\n", 1602b02038faSJohn Youn chan->data_pid_start); 1603b02038faSJohn Youn dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1); 1604b02038faSJohn Youn } 1605b02038faSJohn Youn 1606b02038faSJohn Youn dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); 1607b02038faSJohn Youn 1608b02038faSJohn Youn dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr, 1609b02038faSJohn Youn chan->desc_list_sz, DMA_TO_DEVICE); 1610b02038faSJohn Youn 1611b02038faSJohn Youn dwc2_writel(chan->desc_list_addr, hsotg->regs + HCDMA(chan->hc_num)); 1612b02038faSJohn Youn 1613b02038faSJohn Youn if (dbg_hc(chan)) 1614b02038faSJohn Youn dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n", 1615b02038faSJohn Youn &chan->desc_list_addr, chan->hc_num); 1616b02038faSJohn Youn 1617b02038faSJohn Youn hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1618b02038faSJohn Youn hcchar &= ~HCCHAR_MULTICNT_MASK; 1619b02038faSJohn Youn hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT & 1620b02038faSJohn Youn HCCHAR_MULTICNT_MASK; 1621b02038faSJohn Youn 1622b02038faSJohn Youn if (hcchar & HCCHAR_CHDIS) 1623b02038faSJohn Youn dev_warn(hsotg->dev, 1624b02038faSJohn Youn "%s: chdis set, channel %d, hcchar 0x%08x\n", 1625b02038faSJohn Youn __func__, chan->hc_num, hcchar); 1626b02038faSJohn Youn 1627b02038faSJohn Youn /* Set host channel enable after all other setup is complete */ 1628b02038faSJohn Youn hcchar |= HCCHAR_CHENA; 1629b02038faSJohn Youn hcchar &= ~HCCHAR_CHDIS; 1630b02038faSJohn Youn 1631b02038faSJohn Youn if (dbg_hc(chan)) 1632b02038faSJohn Youn dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", 1633b02038faSJohn Youn (hcchar & HCCHAR_MULTICNT_MASK) >> 1634b02038faSJohn Youn HCCHAR_MULTICNT_SHIFT); 1635b02038faSJohn Youn 1636b02038faSJohn Youn dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1637b02038faSJohn Youn if (dbg_hc(chan)) 1638b02038faSJohn Youn dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, 1639b02038faSJohn Youn chan->hc_num); 1640b02038faSJohn Youn 1641b02038faSJohn Youn chan->xfer_started = 1; 1642b02038faSJohn Youn chan->requests++; 1643b02038faSJohn Youn } 1644b02038faSJohn Youn 1645b02038faSJohn Youn /** 1646b02038faSJohn Youn * dwc2_hc_continue_transfer() - Continues a data transfer that was started by 1647b02038faSJohn Youn * a previous call to dwc2_hc_start_transfer() 1648b02038faSJohn Youn * 1649b02038faSJohn Youn * @hsotg: Programming view of DWC_otg controller 1650b02038faSJohn Youn * @chan: Information needed to initialize the host channel 1651b02038faSJohn Youn * 1652b02038faSJohn Youn * The caller must ensure there is sufficient space in the request queue and Tx 1653b02038faSJohn Youn * Data FIFO. This function should only be called in Slave mode. In DMA mode, 1654b02038faSJohn Youn * the controller acts autonomously to complete transfers programmed to a host 1655b02038faSJohn Youn * channel. 1656b02038faSJohn Youn * 1657b02038faSJohn Youn * For an OUT transfer, a new data packet is loaded into the appropriate FIFO 1658b02038faSJohn Youn * if there is any data remaining to be queued. For an IN transfer, another 1659b02038faSJohn Youn * data packet is always requested. For the SETUP phase of a control transfer, 1660b02038faSJohn Youn * this function does nothing. 1661b02038faSJohn Youn * 1662b02038faSJohn Youn * Return: 1 if a new request is queued, 0 if no more requests are required 1663b02038faSJohn Youn * for this transfer 1664b02038faSJohn Youn */ 1665b02038faSJohn Youn static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, 1666b02038faSJohn Youn struct dwc2_host_chan *chan) 1667b02038faSJohn Youn { 1668b02038faSJohn Youn if (dbg_hc(chan)) 1669b02038faSJohn Youn dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1670b02038faSJohn Youn chan->hc_num); 1671b02038faSJohn Youn 1672b02038faSJohn Youn if (chan->do_split) 1673b02038faSJohn Youn /* SPLITs always queue just once per channel */ 1674b02038faSJohn Youn return 0; 1675b02038faSJohn Youn 1676b02038faSJohn Youn if (chan->data_pid_start == DWC2_HC_PID_SETUP) 1677b02038faSJohn Youn /* SETUPs are queued only once since they can't be NAK'd */ 1678b02038faSJohn Youn return 0; 1679b02038faSJohn Youn 1680b02038faSJohn Youn if (chan->ep_is_in) { 1681b02038faSJohn Youn /* 1682b02038faSJohn Youn * Always queue another request for other IN transfers. If 1683b02038faSJohn Youn * back-to-back INs are issued and NAKs are received for both, 1684b02038faSJohn Youn * the driver may still be processing the first NAK when the 1685b02038faSJohn Youn * second NAK is received. When the interrupt handler clears 1686b02038faSJohn Youn * the NAK interrupt for the first NAK, the second NAK will 1687b02038faSJohn Youn * not be seen. So we can't depend on the NAK interrupt 1688b02038faSJohn Youn * handler to requeue a NAK'd request. Instead, IN requests 1689b02038faSJohn Youn * are issued each time this function is called. When the 1690b02038faSJohn Youn * transfer completes, the extra requests for the channel will 1691b02038faSJohn Youn * be flushed. 1692b02038faSJohn Youn */ 1693b02038faSJohn Youn u32 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1694b02038faSJohn Youn 1695b02038faSJohn Youn dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); 1696b02038faSJohn Youn hcchar |= HCCHAR_CHENA; 1697b02038faSJohn Youn hcchar &= ~HCCHAR_CHDIS; 1698b02038faSJohn Youn if (dbg_hc(chan)) 1699b02038faSJohn Youn dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n", 1700b02038faSJohn Youn hcchar); 1701b02038faSJohn Youn dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1702b02038faSJohn Youn chan->requests++; 1703b02038faSJohn Youn return 1; 1704b02038faSJohn Youn } 1705b02038faSJohn Youn 1706b02038faSJohn Youn /* OUT transfers */ 1707b02038faSJohn Youn 1708b02038faSJohn Youn if (chan->xfer_count < chan->xfer_len) { 1709b02038faSJohn Youn if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1710b02038faSJohn Youn chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1711b02038faSJohn Youn u32 hcchar = dwc2_readl(hsotg->regs + 1712b02038faSJohn Youn HCCHAR(chan->hc_num)); 1713b02038faSJohn Youn 1714b02038faSJohn Youn dwc2_hc_set_even_odd_frame(hsotg, chan, 1715b02038faSJohn Youn &hcchar); 1716b02038faSJohn Youn } 1717b02038faSJohn Youn 1718b02038faSJohn Youn /* Load OUT packet into the appropriate Tx FIFO */ 1719b02038faSJohn Youn dwc2_hc_write_packet(hsotg, chan); 1720b02038faSJohn Youn chan->requests++; 1721b02038faSJohn Youn return 1; 1722b02038faSJohn Youn } 1723b02038faSJohn Youn 1724b02038faSJohn Youn return 0; 1725b02038faSJohn Youn } 1726b02038faSJohn Youn 1727b02038faSJohn Youn /* 1728b02038faSJohn Youn * ========================================================================= 1729b02038faSJohn Youn * HCD 1730b02038faSJohn Youn * ========================================================================= 1731b02038faSJohn Youn */ 1732b02038faSJohn Youn 1733b02038faSJohn Youn /* 1734197ba5f4SPaul Zimmerman * Processes all the URBs in a single list of QHs. Completes them with 1735197ba5f4SPaul Zimmerman * -ETIMEDOUT and frees the QTD. 1736197ba5f4SPaul Zimmerman * 1737197ba5f4SPaul Zimmerman * Must be called with interrupt disabled and spinlock held 1738197ba5f4SPaul Zimmerman */ 1739197ba5f4SPaul Zimmerman static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg, 1740197ba5f4SPaul Zimmerman struct list_head *qh_list) 1741197ba5f4SPaul Zimmerman { 1742197ba5f4SPaul Zimmerman struct dwc2_qh *qh, *qh_tmp; 1743197ba5f4SPaul Zimmerman struct dwc2_qtd *qtd, *qtd_tmp; 1744197ba5f4SPaul Zimmerman 1745197ba5f4SPaul Zimmerman list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 1746197ba5f4SPaul Zimmerman list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 1747197ba5f4SPaul Zimmerman qtd_list_entry) { 17482e84da6eSGregory Herrero dwc2_host_complete(hsotg, qtd, -ECONNRESET); 1749197ba5f4SPaul Zimmerman dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 1750197ba5f4SPaul Zimmerman } 1751197ba5f4SPaul Zimmerman } 1752197ba5f4SPaul Zimmerman } 1753197ba5f4SPaul Zimmerman 1754197ba5f4SPaul Zimmerman static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg, 1755197ba5f4SPaul Zimmerman struct list_head *qh_list) 1756197ba5f4SPaul Zimmerman { 1757197ba5f4SPaul Zimmerman struct dwc2_qtd *qtd, *qtd_tmp; 1758197ba5f4SPaul Zimmerman struct dwc2_qh *qh, *qh_tmp; 1759197ba5f4SPaul Zimmerman unsigned long flags; 1760197ba5f4SPaul Zimmerman 1761197ba5f4SPaul Zimmerman if (!qh_list->next) 1762197ba5f4SPaul Zimmerman /* The list hasn't been initialized yet */ 1763197ba5f4SPaul Zimmerman return; 1764197ba5f4SPaul Zimmerman 1765197ba5f4SPaul Zimmerman spin_lock_irqsave(&hsotg->lock, flags); 1766197ba5f4SPaul Zimmerman 1767197ba5f4SPaul Zimmerman /* Ensure there are no QTDs or URBs left */ 1768197ba5f4SPaul Zimmerman dwc2_kill_urbs_in_qh_list(hsotg, qh_list); 1769197ba5f4SPaul Zimmerman 1770197ba5f4SPaul Zimmerman list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 1771197ba5f4SPaul Zimmerman dwc2_hcd_qh_unlink(hsotg, qh); 1772197ba5f4SPaul Zimmerman 1773197ba5f4SPaul Zimmerman /* Free each QTD in the QH's QTD list */ 1774197ba5f4SPaul Zimmerman list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 1775197ba5f4SPaul Zimmerman qtd_list_entry) 1776197ba5f4SPaul Zimmerman dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 1777197ba5f4SPaul Zimmerman 177816e80218SDouglas Anderson if (qh->channel && qh->channel->qh == qh) 177916e80218SDouglas Anderson qh->channel->qh = NULL; 178016e80218SDouglas Anderson 1781197ba5f4SPaul Zimmerman spin_unlock_irqrestore(&hsotg->lock, flags); 1782197ba5f4SPaul Zimmerman dwc2_hcd_qh_free(hsotg, qh); 1783197ba5f4SPaul Zimmerman spin_lock_irqsave(&hsotg->lock, flags); 1784197ba5f4SPaul Zimmerman } 1785197ba5f4SPaul Zimmerman 1786197ba5f4SPaul Zimmerman spin_unlock_irqrestore(&hsotg->lock, flags); 1787197ba5f4SPaul Zimmerman } 1788197ba5f4SPaul Zimmerman 1789197ba5f4SPaul Zimmerman /* 1790197ba5f4SPaul Zimmerman * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic 1791197ba5f4SPaul Zimmerman * and periodic schedules. The QTD associated with each URB is removed from 1792197ba5f4SPaul Zimmerman * the schedule and freed. This function may be called when a disconnect is 1793197ba5f4SPaul Zimmerman * detected or when the HCD is being stopped. 1794197ba5f4SPaul Zimmerman * 1795197ba5f4SPaul Zimmerman * Must be called with interrupt disabled and spinlock held 1796197ba5f4SPaul Zimmerman */ 1797197ba5f4SPaul Zimmerman static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg) 1798197ba5f4SPaul Zimmerman { 1799197ba5f4SPaul Zimmerman dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive); 1800197ba5f4SPaul Zimmerman dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active); 1801197ba5f4SPaul Zimmerman dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive); 1802197ba5f4SPaul Zimmerman dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready); 1803197ba5f4SPaul Zimmerman dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned); 1804197ba5f4SPaul Zimmerman dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued); 1805197ba5f4SPaul Zimmerman } 1806197ba5f4SPaul Zimmerman 1807197ba5f4SPaul Zimmerman /** 1808197ba5f4SPaul Zimmerman * dwc2_hcd_start() - Starts the HCD when switching to Host mode 1809197ba5f4SPaul Zimmerman * 1810197ba5f4SPaul Zimmerman * @hsotg: Pointer to struct dwc2_hsotg 1811197ba5f4SPaul Zimmerman */ 1812197ba5f4SPaul Zimmerman void dwc2_hcd_start(struct dwc2_hsotg *hsotg) 1813197ba5f4SPaul Zimmerman { 1814197ba5f4SPaul Zimmerman u32 hprt0; 1815197ba5f4SPaul Zimmerman 1816197ba5f4SPaul Zimmerman if (hsotg->op_state == OTG_STATE_B_HOST) { 1817197ba5f4SPaul Zimmerman /* 1818197ba5f4SPaul Zimmerman * Reset the port. During a HNP mode switch the reset 1819197ba5f4SPaul Zimmerman * needs to occur within 1ms and have a duration of at 1820197ba5f4SPaul Zimmerman * least 50ms. 1821197ba5f4SPaul Zimmerman */ 1822197ba5f4SPaul Zimmerman hprt0 = dwc2_read_hprt0(hsotg); 1823197ba5f4SPaul Zimmerman hprt0 |= HPRT0_RST; 182495c8bc36SAntti Seppälä dwc2_writel(hprt0, hsotg->regs + HPRT0); 1825197ba5f4SPaul Zimmerman } 1826197ba5f4SPaul Zimmerman 1827197ba5f4SPaul Zimmerman queue_delayed_work(hsotg->wq_otg, &hsotg->start_work, 1828197ba5f4SPaul Zimmerman msecs_to_jiffies(50)); 1829197ba5f4SPaul Zimmerman } 1830197ba5f4SPaul Zimmerman 1831197ba5f4SPaul Zimmerman /* Must be called with interrupt disabled and spinlock held */ 1832197ba5f4SPaul Zimmerman static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg) 1833197ba5f4SPaul Zimmerman { 1834bea8e86cSJohn Youn int num_channels = hsotg->params.host_channels; 1835197ba5f4SPaul Zimmerman struct dwc2_host_chan *channel; 1836197ba5f4SPaul Zimmerman u32 hcchar; 1837197ba5f4SPaul Zimmerman int i; 1838197ba5f4SPaul Zimmerman 183995832c00SJohn Youn if (!hsotg->params.host_dma) { 1840197ba5f4SPaul Zimmerman /* Flush out any channel requests in slave mode */ 1841197ba5f4SPaul Zimmerman for (i = 0; i < num_channels; i++) { 1842197ba5f4SPaul Zimmerman channel = hsotg->hc_ptr_array[i]; 1843197ba5f4SPaul Zimmerman if (!list_empty(&channel->hc_list_entry)) 1844197ba5f4SPaul Zimmerman continue; 184595c8bc36SAntti Seppälä hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 1846197ba5f4SPaul Zimmerman if (hcchar & HCCHAR_CHENA) { 1847197ba5f4SPaul Zimmerman hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR); 1848197ba5f4SPaul Zimmerman hcchar |= HCCHAR_CHDIS; 184995c8bc36SAntti Seppälä dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 1850197ba5f4SPaul Zimmerman } 1851197ba5f4SPaul Zimmerman } 1852197ba5f4SPaul Zimmerman } 1853197ba5f4SPaul Zimmerman 1854197ba5f4SPaul Zimmerman for (i = 0; i < num_channels; i++) { 1855197ba5f4SPaul Zimmerman channel = hsotg->hc_ptr_array[i]; 1856197ba5f4SPaul Zimmerman if (!list_empty(&channel->hc_list_entry)) 1857197ba5f4SPaul Zimmerman continue; 185895c8bc36SAntti Seppälä hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 1859197ba5f4SPaul Zimmerman if (hcchar & HCCHAR_CHENA) { 1860197ba5f4SPaul Zimmerman /* Halt the channel */ 1861197ba5f4SPaul Zimmerman hcchar |= HCCHAR_CHDIS; 186295c8bc36SAntti Seppälä dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 1863197ba5f4SPaul Zimmerman } 1864197ba5f4SPaul Zimmerman 1865197ba5f4SPaul Zimmerman dwc2_hc_cleanup(hsotg, channel); 1866197ba5f4SPaul Zimmerman list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list); 1867197ba5f4SPaul Zimmerman /* 1868197ba5f4SPaul Zimmerman * Added for Descriptor DMA to prevent channel double cleanup in 1869197ba5f4SPaul Zimmerman * release_channel_ddma(), which is called from ep_disable when 1870197ba5f4SPaul Zimmerman * device disconnects 1871197ba5f4SPaul Zimmerman */ 1872197ba5f4SPaul Zimmerman channel->qh = NULL; 1873197ba5f4SPaul Zimmerman } 18747252f1bfSVincent Palatin /* All channels have been freed, mark them available */ 187595832c00SJohn Youn if (hsotg->params.uframe_sched) { 18767252f1bfSVincent Palatin hsotg->available_host_channels = 1877bea8e86cSJohn Youn hsotg->params.host_channels; 18787252f1bfSVincent Palatin } else { 18797252f1bfSVincent Palatin hsotg->non_periodic_channels = 0; 18807252f1bfSVincent Palatin hsotg->periodic_channels = 0; 18817252f1bfSVincent Palatin } 1882197ba5f4SPaul Zimmerman } 1883197ba5f4SPaul Zimmerman 1884197ba5f4SPaul Zimmerman /** 18856a659531SDouglas Anderson * dwc2_hcd_connect() - Handles connect of the HCD 1886197ba5f4SPaul Zimmerman * 1887197ba5f4SPaul Zimmerman * @hsotg: Pointer to struct dwc2_hsotg 1888197ba5f4SPaul Zimmerman * 1889197ba5f4SPaul Zimmerman * Must be called with interrupt disabled and spinlock held 1890197ba5f4SPaul Zimmerman */ 18916a659531SDouglas Anderson void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) 18926a659531SDouglas Anderson { 18936a659531SDouglas Anderson if (hsotg->lx_state != DWC2_L0) 18946a659531SDouglas Anderson usb_hcd_resume_root_hub(hsotg->priv); 18956a659531SDouglas Anderson 18966a659531SDouglas Anderson hsotg->flags.b.port_connect_status_change = 1; 18976a659531SDouglas Anderson hsotg->flags.b.port_connect_status = 1; 18986a659531SDouglas Anderson } 18996a659531SDouglas Anderson 19006a659531SDouglas Anderson /** 19016a659531SDouglas Anderson * dwc2_hcd_disconnect() - Handles disconnect of the HCD 19026a659531SDouglas Anderson * 19036a659531SDouglas Anderson * @hsotg: Pointer to struct dwc2_hsotg 19046a659531SDouglas Anderson * @force: If true, we won't try to reconnect even if we see device connected. 19056a659531SDouglas Anderson * 19066a659531SDouglas Anderson * Must be called with interrupt disabled and spinlock held 19076a659531SDouglas Anderson */ 19086a659531SDouglas Anderson void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) 1909197ba5f4SPaul Zimmerman { 1910197ba5f4SPaul Zimmerman u32 intr; 19116a659531SDouglas Anderson u32 hprt0; 1912197ba5f4SPaul Zimmerman 1913197ba5f4SPaul Zimmerman /* Set status flags for the hub driver */ 1914197ba5f4SPaul Zimmerman hsotg->flags.b.port_connect_status_change = 1; 1915197ba5f4SPaul Zimmerman hsotg->flags.b.port_connect_status = 0; 1916197ba5f4SPaul Zimmerman 1917197ba5f4SPaul Zimmerman /* 1918197ba5f4SPaul Zimmerman * Shutdown any transfers in process by clearing the Tx FIFO Empty 1919197ba5f4SPaul Zimmerman * interrupt mask and status bits and disabling subsequent host 1920197ba5f4SPaul Zimmerman * channel interrupts. 1921197ba5f4SPaul Zimmerman */ 192295c8bc36SAntti Seppälä intr = dwc2_readl(hsotg->regs + GINTMSK); 1923197ba5f4SPaul Zimmerman intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT); 192495c8bc36SAntti Seppälä dwc2_writel(intr, hsotg->regs + GINTMSK); 1925197ba5f4SPaul Zimmerman intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT; 192695c8bc36SAntti Seppälä dwc2_writel(intr, hsotg->regs + GINTSTS); 1927197ba5f4SPaul Zimmerman 1928197ba5f4SPaul Zimmerman /* 1929197ba5f4SPaul Zimmerman * Turn off the vbus power only if the core has transitioned to device 1930197ba5f4SPaul Zimmerman * mode. If still in host mode, need to keep power on to detect a 1931197ba5f4SPaul Zimmerman * reconnection. 1932197ba5f4SPaul Zimmerman */ 1933197ba5f4SPaul Zimmerman if (dwc2_is_device_mode(hsotg)) { 1934197ba5f4SPaul Zimmerman if (hsotg->op_state != OTG_STATE_A_SUSPEND) { 1935197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "Disconnect: PortPower off\n"); 193695c8bc36SAntti Seppälä dwc2_writel(0, hsotg->regs + HPRT0); 1937197ba5f4SPaul Zimmerman } 1938197ba5f4SPaul Zimmerman 1939197ba5f4SPaul Zimmerman dwc2_disable_host_interrupts(hsotg); 1940197ba5f4SPaul Zimmerman } 1941197ba5f4SPaul Zimmerman 1942197ba5f4SPaul Zimmerman /* Respond with an error status to all URBs in the schedule */ 1943197ba5f4SPaul Zimmerman dwc2_kill_all_urbs(hsotg); 1944197ba5f4SPaul Zimmerman 1945197ba5f4SPaul Zimmerman if (dwc2_is_host_mode(hsotg)) 1946197ba5f4SPaul Zimmerman /* Clean up any host channels that were in use */ 1947197ba5f4SPaul Zimmerman dwc2_hcd_cleanup_channels(hsotg); 1948197ba5f4SPaul Zimmerman 1949197ba5f4SPaul Zimmerman dwc2_host_disconnect(hsotg); 19506a659531SDouglas Anderson 19516a659531SDouglas Anderson /* 19526a659531SDouglas Anderson * Add an extra check here to see if we're actually connected but 19536a659531SDouglas Anderson * we don't have a detection interrupt pending. This can happen if: 19546a659531SDouglas Anderson * 1. hardware sees connect 19556a659531SDouglas Anderson * 2. hardware sees disconnect 19566a659531SDouglas Anderson * 3. hardware sees connect 19576a659531SDouglas Anderson * 4. dwc2_port_intr() - clears connect interrupt 19586a659531SDouglas Anderson * 5. dwc2_handle_common_intr() - calls here 19596a659531SDouglas Anderson * 19606a659531SDouglas Anderson * Without the extra check here we will end calling disconnect 19616a659531SDouglas Anderson * and won't get any future interrupts to handle the connect. 19626a659531SDouglas Anderson */ 19636a659531SDouglas Anderson if (!force) { 19646a659531SDouglas Anderson hprt0 = dwc2_readl(hsotg->regs + HPRT0); 19656a659531SDouglas Anderson if (!(hprt0 & HPRT0_CONNDET) && (hprt0 & HPRT0_CONNSTS)) 19666a659531SDouglas Anderson dwc2_hcd_connect(hsotg); 19676a659531SDouglas Anderson } 1968197ba5f4SPaul Zimmerman } 1969197ba5f4SPaul Zimmerman 1970197ba5f4SPaul Zimmerman /** 1971197ba5f4SPaul Zimmerman * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup 1972197ba5f4SPaul Zimmerman * 1973197ba5f4SPaul Zimmerman * @hsotg: Pointer to struct dwc2_hsotg 1974197ba5f4SPaul Zimmerman */ 1975197ba5f4SPaul Zimmerman static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg) 1976197ba5f4SPaul Zimmerman { 19771fb7f12dSDouglas Anderson if (hsotg->bus_suspended) { 1978197ba5f4SPaul Zimmerman hsotg->flags.b.port_suspend_change = 1; 1979b46146d5SGregory Herrero usb_hcd_resume_root_hub(hsotg->priv); 1980197ba5f4SPaul Zimmerman } 19811fb7f12dSDouglas Anderson 19821fb7f12dSDouglas Anderson if (hsotg->lx_state == DWC2_L1) 19831fb7f12dSDouglas Anderson hsotg->flags.b.port_l1_change = 1; 1984b46146d5SGregory Herrero } 1985197ba5f4SPaul Zimmerman 1986197ba5f4SPaul Zimmerman /** 1987197ba5f4SPaul Zimmerman * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner 1988197ba5f4SPaul Zimmerman * 1989197ba5f4SPaul Zimmerman * @hsotg: Pointer to struct dwc2_hsotg 1990197ba5f4SPaul Zimmerman * 1991197ba5f4SPaul Zimmerman * Must be called with interrupt disabled and spinlock held 1992197ba5f4SPaul Zimmerman */ 1993197ba5f4SPaul Zimmerman void dwc2_hcd_stop(struct dwc2_hsotg *hsotg) 1994197ba5f4SPaul Zimmerman { 1995197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n"); 1996197ba5f4SPaul Zimmerman 1997197ba5f4SPaul Zimmerman /* 1998197ba5f4SPaul Zimmerman * The root hub should be disconnected before this function is called. 1999197ba5f4SPaul Zimmerman * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue) 2000197ba5f4SPaul Zimmerman * and the QH lists (via ..._hcd_endpoint_disable). 2001197ba5f4SPaul Zimmerman */ 2002197ba5f4SPaul Zimmerman 2003197ba5f4SPaul Zimmerman /* Turn off all host-specific interrupts */ 2004197ba5f4SPaul Zimmerman dwc2_disable_host_interrupts(hsotg); 2005197ba5f4SPaul Zimmerman 2006197ba5f4SPaul Zimmerman /* Turn off the vbus power */ 2007197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "PortPower off\n"); 200895c8bc36SAntti Seppälä dwc2_writel(0, hsotg->regs + HPRT0); 2009197ba5f4SPaul Zimmerman } 2010197ba5f4SPaul Zimmerman 201133ad261aSGregory Herrero /* Caller must hold driver lock */ 2012197ba5f4SPaul Zimmerman static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, 2013b58e6ceeSMian Yousaf Kaukab struct dwc2_hcd_urb *urb, struct dwc2_qh *qh, 2014b5a468a6SMian Yousaf Kaukab struct dwc2_qtd *qtd) 2015197ba5f4SPaul Zimmerman { 2016197ba5f4SPaul Zimmerman u32 intr_mask; 2017197ba5f4SPaul Zimmerman int retval; 2018197ba5f4SPaul Zimmerman int dev_speed; 2019197ba5f4SPaul Zimmerman 2020197ba5f4SPaul Zimmerman if (!hsotg->flags.b.port_connect_status) { 2021197ba5f4SPaul Zimmerman /* No longer connected */ 2022197ba5f4SPaul Zimmerman dev_err(hsotg->dev, "Not connected\n"); 2023197ba5f4SPaul Zimmerman return -ENODEV; 2024197ba5f4SPaul Zimmerman } 2025197ba5f4SPaul Zimmerman 2026197ba5f4SPaul Zimmerman dev_speed = dwc2_host_get_speed(hsotg, urb->priv); 2027197ba5f4SPaul Zimmerman 2028197ba5f4SPaul Zimmerman /* Some configurations cannot support LS traffic on a FS root port */ 2029197ba5f4SPaul Zimmerman if ((dev_speed == USB_SPEED_LOW) && 2030197ba5f4SPaul Zimmerman (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) && 2031197ba5f4SPaul Zimmerman (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) { 203295c8bc36SAntti Seppälä u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 2033197ba5f4SPaul Zimmerman u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 2034197ba5f4SPaul Zimmerman 2035197ba5f4SPaul Zimmerman if (prtspd == HPRT0_SPD_FULL_SPEED) 2036197ba5f4SPaul Zimmerman return -ENODEV; 2037197ba5f4SPaul Zimmerman } 2038197ba5f4SPaul Zimmerman 2039197ba5f4SPaul Zimmerman if (!qtd) 2040b5a468a6SMian Yousaf Kaukab return -EINVAL; 2041197ba5f4SPaul Zimmerman 2042197ba5f4SPaul Zimmerman dwc2_hcd_qtd_init(qtd, urb); 2043b58e6ceeSMian Yousaf Kaukab retval = dwc2_hcd_qtd_add(hsotg, qtd, qh); 2044197ba5f4SPaul Zimmerman if (retval) { 2045197ba5f4SPaul Zimmerman dev_err(hsotg->dev, 2046197ba5f4SPaul Zimmerman "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n", 2047197ba5f4SPaul Zimmerman retval); 2048197ba5f4SPaul Zimmerman return retval; 2049197ba5f4SPaul Zimmerman } 2050197ba5f4SPaul Zimmerman 205195c8bc36SAntti Seppälä intr_mask = dwc2_readl(hsotg->regs + GINTMSK); 2052197ba5f4SPaul Zimmerman if (!(intr_mask & GINTSTS_SOF)) { 2053197ba5f4SPaul Zimmerman enum dwc2_transaction_type tr_type; 2054197ba5f4SPaul Zimmerman 2055197ba5f4SPaul Zimmerman if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK && 2056197ba5f4SPaul Zimmerman !(qtd->urb->flags & URB_GIVEBACK_ASAP)) 2057197ba5f4SPaul Zimmerman /* 2058197ba5f4SPaul Zimmerman * Do not schedule SG transactions until qtd has 2059197ba5f4SPaul Zimmerman * URB_GIVEBACK_ASAP set 2060197ba5f4SPaul Zimmerman */ 2061197ba5f4SPaul Zimmerman return 0; 2062197ba5f4SPaul Zimmerman 2063197ba5f4SPaul Zimmerman tr_type = dwc2_hcd_select_transactions(hsotg); 2064197ba5f4SPaul Zimmerman if (tr_type != DWC2_TRANSACTION_NONE) 2065197ba5f4SPaul Zimmerman dwc2_hcd_queue_transactions(hsotg, tr_type); 2066197ba5f4SPaul Zimmerman } 2067197ba5f4SPaul Zimmerman 2068197ba5f4SPaul Zimmerman return 0; 2069197ba5f4SPaul Zimmerman } 2070197ba5f4SPaul Zimmerman 2071197ba5f4SPaul Zimmerman /* Must be called with interrupt disabled and spinlock held */ 2072197ba5f4SPaul Zimmerman static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg, 2073197ba5f4SPaul Zimmerman struct dwc2_hcd_urb *urb) 2074197ba5f4SPaul Zimmerman { 2075197ba5f4SPaul Zimmerman struct dwc2_qh *qh; 2076197ba5f4SPaul Zimmerman struct dwc2_qtd *urb_qtd; 2077197ba5f4SPaul Zimmerman 2078197ba5f4SPaul Zimmerman urb_qtd = urb->qtd; 2079197ba5f4SPaul Zimmerman if (!urb_qtd) { 2080197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n"); 2081197ba5f4SPaul Zimmerman return -EINVAL; 2082197ba5f4SPaul Zimmerman } 2083197ba5f4SPaul Zimmerman 2084197ba5f4SPaul Zimmerman qh = urb_qtd->qh; 2085197ba5f4SPaul Zimmerman if (!qh) { 2086197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n"); 2087197ba5f4SPaul Zimmerman return -EINVAL; 2088197ba5f4SPaul Zimmerman } 2089197ba5f4SPaul Zimmerman 2090197ba5f4SPaul Zimmerman urb->priv = NULL; 2091197ba5f4SPaul Zimmerman 2092197ba5f4SPaul Zimmerman if (urb_qtd->in_process && qh->channel) { 2093197ba5f4SPaul Zimmerman dwc2_dump_channel_info(hsotg, qh->channel); 2094197ba5f4SPaul Zimmerman 2095197ba5f4SPaul Zimmerman /* The QTD is in process (it has been assigned to a channel) */ 2096197ba5f4SPaul Zimmerman if (hsotg->flags.b.port_connect_status) 2097197ba5f4SPaul Zimmerman /* 2098197ba5f4SPaul Zimmerman * If still connected (i.e. in host mode), halt the 2099197ba5f4SPaul Zimmerman * channel so it can be used for other transfers. If 2100197ba5f4SPaul Zimmerman * no longer connected, the host registers can't be 2101197ba5f4SPaul Zimmerman * written to halt the channel since the core is in 2102197ba5f4SPaul Zimmerman * device mode. 2103197ba5f4SPaul Zimmerman */ 2104197ba5f4SPaul Zimmerman dwc2_hc_halt(hsotg, qh->channel, 2105197ba5f4SPaul Zimmerman DWC2_HC_XFER_URB_DEQUEUE); 2106197ba5f4SPaul Zimmerman } 2107197ba5f4SPaul Zimmerman 2108197ba5f4SPaul Zimmerman /* 2109197ba5f4SPaul Zimmerman * Free the QTD and clean up the associated QH. Leave the QH in the 2110197ba5f4SPaul Zimmerman * schedule if it has any remaining QTDs. 2111197ba5f4SPaul Zimmerman */ 211295832c00SJohn Youn if (!hsotg->params.dma_desc_enable) { 2113197ba5f4SPaul Zimmerman u8 in_process = urb_qtd->in_process; 2114197ba5f4SPaul Zimmerman 2115197ba5f4SPaul Zimmerman dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 2116197ba5f4SPaul Zimmerman if (in_process) { 2117197ba5f4SPaul Zimmerman dwc2_hcd_qh_deactivate(hsotg, qh, 0); 2118197ba5f4SPaul Zimmerman qh->channel = NULL; 2119197ba5f4SPaul Zimmerman } else if (list_empty(&qh->qtd_list)) { 2120197ba5f4SPaul Zimmerman dwc2_hcd_qh_unlink(hsotg, qh); 2121197ba5f4SPaul Zimmerman } 2122197ba5f4SPaul Zimmerman } else { 2123197ba5f4SPaul Zimmerman dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 2124197ba5f4SPaul Zimmerman } 2125197ba5f4SPaul Zimmerman 2126197ba5f4SPaul Zimmerman return 0; 2127197ba5f4SPaul Zimmerman } 2128197ba5f4SPaul Zimmerman 2129197ba5f4SPaul Zimmerman /* Must NOT be called with interrupt disabled or spinlock held */ 2130197ba5f4SPaul Zimmerman static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg, 2131197ba5f4SPaul Zimmerman struct usb_host_endpoint *ep, int retry) 2132197ba5f4SPaul Zimmerman { 2133197ba5f4SPaul Zimmerman struct dwc2_qtd *qtd, *qtd_tmp; 2134197ba5f4SPaul Zimmerman struct dwc2_qh *qh; 2135197ba5f4SPaul Zimmerman unsigned long flags; 2136197ba5f4SPaul Zimmerman int rc; 2137197ba5f4SPaul Zimmerman 2138197ba5f4SPaul Zimmerman spin_lock_irqsave(&hsotg->lock, flags); 2139197ba5f4SPaul Zimmerman 2140197ba5f4SPaul Zimmerman qh = ep->hcpriv; 2141197ba5f4SPaul Zimmerman if (!qh) { 2142197ba5f4SPaul Zimmerman rc = -EINVAL; 2143197ba5f4SPaul Zimmerman goto err; 2144197ba5f4SPaul Zimmerman } 2145197ba5f4SPaul Zimmerman 2146197ba5f4SPaul Zimmerman while (!list_empty(&qh->qtd_list) && retry--) { 2147197ba5f4SPaul Zimmerman if (retry == 0) { 2148197ba5f4SPaul Zimmerman dev_err(hsotg->dev, 2149197ba5f4SPaul Zimmerman "## timeout in dwc2_hcd_endpoint_disable() ##\n"); 2150197ba5f4SPaul Zimmerman rc = -EBUSY; 2151197ba5f4SPaul Zimmerman goto err; 2152197ba5f4SPaul Zimmerman } 2153197ba5f4SPaul Zimmerman 2154197ba5f4SPaul Zimmerman spin_unlock_irqrestore(&hsotg->lock, flags); 215504a9db79SNicholas Mc Guire msleep(20); 2156197ba5f4SPaul Zimmerman spin_lock_irqsave(&hsotg->lock, flags); 2157197ba5f4SPaul Zimmerman qh = ep->hcpriv; 2158197ba5f4SPaul Zimmerman if (!qh) { 2159197ba5f4SPaul Zimmerman rc = -EINVAL; 2160197ba5f4SPaul Zimmerman goto err; 2161197ba5f4SPaul Zimmerman } 2162197ba5f4SPaul Zimmerman } 2163197ba5f4SPaul Zimmerman 2164197ba5f4SPaul Zimmerman dwc2_hcd_qh_unlink(hsotg, qh); 2165197ba5f4SPaul Zimmerman 2166197ba5f4SPaul Zimmerman /* Free each QTD in the QH's QTD list */ 2167197ba5f4SPaul Zimmerman list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) 2168197ba5f4SPaul Zimmerman dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 2169197ba5f4SPaul Zimmerman 2170197ba5f4SPaul Zimmerman ep->hcpriv = NULL; 217116e80218SDouglas Anderson 217216e80218SDouglas Anderson if (qh->channel && qh->channel->qh == qh) 217316e80218SDouglas Anderson qh->channel->qh = NULL; 217416e80218SDouglas Anderson 2175197ba5f4SPaul Zimmerman spin_unlock_irqrestore(&hsotg->lock, flags); 217616e80218SDouglas Anderson 2177197ba5f4SPaul Zimmerman dwc2_hcd_qh_free(hsotg, qh); 2178197ba5f4SPaul Zimmerman 2179197ba5f4SPaul Zimmerman return 0; 2180197ba5f4SPaul Zimmerman 2181197ba5f4SPaul Zimmerman err: 2182197ba5f4SPaul Zimmerman ep->hcpriv = NULL; 2183197ba5f4SPaul Zimmerman spin_unlock_irqrestore(&hsotg->lock, flags); 2184197ba5f4SPaul Zimmerman 2185197ba5f4SPaul Zimmerman return rc; 2186197ba5f4SPaul Zimmerman } 2187197ba5f4SPaul Zimmerman 2188197ba5f4SPaul Zimmerman /* Must be called with interrupt disabled and spinlock held */ 2189197ba5f4SPaul Zimmerman static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg, 2190197ba5f4SPaul Zimmerman struct usb_host_endpoint *ep) 2191197ba5f4SPaul Zimmerman { 2192197ba5f4SPaul Zimmerman struct dwc2_qh *qh = ep->hcpriv; 2193197ba5f4SPaul Zimmerman 2194197ba5f4SPaul Zimmerman if (!qh) 2195197ba5f4SPaul Zimmerman return -EINVAL; 2196197ba5f4SPaul Zimmerman 2197197ba5f4SPaul Zimmerman qh->data_toggle = DWC2_HC_PID_DATA0; 2198197ba5f4SPaul Zimmerman 2199197ba5f4SPaul Zimmerman return 0; 2200197ba5f4SPaul Zimmerman } 2201197ba5f4SPaul Zimmerman 2202b02038faSJohn Youn /** 2203b02038faSJohn Youn * dwc2_core_init() - Initializes the DWC_otg controller registers and 2204b02038faSJohn Youn * prepares the core for device mode or host mode operation 2205b02038faSJohn Youn * 2206b02038faSJohn Youn * @hsotg: Programming view of the DWC_otg controller 2207b02038faSJohn Youn * @initial_setup: If true then this is the first init for this instance. 2208b02038faSJohn Youn */ 2209b02038faSJohn Youn static int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup) 2210b02038faSJohn Youn { 2211b02038faSJohn Youn u32 usbcfg, otgctl; 2212b02038faSJohn Youn int retval; 2213b02038faSJohn Youn 2214b02038faSJohn Youn dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); 2215b02038faSJohn Youn 2216b02038faSJohn Youn usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 2217b02038faSJohn Youn 2218b02038faSJohn Youn /* Set ULPI External VBUS bit if needed */ 2219b02038faSJohn Youn usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV; 222095832c00SJohn Youn if (hsotg->params.phy_ulpi_ext_vbus) 2221b02038faSJohn Youn usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV; 2222b02038faSJohn Youn 2223b02038faSJohn Youn /* Set external TS Dline pulsing bit if needed */ 2224b02038faSJohn Youn usbcfg &= ~GUSBCFG_TERMSELDLPULSE; 222595832c00SJohn Youn if (hsotg->params.ts_dline) 2226b02038faSJohn Youn usbcfg |= GUSBCFG_TERMSELDLPULSE; 2227b02038faSJohn Youn 2228b02038faSJohn Youn dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 2229b02038faSJohn Youn 2230b02038faSJohn Youn /* 2231b02038faSJohn Youn * Reset the Controller 2232b02038faSJohn Youn * 2233b02038faSJohn Youn * We only need to reset the controller if this is a re-init. 2234b02038faSJohn Youn * For the first init we know for sure that earlier code reset us (it 2235b02038faSJohn Youn * needed to in order to properly detect various parameters). 2236b02038faSJohn Youn */ 2237b02038faSJohn Youn if (!initial_setup) { 2238b02038faSJohn Youn retval = dwc2_core_reset_and_force_dr_mode(hsotg); 2239b02038faSJohn Youn if (retval) { 2240b02038faSJohn Youn dev_err(hsotg->dev, "%s(): Reset failed, aborting\n", 2241b02038faSJohn Youn __func__); 2242b02038faSJohn Youn return retval; 2243b02038faSJohn Youn } 2244b02038faSJohn Youn } 2245b02038faSJohn Youn 2246b02038faSJohn Youn /* 2247b02038faSJohn Youn * This needs to happen in FS mode before any other programming occurs 2248b02038faSJohn Youn */ 2249b02038faSJohn Youn retval = dwc2_phy_init(hsotg, initial_setup); 2250b02038faSJohn Youn if (retval) 2251b02038faSJohn Youn return retval; 2252b02038faSJohn Youn 2253b02038faSJohn Youn /* Program the GAHBCFG Register */ 2254b02038faSJohn Youn retval = dwc2_gahbcfg_init(hsotg); 2255b02038faSJohn Youn if (retval) 2256b02038faSJohn Youn return retval; 2257b02038faSJohn Youn 2258b02038faSJohn Youn /* Program the GUSBCFG register */ 2259b02038faSJohn Youn dwc2_gusbcfg_init(hsotg); 2260b02038faSJohn Youn 2261b02038faSJohn Youn /* Program the GOTGCTL register */ 2262b02038faSJohn Youn otgctl = dwc2_readl(hsotg->regs + GOTGCTL); 2263b02038faSJohn Youn otgctl &= ~GOTGCTL_OTGVER; 2264b02038faSJohn Youn dwc2_writel(otgctl, hsotg->regs + GOTGCTL); 2265b02038faSJohn Youn 2266b02038faSJohn Youn /* Clear the SRP success bit for FS-I2c */ 2267b02038faSJohn Youn hsotg->srp_success = 0; 2268b02038faSJohn Youn 2269b02038faSJohn Youn /* Enable common interrupts */ 2270b02038faSJohn Youn dwc2_enable_common_interrupts(hsotg); 2271b02038faSJohn Youn 2272b02038faSJohn Youn /* 2273b02038faSJohn Youn * Do device or host initialization based on mode during PCD and 2274b02038faSJohn Youn * HCD initialization 2275b02038faSJohn Youn */ 2276b02038faSJohn Youn if (dwc2_is_host_mode(hsotg)) { 2277b02038faSJohn Youn dev_dbg(hsotg->dev, "Host Mode\n"); 2278b02038faSJohn Youn hsotg->op_state = OTG_STATE_A_HOST; 2279b02038faSJohn Youn } else { 2280b02038faSJohn Youn dev_dbg(hsotg->dev, "Device Mode\n"); 2281b02038faSJohn Youn hsotg->op_state = OTG_STATE_B_PERIPHERAL; 2282b02038faSJohn Youn } 2283b02038faSJohn Youn 2284b02038faSJohn Youn return 0; 2285b02038faSJohn Youn } 2286b02038faSJohn Youn 2287b02038faSJohn Youn /** 2288b02038faSJohn Youn * dwc2_core_host_init() - Initializes the DWC_otg controller registers for 2289b02038faSJohn Youn * Host mode 2290b02038faSJohn Youn * 2291b02038faSJohn Youn * @hsotg: Programming view of DWC_otg controller 2292b02038faSJohn Youn * 2293b02038faSJohn Youn * This function flushes the Tx and Rx FIFOs and flushes any entries in the 2294b02038faSJohn Youn * request queues. Host channels are reset to ensure that they are ready for 2295b02038faSJohn Youn * performing transfers. 2296b02038faSJohn Youn */ 2297b02038faSJohn Youn static void dwc2_core_host_init(struct dwc2_hsotg *hsotg) 2298b02038faSJohn Youn { 2299b02038faSJohn Youn u32 hcfg, hfir, otgctl; 2300b02038faSJohn Youn 2301b02038faSJohn Youn dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); 2302b02038faSJohn Youn 2303b02038faSJohn Youn /* Restart the Phy Clock */ 2304b02038faSJohn Youn dwc2_writel(0, hsotg->regs + PCGCTL); 2305b02038faSJohn Youn 2306b02038faSJohn Youn /* Initialize Host Configuration Register */ 2307b02038faSJohn Youn dwc2_init_fs_ls_pclk_sel(hsotg); 230838e9002bSVardan Mikayelyan if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL || 230938e9002bSVardan Mikayelyan hsotg->params.speed == DWC2_SPEED_PARAM_LOW) { 2310b02038faSJohn Youn hcfg = dwc2_readl(hsotg->regs + HCFG); 2311b02038faSJohn Youn hcfg |= HCFG_FSLSSUPP; 2312b02038faSJohn Youn dwc2_writel(hcfg, hsotg->regs + HCFG); 2313b02038faSJohn Youn } 2314b02038faSJohn Youn 2315b02038faSJohn Youn /* 2316b02038faSJohn Youn * This bit allows dynamic reloading of the HFIR register during 2317b02038faSJohn Youn * runtime. This bit needs to be programmed during initial configuration 2318b02038faSJohn Youn * and its value must not be changed during runtime. 2319b02038faSJohn Youn */ 232095832c00SJohn Youn if (hsotg->params.reload_ctl) { 2321b02038faSJohn Youn hfir = dwc2_readl(hsotg->regs + HFIR); 2322b02038faSJohn Youn hfir |= HFIR_RLDCTRL; 2323b02038faSJohn Youn dwc2_writel(hfir, hsotg->regs + HFIR); 2324b02038faSJohn Youn } 2325b02038faSJohn Youn 232695832c00SJohn Youn if (hsotg->params.dma_desc_enable) { 2327b02038faSJohn Youn u32 op_mode = hsotg->hw_params.op_mode; 2328b02038faSJohn Youn 2329b02038faSJohn Youn if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a || 2330b02038faSJohn Youn !hsotg->hw_params.dma_desc_enable || 2331b02038faSJohn Youn op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE || 2332b02038faSJohn Youn op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE || 2333b02038faSJohn Youn op_mode == GHWCFG2_OP_MODE_UNDEFINED) { 2334b02038faSJohn Youn dev_err(hsotg->dev, 2335b02038faSJohn Youn "Hardware does not support descriptor DMA mode -\n"); 2336b02038faSJohn Youn dev_err(hsotg->dev, 2337b02038faSJohn Youn "falling back to buffer DMA mode.\n"); 233895832c00SJohn Youn hsotg->params.dma_desc_enable = false; 2339b02038faSJohn Youn } else { 2340b02038faSJohn Youn hcfg = dwc2_readl(hsotg->regs + HCFG); 2341b02038faSJohn Youn hcfg |= HCFG_DESCDMA; 2342b02038faSJohn Youn dwc2_writel(hcfg, hsotg->regs + HCFG); 2343b02038faSJohn Youn } 2344b02038faSJohn Youn } 2345b02038faSJohn Youn 2346b02038faSJohn Youn /* Configure data FIFO sizes */ 2347b02038faSJohn Youn dwc2_config_fifos(hsotg); 2348b02038faSJohn Youn 2349b02038faSJohn Youn /* TODO - check this */ 2350b02038faSJohn Youn /* Clear Host Set HNP Enable in the OTG Control Register */ 2351b02038faSJohn Youn otgctl = dwc2_readl(hsotg->regs + GOTGCTL); 2352b02038faSJohn Youn otgctl &= ~GOTGCTL_HSTSETHNPEN; 2353b02038faSJohn Youn dwc2_writel(otgctl, hsotg->regs + GOTGCTL); 2354b02038faSJohn Youn 2355b02038faSJohn Youn /* Make sure the FIFOs are flushed */ 2356b02038faSJohn Youn dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */); 2357b02038faSJohn Youn dwc2_flush_rx_fifo(hsotg); 2358b02038faSJohn Youn 2359b02038faSJohn Youn /* Clear Host Set HNP Enable in the OTG Control Register */ 2360b02038faSJohn Youn otgctl = dwc2_readl(hsotg->regs + GOTGCTL); 2361b02038faSJohn Youn otgctl &= ~GOTGCTL_HSTSETHNPEN; 2362b02038faSJohn Youn dwc2_writel(otgctl, hsotg->regs + GOTGCTL); 2363b02038faSJohn Youn 236495832c00SJohn Youn if (!hsotg->params.dma_desc_enable) { 2365b02038faSJohn Youn int num_channels, i; 2366b02038faSJohn Youn u32 hcchar; 2367b02038faSJohn Youn 2368b02038faSJohn Youn /* Flush out any leftover queued requests */ 2369bea8e86cSJohn Youn num_channels = hsotg->params.host_channels; 2370b02038faSJohn Youn for (i = 0; i < num_channels; i++) { 2371b02038faSJohn Youn hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 2372b02038faSJohn Youn hcchar &= ~HCCHAR_CHENA; 2373b02038faSJohn Youn hcchar |= HCCHAR_CHDIS; 2374b02038faSJohn Youn hcchar &= ~HCCHAR_EPDIR; 2375b02038faSJohn Youn dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 2376b02038faSJohn Youn } 2377b02038faSJohn Youn 2378b02038faSJohn Youn /* Halt all channels to put them into a known state */ 2379b02038faSJohn Youn for (i = 0; i < num_channels; i++) { 2380b02038faSJohn Youn int count = 0; 2381b02038faSJohn Youn 2382b02038faSJohn Youn hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 2383b02038faSJohn Youn hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS; 2384b02038faSJohn Youn hcchar &= ~HCCHAR_EPDIR; 2385b02038faSJohn Youn dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 2386b02038faSJohn Youn dev_dbg(hsotg->dev, "%s: Halt channel %d\n", 2387b02038faSJohn Youn __func__, i); 2388b02038faSJohn Youn do { 2389b02038faSJohn Youn hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 2390b02038faSJohn Youn if (++count > 1000) { 2391b02038faSJohn Youn dev_err(hsotg->dev, 2392b02038faSJohn Youn "Unable to clear enable on channel %d\n", 2393b02038faSJohn Youn i); 2394b02038faSJohn Youn break; 2395b02038faSJohn Youn } 2396b02038faSJohn Youn udelay(1); 2397b02038faSJohn Youn } while (hcchar & HCCHAR_CHENA); 2398b02038faSJohn Youn } 2399b02038faSJohn Youn } 2400b02038faSJohn Youn 2401b02038faSJohn Youn /* Turn on the vbus power */ 2402b02038faSJohn Youn dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state); 2403b02038faSJohn Youn if (hsotg->op_state == OTG_STATE_A_HOST) { 2404b02038faSJohn Youn u32 hprt0 = dwc2_read_hprt0(hsotg); 2405b02038faSJohn Youn 2406b02038faSJohn Youn dev_dbg(hsotg->dev, "Init: Power Port (%d)\n", 2407b02038faSJohn Youn !!(hprt0 & HPRT0_PWR)); 2408b02038faSJohn Youn if (!(hprt0 & HPRT0_PWR)) { 2409b02038faSJohn Youn hprt0 |= HPRT0_PWR; 2410b02038faSJohn Youn dwc2_writel(hprt0, hsotg->regs + HPRT0); 2411b02038faSJohn Youn } 2412b02038faSJohn Youn } 2413b02038faSJohn Youn 2414b02038faSJohn Youn dwc2_enable_host_interrupts(hsotg); 2415b02038faSJohn Youn } 2416b02038faSJohn Youn 2417197ba5f4SPaul Zimmerman /* 2418197ba5f4SPaul Zimmerman * Initializes dynamic portions of the DWC_otg HCD state 2419197ba5f4SPaul Zimmerman * 2420197ba5f4SPaul Zimmerman * Must be called with interrupt disabled and spinlock held 2421197ba5f4SPaul Zimmerman */ 2422197ba5f4SPaul Zimmerman static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg) 2423197ba5f4SPaul Zimmerman { 2424197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan, *chan_tmp; 2425197ba5f4SPaul Zimmerman int num_channels; 2426197ba5f4SPaul Zimmerman int i; 2427197ba5f4SPaul Zimmerman 2428197ba5f4SPaul Zimmerman hsotg->flags.d32 = 0; 2429197ba5f4SPaul Zimmerman hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active; 2430197ba5f4SPaul Zimmerman 243195832c00SJohn Youn if (hsotg->params.uframe_sched) { 2432197ba5f4SPaul Zimmerman hsotg->available_host_channels = 2433bea8e86cSJohn Youn hsotg->params.host_channels; 2434197ba5f4SPaul Zimmerman } else { 2435197ba5f4SPaul Zimmerman hsotg->non_periodic_channels = 0; 2436197ba5f4SPaul Zimmerman hsotg->periodic_channels = 0; 2437197ba5f4SPaul Zimmerman } 2438197ba5f4SPaul Zimmerman 2439197ba5f4SPaul Zimmerman /* 2440197ba5f4SPaul Zimmerman * Put all channels in the free channel list and clean up channel 2441197ba5f4SPaul Zimmerman * states 2442197ba5f4SPaul Zimmerman */ 2443197ba5f4SPaul Zimmerman list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list, 2444197ba5f4SPaul Zimmerman hc_list_entry) 2445197ba5f4SPaul Zimmerman list_del_init(&chan->hc_list_entry); 2446197ba5f4SPaul Zimmerman 2447bea8e86cSJohn Youn num_channels = hsotg->params.host_channels; 2448197ba5f4SPaul Zimmerman for (i = 0; i < num_channels; i++) { 2449197ba5f4SPaul Zimmerman chan = hsotg->hc_ptr_array[i]; 2450197ba5f4SPaul Zimmerman list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list); 2451197ba5f4SPaul Zimmerman dwc2_hc_cleanup(hsotg, chan); 2452197ba5f4SPaul Zimmerman } 2453197ba5f4SPaul Zimmerman 2454197ba5f4SPaul Zimmerman /* Initialize the DWC core for host mode operation */ 2455197ba5f4SPaul Zimmerman dwc2_core_host_init(hsotg); 2456197ba5f4SPaul Zimmerman } 2457197ba5f4SPaul Zimmerman 2458197ba5f4SPaul Zimmerman static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg, 2459197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan, 2460197ba5f4SPaul Zimmerman struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 2461197ba5f4SPaul Zimmerman { 2462197ba5f4SPaul Zimmerman int hub_addr, hub_port; 2463197ba5f4SPaul Zimmerman 2464197ba5f4SPaul Zimmerman chan->do_split = 1; 2465197ba5f4SPaul Zimmerman chan->xact_pos = qtd->isoc_split_pos; 2466197ba5f4SPaul Zimmerman chan->complete_split = qtd->complete_split; 2467197ba5f4SPaul Zimmerman dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port); 2468197ba5f4SPaul Zimmerman chan->hub_addr = (u8)hub_addr; 2469197ba5f4SPaul Zimmerman chan->hub_port = (u8)hub_port; 2470197ba5f4SPaul Zimmerman } 2471197ba5f4SPaul Zimmerman 24723bc04e28SDouglas Anderson static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg, 2473197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan, 24743bc04e28SDouglas Anderson struct dwc2_qtd *qtd) 2475197ba5f4SPaul Zimmerman { 2476197ba5f4SPaul Zimmerman struct dwc2_hcd_urb *urb = qtd->urb; 2477197ba5f4SPaul Zimmerman struct dwc2_hcd_iso_packet_desc *frame_desc; 2478197ba5f4SPaul Zimmerman 2479197ba5f4SPaul Zimmerman switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) { 2480197ba5f4SPaul Zimmerman case USB_ENDPOINT_XFER_CONTROL: 2481197ba5f4SPaul Zimmerman chan->ep_type = USB_ENDPOINT_XFER_CONTROL; 2482197ba5f4SPaul Zimmerman 2483197ba5f4SPaul Zimmerman switch (qtd->control_phase) { 2484197ba5f4SPaul Zimmerman case DWC2_CONTROL_SETUP: 2485197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " Control setup transaction\n"); 2486197ba5f4SPaul Zimmerman chan->do_ping = 0; 2487197ba5f4SPaul Zimmerman chan->ep_is_in = 0; 2488197ba5f4SPaul Zimmerman chan->data_pid_start = DWC2_HC_PID_SETUP; 248995832c00SJohn Youn if (hsotg->params.host_dma) 2490197ba5f4SPaul Zimmerman chan->xfer_dma = urb->setup_dma; 2491197ba5f4SPaul Zimmerman else 2492197ba5f4SPaul Zimmerman chan->xfer_buf = urb->setup_packet; 2493197ba5f4SPaul Zimmerman chan->xfer_len = 8; 2494197ba5f4SPaul Zimmerman break; 2495197ba5f4SPaul Zimmerman 2496197ba5f4SPaul Zimmerman case DWC2_CONTROL_DATA: 2497197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " Control data transaction\n"); 2498197ba5f4SPaul Zimmerman chan->data_pid_start = qtd->data_toggle; 2499197ba5f4SPaul Zimmerman break; 2500197ba5f4SPaul Zimmerman 2501197ba5f4SPaul Zimmerman case DWC2_CONTROL_STATUS: 2502197ba5f4SPaul Zimmerman /* 2503197ba5f4SPaul Zimmerman * Direction is opposite of data direction or IN if no 2504197ba5f4SPaul Zimmerman * data 2505197ba5f4SPaul Zimmerman */ 2506197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " Control status transaction\n"); 2507197ba5f4SPaul Zimmerman if (urb->length == 0) 2508197ba5f4SPaul Zimmerman chan->ep_is_in = 1; 2509197ba5f4SPaul Zimmerman else 2510197ba5f4SPaul Zimmerman chan->ep_is_in = 2511197ba5f4SPaul Zimmerman dwc2_hcd_is_pipe_out(&urb->pipe_info); 2512197ba5f4SPaul Zimmerman if (chan->ep_is_in) 2513197ba5f4SPaul Zimmerman chan->do_ping = 0; 2514197ba5f4SPaul Zimmerman chan->data_pid_start = DWC2_HC_PID_DATA1; 2515197ba5f4SPaul Zimmerman chan->xfer_len = 0; 251695832c00SJohn Youn if (hsotg->params.host_dma) 2517197ba5f4SPaul Zimmerman chan->xfer_dma = hsotg->status_buf_dma; 2518197ba5f4SPaul Zimmerman else 2519197ba5f4SPaul Zimmerman chan->xfer_buf = hsotg->status_buf; 2520197ba5f4SPaul Zimmerman break; 2521197ba5f4SPaul Zimmerman } 2522197ba5f4SPaul Zimmerman break; 2523197ba5f4SPaul Zimmerman 2524197ba5f4SPaul Zimmerman case USB_ENDPOINT_XFER_BULK: 2525197ba5f4SPaul Zimmerman chan->ep_type = USB_ENDPOINT_XFER_BULK; 2526197ba5f4SPaul Zimmerman break; 2527197ba5f4SPaul Zimmerman 2528197ba5f4SPaul Zimmerman case USB_ENDPOINT_XFER_INT: 2529197ba5f4SPaul Zimmerman chan->ep_type = USB_ENDPOINT_XFER_INT; 2530197ba5f4SPaul Zimmerman break; 2531197ba5f4SPaul Zimmerman 2532197ba5f4SPaul Zimmerman case USB_ENDPOINT_XFER_ISOC: 2533197ba5f4SPaul Zimmerman chan->ep_type = USB_ENDPOINT_XFER_ISOC; 253495832c00SJohn Youn if (hsotg->params.dma_desc_enable) 2535197ba5f4SPaul Zimmerman break; 2536197ba5f4SPaul Zimmerman 2537197ba5f4SPaul Zimmerman frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; 2538197ba5f4SPaul Zimmerman frame_desc->status = 0; 2539197ba5f4SPaul Zimmerman 254095832c00SJohn Youn if (hsotg->params.host_dma) { 2541197ba5f4SPaul Zimmerman chan->xfer_dma = urb->dma; 2542197ba5f4SPaul Zimmerman chan->xfer_dma += frame_desc->offset + 2543197ba5f4SPaul Zimmerman qtd->isoc_split_offset; 2544197ba5f4SPaul Zimmerman } else { 2545197ba5f4SPaul Zimmerman chan->xfer_buf = urb->buf; 2546197ba5f4SPaul Zimmerman chan->xfer_buf += frame_desc->offset + 2547197ba5f4SPaul Zimmerman qtd->isoc_split_offset; 2548197ba5f4SPaul Zimmerman } 2549197ba5f4SPaul Zimmerman 2550197ba5f4SPaul Zimmerman chan->xfer_len = frame_desc->length - qtd->isoc_split_offset; 2551197ba5f4SPaul Zimmerman 2552197ba5f4SPaul Zimmerman if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) { 2553197ba5f4SPaul Zimmerman if (chan->xfer_len <= 188) 2554197ba5f4SPaul Zimmerman chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL; 2555197ba5f4SPaul Zimmerman else 2556197ba5f4SPaul Zimmerman chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN; 2557197ba5f4SPaul Zimmerman } 2558197ba5f4SPaul Zimmerman break; 2559197ba5f4SPaul Zimmerman } 2560197ba5f4SPaul Zimmerman } 2561197ba5f4SPaul Zimmerman 25623bc04e28SDouglas Anderson #define DWC2_USB_DMA_ALIGN 4 25633bc04e28SDouglas Anderson 25643bc04e28SDouglas Anderson struct dma_aligned_buffer { 25653bc04e28SDouglas Anderson void *kmalloc_ptr; 25663bc04e28SDouglas Anderson void *old_xfer_buffer; 25673bc04e28SDouglas Anderson u8 data[0]; 25683bc04e28SDouglas Anderson }; 25693bc04e28SDouglas Anderson 25703bc04e28SDouglas Anderson static void dwc2_free_dma_aligned_buffer(struct urb *urb) 2571197ba5f4SPaul Zimmerman { 25723bc04e28SDouglas Anderson struct dma_aligned_buffer *temp; 2573197ba5f4SPaul Zimmerman 25743bc04e28SDouglas Anderson if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER)) 25753bc04e28SDouglas Anderson return; 2576197ba5f4SPaul Zimmerman 25773bc04e28SDouglas Anderson temp = container_of(urb->transfer_buffer, 25783bc04e28SDouglas Anderson struct dma_aligned_buffer, data); 25793bc04e28SDouglas Anderson 25803bc04e28SDouglas Anderson if (usb_urb_dir_in(urb)) 25813bc04e28SDouglas Anderson memcpy(temp->old_xfer_buffer, temp->data, 25823bc04e28SDouglas Anderson urb->transfer_buffer_length); 25833bc04e28SDouglas Anderson urb->transfer_buffer = temp->old_xfer_buffer; 25843bc04e28SDouglas Anderson kfree(temp->kmalloc_ptr); 25853bc04e28SDouglas Anderson 25863bc04e28SDouglas Anderson urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER; 2587197ba5f4SPaul Zimmerman } 2588197ba5f4SPaul Zimmerman 25893bc04e28SDouglas Anderson static int dwc2_alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags) 25903bc04e28SDouglas Anderson { 25913bc04e28SDouglas Anderson struct dma_aligned_buffer *temp, *kmalloc_ptr; 25923bc04e28SDouglas Anderson size_t kmalloc_size; 25935dce9555SPaul Zimmerman 25943bc04e28SDouglas Anderson if (urb->num_sgs || urb->sg || 25953bc04e28SDouglas Anderson urb->transfer_buffer_length == 0 || 25963bc04e28SDouglas Anderson !((uintptr_t)urb->transfer_buffer & (DWC2_USB_DMA_ALIGN - 1))) 2597197ba5f4SPaul Zimmerman return 0; 25983bc04e28SDouglas Anderson 25993bc04e28SDouglas Anderson /* Allocate a buffer with enough padding for alignment */ 26003bc04e28SDouglas Anderson kmalloc_size = urb->transfer_buffer_length + 26013bc04e28SDouglas Anderson sizeof(struct dma_aligned_buffer) + DWC2_USB_DMA_ALIGN - 1; 26023bc04e28SDouglas Anderson 26033bc04e28SDouglas Anderson kmalloc_ptr = kmalloc(kmalloc_size, mem_flags); 26043bc04e28SDouglas Anderson if (!kmalloc_ptr) 26053bc04e28SDouglas Anderson return -ENOMEM; 26063bc04e28SDouglas Anderson 26073bc04e28SDouglas Anderson /* Position our struct dma_aligned_buffer such that data is aligned */ 26083bc04e28SDouglas Anderson temp = PTR_ALIGN(kmalloc_ptr + 1, DWC2_USB_DMA_ALIGN) - 1; 26093bc04e28SDouglas Anderson temp->kmalloc_ptr = kmalloc_ptr; 26103bc04e28SDouglas Anderson temp->old_xfer_buffer = urb->transfer_buffer; 26113bc04e28SDouglas Anderson if (usb_urb_dir_out(urb)) 26123bc04e28SDouglas Anderson memcpy(temp->data, urb->transfer_buffer, 26133bc04e28SDouglas Anderson urb->transfer_buffer_length); 26143bc04e28SDouglas Anderson urb->transfer_buffer = temp->data; 26153bc04e28SDouglas Anderson 26163bc04e28SDouglas Anderson urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER; 26173bc04e28SDouglas Anderson 26183bc04e28SDouglas Anderson return 0; 26193bc04e28SDouglas Anderson } 26203bc04e28SDouglas Anderson 26213bc04e28SDouglas Anderson static int dwc2_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, 26223bc04e28SDouglas Anderson gfp_t mem_flags) 26233bc04e28SDouglas Anderson { 26243bc04e28SDouglas Anderson int ret; 26253bc04e28SDouglas Anderson 26263bc04e28SDouglas Anderson /* We assume setup_dma is always aligned; warn if not */ 26273bc04e28SDouglas Anderson WARN_ON_ONCE(urb->setup_dma && 26283bc04e28SDouglas Anderson (urb->setup_dma & (DWC2_USB_DMA_ALIGN - 1))); 26293bc04e28SDouglas Anderson 26303bc04e28SDouglas Anderson ret = dwc2_alloc_dma_aligned_buffer(urb, mem_flags); 26313bc04e28SDouglas Anderson if (ret) 26323bc04e28SDouglas Anderson return ret; 26333bc04e28SDouglas Anderson 26343bc04e28SDouglas Anderson ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); 26353bc04e28SDouglas Anderson if (ret) 26363bc04e28SDouglas Anderson dwc2_free_dma_aligned_buffer(urb); 26373bc04e28SDouglas Anderson 26383bc04e28SDouglas Anderson return ret; 26393bc04e28SDouglas Anderson } 26403bc04e28SDouglas Anderson 26413bc04e28SDouglas Anderson static void dwc2_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb) 26423bc04e28SDouglas Anderson { 26433bc04e28SDouglas Anderson usb_hcd_unmap_urb_for_dma(hcd, urb); 26443bc04e28SDouglas Anderson dwc2_free_dma_aligned_buffer(urb); 2645197ba5f4SPaul Zimmerman } 2646197ba5f4SPaul Zimmerman 2647197ba5f4SPaul Zimmerman /** 2648197ba5f4SPaul Zimmerman * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host 2649197ba5f4SPaul Zimmerman * channel and initializes the host channel to perform the transactions. The 2650197ba5f4SPaul Zimmerman * host channel is removed from the free list. 2651197ba5f4SPaul Zimmerman * 2652197ba5f4SPaul Zimmerman * @hsotg: The HCD state structure 2653197ba5f4SPaul Zimmerman * @qh: Transactions from the first QTD for this QH are selected and assigned 2654197ba5f4SPaul Zimmerman * to a free host channel 2655197ba5f4SPaul Zimmerman */ 2656197ba5f4SPaul Zimmerman static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 2657197ba5f4SPaul Zimmerman { 2658197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan; 2659197ba5f4SPaul Zimmerman struct dwc2_hcd_urb *urb; 2660197ba5f4SPaul Zimmerman struct dwc2_qtd *qtd; 2661197ba5f4SPaul Zimmerman 2662197ba5f4SPaul Zimmerman if (dbg_qh(qh)) 2663197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh); 2664197ba5f4SPaul Zimmerman 2665197ba5f4SPaul Zimmerman if (list_empty(&qh->qtd_list)) { 2666197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "No QTDs in QH list\n"); 2667197ba5f4SPaul Zimmerman return -ENOMEM; 2668197ba5f4SPaul Zimmerman } 2669197ba5f4SPaul Zimmerman 2670197ba5f4SPaul Zimmerman if (list_empty(&hsotg->free_hc_list)) { 2671197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "No free channel to assign\n"); 2672197ba5f4SPaul Zimmerman return -ENOMEM; 2673197ba5f4SPaul Zimmerman } 2674197ba5f4SPaul Zimmerman 2675197ba5f4SPaul Zimmerman chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan, 2676197ba5f4SPaul Zimmerman hc_list_entry); 2677197ba5f4SPaul Zimmerman 2678197ba5f4SPaul Zimmerman /* Remove host channel from free list */ 2679197ba5f4SPaul Zimmerman list_del_init(&chan->hc_list_entry); 2680197ba5f4SPaul Zimmerman 2681197ba5f4SPaul Zimmerman qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry); 2682197ba5f4SPaul Zimmerman urb = qtd->urb; 2683197ba5f4SPaul Zimmerman qh->channel = chan; 2684197ba5f4SPaul Zimmerman qtd->in_process = 1; 2685197ba5f4SPaul Zimmerman 2686197ba5f4SPaul Zimmerman /* 2687197ba5f4SPaul Zimmerman * Use usb_pipedevice to determine device address. This address is 2688197ba5f4SPaul Zimmerman * 0 before the SET_ADDRESS command and the correct address afterward. 2689197ba5f4SPaul Zimmerman */ 2690197ba5f4SPaul Zimmerman chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info); 2691197ba5f4SPaul Zimmerman chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info); 2692197ba5f4SPaul Zimmerman chan->speed = qh->dev_speed; 2693197ba5f4SPaul Zimmerman chan->max_packet = dwc2_max_packet(qh->maxp); 2694197ba5f4SPaul Zimmerman 2695197ba5f4SPaul Zimmerman chan->xfer_started = 0; 2696197ba5f4SPaul Zimmerman chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS; 2697197ba5f4SPaul Zimmerman chan->error_state = (qtd->error_count > 0); 2698197ba5f4SPaul Zimmerman chan->halt_on_queue = 0; 2699197ba5f4SPaul Zimmerman chan->halt_pending = 0; 2700197ba5f4SPaul Zimmerman chan->requests = 0; 2701197ba5f4SPaul Zimmerman 2702197ba5f4SPaul Zimmerman /* 2703197ba5f4SPaul Zimmerman * The following values may be modified in the transfer type section 2704197ba5f4SPaul Zimmerman * below. The xfer_len value may be reduced when the transfer is 2705197ba5f4SPaul Zimmerman * started to accommodate the max widths of the XferSize and PktCnt 2706197ba5f4SPaul Zimmerman * fields in the HCTSIZn register. 2707197ba5f4SPaul Zimmerman */ 2708197ba5f4SPaul Zimmerman 2709197ba5f4SPaul Zimmerman chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0); 2710197ba5f4SPaul Zimmerman if (chan->ep_is_in) 2711197ba5f4SPaul Zimmerman chan->do_ping = 0; 2712197ba5f4SPaul Zimmerman else 2713197ba5f4SPaul Zimmerman chan->do_ping = qh->ping_state; 2714197ba5f4SPaul Zimmerman 2715197ba5f4SPaul Zimmerman chan->data_pid_start = qh->data_toggle; 2716197ba5f4SPaul Zimmerman chan->multi_count = 1; 2717197ba5f4SPaul Zimmerman 2718197ba5f4SPaul Zimmerman if (urb->actual_length > urb->length && 2719197ba5f4SPaul Zimmerman !dwc2_hcd_is_pipe_in(&urb->pipe_info)) 2720197ba5f4SPaul Zimmerman urb->actual_length = urb->length; 2721197ba5f4SPaul Zimmerman 272295832c00SJohn Youn if (hsotg->params.host_dma) 2723197ba5f4SPaul Zimmerman chan->xfer_dma = urb->dma + urb->actual_length; 27243bc04e28SDouglas Anderson else 2725197ba5f4SPaul Zimmerman chan->xfer_buf = (u8 *)urb->buf + urb->actual_length; 2726197ba5f4SPaul Zimmerman 2727197ba5f4SPaul Zimmerman chan->xfer_len = urb->length - urb->actual_length; 2728197ba5f4SPaul Zimmerman chan->xfer_count = 0; 2729197ba5f4SPaul Zimmerman 2730197ba5f4SPaul Zimmerman /* Set the split attributes if required */ 2731197ba5f4SPaul Zimmerman if (qh->do_split) 2732197ba5f4SPaul Zimmerman dwc2_hc_init_split(hsotg, chan, qtd, urb); 2733197ba5f4SPaul Zimmerman else 2734197ba5f4SPaul Zimmerman chan->do_split = 0; 2735197ba5f4SPaul Zimmerman 2736197ba5f4SPaul Zimmerman /* Set the transfer attributes */ 27373bc04e28SDouglas Anderson dwc2_hc_init_xfer(hsotg, chan, qtd); 2738197ba5f4SPaul Zimmerman 2739197ba5f4SPaul Zimmerman if (chan->ep_type == USB_ENDPOINT_XFER_INT || 2740197ba5f4SPaul Zimmerman chan->ep_type == USB_ENDPOINT_XFER_ISOC) 2741197ba5f4SPaul Zimmerman /* 2742197ba5f4SPaul Zimmerman * This value may be modified when the transfer is started 2743197ba5f4SPaul Zimmerman * to reflect the actual transfer length 2744197ba5f4SPaul Zimmerman */ 2745197ba5f4SPaul Zimmerman chan->multi_count = dwc2_hb_mult(qh->maxp); 2746197ba5f4SPaul Zimmerman 274795832c00SJohn Youn if (hsotg->params.dma_desc_enable) { 2748197ba5f4SPaul Zimmerman chan->desc_list_addr = qh->desc_list_dma; 274995105a99SGregory Herrero chan->desc_list_sz = qh->desc_list_sz; 275095105a99SGregory Herrero } 2751197ba5f4SPaul Zimmerman 2752197ba5f4SPaul Zimmerman dwc2_hc_init(hsotg, chan); 2753197ba5f4SPaul Zimmerman chan->qh = qh; 2754197ba5f4SPaul Zimmerman 2755197ba5f4SPaul Zimmerman return 0; 2756197ba5f4SPaul Zimmerman } 2757197ba5f4SPaul Zimmerman 2758197ba5f4SPaul Zimmerman /** 2759197ba5f4SPaul Zimmerman * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer 2760197ba5f4SPaul Zimmerman * schedule and assigns them to available host channels. Called from the HCD 2761197ba5f4SPaul Zimmerman * interrupt handler functions. 2762197ba5f4SPaul Zimmerman * 2763197ba5f4SPaul Zimmerman * @hsotg: The HCD state structure 2764197ba5f4SPaul Zimmerman * 2765197ba5f4SPaul Zimmerman * Return: The types of new transactions that were assigned to host channels 2766197ba5f4SPaul Zimmerman */ 2767197ba5f4SPaul Zimmerman enum dwc2_transaction_type dwc2_hcd_select_transactions( 2768197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg) 2769197ba5f4SPaul Zimmerman { 2770197ba5f4SPaul Zimmerman enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE; 2771197ba5f4SPaul Zimmerman struct list_head *qh_ptr; 2772197ba5f4SPaul Zimmerman struct dwc2_qh *qh; 2773197ba5f4SPaul Zimmerman int num_channels; 2774197ba5f4SPaul Zimmerman 2775197ba5f4SPaul Zimmerman #ifdef DWC2_DEBUG_SOF 2776197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " Select Transactions\n"); 2777197ba5f4SPaul Zimmerman #endif 2778197ba5f4SPaul Zimmerman 2779197ba5f4SPaul Zimmerman /* Process entries in the periodic ready list */ 2780197ba5f4SPaul Zimmerman qh_ptr = hsotg->periodic_sched_ready.next; 2781197ba5f4SPaul Zimmerman while (qh_ptr != &hsotg->periodic_sched_ready) { 2782197ba5f4SPaul Zimmerman if (list_empty(&hsotg->free_hc_list)) 2783197ba5f4SPaul Zimmerman break; 278495832c00SJohn Youn if (hsotg->params.uframe_sched) { 2785197ba5f4SPaul Zimmerman if (hsotg->available_host_channels <= 1) 2786197ba5f4SPaul Zimmerman break; 2787197ba5f4SPaul Zimmerman hsotg->available_host_channels--; 2788197ba5f4SPaul Zimmerman } 2789197ba5f4SPaul Zimmerman qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 2790197ba5f4SPaul Zimmerman if (dwc2_assign_and_init_hc(hsotg, qh)) 2791197ba5f4SPaul Zimmerman break; 2792197ba5f4SPaul Zimmerman 2793197ba5f4SPaul Zimmerman /* 2794197ba5f4SPaul Zimmerman * Move the QH from the periodic ready schedule to the 2795197ba5f4SPaul Zimmerman * periodic assigned schedule 2796197ba5f4SPaul Zimmerman */ 2797197ba5f4SPaul Zimmerman qh_ptr = qh_ptr->next; 279894ef7aeeSDouglas Anderson list_move_tail(&qh->qh_list_entry, 279994ef7aeeSDouglas Anderson &hsotg->periodic_sched_assigned); 2800197ba5f4SPaul Zimmerman ret_val = DWC2_TRANSACTION_PERIODIC; 2801197ba5f4SPaul Zimmerman } 2802197ba5f4SPaul Zimmerman 2803197ba5f4SPaul Zimmerman /* 2804197ba5f4SPaul Zimmerman * Process entries in the inactive portion of the non-periodic 2805197ba5f4SPaul Zimmerman * schedule. Some free host channels may not be used if they are 2806197ba5f4SPaul Zimmerman * reserved for periodic transfers. 2807197ba5f4SPaul Zimmerman */ 2808bea8e86cSJohn Youn num_channels = hsotg->params.host_channels; 2809197ba5f4SPaul Zimmerman qh_ptr = hsotg->non_periodic_sched_inactive.next; 2810197ba5f4SPaul Zimmerman while (qh_ptr != &hsotg->non_periodic_sched_inactive) { 281195832c00SJohn Youn if (!hsotg->params.uframe_sched && 2812197ba5f4SPaul Zimmerman hsotg->non_periodic_channels >= num_channels - 2813197ba5f4SPaul Zimmerman hsotg->periodic_channels) 2814197ba5f4SPaul Zimmerman break; 2815197ba5f4SPaul Zimmerman if (list_empty(&hsotg->free_hc_list)) 2816197ba5f4SPaul Zimmerman break; 2817197ba5f4SPaul Zimmerman qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 281895832c00SJohn Youn if (hsotg->params.uframe_sched) { 2819197ba5f4SPaul Zimmerman if (hsotg->available_host_channels < 1) 2820197ba5f4SPaul Zimmerman break; 2821197ba5f4SPaul Zimmerman hsotg->available_host_channels--; 2822197ba5f4SPaul Zimmerman } 2823197ba5f4SPaul Zimmerman 2824197ba5f4SPaul Zimmerman if (dwc2_assign_and_init_hc(hsotg, qh)) 2825197ba5f4SPaul Zimmerman break; 2826197ba5f4SPaul Zimmerman 2827197ba5f4SPaul Zimmerman /* 2828197ba5f4SPaul Zimmerman * Move the QH from the non-periodic inactive schedule to the 2829197ba5f4SPaul Zimmerman * non-periodic active schedule 2830197ba5f4SPaul Zimmerman */ 2831197ba5f4SPaul Zimmerman qh_ptr = qh_ptr->next; 283294ef7aeeSDouglas Anderson list_move_tail(&qh->qh_list_entry, 2833197ba5f4SPaul Zimmerman &hsotg->non_periodic_sched_active); 2834197ba5f4SPaul Zimmerman 2835197ba5f4SPaul Zimmerman if (ret_val == DWC2_TRANSACTION_NONE) 2836197ba5f4SPaul Zimmerman ret_val = DWC2_TRANSACTION_NON_PERIODIC; 2837197ba5f4SPaul Zimmerman else 2838197ba5f4SPaul Zimmerman ret_val = DWC2_TRANSACTION_ALL; 2839197ba5f4SPaul Zimmerman 284095832c00SJohn Youn if (!hsotg->params.uframe_sched) 2841197ba5f4SPaul Zimmerman hsotg->non_periodic_channels++; 2842197ba5f4SPaul Zimmerman } 2843197ba5f4SPaul Zimmerman 2844197ba5f4SPaul Zimmerman return ret_val; 2845197ba5f4SPaul Zimmerman } 2846197ba5f4SPaul Zimmerman 2847197ba5f4SPaul Zimmerman /** 2848197ba5f4SPaul Zimmerman * dwc2_queue_transaction() - Attempts to queue a single transaction request for 2849197ba5f4SPaul Zimmerman * a host channel associated with either a periodic or non-periodic transfer 2850197ba5f4SPaul Zimmerman * 2851197ba5f4SPaul Zimmerman * @hsotg: The HCD state structure 2852197ba5f4SPaul Zimmerman * @chan: Host channel descriptor associated with either a periodic or 2853197ba5f4SPaul Zimmerman * non-periodic transfer 2854197ba5f4SPaul Zimmerman * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO 2855197ba5f4SPaul Zimmerman * for periodic transfers or the non-periodic Tx FIFO 2856197ba5f4SPaul Zimmerman * for non-periodic transfers 2857197ba5f4SPaul Zimmerman * 2858197ba5f4SPaul Zimmerman * Return: 1 if a request is queued and more requests may be needed to 2859197ba5f4SPaul Zimmerman * complete the transfer, 0 if no more requests are required for this 2860197ba5f4SPaul Zimmerman * transfer, -1 if there is insufficient space in the Tx FIFO 2861197ba5f4SPaul Zimmerman * 2862197ba5f4SPaul Zimmerman * This function assumes that there is space available in the appropriate 2863197ba5f4SPaul Zimmerman * request queue. For an OUT transfer or SETUP transaction in Slave mode, 2864197ba5f4SPaul Zimmerman * it checks whether space is available in the appropriate Tx FIFO. 2865197ba5f4SPaul Zimmerman * 2866197ba5f4SPaul Zimmerman * Must be called with interrupt disabled and spinlock held 2867197ba5f4SPaul Zimmerman */ 2868197ba5f4SPaul Zimmerman static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg, 2869197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan, 2870197ba5f4SPaul Zimmerman u16 fifo_dwords_avail) 2871197ba5f4SPaul Zimmerman { 2872197ba5f4SPaul Zimmerman int retval = 0; 2873197ba5f4SPaul Zimmerman 2874c9c8ac01SDouglas Anderson if (chan->do_split) 2875c9c8ac01SDouglas Anderson /* Put ourselves on the list to keep order straight */ 2876c9c8ac01SDouglas Anderson list_move_tail(&chan->split_order_list_entry, 2877c9c8ac01SDouglas Anderson &hsotg->split_order); 2878c9c8ac01SDouglas Anderson 287995832c00SJohn Youn if (hsotg->params.host_dma) { 288095832c00SJohn Youn if (hsotg->params.dma_desc_enable) { 2881197ba5f4SPaul Zimmerman if (!chan->xfer_started || 2882197ba5f4SPaul Zimmerman chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 2883197ba5f4SPaul Zimmerman dwc2_hcd_start_xfer_ddma(hsotg, chan->qh); 2884197ba5f4SPaul Zimmerman chan->qh->ping_state = 0; 2885197ba5f4SPaul Zimmerman } 2886197ba5f4SPaul Zimmerman } else if (!chan->xfer_started) { 2887197ba5f4SPaul Zimmerman dwc2_hc_start_transfer(hsotg, chan); 2888197ba5f4SPaul Zimmerman chan->qh->ping_state = 0; 2889197ba5f4SPaul Zimmerman } 2890197ba5f4SPaul Zimmerman } else if (chan->halt_pending) { 2891197ba5f4SPaul Zimmerman /* Don't queue a request if the channel has been halted */ 2892197ba5f4SPaul Zimmerman } else if (chan->halt_on_queue) { 2893197ba5f4SPaul Zimmerman dwc2_hc_halt(hsotg, chan, chan->halt_status); 2894197ba5f4SPaul Zimmerman } else if (chan->do_ping) { 2895197ba5f4SPaul Zimmerman if (!chan->xfer_started) 2896197ba5f4SPaul Zimmerman dwc2_hc_start_transfer(hsotg, chan); 2897197ba5f4SPaul Zimmerman } else if (!chan->ep_is_in || 2898197ba5f4SPaul Zimmerman chan->data_pid_start == DWC2_HC_PID_SETUP) { 2899197ba5f4SPaul Zimmerman if ((fifo_dwords_avail * 4) >= chan->max_packet) { 2900197ba5f4SPaul Zimmerman if (!chan->xfer_started) { 2901197ba5f4SPaul Zimmerman dwc2_hc_start_transfer(hsotg, chan); 2902197ba5f4SPaul Zimmerman retval = 1; 2903197ba5f4SPaul Zimmerman } else { 2904197ba5f4SPaul Zimmerman retval = dwc2_hc_continue_transfer(hsotg, chan); 2905197ba5f4SPaul Zimmerman } 2906197ba5f4SPaul Zimmerman } else { 2907197ba5f4SPaul Zimmerman retval = -1; 2908197ba5f4SPaul Zimmerman } 2909197ba5f4SPaul Zimmerman } else { 2910197ba5f4SPaul Zimmerman if (!chan->xfer_started) { 2911197ba5f4SPaul Zimmerman dwc2_hc_start_transfer(hsotg, chan); 2912197ba5f4SPaul Zimmerman retval = 1; 2913197ba5f4SPaul Zimmerman } else { 2914197ba5f4SPaul Zimmerman retval = dwc2_hc_continue_transfer(hsotg, chan); 2915197ba5f4SPaul Zimmerman } 2916197ba5f4SPaul Zimmerman } 2917197ba5f4SPaul Zimmerman 2918197ba5f4SPaul Zimmerman return retval; 2919197ba5f4SPaul Zimmerman } 2920197ba5f4SPaul Zimmerman 2921197ba5f4SPaul Zimmerman /* 2922197ba5f4SPaul Zimmerman * Processes periodic channels for the next frame and queues transactions for 2923197ba5f4SPaul Zimmerman * these channels to the DWC_otg controller. After queueing transactions, the 2924197ba5f4SPaul Zimmerman * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions 2925197ba5f4SPaul Zimmerman * to queue as Periodic Tx FIFO or request queue space becomes available. 2926197ba5f4SPaul Zimmerman * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. 2927197ba5f4SPaul Zimmerman * 2928197ba5f4SPaul Zimmerman * Must be called with interrupt disabled and spinlock held 2929197ba5f4SPaul Zimmerman */ 2930197ba5f4SPaul Zimmerman static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) 2931197ba5f4SPaul Zimmerman { 2932197ba5f4SPaul Zimmerman struct list_head *qh_ptr; 2933197ba5f4SPaul Zimmerman struct dwc2_qh *qh; 2934197ba5f4SPaul Zimmerman u32 tx_status; 2935197ba5f4SPaul Zimmerman u32 fspcavail; 2936197ba5f4SPaul Zimmerman u32 gintmsk; 2937197ba5f4SPaul Zimmerman int status; 29384e50e011SDouglas Anderson bool no_queue_space = false; 29394e50e011SDouglas Anderson bool no_fifo_space = false; 2940197ba5f4SPaul Zimmerman u32 qspcavail; 2941197ba5f4SPaul Zimmerman 29424e50e011SDouglas Anderson /* If empty list then just adjust interrupt enables */ 29434e50e011SDouglas Anderson if (list_empty(&hsotg->periodic_sched_assigned)) 29444e50e011SDouglas Anderson goto exit; 29454e50e011SDouglas Anderson 2946197ba5f4SPaul Zimmerman if (dbg_perio()) 2947197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, "Queue periodic transactions\n"); 2948197ba5f4SPaul Zimmerman 294995c8bc36SAntti Seppälä tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 2950197ba5f4SPaul Zimmerman qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 2951197ba5f4SPaul Zimmerman TXSTS_QSPCAVAIL_SHIFT; 2952197ba5f4SPaul Zimmerman fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 2953197ba5f4SPaul Zimmerman TXSTS_FSPCAVAIL_SHIFT; 2954197ba5f4SPaul Zimmerman 2955197ba5f4SPaul Zimmerman if (dbg_perio()) { 2956197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n", 2957197ba5f4SPaul Zimmerman qspcavail); 2958197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n", 2959197ba5f4SPaul Zimmerman fspcavail); 2960197ba5f4SPaul Zimmerman } 2961197ba5f4SPaul Zimmerman 2962197ba5f4SPaul Zimmerman qh_ptr = hsotg->periodic_sched_assigned.next; 2963197ba5f4SPaul Zimmerman while (qh_ptr != &hsotg->periodic_sched_assigned) { 296495c8bc36SAntti Seppälä tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 2965197ba5f4SPaul Zimmerman qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 2966197ba5f4SPaul Zimmerman TXSTS_QSPCAVAIL_SHIFT; 2967197ba5f4SPaul Zimmerman if (qspcavail == 0) { 2968fdb09b3eSNicholas Mc Guire no_queue_space = true; 2969197ba5f4SPaul Zimmerman break; 2970197ba5f4SPaul Zimmerman } 2971197ba5f4SPaul Zimmerman 2972197ba5f4SPaul Zimmerman qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 2973197ba5f4SPaul Zimmerman if (!qh->channel) { 2974197ba5f4SPaul Zimmerman qh_ptr = qh_ptr->next; 2975197ba5f4SPaul Zimmerman continue; 2976197ba5f4SPaul Zimmerman } 2977197ba5f4SPaul Zimmerman 2978197ba5f4SPaul Zimmerman /* Make sure EP's TT buffer is clean before queueing qtds */ 2979197ba5f4SPaul Zimmerman if (qh->tt_buffer_dirty) { 2980197ba5f4SPaul Zimmerman qh_ptr = qh_ptr->next; 2981197ba5f4SPaul Zimmerman continue; 2982197ba5f4SPaul Zimmerman } 2983197ba5f4SPaul Zimmerman 2984197ba5f4SPaul Zimmerman /* 2985197ba5f4SPaul Zimmerman * Set a flag if we're queuing high-bandwidth in slave mode. 2986197ba5f4SPaul Zimmerman * The flag prevents any halts to get into the request queue in 2987197ba5f4SPaul Zimmerman * the middle of multiple high-bandwidth packets getting queued. 2988197ba5f4SPaul Zimmerman */ 298995832c00SJohn Youn if (!hsotg->params.host_dma && 2990197ba5f4SPaul Zimmerman qh->channel->multi_count > 1) 2991197ba5f4SPaul Zimmerman hsotg->queuing_high_bandwidth = 1; 2992197ba5f4SPaul Zimmerman 2993197ba5f4SPaul Zimmerman fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 2994197ba5f4SPaul Zimmerman TXSTS_FSPCAVAIL_SHIFT; 2995197ba5f4SPaul Zimmerman status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 2996197ba5f4SPaul Zimmerman if (status < 0) { 2997fdb09b3eSNicholas Mc Guire no_fifo_space = true; 2998197ba5f4SPaul Zimmerman break; 2999197ba5f4SPaul Zimmerman } 3000197ba5f4SPaul Zimmerman 3001197ba5f4SPaul Zimmerman /* 3002197ba5f4SPaul Zimmerman * In Slave mode, stay on the current transfer until there is 3003197ba5f4SPaul Zimmerman * nothing more to do or the high-bandwidth request count is 3004197ba5f4SPaul Zimmerman * reached. In DMA mode, only need to queue one request. The 3005197ba5f4SPaul Zimmerman * controller automatically handles multiple packets for 3006197ba5f4SPaul Zimmerman * high-bandwidth transfers. 3007197ba5f4SPaul Zimmerman */ 300895832c00SJohn Youn if (hsotg->params.host_dma || status == 0 || 3009197ba5f4SPaul Zimmerman qh->channel->requests == qh->channel->multi_count) { 3010197ba5f4SPaul Zimmerman qh_ptr = qh_ptr->next; 3011197ba5f4SPaul Zimmerman /* 3012197ba5f4SPaul Zimmerman * Move the QH from the periodic assigned schedule to 3013197ba5f4SPaul Zimmerman * the periodic queued schedule 3014197ba5f4SPaul Zimmerman */ 301594ef7aeeSDouglas Anderson list_move_tail(&qh->qh_list_entry, 3016197ba5f4SPaul Zimmerman &hsotg->periodic_sched_queued); 3017197ba5f4SPaul Zimmerman 3018197ba5f4SPaul Zimmerman /* done queuing high bandwidth */ 3019197ba5f4SPaul Zimmerman hsotg->queuing_high_bandwidth = 0; 3020197ba5f4SPaul Zimmerman } 3021197ba5f4SPaul Zimmerman } 3022197ba5f4SPaul Zimmerman 30234e50e011SDouglas Anderson exit: 30244e50e011SDouglas Anderson if (no_queue_space || no_fifo_space || 302595832c00SJohn Youn (!hsotg->params.host_dma && 30264e50e011SDouglas Anderson !list_empty(&hsotg->periodic_sched_assigned))) { 3027197ba5f4SPaul Zimmerman /* 3028197ba5f4SPaul Zimmerman * May need to queue more transactions as the request 3029197ba5f4SPaul Zimmerman * queue or Tx FIFO empties. Enable the periodic Tx 3030197ba5f4SPaul Zimmerman * FIFO empty interrupt. (Always use the half-empty 3031197ba5f4SPaul Zimmerman * level to ensure that new requests are loaded as 3032197ba5f4SPaul Zimmerman * soon as possible.) 3033197ba5f4SPaul Zimmerman */ 303495c8bc36SAntti Seppälä gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 30354e50e011SDouglas Anderson if (!(gintmsk & GINTSTS_PTXFEMP)) { 3036197ba5f4SPaul Zimmerman gintmsk |= GINTSTS_PTXFEMP; 303795c8bc36SAntti Seppälä dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 30384e50e011SDouglas Anderson } 3039197ba5f4SPaul Zimmerman } else { 3040197ba5f4SPaul Zimmerman /* 3041197ba5f4SPaul Zimmerman * Disable the Tx FIFO empty interrupt since there are 3042197ba5f4SPaul Zimmerman * no more transactions that need to be queued right 3043197ba5f4SPaul Zimmerman * now. This function is called from interrupt 3044197ba5f4SPaul Zimmerman * handlers to queue more transactions as transfer 3045197ba5f4SPaul Zimmerman * states change. 3046197ba5f4SPaul Zimmerman */ 304795c8bc36SAntti Seppälä gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 30484e50e011SDouglas Anderson if (gintmsk & GINTSTS_PTXFEMP) { 3049197ba5f4SPaul Zimmerman gintmsk &= ~GINTSTS_PTXFEMP; 305095c8bc36SAntti Seppälä dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3051197ba5f4SPaul Zimmerman } 3052197ba5f4SPaul Zimmerman } 3053197ba5f4SPaul Zimmerman } 3054197ba5f4SPaul Zimmerman 3055197ba5f4SPaul Zimmerman /* 3056197ba5f4SPaul Zimmerman * Processes active non-periodic channels and queues transactions for these 3057197ba5f4SPaul Zimmerman * channels to the DWC_otg controller. After queueing transactions, the NP Tx 3058197ba5f4SPaul Zimmerman * FIFO Empty interrupt is enabled if there are more transactions to queue as 3059197ba5f4SPaul Zimmerman * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx 3060197ba5f4SPaul Zimmerman * FIFO Empty interrupt is disabled. 3061197ba5f4SPaul Zimmerman * 3062197ba5f4SPaul Zimmerman * Must be called with interrupt disabled and spinlock held 3063197ba5f4SPaul Zimmerman */ 3064197ba5f4SPaul Zimmerman static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg) 3065197ba5f4SPaul Zimmerman { 3066197ba5f4SPaul Zimmerman struct list_head *orig_qh_ptr; 3067197ba5f4SPaul Zimmerman struct dwc2_qh *qh; 3068197ba5f4SPaul Zimmerman u32 tx_status; 3069197ba5f4SPaul Zimmerman u32 qspcavail; 3070197ba5f4SPaul Zimmerman u32 fspcavail; 3071197ba5f4SPaul Zimmerman u32 gintmsk; 3072197ba5f4SPaul Zimmerman int status; 3073197ba5f4SPaul Zimmerman int no_queue_space = 0; 3074197ba5f4SPaul Zimmerman int no_fifo_space = 0; 3075197ba5f4SPaul Zimmerman int more_to_do = 0; 3076197ba5f4SPaul Zimmerman 3077197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n"); 3078197ba5f4SPaul Zimmerman 307995c8bc36SAntti Seppälä tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 3080197ba5f4SPaul Zimmerman qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3081197ba5f4SPaul Zimmerman TXSTS_QSPCAVAIL_SHIFT; 3082197ba5f4SPaul Zimmerman fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3083197ba5f4SPaul Zimmerman TXSTS_FSPCAVAIL_SHIFT; 3084197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n", 3085197ba5f4SPaul Zimmerman qspcavail); 3086197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n", 3087197ba5f4SPaul Zimmerman fspcavail); 3088197ba5f4SPaul Zimmerman 3089197ba5f4SPaul Zimmerman /* 3090197ba5f4SPaul Zimmerman * Keep track of the starting point. Skip over the start-of-list 3091197ba5f4SPaul Zimmerman * entry. 3092197ba5f4SPaul Zimmerman */ 3093197ba5f4SPaul Zimmerman if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active) 3094197ba5f4SPaul Zimmerman hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 3095197ba5f4SPaul Zimmerman orig_qh_ptr = hsotg->non_periodic_qh_ptr; 3096197ba5f4SPaul Zimmerman 3097197ba5f4SPaul Zimmerman /* 3098197ba5f4SPaul Zimmerman * Process once through the active list or until no more space is 3099197ba5f4SPaul Zimmerman * available in the request queue or the Tx FIFO 3100197ba5f4SPaul Zimmerman */ 3101197ba5f4SPaul Zimmerman do { 310295c8bc36SAntti Seppälä tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 3103197ba5f4SPaul Zimmerman qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3104197ba5f4SPaul Zimmerman TXSTS_QSPCAVAIL_SHIFT; 310595832c00SJohn Youn if (!hsotg->params.host_dma && qspcavail == 0) { 3106197ba5f4SPaul Zimmerman no_queue_space = 1; 3107197ba5f4SPaul Zimmerman break; 3108197ba5f4SPaul Zimmerman } 3109197ba5f4SPaul Zimmerman 3110197ba5f4SPaul Zimmerman qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh, 3111197ba5f4SPaul Zimmerman qh_list_entry); 3112197ba5f4SPaul Zimmerman if (!qh->channel) 3113197ba5f4SPaul Zimmerman goto next; 3114197ba5f4SPaul Zimmerman 3115197ba5f4SPaul Zimmerman /* Make sure EP's TT buffer is clean before queueing qtds */ 3116197ba5f4SPaul Zimmerman if (qh->tt_buffer_dirty) 3117197ba5f4SPaul Zimmerman goto next; 3118197ba5f4SPaul Zimmerman 3119197ba5f4SPaul Zimmerman fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3120197ba5f4SPaul Zimmerman TXSTS_FSPCAVAIL_SHIFT; 3121197ba5f4SPaul Zimmerman status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 3122197ba5f4SPaul Zimmerman 3123197ba5f4SPaul Zimmerman if (status > 0) { 3124197ba5f4SPaul Zimmerman more_to_do = 1; 3125197ba5f4SPaul Zimmerman } else if (status < 0) { 3126197ba5f4SPaul Zimmerman no_fifo_space = 1; 3127197ba5f4SPaul Zimmerman break; 3128197ba5f4SPaul Zimmerman } 3129197ba5f4SPaul Zimmerman next: 3130197ba5f4SPaul Zimmerman /* Advance to next QH, skipping start-of-list entry */ 3131197ba5f4SPaul Zimmerman hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 3132197ba5f4SPaul Zimmerman if (hsotg->non_periodic_qh_ptr == 3133197ba5f4SPaul Zimmerman &hsotg->non_periodic_sched_active) 3134197ba5f4SPaul Zimmerman hsotg->non_periodic_qh_ptr = 3135197ba5f4SPaul Zimmerman hsotg->non_periodic_qh_ptr->next; 3136197ba5f4SPaul Zimmerman } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr); 3137197ba5f4SPaul Zimmerman 313895832c00SJohn Youn if (!hsotg->params.host_dma) { 313995c8bc36SAntti Seppälä tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 3140197ba5f4SPaul Zimmerman qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3141197ba5f4SPaul Zimmerman TXSTS_QSPCAVAIL_SHIFT; 3142197ba5f4SPaul Zimmerman fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3143197ba5f4SPaul Zimmerman TXSTS_FSPCAVAIL_SHIFT; 3144197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, 3145197ba5f4SPaul Zimmerman " NP Tx Req Queue Space Avail (after queue): %d\n", 3146197ba5f4SPaul Zimmerman qspcavail); 3147197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, 3148197ba5f4SPaul Zimmerman " NP Tx FIFO Space Avail (after queue): %d\n", 3149197ba5f4SPaul Zimmerman fspcavail); 3150197ba5f4SPaul Zimmerman 3151197ba5f4SPaul Zimmerman if (more_to_do || no_queue_space || no_fifo_space) { 3152197ba5f4SPaul Zimmerman /* 3153197ba5f4SPaul Zimmerman * May need to queue more transactions as the request 3154197ba5f4SPaul Zimmerman * queue or Tx FIFO empties. Enable the non-periodic 3155197ba5f4SPaul Zimmerman * Tx FIFO empty interrupt. (Always use the half-empty 3156197ba5f4SPaul Zimmerman * level to ensure that new requests are loaded as 3157197ba5f4SPaul Zimmerman * soon as possible.) 3158197ba5f4SPaul Zimmerman */ 315995c8bc36SAntti Seppälä gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3160197ba5f4SPaul Zimmerman gintmsk |= GINTSTS_NPTXFEMP; 316195c8bc36SAntti Seppälä dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3162197ba5f4SPaul Zimmerman } else { 3163197ba5f4SPaul Zimmerman /* 3164197ba5f4SPaul Zimmerman * Disable the Tx FIFO empty interrupt since there are 3165197ba5f4SPaul Zimmerman * no more transactions that need to be queued right 3166197ba5f4SPaul Zimmerman * now. This function is called from interrupt 3167197ba5f4SPaul Zimmerman * handlers to queue more transactions as transfer 3168197ba5f4SPaul Zimmerman * states change. 3169197ba5f4SPaul Zimmerman */ 317095c8bc36SAntti Seppälä gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3171197ba5f4SPaul Zimmerman gintmsk &= ~GINTSTS_NPTXFEMP; 317295c8bc36SAntti Seppälä dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3173197ba5f4SPaul Zimmerman } 3174197ba5f4SPaul Zimmerman } 3175197ba5f4SPaul Zimmerman } 3176197ba5f4SPaul Zimmerman 3177197ba5f4SPaul Zimmerman /** 3178197ba5f4SPaul Zimmerman * dwc2_hcd_queue_transactions() - Processes the currently active host channels 3179197ba5f4SPaul Zimmerman * and queues transactions for these channels to the DWC_otg controller. Called 3180197ba5f4SPaul Zimmerman * from the HCD interrupt handler functions. 3181197ba5f4SPaul Zimmerman * 3182197ba5f4SPaul Zimmerman * @hsotg: The HCD state structure 3183197ba5f4SPaul Zimmerman * @tr_type: The type(s) of transactions to queue (non-periodic, periodic, 3184197ba5f4SPaul Zimmerman * or both) 3185197ba5f4SPaul Zimmerman * 3186197ba5f4SPaul Zimmerman * Must be called with interrupt disabled and spinlock held 3187197ba5f4SPaul Zimmerman */ 3188197ba5f4SPaul Zimmerman void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 3189197ba5f4SPaul Zimmerman enum dwc2_transaction_type tr_type) 3190197ba5f4SPaul Zimmerman { 3191197ba5f4SPaul Zimmerman #ifdef DWC2_DEBUG_SOF 3192197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, "Queue Transactions\n"); 3193197ba5f4SPaul Zimmerman #endif 3194197ba5f4SPaul Zimmerman /* Process host channels associated with periodic transfers */ 31954e50e011SDouglas Anderson if (tr_type == DWC2_TRANSACTION_PERIODIC || 31964e50e011SDouglas Anderson tr_type == DWC2_TRANSACTION_ALL) 3197197ba5f4SPaul Zimmerman dwc2_process_periodic_channels(hsotg); 3198197ba5f4SPaul Zimmerman 3199197ba5f4SPaul Zimmerman /* Process host channels associated with non-periodic transfers */ 3200197ba5f4SPaul Zimmerman if (tr_type == DWC2_TRANSACTION_NON_PERIODIC || 3201197ba5f4SPaul Zimmerman tr_type == DWC2_TRANSACTION_ALL) { 3202197ba5f4SPaul Zimmerman if (!list_empty(&hsotg->non_periodic_sched_active)) { 3203197ba5f4SPaul Zimmerman dwc2_process_non_periodic_channels(hsotg); 3204197ba5f4SPaul Zimmerman } else { 3205197ba5f4SPaul Zimmerman /* 3206197ba5f4SPaul Zimmerman * Ensure NP Tx FIFO empty interrupt is disabled when 3207197ba5f4SPaul Zimmerman * there are no non-periodic transfers to process 3208197ba5f4SPaul Zimmerman */ 320995c8bc36SAntti Seppälä u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3210197ba5f4SPaul Zimmerman 3211197ba5f4SPaul Zimmerman gintmsk &= ~GINTSTS_NPTXFEMP; 321295c8bc36SAntti Seppälä dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3213197ba5f4SPaul Zimmerman } 3214197ba5f4SPaul Zimmerman } 3215197ba5f4SPaul Zimmerman } 3216197ba5f4SPaul Zimmerman 3217197ba5f4SPaul Zimmerman static void dwc2_conn_id_status_change(struct work_struct *work) 3218197ba5f4SPaul Zimmerman { 3219197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 3220197ba5f4SPaul Zimmerman wf_otg); 3221197ba5f4SPaul Zimmerman u32 count = 0; 3222197ba5f4SPaul Zimmerman u32 gotgctl; 32235390d438SMian Yousaf Kaukab unsigned long flags; 3224197ba5f4SPaul Zimmerman 3225197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "%s()\n", __func__); 3226197ba5f4SPaul Zimmerman 322795c8bc36SAntti Seppälä gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 3228197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl); 3229197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n", 3230197ba5f4SPaul Zimmerman !!(gotgctl & GOTGCTL_CONID_B)); 3231197ba5f4SPaul Zimmerman 3232197ba5f4SPaul Zimmerman /* B-Device connector (Device Mode) */ 3233197ba5f4SPaul Zimmerman if (gotgctl & GOTGCTL_CONID_B) { 3234197ba5f4SPaul Zimmerman /* Wait for switch to device mode */ 3235197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "connId B\n"); 3236*9156a7efSChen Yu if (hsotg->bus_suspended) { 3237*9156a7efSChen Yu dev_info(hsotg->dev, 3238*9156a7efSChen Yu "Do port resume before switching to device mode\n"); 3239*9156a7efSChen Yu dwc2_port_resume(hsotg); 3240*9156a7efSChen Yu } 3241197ba5f4SPaul Zimmerman while (!dwc2_is_device_mode(hsotg)) { 3242197ba5f4SPaul Zimmerman dev_info(hsotg->dev, 3243197ba5f4SPaul Zimmerman "Waiting for Peripheral Mode, Mode=%s\n", 3244197ba5f4SPaul Zimmerman dwc2_is_host_mode(hsotg) ? "Host" : 3245197ba5f4SPaul Zimmerman "Peripheral"); 324604a9db79SNicholas Mc Guire msleep(20); 3247fc30c4bbSJohn Stultz /* 3248fc30c4bbSJohn Stultz * Sometimes the initial GOTGCTRL read is wrong, so 3249fc30c4bbSJohn Stultz * check it again and jump to host mode if that was 3250fc30c4bbSJohn Stultz * the case. 3251fc30c4bbSJohn Stultz */ 3252fc30c4bbSJohn Stultz gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 3253fc30c4bbSJohn Stultz if (!(gotgctl & GOTGCTL_CONID_B)) 3254fc30c4bbSJohn Stultz goto host; 3255197ba5f4SPaul Zimmerman if (++count > 250) 3256197ba5f4SPaul Zimmerman break; 3257197ba5f4SPaul Zimmerman } 3258197ba5f4SPaul Zimmerman if (count > 250) 3259197ba5f4SPaul Zimmerman dev_err(hsotg->dev, 3260197ba5f4SPaul Zimmerman "Connection id status change timed out\n"); 3261197ba5f4SPaul Zimmerman hsotg->op_state = OTG_STATE_B_PERIPHERAL; 32620fe239bcSDouglas Anderson dwc2_core_init(hsotg, false); 3263197ba5f4SPaul Zimmerman dwc2_enable_global_interrupts(hsotg); 32645390d438SMian Yousaf Kaukab spin_lock_irqsave(&hsotg->lock, flags); 32651f91b4ccSFelipe Balbi dwc2_hsotg_core_init_disconnected(hsotg, false); 32665390d438SMian Yousaf Kaukab spin_unlock_irqrestore(&hsotg->lock, flags); 32671f91b4ccSFelipe Balbi dwc2_hsotg_core_connect(hsotg); 3268197ba5f4SPaul Zimmerman } else { 3269fc30c4bbSJohn Stultz host: 3270197ba5f4SPaul Zimmerman /* A-Device connector (Host Mode) */ 3271197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "connId A\n"); 3272197ba5f4SPaul Zimmerman while (!dwc2_is_host_mode(hsotg)) { 3273197ba5f4SPaul Zimmerman dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n", 3274197ba5f4SPaul Zimmerman dwc2_is_host_mode(hsotg) ? 3275197ba5f4SPaul Zimmerman "Host" : "Peripheral"); 327604a9db79SNicholas Mc Guire msleep(20); 3277197ba5f4SPaul Zimmerman if (++count > 250) 3278197ba5f4SPaul Zimmerman break; 3279197ba5f4SPaul Zimmerman } 3280197ba5f4SPaul Zimmerman if (count > 250) 3281197ba5f4SPaul Zimmerman dev_err(hsotg->dev, 3282197ba5f4SPaul Zimmerman "Connection id status change timed out\n"); 3283197ba5f4SPaul Zimmerman hsotg->op_state = OTG_STATE_A_HOST; 3284197ba5f4SPaul Zimmerman 3285197ba5f4SPaul Zimmerman /* Initialize the Core for Host mode */ 32860fe239bcSDouglas Anderson dwc2_core_init(hsotg, false); 3287197ba5f4SPaul Zimmerman dwc2_enable_global_interrupts(hsotg); 3288197ba5f4SPaul Zimmerman dwc2_hcd_start(hsotg); 3289197ba5f4SPaul Zimmerman } 3290197ba5f4SPaul Zimmerman } 3291197ba5f4SPaul Zimmerman 3292197ba5f4SPaul Zimmerman static void dwc2_wakeup_detected(unsigned long data) 3293197ba5f4SPaul Zimmerman { 3294197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data; 3295197ba5f4SPaul Zimmerman u32 hprt0; 3296197ba5f4SPaul Zimmerman 3297197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "%s()\n", __func__); 3298197ba5f4SPaul Zimmerman 3299197ba5f4SPaul Zimmerman /* 3300197ba5f4SPaul Zimmerman * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms 3301197ba5f4SPaul Zimmerman * so that OPT tests pass with all PHYs.) 3302197ba5f4SPaul Zimmerman */ 3303197ba5f4SPaul Zimmerman hprt0 = dwc2_read_hprt0(hsotg); 3304197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0); 3305197ba5f4SPaul Zimmerman hprt0 &= ~HPRT0_RES; 330695c8bc36SAntti Seppälä dwc2_writel(hprt0, hsotg->regs + HPRT0); 3307197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n", 330895c8bc36SAntti Seppälä dwc2_readl(hsotg->regs + HPRT0)); 3309197ba5f4SPaul Zimmerman 3310197ba5f4SPaul Zimmerman dwc2_hcd_rem_wakeup(hsotg); 3311fdb09b3eSNicholas Mc Guire hsotg->bus_suspended = false; 3312197ba5f4SPaul Zimmerman 3313197ba5f4SPaul Zimmerman /* Change to L0 state */ 3314197ba5f4SPaul Zimmerman hsotg->lx_state = DWC2_L0; 3315197ba5f4SPaul Zimmerman } 3316197ba5f4SPaul Zimmerman 3317197ba5f4SPaul Zimmerman static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg) 3318197ba5f4SPaul Zimmerman { 3319197ba5f4SPaul Zimmerman struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 3320197ba5f4SPaul Zimmerman 3321197ba5f4SPaul Zimmerman return hcd->self.b_hnp_enable; 3322197ba5f4SPaul Zimmerman } 3323197ba5f4SPaul Zimmerman 3324197ba5f4SPaul Zimmerman /* Must NOT be called with interrupt disabled or spinlock held */ 3325197ba5f4SPaul Zimmerman static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) 3326197ba5f4SPaul Zimmerman { 3327197ba5f4SPaul Zimmerman unsigned long flags; 3328197ba5f4SPaul Zimmerman u32 hprt0; 3329197ba5f4SPaul Zimmerman u32 pcgctl; 3330197ba5f4SPaul Zimmerman u32 gotgctl; 3331197ba5f4SPaul Zimmerman 3332197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "%s()\n", __func__); 3333197ba5f4SPaul Zimmerman 3334197ba5f4SPaul Zimmerman spin_lock_irqsave(&hsotg->lock, flags); 3335197ba5f4SPaul Zimmerman 3336197ba5f4SPaul Zimmerman if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) { 333795c8bc36SAntti Seppälä gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 3338197ba5f4SPaul Zimmerman gotgctl |= GOTGCTL_HSTSETHNPEN; 333995c8bc36SAntti Seppälä dwc2_writel(gotgctl, hsotg->regs + GOTGCTL); 3340197ba5f4SPaul Zimmerman hsotg->op_state = OTG_STATE_A_SUSPEND; 3341197ba5f4SPaul Zimmerman } 3342197ba5f4SPaul Zimmerman 3343197ba5f4SPaul Zimmerman hprt0 = dwc2_read_hprt0(hsotg); 3344197ba5f4SPaul Zimmerman hprt0 |= HPRT0_SUSP; 334595c8bc36SAntti Seppälä dwc2_writel(hprt0, hsotg->regs + HPRT0); 3346197ba5f4SPaul Zimmerman 3347fdb09b3eSNicholas Mc Guire hsotg->bus_suspended = true; 3348197ba5f4SPaul Zimmerman 3349a2a23d3fSGregory Herrero /* 3350a2a23d3fSGregory Herrero * If hibernation is supported, Phy clock will be suspended 3351a2a23d3fSGregory Herrero * after registers are backuped. 3352a2a23d3fSGregory Herrero */ 3353bea8e86cSJohn Youn if (!hsotg->params.hibernation) { 3354197ba5f4SPaul Zimmerman /* Suspend the Phy Clock */ 335595c8bc36SAntti Seppälä pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 3356197ba5f4SPaul Zimmerman pcgctl |= PCGCTL_STOPPCLK; 335795c8bc36SAntti Seppälä dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 3358197ba5f4SPaul Zimmerman udelay(10); 3359a2a23d3fSGregory Herrero } 3360197ba5f4SPaul Zimmerman 3361197ba5f4SPaul Zimmerman /* For HNP the bus must be suspended for at least 200ms */ 3362197ba5f4SPaul Zimmerman if (dwc2_host_is_b_hnp_enabled(hsotg)) { 336395c8bc36SAntti Seppälä pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 3364197ba5f4SPaul Zimmerman pcgctl &= ~PCGCTL_STOPPCLK; 336595c8bc36SAntti Seppälä dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 3366197ba5f4SPaul Zimmerman 3367197ba5f4SPaul Zimmerman spin_unlock_irqrestore(&hsotg->lock, flags); 3368197ba5f4SPaul Zimmerman 336904a9db79SNicholas Mc Guire msleep(200); 3370197ba5f4SPaul Zimmerman } else { 3371197ba5f4SPaul Zimmerman spin_unlock_irqrestore(&hsotg->lock, flags); 3372197ba5f4SPaul Zimmerman } 3373197ba5f4SPaul Zimmerman } 3374197ba5f4SPaul Zimmerman 337530db103cSGregory Herrero /* Must NOT be called with interrupt disabled or spinlock held */ 337630db103cSGregory Herrero static void dwc2_port_resume(struct dwc2_hsotg *hsotg) 337730db103cSGregory Herrero { 337830db103cSGregory Herrero unsigned long flags; 337930db103cSGregory Herrero u32 hprt0; 338030db103cSGregory Herrero u32 pcgctl; 338130db103cSGregory Herrero 33824d273c2aSDouglas Anderson spin_lock_irqsave(&hsotg->lock, flags); 33834d273c2aSDouglas Anderson 3384a2a23d3fSGregory Herrero /* 3385a2a23d3fSGregory Herrero * If hibernation is supported, Phy clock is already resumed 3386a2a23d3fSGregory Herrero * after registers restore. 3387a2a23d3fSGregory Herrero */ 3388bea8e86cSJohn Youn if (!hsotg->params.hibernation) { 338930db103cSGregory Herrero pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 339030db103cSGregory Herrero pcgctl &= ~PCGCTL_STOPPCLK; 339130db103cSGregory Herrero dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 33924d273c2aSDouglas Anderson spin_unlock_irqrestore(&hsotg->lock, flags); 339304a9db79SNicholas Mc Guire msleep(20); 33944d273c2aSDouglas Anderson spin_lock_irqsave(&hsotg->lock, flags); 3395a2a23d3fSGregory Herrero } 339630db103cSGregory Herrero 339730db103cSGregory Herrero hprt0 = dwc2_read_hprt0(hsotg); 339830db103cSGregory Herrero hprt0 |= HPRT0_RES; 339930db103cSGregory Herrero hprt0 &= ~HPRT0_SUSP; 340030db103cSGregory Herrero dwc2_writel(hprt0, hsotg->regs + HPRT0); 340130db103cSGregory Herrero spin_unlock_irqrestore(&hsotg->lock, flags); 340230db103cSGregory Herrero 340330db103cSGregory Herrero msleep(USB_RESUME_TIMEOUT); 340430db103cSGregory Herrero 340530db103cSGregory Herrero spin_lock_irqsave(&hsotg->lock, flags); 340630db103cSGregory Herrero hprt0 = dwc2_read_hprt0(hsotg); 340730db103cSGregory Herrero hprt0 &= ~(HPRT0_RES | HPRT0_SUSP); 340830db103cSGregory Herrero dwc2_writel(hprt0, hsotg->regs + HPRT0); 3409fdb09b3eSNicholas Mc Guire hsotg->bus_suspended = false; 341030db103cSGregory Herrero spin_unlock_irqrestore(&hsotg->lock, flags); 341130db103cSGregory Herrero } 341230db103cSGregory Herrero 3413197ba5f4SPaul Zimmerman /* Handles hub class-specific requests */ 3414197ba5f4SPaul Zimmerman static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, 3415197ba5f4SPaul Zimmerman u16 wvalue, u16 windex, char *buf, u16 wlength) 3416197ba5f4SPaul Zimmerman { 3417197ba5f4SPaul Zimmerman struct usb_hub_descriptor *hub_desc; 3418197ba5f4SPaul Zimmerman int retval = 0; 3419197ba5f4SPaul Zimmerman u32 hprt0; 3420197ba5f4SPaul Zimmerman u32 port_status; 3421197ba5f4SPaul Zimmerman u32 speed; 3422197ba5f4SPaul Zimmerman u32 pcgctl; 3423197ba5f4SPaul Zimmerman 3424197ba5f4SPaul Zimmerman switch (typereq) { 3425197ba5f4SPaul Zimmerman case ClearHubFeature: 3426197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue); 3427197ba5f4SPaul Zimmerman 3428197ba5f4SPaul Zimmerman switch (wvalue) { 3429197ba5f4SPaul Zimmerman case C_HUB_LOCAL_POWER: 3430197ba5f4SPaul Zimmerman case C_HUB_OVER_CURRENT: 3431197ba5f4SPaul Zimmerman /* Nothing required here */ 3432197ba5f4SPaul Zimmerman break; 3433197ba5f4SPaul Zimmerman 3434197ba5f4SPaul Zimmerman default: 3435197ba5f4SPaul Zimmerman retval = -EINVAL; 3436197ba5f4SPaul Zimmerman dev_err(hsotg->dev, 3437197ba5f4SPaul Zimmerman "ClearHubFeature request %1xh unknown\n", 3438197ba5f4SPaul Zimmerman wvalue); 3439197ba5f4SPaul Zimmerman } 3440197ba5f4SPaul Zimmerman break; 3441197ba5f4SPaul Zimmerman 3442197ba5f4SPaul Zimmerman case ClearPortFeature: 3443197ba5f4SPaul Zimmerman if (wvalue != USB_PORT_FEAT_L1) 3444197ba5f4SPaul Zimmerman if (!windex || windex > 1) 3445197ba5f4SPaul Zimmerman goto error; 3446197ba5f4SPaul Zimmerman switch (wvalue) { 3447197ba5f4SPaul Zimmerman case USB_PORT_FEAT_ENABLE: 3448197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 3449197ba5f4SPaul Zimmerman "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); 3450197ba5f4SPaul Zimmerman hprt0 = dwc2_read_hprt0(hsotg); 3451197ba5f4SPaul Zimmerman hprt0 |= HPRT0_ENA; 345295c8bc36SAntti Seppälä dwc2_writel(hprt0, hsotg->regs + HPRT0); 3453197ba5f4SPaul Zimmerman break; 3454197ba5f4SPaul Zimmerman 3455197ba5f4SPaul Zimmerman case USB_PORT_FEAT_SUSPEND: 3456197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 3457197ba5f4SPaul Zimmerman "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); 3458b0bb9bb6SPaul Zimmerman 3459bea78555SGregory Herrero if (hsotg->bus_suspended) 346030db103cSGregory Herrero dwc2_port_resume(hsotg); 3461197ba5f4SPaul Zimmerman break; 3462197ba5f4SPaul Zimmerman 3463197ba5f4SPaul Zimmerman case USB_PORT_FEAT_POWER: 3464197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 3465197ba5f4SPaul Zimmerman "ClearPortFeature USB_PORT_FEAT_POWER\n"); 3466197ba5f4SPaul Zimmerman hprt0 = dwc2_read_hprt0(hsotg); 3467197ba5f4SPaul Zimmerman hprt0 &= ~HPRT0_PWR; 346895c8bc36SAntti Seppälä dwc2_writel(hprt0, hsotg->regs + HPRT0); 3469197ba5f4SPaul Zimmerman break; 3470197ba5f4SPaul Zimmerman 3471197ba5f4SPaul Zimmerman case USB_PORT_FEAT_INDICATOR: 3472197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 3473197ba5f4SPaul Zimmerman "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); 3474197ba5f4SPaul Zimmerman /* Port indicator not supported */ 3475197ba5f4SPaul Zimmerman break; 3476197ba5f4SPaul Zimmerman 3477197ba5f4SPaul Zimmerman case USB_PORT_FEAT_C_CONNECTION: 3478197ba5f4SPaul Zimmerman /* 3479197ba5f4SPaul Zimmerman * Clears driver's internal Connect Status Change flag 3480197ba5f4SPaul Zimmerman */ 3481197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 3482197ba5f4SPaul Zimmerman "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); 3483197ba5f4SPaul Zimmerman hsotg->flags.b.port_connect_status_change = 0; 3484197ba5f4SPaul Zimmerman break; 3485197ba5f4SPaul Zimmerman 3486197ba5f4SPaul Zimmerman case USB_PORT_FEAT_C_RESET: 3487197ba5f4SPaul Zimmerman /* Clears driver's internal Port Reset Change flag */ 3488197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 3489197ba5f4SPaul Zimmerman "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); 3490197ba5f4SPaul Zimmerman hsotg->flags.b.port_reset_change = 0; 3491197ba5f4SPaul Zimmerman break; 3492197ba5f4SPaul Zimmerman 3493197ba5f4SPaul Zimmerman case USB_PORT_FEAT_C_ENABLE: 3494197ba5f4SPaul Zimmerman /* 3495197ba5f4SPaul Zimmerman * Clears the driver's internal Port Enable/Disable 3496197ba5f4SPaul Zimmerman * Change flag 3497197ba5f4SPaul Zimmerman */ 3498197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 3499197ba5f4SPaul Zimmerman "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); 3500197ba5f4SPaul Zimmerman hsotg->flags.b.port_enable_change = 0; 3501197ba5f4SPaul Zimmerman break; 3502197ba5f4SPaul Zimmerman 3503197ba5f4SPaul Zimmerman case USB_PORT_FEAT_C_SUSPEND: 3504197ba5f4SPaul Zimmerman /* 3505197ba5f4SPaul Zimmerman * Clears the driver's internal Port Suspend Change 3506197ba5f4SPaul Zimmerman * flag, which is set when resume signaling on the host 3507197ba5f4SPaul Zimmerman * port is complete 3508197ba5f4SPaul Zimmerman */ 3509197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 3510197ba5f4SPaul Zimmerman "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); 3511197ba5f4SPaul Zimmerman hsotg->flags.b.port_suspend_change = 0; 3512197ba5f4SPaul Zimmerman break; 3513197ba5f4SPaul Zimmerman 3514197ba5f4SPaul Zimmerman case USB_PORT_FEAT_C_PORT_L1: 3515197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 3516197ba5f4SPaul Zimmerman "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n"); 3517197ba5f4SPaul Zimmerman hsotg->flags.b.port_l1_change = 0; 3518197ba5f4SPaul Zimmerman break; 3519197ba5f4SPaul Zimmerman 3520197ba5f4SPaul Zimmerman case USB_PORT_FEAT_C_OVER_CURRENT: 3521197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 3522197ba5f4SPaul Zimmerman "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); 3523197ba5f4SPaul Zimmerman hsotg->flags.b.port_over_current_change = 0; 3524197ba5f4SPaul Zimmerman break; 3525197ba5f4SPaul Zimmerman 3526197ba5f4SPaul Zimmerman default: 3527197ba5f4SPaul Zimmerman retval = -EINVAL; 3528197ba5f4SPaul Zimmerman dev_err(hsotg->dev, 3529197ba5f4SPaul Zimmerman "ClearPortFeature request %1xh unknown or unsupported\n", 3530197ba5f4SPaul Zimmerman wvalue); 3531197ba5f4SPaul Zimmerman } 3532197ba5f4SPaul Zimmerman break; 3533197ba5f4SPaul Zimmerman 3534197ba5f4SPaul Zimmerman case GetHubDescriptor: 3535197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "GetHubDescriptor\n"); 3536197ba5f4SPaul Zimmerman hub_desc = (struct usb_hub_descriptor *)buf; 3537197ba5f4SPaul Zimmerman hub_desc->bDescLength = 9; 3538a5dd0395SSergei Shtylyov hub_desc->bDescriptorType = USB_DT_HUB; 3539197ba5f4SPaul Zimmerman hub_desc->bNbrPorts = 1; 35403d040de8SSergei Shtylyov hub_desc->wHubCharacteristics = 35413d040de8SSergei Shtylyov cpu_to_le16(HUB_CHAR_COMMON_LPSM | 35423d040de8SSergei Shtylyov HUB_CHAR_INDV_PORT_OCPM); 3543197ba5f4SPaul Zimmerman hub_desc->bPwrOn2PwrGood = 1; 3544197ba5f4SPaul Zimmerman hub_desc->bHubContrCurrent = 0; 3545197ba5f4SPaul Zimmerman hub_desc->u.hs.DeviceRemovable[0] = 0; 3546197ba5f4SPaul Zimmerman hub_desc->u.hs.DeviceRemovable[1] = 0xff; 3547197ba5f4SPaul Zimmerman break; 3548197ba5f4SPaul Zimmerman 3549197ba5f4SPaul Zimmerman case GetHubStatus: 3550197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "GetHubStatus\n"); 3551197ba5f4SPaul Zimmerman memset(buf, 0, 4); 3552197ba5f4SPaul Zimmerman break; 3553197ba5f4SPaul Zimmerman 3554197ba5f4SPaul Zimmerman case GetPortStatus: 3555197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, 3556197ba5f4SPaul Zimmerman "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex, 3557197ba5f4SPaul Zimmerman hsotg->flags.d32); 3558197ba5f4SPaul Zimmerman if (!windex || windex > 1) 3559197ba5f4SPaul Zimmerman goto error; 3560197ba5f4SPaul Zimmerman 3561197ba5f4SPaul Zimmerman port_status = 0; 3562197ba5f4SPaul Zimmerman if (hsotg->flags.b.port_connect_status_change) 3563197ba5f4SPaul Zimmerman port_status |= USB_PORT_STAT_C_CONNECTION << 16; 3564197ba5f4SPaul Zimmerman if (hsotg->flags.b.port_enable_change) 3565197ba5f4SPaul Zimmerman port_status |= USB_PORT_STAT_C_ENABLE << 16; 3566197ba5f4SPaul Zimmerman if (hsotg->flags.b.port_suspend_change) 3567197ba5f4SPaul Zimmerman port_status |= USB_PORT_STAT_C_SUSPEND << 16; 3568197ba5f4SPaul Zimmerman if (hsotg->flags.b.port_l1_change) 3569197ba5f4SPaul Zimmerman port_status |= USB_PORT_STAT_C_L1 << 16; 3570197ba5f4SPaul Zimmerman if (hsotg->flags.b.port_reset_change) 3571197ba5f4SPaul Zimmerman port_status |= USB_PORT_STAT_C_RESET << 16; 3572197ba5f4SPaul Zimmerman if (hsotg->flags.b.port_over_current_change) { 3573197ba5f4SPaul Zimmerman dev_warn(hsotg->dev, "Overcurrent change detected\n"); 3574197ba5f4SPaul Zimmerman port_status |= USB_PORT_STAT_C_OVERCURRENT << 16; 3575197ba5f4SPaul Zimmerman } 3576197ba5f4SPaul Zimmerman 3577197ba5f4SPaul Zimmerman if (!hsotg->flags.b.port_connect_status) { 3578197ba5f4SPaul Zimmerman /* 3579197ba5f4SPaul Zimmerman * The port is disconnected, which means the core is 3580197ba5f4SPaul Zimmerman * either in device mode or it soon will be. Just 3581197ba5f4SPaul Zimmerman * return 0's for the remainder of the port status 3582197ba5f4SPaul Zimmerman * since the port register can't be read if the core 3583197ba5f4SPaul Zimmerman * is in device mode. 3584197ba5f4SPaul Zimmerman */ 3585197ba5f4SPaul Zimmerman *(__le32 *)buf = cpu_to_le32(port_status); 3586197ba5f4SPaul Zimmerman break; 3587197ba5f4SPaul Zimmerman } 3588197ba5f4SPaul Zimmerman 358995c8bc36SAntti Seppälä hprt0 = dwc2_readl(hsotg->regs + HPRT0); 3590197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0); 3591197ba5f4SPaul Zimmerman 3592197ba5f4SPaul Zimmerman if (hprt0 & HPRT0_CONNSTS) 3593197ba5f4SPaul Zimmerman port_status |= USB_PORT_STAT_CONNECTION; 3594197ba5f4SPaul Zimmerman if (hprt0 & HPRT0_ENA) 3595197ba5f4SPaul Zimmerman port_status |= USB_PORT_STAT_ENABLE; 3596197ba5f4SPaul Zimmerman if (hprt0 & HPRT0_SUSP) 3597197ba5f4SPaul Zimmerman port_status |= USB_PORT_STAT_SUSPEND; 3598197ba5f4SPaul Zimmerman if (hprt0 & HPRT0_OVRCURRACT) 3599197ba5f4SPaul Zimmerman port_status |= USB_PORT_STAT_OVERCURRENT; 3600197ba5f4SPaul Zimmerman if (hprt0 & HPRT0_RST) 3601197ba5f4SPaul Zimmerman port_status |= USB_PORT_STAT_RESET; 3602197ba5f4SPaul Zimmerman if (hprt0 & HPRT0_PWR) 3603197ba5f4SPaul Zimmerman port_status |= USB_PORT_STAT_POWER; 3604197ba5f4SPaul Zimmerman 3605197ba5f4SPaul Zimmerman speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 3606197ba5f4SPaul Zimmerman if (speed == HPRT0_SPD_HIGH_SPEED) 3607197ba5f4SPaul Zimmerman port_status |= USB_PORT_STAT_HIGH_SPEED; 3608197ba5f4SPaul Zimmerman else if (speed == HPRT0_SPD_LOW_SPEED) 3609197ba5f4SPaul Zimmerman port_status |= USB_PORT_STAT_LOW_SPEED; 3610197ba5f4SPaul Zimmerman 3611197ba5f4SPaul Zimmerman if (hprt0 & HPRT0_TSTCTL_MASK) 3612197ba5f4SPaul Zimmerman port_status |= USB_PORT_STAT_TEST; 3613197ba5f4SPaul Zimmerman /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ 3614197ba5f4SPaul Zimmerman 3615bea8e86cSJohn Youn if (hsotg->params.dma_desc_fs_enable) { 3616fbb9e22bSMian Yousaf Kaukab /* 3617fbb9e22bSMian Yousaf Kaukab * Enable descriptor DMA only if a full speed 3618fbb9e22bSMian Yousaf Kaukab * device is connected. 3619fbb9e22bSMian Yousaf Kaukab */ 3620fbb9e22bSMian Yousaf Kaukab if (hsotg->new_connection && 3621fbb9e22bSMian Yousaf Kaukab ((port_status & 3622fbb9e22bSMian Yousaf Kaukab (USB_PORT_STAT_CONNECTION | 3623fbb9e22bSMian Yousaf Kaukab USB_PORT_STAT_HIGH_SPEED | 3624fbb9e22bSMian Yousaf Kaukab USB_PORT_STAT_LOW_SPEED)) == 3625fbb9e22bSMian Yousaf Kaukab USB_PORT_STAT_CONNECTION)) { 3626fbb9e22bSMian Yousaf Kaukab u32 hcfg; 3627fbb9e22bSMian Yousaf Kaukab 3628fbb9e22bSMian Yousaf Kaukab dev_info(hsotg->dev, "Enabling descriptor DMA mode\n"); 362995832c00SJohn Youn hsotg->params.dma_desc_enable = true; 3630fbb9e22bSMian Yousaf Kaukab hcfg = dwc2_readl(hsotg->regs + HCFG); 3631fbb9e22bSMian Yousaf Kaukab hcfg |= HCFG_DESCDMA; 3632fbb9e22bSMian Yousaf Kaukab dwc2_writel(hcfg, hsotg->regs + HCFG); 3633fbb9e22bSMian Yousaf Kaukab hsotg->new_connection = false; 3634fbb9e22bSMian Yousaf Kaukab } 3635fbb9e22bSMian Yousaf Kaukab } 3636fbb9e22bSMian Yousaf Kaukab 3637197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status); 3638197ba5f4SPaul Zimmerman *(__le32 *)buf = cpu_to_le32(port_status); 3639197ba5f4SPaul Zimmerman break; 3640197ba5f4SPaul Zimmerman 3641197ba5f4SPaul Zimmerman case SetHubFeature: 3642197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "SetHubFeature\n"); 3643197ba5f4SPaul Zimmerman /* No HUB features supported */ 3644197ba5f4SPaul Zimmerman break; 3645197ba5f4SPaul Zimmerman 3646197ba5f4SPaul Zimmerman case SetPortFeature: 3647197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "SetPortFeature\n"); 3648197ba5f4SPaul Zimmerman if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1)) 3649197ba5f4SPaul Zimmerman goto error; 3650197ba5f4SPaul Zimmerman 3651197ba5f4SPaul Zimmerman if (!hsotg->flags.b.port_connect_status) { 3652197ba5f4SPaul Zimmerman /* 3653197ba5f4SPaul Zimmerman * The port is disconnected, which means the core is 3654197ba5f4SPaul Zimmerman * either in device mode or it soon will be. Just 3655197ba5f4SPaul Zimmerman * return without doing anything since the port 3656197ba5f4SPaul Zimmerman * register can't be written if the core is in device 3657197ba5f4SPaul Zimmerman * mode. 3658197ba5f4SPaul Zimmerman */ 3659197ba5f4SPaul Zimmerman break; 3660197ba5f4SPaul Zimmerman } 3661197ba5f4SPaul Zimmerman 3662197ba5f4SPaul Zimmerman switch (wvalue) { 3663197ba5f4SPaul Zimmerman case USB_PORT_FEAT_SUSPEND: 3664197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 3665197ba5f4SPaul Zimmerman "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); 3666197ba5f4SPaul Zimmerman if (windex != hsotg->otg_port) 3667197ba5f4SPaul Zimmerman goto error; 3668197ba5f4SPaul Zimmerman dwc2_port_suspend(hsotg, windex); 3669197ba5f4SPaul Zimmerman break; 3670197ba5f4SPaul Zimmerman 3671197ba5f4SPaul Zimmerman case USB_PORT_FEAT_POWER: 3672197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 3673197ba5f4SPaul Zimmerman "SetPortFeature - USB_PORT_FEAT_POWER\n"); 3674197ba5f4SPaul Zimmerman hprt0 = dwc2_read_hprt0(hsotg); 3675197ba5f4SPaul Zimmerman hprt0 |= HPRT0_PWR; 367695c8bc36SAntti Seppälä dwc2_writel(hprt0, hsotg->regs + HPRT0); 3677197ba5f4SPaul Zimmerman break; 3678197ba5f4SPaul Zimmerman 3679197ba5f4SPaul Zimmerman case USB_PORT_FEAT_RESET: 3680197ba5f4SPaul Zimmerman hprt0 = dwc2_read_hprt0(hsotg); 3681197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 3682197ba5f4SPaul Zimmerman "SetPortFeature - USB_PORT_FEAT_RESET\n"); 368395c8bc36SAntti Seppälä pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 3684197ba5f4SPaul Zimmerman pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK); 368595c8bc36SAntti Seppälä dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 3686197ba5f4SPaul Zimmerman /* ??? Original driver does this */ 368795c8bc36SAntti Seppälä dwc2_writel(0, hsotg->regs + PCGCTL); 3688197ba5f4SPaul Zimmerman 3689197ba5f4SPaul Zimmerman hprt0 = dwc2_read_hprt0(hsotg); 3690197ba5f4SPaul Zimmerman /* Clear suspend bit if resetting from suspend state */ 3691197ba5f4SPaul Zimmerman hprt0 &= ~HPRT0_SUSP; 3692197ba5f4SPaul Zimmerman 3693197ba5f4SPaul Zimmerman /* 3694197ba5f4SPaul Zimmerman * When B-Host the Port reset bit is set in the Start 3695197ba5f4SPaul Zimmerman * HCD Callback function, so that the reset is started 3696197ba5f4SPaul Zimmerman * within 1ms of the HNP success interrupt 3697197ba5f4SPaul Zimmerman */ 3698197ba5f4SPaul Zimmerman if (!dwc2_hcd_is_b_host(hsotg)) { 3699197ba5f4SPaul Zimmerman hprt0 |= HPRT0_PWR | HPRT0_RST; 3700197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 3701197ba5f4SPaul Zimmerman "In host mode, hprt0=%08x\n", hprt0); 370295c8bc36SAntti Seppälä dwc2_writel(hprt0, hsotg->regs + HPRT0); 3703197ba5f4SPaul Zimmerman } 3704197ba5f4SPaul Zimmerman 3705197ba5f4SPaul Zimmerman /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ 370604a9db79SNicholas Mc Guire msleep(50); 3707197ba5f4SPaul Zimmerman hprt0 &= ~HPRT0_RST; 370895c8bc36SAntti Seppälä dwc2_writel(hprt0, hsotg->regs + HPRT0); 3709197ba5f4SPaul Zimmerman hsotg->lx_state = DWC2_L0; /* Now back to On state */ 3710197ba5f4SPaul Zimmerman break; 3711197ba5f4SPaul Zimmerman 3712197ba5f4SPaul Zimmerman case USB_PORT_FEAT_INDICATOR: 3713197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 3714197ba5f4SPaul Zimmerman "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); 3715197ba5f4SPaul Zimmerman /* Not supported */ 3716197ba5f4SPaul Zimmerman break; 3717197ba5f4SPaul Zimmerman 371896d480e6SJingwu Lin case USB_PORT_FEAT_TEST: 371996d480e6SJingwu Lin hprt0 = dwc2_read_hprt0(hsotg); 372096d480e6SJingwu Lin dev_dbg(hsotg->dev, 372196d480e6SJingwu Lin "SetPortFeature - USB_PORT_FEAT_TEST\n"); 372296d480e6SJingwu Lin hprt0 &= ~HPRT0_TSTCTL_MASK; 372396d480e6SJingwu Lin hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT; 372495c8bc36SAntti Seppälä dwc2_writel(hprt0, hsotg->regs + HPRT0); 372596d480e6SJingwu Lin break; 372696d480e6SJingwu Lin 3727197ba5f4SPaul Zimmerman default: 3728197ba5f4SPaul Zimmerman retval = -EINVAL; 3729197ba5f4SPaul Zimmerman dev_err(hsotg->dev, 3730197ba5f4SPaul Zimmerman "SetPortFeature %1xh unknown or unsupported\n", 3731197ba5f4SPaul Zimmerman wvalue); 3732197ba5f4SPaul Zimmerman break; 3733197ba5f4SPaul Zimmerman } 3734197ba5f4SPaul Zimmerman break; 3735197ba5f4SPaul Zimmerman 3736197ba5f4SPaul Zimmerman default: 3737197ba5f4SPaul Zimmerman error: 3738197ba5f4SPaul Zimmerman retval = -EINVAL; 3739197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 3740197ba5f4SPaul Zimmerman "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n", 3741197ba5f4SPaul Zimmerman typereq, windex, wvalue); 3742197ba5f4SPaul Zimmerman break; 3743197ba5f4SPaul Zimmerman } 3744197ba5f4SPaul Zimmerman 3745197ba5f4SPaul Zimmerman return retval; 3746197ba5f4SPaul Zimmerman } 3747197ba5f4SPaul Zimmerman 3748197ba5f4SPaul Zimmerman static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port) 3749197ba5f4SPaul Zimmerman { 3750197ba5f4SPaul Zimmerman int retval; 3751197ba5f4SPaul Zimmerman 3752197ba5f4SPaul Zimmerman if (port != 1) 3753197ba5f4SPaul Zimmerman return -EINVAL; 3754197ba5f4SPaul Zimmerman 3755197ba5f4SPaul Zimmerman retval = (hsotg->flags.b.port_connect_status_change || 3756197ba5f4SPaul Zimmerman hsotg->flags.b.port_reset_change || 3757197ba5f4SPaul Zimmerman hsotg->flags.b.port_enable_change || 3758197ba5f4SPaul Zimmerman hsotg->flags.b.port_suspend_change || 3759197ba5f4SPaul Zimmerman hsotg->flags.b.port_over_current_change); 3760197ba5f4SPaul Zimmerman 3761197ba5f4SPaul Zimmerman if (retval) { 3762197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 3763197ba5f4SPaul Zimmerman "DWC OTG HCD HUB STATUS DATA: Root port status changed\n"); 3764197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " port_connect_status_change: %d\n", 3765197ba5f4SPaul Zimmerman hsotg->flags.b.port_connect_status_change); 3766197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " port_reset_change: %d\n", 3767197ba5f4SPaul Zimmerman hsotg->flags.b.port_reset_change); 3768197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " port_enable_change: %d\n", 3769197ba5f4SPaul Zimmerman hsotg->flags.b.port_enable_change); 3770197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " port_suspend_change: %d\n", 3771197ba5f4SPaul Zimmerman hsotg->flags.b.port_suspend_change); 3772197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " port_over_current_change: %d\n", 3773197ba5f4SPaul Zimmerman hsotg->flags.b.port_over_current_change); 3774197ba5f4SPaul Zimmerman } 3775197ba5f4SPaul Zimmerman 3776197ba5f4SPaul Zimmerman return retval; 3777197ba5f4SPaul Zimmerman } 3778197ba5f4SPaul Zimmerman 3779197ba5f4SPaul Zimmerman int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 3780197ba5f4SPaul Zimmerman { 378195c8bc36SAntti Seppälä u32 hfnum = dwc2_readl(hsotg->regs + HFNUM); 3782197ba5f4SPaul Zimmerman 3783197ba5f4SPaul Zimmerman #ifdef DWC2_DEBUG_SOF 3784197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n", 3785197ba5f4SPaul Zimmerman (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT); 3786197ba5f4SPaul Zimmerman #endif 3787197ba5f4SPaul Zimmerman return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 3788197ba5f4SPaul Zimmerman } 3789197ba5f4SPaul Zimmerman 3790fae4e826SDouglas Anderson int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us) 3791fae4e826SDouglas Anderson { 3792fae4e826SDouglas Anderson u32 hprt = dwc2_readl(hsotg->regs + HPRT0); 3793fae4e826SDouglas Anderson u32 hfir = dwc2_readl(hsotg->regs + HFIR); 3794fae4e826SDouglas Anderson u32 hfnum = dwc2_readl(hsotg->regs + HFNUM); 3795fae4e826SDouglas Anderson unsigned int us_per_frame; 3796fae4e826SDouglas Anderson unsigned int frame_number; 3797fae4e826SDouglas Anderson unsigned int remaining; 3798fae4e826SDouglas Anderson unsigned int interval; 3799fae4e826SDouglas Anderson unsigned int phy_clks; 3800fae4e826SDouglas Anderson 3801fae4e826SDouglas Anderson /* High speed has 125 us per (micro) frame; others are 1 ms per */ 3802fae4e826SDouglas Anderson us_per_frame = (hprt & HPRT0_SPD_MASK) ? 1000 : 125; 3803fae4e826SDouglas Anderson 3804fae4e826SDouglas Anderson /* Extract fields */ 3805fae4e826SDouglas Anderson frame_number = (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 3806fae4e826SDouglas Anderson remaining = (hfnum & HFNUM_FRREM_MASK) >> HFNUM_FRREM_SHIFT; 3807fae4e826SDouglas Anderson interval = (hfir & HFIR_FRINT_MASK) >> HFIR_FRINT_SHIFT; 3808fae4e826SDouglas Anderson 3809fae4e826SDouglas Anderson /* 3810fae4e826SDouglas Anderson * Number of phy clocks since the last tick of the frame number after 3811fae4e826SDouglas Anderson * "us" has passed. 3812fae4e826SDouglas Anderson */ 3813fae4e826SDouglas Anderson phy_clks = (interval - remaining) + 3814fae4e826SDouglas Anderson DIV_ROUND_UP(interval * us, us_per_frame); 3815fae4e826SDouglas Anderson 3816fae4e826SDouglas Anderson return dwc2_frame_num_inc(frame_number, phy_clks / interval); 3817fae4e826SDouglas Anderson } 3818fae4e826SDouglas Anderson 3819197ba5f4SPaul Zimmerman int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg) 3820197ba5f4SPaul Zimmerman { 3821197ba5f4SPaul Zimmerman return hsotg->op_state == OTG_STATE_B_HOST; 3822197ba5f4SPaul Zimmerman } 3823197ba5f4SPaul Zimmerman 3824197ba5f4SPaul Zimmerman static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg, 3825197ba5f4SPaul Zimmerman int iso_desc_count, 3826197ba5f4SPaul Zimmerman gfp_t mem_flags) 3827197ba5f4SPaul Zimmerman { 3828197ba5f4SPaul Zimmerman struct dwc2_hcd_urb *urb; 3829197ba5f4SPaul Zimmerman u32 size = sizeof(*urb) + iso_desc_count * 3830197ba5f4SPaul Zimmerman sizeof(struct dwc2_hcd_iso_packet_desc); 3831197ba5f4SPaul Zimmerman 3832197ba5f4SPaul Zimmerman urb = kzalloc(size, mem_flags); 3833197ba5f4SPaul Zimmerman if (urb) 3834197ba5f4SPaul Zimmerman urb->packet_count = iso_desc_count; 3835197ba5f4SPaul Zimmerman return urb; 3836197ba5f4SPaul Zimmerman } 3837197ba5f4SPaul Zimmerman 3838197ba5f4SPaul Zimmerman static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg, 3839197ba5f4SPaul Zimmerman struct dwc2_hcd_urb *urb, u8 dev_addr, 3840197ba5f4SPaul Zimmerman u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps) 3841197ba5f4SPaul Zimmerman { 3842197ba5f4SPaul Zimmerman if (dbg_perio() || 3843197ba5f4SPaul Zimmerman ep_type == USB_ENDPOINT_XFER_BULK || 3844197ba5f4SPaul Zimmerman ep_type == USB_ENDPOINT_XFER_CONTROL) 3845197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, 3846197ba5f4SPaul Zimmerman "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n", 3847197ba5f4SPaul Zimmerman dev_addr, ep_num, ep_dir, ep_type, mps); 3848197ba5f4SPaul Zimmerman urb->pipe_info.dev_addr = dev_addr; 3849197ba5f4SPaul Zimmerman urb->pipe_info.ep_num = ep_num; 3850197ba5f4SPaul Zimmerman urb->pipe_info.pipe_type = ep_type; 3851197ba5f4SPaul Zimmerman urb->pipe_info.pipe_dir = ep_dir; 3852197ba5f4SPaul Zimmerman urb->pipe_info.mps = mps; 3853197ba5f4SPaul Zimmerman } 3854197ba5f4SPaul Zimmerman 3855197ba5f4SPaul Zimmerman /* 3856197ba5f4SPaul Zimmerman * NOTE: This function will be removed once the peripheral controller code 3857197ba5f4SPaul Zimmerman * is integrated and the driver is stable 3858197ba5f4SPaul Zimmerman */ 3859197ba5f4SPaul Zimmerman void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg) 3860197ba5f4SPaul Zimmerman { 3861197ba5f4SPaul Zimmerman #ifdef DEBUG 3862197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan; 3863197ba5f4SPaul Zimmerman struct dwc2_hcd_urb *urb; 3864197ba5f4SPaul Zimmerman struct dwc2_qtd *qtd; 3865197ba5f4SPaul Zimmerman int num_channels; 3866197ba5f4SPaul Zimmerman u32 np_tx_status; 3867197ba5f4SPaul Zimmerman u32 p_tx_status; 3868197ba5f4SPaul Zimmerman int i; 3869197ba5f4SPaul Zimmerman 3870bea8e86cSJohn Youn num_channels = hsotg->params.host_channels; 3871197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "\n"); 3872197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 3873197ba5f4SPaul Zimmerman "************************************************************\n"); 3874197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "HCD State:\n"); 3875197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels); 3876197ba5f4SPaul Zimmerman 3877197ba5f4SPaul Zimmerman for (i = 0; i < num_channels; i++) { 3878197ba5f4SPaul Zimmerman chan = hsotg->hc_ptr_array[i]; 3879197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " Channel %d:\n", i); 3880197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 3881197ba5f4SPaul Zimmerman " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 3882197ba5f4SPaul Zimmerman chan->dev_addr, chan->ep_num, chan->ep_is_in); 3883197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " speed: %d\n", chan->speed); 3884197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 3885197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 3886197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " data_pid_start: %d\n", 3887197ba5f4SPaul Zimmerman chan->data_pid_start); 3888197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count); 3889197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " xfer_started: %d\n", 3890197ba5f4SPaul Zimmerman chan->xfer_started); 3891197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 3892197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 3893197ba5f4SPaul Zimmerman (unsigned long)chan->xfer_dma); 3894197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 3895197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count); 3896197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " halt_on_queue: %d\n", 3897197ba5f4SPaul Zimmerman chan->halt_on_queue); 3898197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " halt_pending: %d\n", 3899197ba5f4SPaul Zimmerman chan->halt_pending); 3900197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 3901197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split); 3902197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " complete_split: %d\n", 3903197ba5f4SPaul Zimmerman chan->complete_split); 3904197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr); 3905197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port); 3906197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos); 3907197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " requests: %d\n", chan->requests); 3908197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 3909197ba5f4SPaul Zimmerman 3910197ba5f4SPaul Zimmerman if (chan->xfer_started) { 3911197ba5f4SPaul Zimmerman u32 hfnum, hcchar, hctsiz, hcint, hcintmsk; 3912197ba5f4SPaul Zimmerman 391395c8bc36SAntti Seppälä hfnum = dwc2_readl(hsotg->regs + HFNUM); 391495c8bc36SAntti Seppälä hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 391595c8bc36SAntti Seppälä hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(i)); 391695c8bc36SAntti Seppälä hcint = dwc2_readl(hsotg->regs + HCINT(i)); 391795c8bc36SAntti Seppälä hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(i)); 3918197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum); 3919197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar); 3920197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz); 3921197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint); 3922197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk); 3923197ba5f4SPaul Zimmerman } 3924197ba5f4SPaul Zimmerman 3925197ba5f4SPaul Zimmerman if (!(chan->xfer_started && chan->qh)) 3926197ba5f4SPaul Zimmerman continue; 3927197ba5f4SPaul Zimmerman 3928197ba5f4SPaul Zimmerman list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) { 3929197ba5f4SPaul Zimmerman if (!qtd->in_process) 3930197ba5f4SPaul Zimmerman break; 3931197ba5f4SPaul Zimmerman urb = qtd->urb; 3932197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " URB Info:\n"); 3933197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n", 3934197ba5f4SPaul Zimmerman qtd, urb); 3935197ba5f4SPaul Zimmerman if (urb) { 3936197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 3937197ba5f4SPaul Zimmerman " Dev: %d, EP: %d %s\n", 3938197ba5f4SPaul Zimmerman dwc2_hcd_get_dev_addr(&urb->pipe_info), 3939197ba5f4SPaul Zimmerman dwc2_hcd_get_ep_num(&urb->pipe_info), 3940197ba5f4SPaul Zimmerman dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 3941197ba5f4SPaul Zimmerman "IN" : "OUT"); 3942197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 3943197ba5f4SPaul Zimmerman " Max packet size: %d\n", 3944197ba5f4SPaul Zimmerman dwc2_hcd_get_mps(&urb->pipe_info)); 3945197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 3946197ba5f4SPaul Zimmerman " transfer_buffer: %p\n", 3947197ba5f4SPaul Zimmerman urb->buf); 3948197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 3949197ba5f4SPaul Zimmerman " transfer_dma: %08lx\n", 3950197ba5f4SPaul Zimmerman (unsigned long)urb->dma); 3951197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 3952197ba5f4SPaul Zimmerman " transfer_buffer_length: %d\n", 3953197ba5f4SPaul Zimmerman urb->length); 3954197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " actual_length: %d\n", 3955197ba5f4SPaul Zimmerman urb->actual_length); 3956197ba5f4SPaul Zimmerman } 3957197ba5f4SPaul Zimmerman } 3958197ba5f4SPaul Zimmerman } 3959197ba5f4SPaul Zimmerman 3960197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " non_periodic_channels: %d\n", 3961197ba5f4SPaul Zimmerman hsotg->non_periodic_channels); 3962197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " periodic_channels: %d\n", 3963197ba5f4SPaul Zimmerman hsotg->periodic_channels); 3964197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs); 396595c8bc36SAntti Seppälä np_tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 3966197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n", 3967197ba5f4SPaul Zimmerman (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 3968197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n", 3969197ba5f4SPaul Zimmerman (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 397095c8bc36SAntti Seppälä p_tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 3971197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n", 3972197ba5f4SPaul Zimmerman (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 3973197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n", 3974197ba5f4SPaul Zimmerman (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 3975197ba5f4SPaul Zimmerman dwc2_hcd_dump_frrem(hsotg); 3976197ba5f4SPaul Zimmerman dwc2_dump_global_registers(hsotg); 3977197ba5f4SPaul Zimmerman dwc2_dump_host_registers(hsotg); 3978197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 3979197ba5f4SPaul Zimmerman "************************************************************\n"); 3980197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "\n"); 3981197ba5f4SPaul Zimmerman #endif 3982197ba5f4SPaul Zimmerman } 3983197ba5f4SPaul Zimmerman 3984197ba5f4SPaul Zimmerman /* 3985197ba5f4SPaul Zimmerman * NOTE: This function will be removed once the peripheral controller code 3986197ba5f4SPaul Zimmerman * is integrated and the driver is stable 3987197ba5f4SPaul Zimmerman */ 3988197ba5f4SPaul Zimmerman void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg) 3989197ba5f4SPaul Zimmerman { 3990197ba5f4SPaul Zimmerman #ifdef DWC2_DUMP_FRREM 3991197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "Frame remaining at SOF:\n"); 3992197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 3993197ba5f4SPaul Zimmerman hsotg->frrem_samples, hsotg->frrem_accum, 3994197ba5f4SPaul Zimmerman hsotg->frrem_samples > 0 ? 3995197ba5f4SPaul Zimmerman hsotg->frrem_accum / hsotg->frrem_samples : 0); 3996197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "\n"); 3997197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n"); 3998197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 3999197ba5f4SPaul Zimmerman hsotg->hfnum_7_samples, 4000197ba5f4SPaul Zimmerman hsotg->hfnum_7_frrem_accum, 4001197ba5f4SPaul Zimmerman hsotg->hfnum_7_samples > 0 ? 4002197ba5f4SPaul Zimmerman hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0); 4003197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n"); 4004197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4005197ba5f4SPaul Zimmerman hsotg->hfnum_0_samples, 4006197ba5f4SPaul Zimmerman hsotg->hfnum_0_frrem_accum, 4007197ba5f4SPaul Zimmerman hsotg->hfnum_0_samples > 0 ? 4008197ba5f4SPaul Zimmerman hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0); 4009197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n"); 4010197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4011197ba5f4SPaul Zimmerman hsotg->hfnum_other_samples, 4012197ba5f4SPaul Zimmerman hsotg->hfnum_other_frrem_accum, 4013197ba5f4SPaul Zimmerman hsotg->hfnum_other_samples > 0 ? 4014197ba5f4SPaul Zimmerman hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples : 4015197ba5f4SPaul Zimmerman 0); 4016197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "\n"); 4017197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n"); 4018197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4019197ba5f4SPaul Zimmerman hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a, 4020197ba5f4SPaul Zimmerman hsotg->hfnum_7_samples_a > 0 ? 4021197ba5f4SPaul Zimmerman hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0); 4022197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n"); 4023197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4024197ba5f4SPaul Zimmerman hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a, 4025197ba5f4SPaul Zimmerman hsotg->hfnum_0_samples_a > 0 ? 4026197ba5f4SPaul Zimmerman hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0); 4027197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n"); 4028197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4029197ba5f4SPaul Zimmerman hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a, 4030197ba5f4SPaul Zimmerman hsotg->hfnum_other_samples_a > 0 ? 4031197ba5f4SPaul Zimmerman hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a 4032197ba5f4SPaul Zimmerman : 0); 4033197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "\n"); 4034197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n"); 4035197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4036197ba5f4SPaul Zimmerman hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b, 4037197ba5f4SPaul Zimmerman hsotg->hfnum_7_samples_b > 0 ? 4038197ba5f4SPaul Zimmerman hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0); 4039197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n"); 4040197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4041197ba5f4SPaul Zimmerman hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b, 4042197ba5f4SPaul Zimmerman (hsotg->hfnum_0_samples_b > 0) ? 4043197ba5f4SPaul Zimmerman hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0); 4044197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n"); 4045197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4046197ba5f4SPaul Zimmerman hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b, 4047197ba5f4SPaul Zimmerman (hsotg->hfnum_other_samples_b > 0) ? 4048197ba5f4SPaul Zimmerman hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b 4049197ba5f4SPaul Zimmerman : 0); 4050197ba5f4SPaul Zimmerman #endif 4051197ba5f4SPaul Zimmerman } 4052197ba5f4SPaul Zimmerman 4053197ba5f4SPaul Zimmerman struct wrapper_priv_data { 4054197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg; 4055197ba5f4SPaul Zimmerman }; 4056197ba5f4SPaul Zimmerman 4057197ba5f4SPaul Zimmerman /* Gets the dwc2_hsotg from a usb_hcd */ 4058197ba5f4SPaul Zimmerman static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd) 4059197ba5f4SPaul Zimmerman { 4060197ba5f4SPaul Zimmerman struct wrapper_priv_data *p; 4061197ba5f4SPaul Zimmerman 4062197ba5f4SPaul Zimmerman p = (struct wrapper_priv_data *)&hcd->hcd_priv; 4063197ba5f4SPaul Zimmerman return p->hsotg; 4064197ba5f4SPaul Zimmerman } 4065197ba5f4SPaul Zimmerman 40669f9f09b0SDouglas Anderson /** 40679f9f09b0SDouglas Anderson * dwc2_host_get_tt_info() - Get the dwc2_tt associated with context 40689f9f09b0SDouglas Anderson * 40699f9f09b0SDouglas Anderson * This will get the dwc2_tt structure (and ttport) associated with the given 40709f9f09b0SDouglas Anderson * context (which is really just a struct urb pointer). 40719f9f09b0SDouglas Anderson * 40729f9f09b0SDouglas Anderson * The first time this is called for a given TT we allocate memory for our 40739f9f09b0SDouglas Anderson * structure. When everyone is done and has called dwc2_host_put_tt_info() 40749f9f09b0SDouglas Anderson * then the refcount for the structure will go to 0 and we'll free it. 40759f9f09b0SDouglas Anderson * 40769f9f09b0SDouglas Anderson * @hsotg: The HCD state structure for the DWC OTG controller. 40779f9f09b0SDouglas Anderson * @qh: The QH structure. 40789f9f09b0SDouglas Anderson * @context: The priv pointer from a struct dwc2_hcd_urb. 40799f9f09b0SDouglas Anderson * @mem_flags: Flags for allocating memory. 40809f9f09b0SDouglas Anderson * @ttport: We'll return this device's port number here. That's used to 40819f9f09b0SDouglas Anderson * reference into the bitmap if we're on a multi_tt hub. 40829f9f09b0SDouglas Anderson * 40839f9f09b0SDouglas Anderson * Return: a pointer to a struct dwc2_tt. Don't forget to call 40849f9f09b0SDouglas Anderson * dwc2_host_put_tt_info()! Returns NULL upon memory alloc failure. 40859f9f09b0SDouglas Anderson */ 40869f9f09b0SDouglas Anderson 40879f9f09b0SDouglas Anderson struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context, 40889f9f09b0SDouglas Anderson gfp_t mem_flags, int *ttport) 40899f9f09b0SDouglas Anderson { 40909f9f09b0SDouglas Anderson struct urb *urb = context; 40919f9f09b0SDouglas Anderson struct dwc2_tt *dwc_tt = NULL; 40929f9f09b0SDouglas Anderson 40939f9f09b0SDouglas Anderson if (urb->dev->tt) { 40949f9f09b0SDouglas Anderson *ttport = urb->dev->ttport; 40959f9f09b0SDouglas Anderson 40969f9f09b0SDouglas Anderson dwc_tt = urb->dev->tt->hcpriv; 40979da51974SJohn Youn if (!dwc_tt) { 40989f9f09b0SDouglas Anderson size_t bitmap_size; 40999f9f09b0SDouglas Anderson 41009f9f09b0SDouglas Anderson /* 41019f9f09b0SDouglas Anderson * For single_tt we need one schedule. For multi_tt 41029f9f09b0SDouglas Anderson * we need one per port. 41039f9f09b0SDouglas Anderson */ 41049f9f09b0SDouglas Anderson bitmap_size = DWC2_ELEMENTS_PER_LS_BITMAP * 41059f9f09b0SDouglas Anderson sizeof(dwc_tt->periodic_bitmaps[0]); 41069f9f09b0SDouglas Anderson if (urb->dev->tt->multi) 41079f9f09b0SDouglas Anderson bitmap_size *= urb->dev->tt->hub->maxchild; 41089f9f09b0SDouglas Anderson 41099f9f09b0SDouglas Anderson dwc_tt = kzalloc(sizeof(*dwc_tt) + bitmap_size, 41109f9f09b0SDouglas Anderson mem_flags); 41119da51974SJohn Youn if (!dwc_tt) 41129f9f09b0SDouglas Anderson return NULL; 41139f9f09b0SDouglas Anderson 41149f9f09b0SDouglas Anderson dwc_tt->usb_tt = urb->dev->tt; 41159f9f09b0SDouglas Anderson dwc_tt->usb_tt->hcpriv = dwc_tt; 41169f9f09b0SDouglas Anderson } 41179f9f09b0SDouglas Anderson 41189f9f09b0SDouglas Anderson dwc_tt->refcount++; 41199f9f09b0SDouglas Anderson } 41209f9f09b0SDouglas Anderson 41219f9f09b0SDouglas Anderson return dwc_tt; 41229f9f09b0SDouglas Anderson } 41239f9f09b0SDouglas Anderson 41249f9f09b0SDouglas Anderson /** 41259f9f09b0SDouglas Anderson * dwc2_host_put_tt_info() - Put the dwc2_tt from dwc2_host_get_tt_info() 41269f9f09b0SDouglas Anderson * 41279f9f09b0SDouglas Anderson * Frees resources allocated by dwc2_host_get_tt_info() if all current holders 41289f9f09b0SDouglas Anderson * of the structure are done. 41299f9f09b0SDouglas Anderson * 41309f9f09b0SDouglas Anderson * It's OK to call this with NULL. 41319f9f09b0SDouglas Anderson * 41329f9f09b0SDouglas Anderson * @hsotg: The HCD state structure for the DWC OTG controller. 41339f9f09b0SDouglas Anderson * @dwc_tt: The pointer returned by dwc2_host_get_tt_info. 41349f9f09b0SDouglas Anderson */ 41359f9f09b0SDouglas Anderson void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, struct dwc2_tt *dwc_tt) 41369f9f09b0SDouglas Anderson { 41379f9f09b0SDouglas Anderson /* Model kfree and make put of NULL a no-op */ 41389da51974SJohn Youn if (!dwc_tt) 41399f9f09b0SDouglas Anderson return; 41409f9f09b0SDouglas Anderson 41419f9f09b0SDouglas Anderson WARN_ON(dwc_tt->refcount < 1); 41429f9f09b0SDouglas Anderson 41439f9f09b0SDouglas Anderson dwc_tt->refcount--; 41449f9f09b0SDouglas Anderson if (!dwc_tt->refcount) { 41459f9f09b0SDouglas Anderson dwc_tt->usb_tt->hcpriv = NULL; 41469f9f09b0SDouglas Anderson kfree(dwc_tt); 41479f9f09b0SDouglas Anderson } 41489f9f09b0SDouglas Anderson } 41499f9f09b0SDouglas Anderson 4150197ba5f4SPaul Zimmerman int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context) 4151197ba5f4SPaul Zimmerman { 4152197ba5f4SPaul Zimmerman struct urb *urb = context; 4153197ba5f4SPaul Zimmerman 4154197ba5f4SPaul Zimmerman return urb->dev->speed; 4155197ba5f4SPaul Zimmerman } 4156197ba5f4SPaul Zimmerman 4157197ba5f4SPaul Zimmerman static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw, 4158197ba5f4SPaul Zimmerman struct urb *urb) 4159197ba5f4SPaul Zimmerman { 4160197ba5f4SPaul Zimmerman struct usb_bus *bus = hcd_to_bus(hcd); 4161197ba5f4SPaul Zimmerman 4162197ba5f4SPaul Zimmerman if (urb->interval) 4163197ba5f4SPaul Zimmerman bus->bandwidth_allocated += bw / urb->interval; 4164197ba5f4SPaul Zimmerman if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 4165197ba5f4SPaul Zimmerman bus->bandwidth_isoc_reqs++; 4166197ba5f4SPaul Zimmerman else 4167197ba5f4SPaul Zimmerman bus->bandwidth_int_reqs++; 4168197ba5f4SPaul Zimmerman } 4169197ba5f4SPaul Zimmerman 4170197ba5f4SPaul Zimmerman static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw, 4171197ba5f4SPaul Zimmerman struct urb *urb) 4172197ba5f4SPaul Zimmerman { 4173197ba5f4SPaul Zimmerman struct usb_bus *bus = hcd_to_bus(hcd); 4174197ba5f4SPaul Zimmerman 4175197ba5f4SPaul Zimmerman if (urb->interval) 4176197ba5f4SPaul Zimmerman bus->bandwidth_allocated -= bw / urb->interval; 4177197ba5f4SPaul Zimmerman if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 4178197ba5f4SPaul Zimmerman bus->bandwidth_isoc_reqs--; 4179197ba5f4SPaul Zimmerman else 4180197ba5f4SPaul Zimmerman bus->bandwidth_int_reqs--; 4181197ba5f4SPaul Zimmerman } 4182197ba5f4SPaul Zimmerman 4183197ba5f4SPaul Zimmerman /* 4184197ba5f4SPaul Zimmerman * Sets the final status of an URB and returns it to the upper layer. Any 4185197ba5f4SPaul Zimmerman * required cleanup of the URB is performed. 4186197ba5f4SPaul Zimmerman * 4187197ba5f4SPaul Zimmerman * Must be called with interrupt disabled and spinlock held 4188197ba5f4SPaul Zimmerman */ 4189197ba5f4SPaul Zimmerman void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 4190197ba5f4SPaul Zimmerman int status) 4191197ba5f4SPaul Zimmerman { 4192197ba5f4SPaul Zimmerman struct urb *urb; 4193197ba5f4SPaul Zimmerman int i; 4194197ba5f4SPaul Zimmerman 4195197ba5f4SPaul Zimmerman if (!qtd) { 4196197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__); 4197197ba5f4SPaul Zimmerman return; 4198197ba5f4SPaul Zimmerman } 4199197ba5f4SPaul Zimmerman 4200197ba5f4SPaul Zimmerman if (!qtd->urb) { 4201197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__); 4202197ba5f4SPaul Zimmerman return; 4203197ba5f4SPaul Zimmerman } 4204197ba5f4SPaul Zimmerman 4205197ba5f4SPaul Zimmerman urb = qtd->urb->priv; 4206197ba5f4SPaul Zimmerman if (!urb) { 4207197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__); 4208197ba5f4SPaul Zimmerman return; 4209197ba5f4SPaul Zimmerman } 4210197ba5f4SPaul Zimmerman 4211197ba5f4SPaul Zimmerman urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb); 4212197ba5f4SPaul Zimmerman 4213197ba5f4SPaul Zimmerman if (dbg_urb(urb)) 4214197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, 4215197ba5f4SPaul Zimmerman "%s: urb %p device %d ep %d-%s status %d actual %d\n", 4216197ba5f4SPaul Zimmerman __func__, urb, usb_pipedevice(urb->pipe), 4217197ba5f4SPaul Zimmerman usb_pipeendpoint(urb->pipe), 4218197ba5f4SPaul Zimmerman usb_pipein(urb->pipe) ? "IN" : "OUT", status, 4219197ba5f4SPaul Zimmerman urb->actual_length); 4220197ba5f4SPaul Zimmerman 4221197ba5f4SPaul Zimmerman if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 4222197ba5f4SPaul Zimmerman urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb); 4223197ba5f4SPaul Zimmerman for (i = 0; i < urb->number_of_packets; ++i) { 4224197ba5f4SPaul Zimmerman urb->iso_frame_desc[i].actual_length = 4225197ba5f4SPaul Zimmerman dwc2_hcd_urb_get_iso_desc_actual_length( 4226197ba5f4SPaul Zimmerman qtd->urb, i); 4227197ba5f4SPaul Zimmerman urb->iso_frame_desc[i].status = 4228197ba5f4SPaul Zimmerman dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i); 4229197ba5f4SPaul Zimmerman } 4230197ba5f4SPaul Zimmerman } 4231197ba5f4SPaul Zimmerman 4232fe9b1773SGregory Herrero if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) { 4233fe9b1773SGregory Herrero for (i = 0; i < urb->number_of_packets; i++) 4234fe9b1773SGregory Herrero dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n", 4235fe9b1773SGregory Herrero i, urb->iso_frame_desc[i].status); 4236fe9b1773SGregory Herrero } 4237fe9b1773SGregory Herrero 4238197ba5f4SPaul Zimmerman urb->status = status; 4239197ba5f4SPaul Zimmerman if (!status) { 4240197ba5f4SPaul Zimmerman if ((urb->transfer_flags & URB_SHORT_NOT_OK) && 4241197ba5f4SPaul Zimmerman urb->actual_length < urb->transfer_buffer_length) 4242197ba5f4SPaul Zimmerman urb->status = -EREMOTEIO; 4243197ba5f4SPaul Zimmerman } 4244197ba5f4SPaul Zimmerman 4245197ba5f4SPaul Zimmerman if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || 4246197ba5f4SPaul Zimmerman usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { 4247197ba5f4SPaul Zimmerman struct usb_host_endpoint *ep = urb->ep; 4248197ba5f4SPaul Zimmerman 4249197ba5f4SPaul Zimmerman if (ep) 4250197ba5f4SPaul Zimmerman dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg), 4251197ba5f4SPaul Zimmerman dwc2_hcd_get_ep_bandwidth(hsotg, ep), 4252197ba5f4SPaul Zimmerman urb); 4253197ba5f4SPaul Zimmerman } 4254197ba5f4SPaul Zimmerman 4255197ba5f4SPaul Zimmerman usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb); 4256197ba5f4SPaul Zimmerman urb->hcpriv = NULL; 4257197ba5f4SPaul Zimmerman kfree(qtd->urb); 4258197ba5f4SPaul Zimmerman qtd->urb = NULL; 4259197ba5f4SPaul Zimmerman 4260197ba5f4SPaul Zimmerman usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status); 4261197ba5f4SPaul Zimmerman } 4262197ba5f4SPaul Zimmerman 4263197ba5f4SPaul Zimmerman /* 4264197ba5f4SPaul Zimmerman * Work queue function for starting the HCD when A-Cable is connected 4265197ba5f4SPaul Zimmerman */ 4266197ba5f4SPaul Zimmerman static void dwc2_hcd_start_func(struct work_struct *work) 4267197ba5f4SPaul Zimmerman { 4268197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 4269197ba5f4SPaul Zimmerman start_work.work); 4270197ba5f4SPaul Zimmerman 4271197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg); 4272197ba5f4SPaul Zimmerman dwc2_host_start(hsotg); 4273197ba5f4SPaul Zimmerman } 4274197ba5f4SPaul Zimmerman 4275197ba5f4SPaul Zimmerman /* 4276197ba5f4SPaul Zimmerman * Reset work queue function 4277197ba5f4SPaul Zimmerman */ 4278197ba5f4SPaul Zimmerman static void dwc2_hcd_reset_func(struct work_struct *work) 4279197ba5f4SPaul Zimmerman { 4280197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 4281197ba5f4SPaul Zimmerman reset_work.work); 42824a065c7bSDouglas Anderson unsigned long flags; 4283197ba5f4SPaul Zimmerman u32 hprt0; 4284197ba5f4SPaul Zimmerman 4285197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "USB RESET function called\n"); 42864a065c7bSDouglas Anderson 42874a065c7bSDouglas Anderson spin_lock_irqsave(&hsotg->lock, flags); 42884a065c7bSDouglas Anderson 4289197ba5f4SPaul Zimmerman hprt0 = dwc2_read_hprt0(hsotg); 4290197ba5f4SPaul Zimmerman hprt0 &= ~HPRT0_RST; 429195c8bc36SAntti Seppälä dwc2_writel(hprt0, hsotg->regs + HPRT0); 4292197ba5f4SPaul Zimmerman hsotg->flags.b.port_reset_change = 1; 42934a065c7bSDouglas Anderson 42944a065c7bSDouglas Anderson spin_unlock_irqrestore(&hsotg->lock, flags); 4295197ba5f4SPaul Zimmerman } 4296197ba5f4SPaul Zimmerman 4297197ba5f4SPaul Zimmerman /* 4298197ba5f4SPaul Zimmerman * ========================================================================= 4299197ba5f4SPaul Zimmerman * Linux HC Driver Functions 4300197ba5f4SPaul Zimmerman * ========================================================================= 4301197ba5f4SPaul Zimmerman */ 4302197ba5f4SPaul Zimmerman 4303197ba5f4SPaul Zimmerman /* 4304197ba5f4SPaul Zimmerman * Initializes the DWC_otg controller and its root hub and prepares it for host 4305197ba5f4SPaul Zimmerman * mode operation. Activates the root port. Returns 0 on success and a negative 4306197ba5f4SPaul Zimmerman * error code on failure. 4307197ba5f4SPaul Zimmerman */ 4308197ba5f4SPaul Zimmerman static int _dwc2_hcd_start(struct usb_hcd *hcd) 4309197ba5f4SPaul Zimmerman { 4310197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4311197ba5f4SPaul Zimmerman struct usb_bus *bus = hcd_to_bus(hcd); 4312197ba5f4SPaul Zimmerman unsigned long flags; 4313197ba5f4SPaul Zimmerman 4314197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "DWC OTG HCD START\n"); 4315197ba5f4SPaul Zimmerman 4316197ba5f4SPaul Zimmerman spin_lock_irqsave(&hsotg->lock, flags); 431731927b6bSGregory Herrero hsotg->lx_state = DWC2_L0; 4318197ba5f4SPaul Zimmerman hcd->state = HC_STATE_RUNNING; 431931927b6bSGregory Herrero set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4320197ba5f4SPaul Zimmerman 4321197ba5f4SPaul Zimmerman if (dwc2_is_device_mode(hsotg)) { 4322197ba5f4SPaul Zimmerman spin_unlock_irqrestore(&hsotg->lock, flags); 4323197ba5f4SPaul Zimmerman return 0; /* why 0 ?? */ 4324197ba5f4SPaul Zimmerman } 4325197ba5f4SPaul Zimmerman 4326197ba5f4SPaul Zimmerman dwc2_hcd_reinit(hsotg); 4327197ba5f4SPaul Zimmerman 4328197ba5f4SPaul Zimmerman /* Initialize and connect root hub if one is not already attached */ 4329197ba5f4SPaul Zimmerman if (bus->root_hub) { 4330197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n"); 4331197ba5f4SPaul Zimmerman /* Inform the HUB driver to resume */ 4332197ba5f4SPaul Zimmerman usb_hcd_resume_root_hub(hcd); 4333197ba5f4SPaul Zimmerman } 4334197ba5f4SPaul Zimmerman 4335197ba5f4SPaul Zimmerman spin_unlock_irqrestore(&hsotg->lock, flags); 4336197ba5f4SPaul Zimmerman return 0; 4337197ba5f4SPaul Zimmerman } 4338197ba5f4SPaul Zimmerman 4339197ba5f4SPaul Zimmerman /* 4340197ba5f4SPaul Zimmerman * Halts the DWC_otg host mode operations in a clean manner. USB transfers are 4341197ba5f4SPaul Zimmerman * stopped. 4342197ba5f4SPaul Zimmerman */ 4343197ba5f4SPaul Zimmerman static void _dwc2_hcd_stop(struct usb_hcd *hcd) 4344197ba5f4SPaul Zimmerman { 4345197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4346197ba5f4SPaul Zimmerman unsigned long flags; 4347197ba5f4SPaul Zimmerman 43485bbf6ce0SGregory Herrero /* Turn off all host-specific interrupts */ 43495bbf6ce0SGregory Herrero dwc2_disable_host_interrupts(hsotg); 43505bbf6ce0SGregory Herrero 4351091473adSGregory Herrero /* Wait for interrupt processing to finish */ 4352091473adSGregory Herrero synchronize_irq(hcd->irq); 4353091473adSGregory Herrero 4354197ba5f4SPaul Zimmerman spin_lock_irqsave(&hsotg->lock, flags); 4355091473adSGregory Herrero /* Ensure hcd is disconnected */ 43566a659531SDouglas Anderson dwc2_hcd_disconnect(hsotg, true); 4357197ba5f4SPaul Zimmerman dwc2_hcd_stop(hsotg); 435831927b6bSGregory Herrero hsotg->lx_state = DWC2_L3; 435931927b6bSGregory Herrero hcd->state = HC_STATE_HALT; 436031927b6bSGregory Herrero clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4361197ba5f4SPaul Zimmerman spin_unlock_irqrestore(&hsotg->lock, flags); 4362197ba5f4SPaul Zimmerman 4363197ba5f4SPaul Zimmerman usleep_range(1000, 3000); 4364197ba5f4SPaul Zimmerman } 4365197ba5f4SPaul Zimmerman 436699a65798SGregory Herrero static int _dwc2_hcd_suspend(struct usb_hcd *hcd) 436799a65798SGregory Herrero { 436899a65798SGregory Herrero struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4369a2a23d3fSGregory Herrero unsigned long flags; 4370a2a23d3fSGregory Herrero int ret = 0; 4371a2a23d3fSGregory Herrero u32 hprt0; 437299a65798SGregory Herrero 4373a2a23d3fSGregory Herrero spin_lock_irqsave(&hsotg->lock, flags); 4374a2a23d3fSGregory Herrero 4375a2a23d3fSGregory Herrero if (hsotg->lx_state != DWC2_L0) 4376a2a23d3fSGregory Herrero goto unlock; 4377a2a23d3fSGregory Herrero 4378a2a23d3fSGregory Herrero if (!HCD_HW_ACCESSIBLE(hcd)) 4379a2a23d3fSGregory Herrero goto unlock; 4380a2a23d3fSGregory Herrero 4381bea8e86cSJohn Youn if (!hsotg->params.hibernation) 4382a2a23d3fSGregory Herrero goto skip_power_saving; 4383a2a23d3fSGregory Herrero 4384a2a23d3fSGregory Herrero /* 4385a2a23d3fSGregory Herrero * Drive USB suspend and disable port Power 4386a2a23d3fSGregory Herrero * if usb bus is not suspended. 4387a2a23d3fSGregory Herrero */ 4388a2a23d3fSGregory Herrero if (!hsotg->bus_suspended) { 4389a2a23d3fSGregory Herrero hprt0 = dwc2_read_hprt0(hsotg); 4390a2a23d3fSGregory Herrero hprt0 |= HPRT0_SUSP; 4391a2a23d3fSGregory Herrero hprt0 &= ~HPRT0_PWR; 4392a2a23d3fSGregory Herrero dwc2_writel(hprt0, hsotg->regs + HPRT0); 4393a2a23d3fSGregory Herrero } 4394a2a23d3fSGregory Herrero 4395a2a23d3fSGregory Herrero /* Enter hibernation */ 4396a2a23d3fSGregory Herrero ret = dwc2_enter_hibernation(hsotg); 4397a2a23d3fSGregory Herrero if (ret) { 4398a2a23d3fSGregory Herrero if (ret != -ENOTSUPP) 4399a2a23d3fSGregory Herrero dev_err(hsotg->dev, 4400a2a23d3fSGregory Herrero "enter hibernation failed\n"); 4401a2a23d3fSGregory Herrero goto skip_power_saving; 4402a2a23d3fSGregory Herrero } 4403a2a23d3fSGregory Herrero 4404a2a23d3fSGregory Herrero /* Ask phy to be suspended */ 4405a2a23d3fSGregory Herrero if (!IS_ERR_OR_NULL(hsotg->uphy)) { 4406a2a23d3fSGregory Herrero spin_unlock_irqrestore(&hsotg->lock, flags); 4407a2a23d3fSGregory Herrero usb_phy_set_suspend(hsotg->uphy, true); 4408a2a23d3fSGregory Herrero spin_lock_irqsave(&hsotg->lock, flags); 4409a2a23d3fSGregory Herrero } 4410a2a23d3fSGregory Herrero 4411a2a23d3fSGregory Herrero /* After entering hibernation, hardware is no more accessible */ 4412a2a23d3fSGregory Herrero clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4413a2a23d3fSGregory Herrero 4414a2a23d3fSGregory Herrero skip_power_saving: 441599a65798SGregory Herrero hsotg->lx_state = DWC2_L2; 4416a2a23d3fSGregory Herrero unlock: 4417a2a23d3fSGregory Herrero spin_unlock_irqrestore(&hsotg->lock, flags); 4418a2a23d3fSGregory Herrero 4419a2a23d3fSGregory Herrero return ret; 442099a65798SGregory Herrero } 442199a65798SGregory Herrero 442299a65798SGregory Herrero static int _dwc2_hcd_resume(struct usb_hcd *hcd) 442399a65798SGregory Herrero { 442499a65798SGregory Herrero struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4425a2a23d3fSGregory Herrero unsigned long flags; 4426a2a23d3fSGregory Herrero int ret = 0; 4427a2a23d3fSGregory Herrero 4428a2a23d3fSGregory Herrero spin_lock_irqsave(&hsotg->lock, flags); 4429a2a23d3fSGregory Herrero 4430a2a23d3fSGregory Herrero if (hsotg->lx_state != DWC2_L2) 4431a2a23d3fSGregory Herrero goto unlock; 4432a2a23d3fSGregory Herrero 4433bea8e86cSJohn Youn if (!hsotg->params.hibernation) { 4434a2a23d3fSGregory Herrero hsotg->lx_state = DWC2_L0; 4435a2a23d3fSGregory Herrero goto unlock; 4436a2a23d3fSGregory Herrero } 4437a2a23d3fSGregory Herrero 4438a2a23d3fSGregory Herrero /* 4439a2a23d3fSGregory Herrero * Set HW accessible bit before powering on the controller 4440a2a23d3fSGregory Herrero * since an interrupt may rise. 4441a2a23d3fSGregory Herrero */ 4442a2a23d3fSGregory Herrero set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4443a2a23d3fSGregory Herrero 4444a2a23d3fSGregory Herrero /* 4445a2a23d3fSGregory Herrero * Enable power if not already done. 4446a2a23d3fSGregory Herrero * This must not be spinlocked since duration 4447a2a23d3fSGregory Herrero * of this call is unknown. 4448a2a23d3fSGregory Herrero */ 4449a2a23d3fSGregory Herrero if (!IS_ERR_OR_NULL(hsotg->uphy)) { 4450a2a23d3fSGregory Herrero spin_unlock_irqrestore(&hsotg->lock, flags); 4451a2a23d3fSGregory Herrero usb_phy_set_suspend(hsotg->uphy, false); 4452a2a23d3fSGregory Herrero spin_lock_irqsave(&hsotg->lock, flags); 4453a2a23d3fSGregory Herrero } 4454a2a23d3fSGregory Herrero 4455a2a23d3fSGregory Herrero /* Exit hibernation */ 4456a2a23d3fSGregory Herrero ret = dwc2_exit_hibernation(hsotg, true); 4457a2a23d3fSGregory Herrero if (ret && (ret != -ENOTSUPP)) 4458a2a23d3fSGregory Herrero dev_err(hsotg->dev, "exit hibernation failed\n"); 445999a65798SGregory Herrero 446099a65798SGregory Herrero hsotg->lx_state = DWC2_L0; 4461a2a23d3fSGregory Herrero 4462a2a23d3fSGregory Herrero spin_unlock_irqrestore(&hsotg->lock, flags); 4463a2a23d3fSGregory Herrero 4464a2a23d3fSGregory Herrero if (hsotg->bus_suspended) { 4465a2a23d3fSGregory Herrero spin_lock_irqsave(&hsotg->lock, flags); 4466a2a23d3fSGregory Herrero hsotg->flags.b.port_suspend_change = 1; 4467a2a23d3fSGregory Herrero spin_unlock_irqrestore(&hsotg->lock, flags); 4468a2a23d3fSGregory Herrero dwc2_port_resume(hsotg); 4469a2a23d3fSGregory Herrero } else { 44705634e016SGregory Herrero /* Wait for controller to correctly update D+/D- level */ 44715634e016SGregory Herrero usleep_range(3000, 5000); 44725634e016SGregory Herrero 4473a2a23d3fSGregory Herrero /* 4474a2a23d3fSGregory Herrero * Clear Port Enable and Port Status changes. 4475a2a23d3fSGregory Herrero * Enable Port Power. 4476a2a23d3fSGregory Herrero */ 4477a2a23d3fSGregory Herrero dwc2_writel(HPRT0_PWR | HPRT0_CONNDET | 4478a2a23d3fSGregory Herrero HPRT0_ENACHG, hsotg->regs + HPRT0); 4479a2a23d3fSGregory Herrero /* Wait for controller to detect Port Connect */ 44805634e016SGregory Herrero usleep_range(5000, 7000); 4481a2a23d3fSGregory Herrero } 4482a2a23d3fSGregory Herrero 4483a2a23d3fSGregory Herrero return ret; 4484a2a23d3fSGregory Herrero unlock: 4485a2a23d3fSGregory Herrero spin_unlock_irqrestore(&hsotg->lock, flags); 4486a2a23d3fSGregory Herrero 4487a2a23d3fSGregory Herrero return ret; 448899a65798SGregory Herrero } 448999a65798SGregory Herrero 4490197ba5f4SPaul Zimmerman /* Returns the current frame number */ 4491197ba5f4SPaul Zimmerman static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd) 4492197ba5f4SPaul Zimmerman { 4493197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4494197ba5f4SPaul Zimmerman 4495197ba5f4SPaul Zimmerman return dwc2_hcd_get_frame_number(hsotg); 4496197ba5f4SPaul Zimmerman } 4497197ba5f4SPaul Zimmerman 4498197ba5f4SPaul Zimmerman static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb, 4499197ba5f4SPaul Zimmerman char *fn_name) 4500197ba5f4SPaul Zimmerman { 4501197ba5f4SPaul Zimmerman #ifdef VERBOSE_DEBUG 4502197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4503197ba5f4SPaul Zimmerman char *pipetype; 4504197ba5f4SPaul Zimmerman char *speed; 4505197ba5f4SPaul Zimmerman 4506197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb); 4507197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " Device address: %d\n", 4508197ba5f4SPaul Zimmerman usb_pipedevice(urb->pipe)); 4509197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n", 4510197ba5f4SPaul Zimmerman usb_pipeendpoint(urb->pipe), 4511197ba5f4SPaul Zimmerman usb_pipein(urb->pipe) ? "IN" : "OUT"); 4512197ba5f4SPaul Zimmerman 4513197ba5f4SPaul Zimmerman switch (usb_pipetype(urb->pipe)) { 4514197ba5f4SPaul Zimmerman case PIPE_CONTROL: 4515197ba5f4SPaul Zimmerman pipetype = "CONTROL"; 4516197ba5f4SPaul Zimmerman break; 4517197ba5f4SPaul Zimmerman case PIPE_BULK: 4518197ba5f4SPaul Zimmerman pipetype = "BULK"; 4519197ba5f4SPaul Zimmerman break; 4520197ba5f4SPaul Zimmerman case PIPE_INTERRUPT: 4521197ba5f4SPaul Zimmerman pipetype = "INTERRUPT"; 4522197ba5f4SPaul Zimmerman break; 4523197ba5f4SPaul Zimmerman case PIPE_ISOCHRONOUS: 4524197ba5f4SPaul Zimmerman pipetype = "ISOCHRONOUS"; 4525197ba5f4SPaul Zimmerman break; 4526197ba5f4SPaul Zimmerman } 4527197ba5f4SPaul Zimmerman 4528197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype, 4529197ba5f4SPaul Zimmerman usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ? 4530197ba5f4SPaul Zimmerman "IN" : "OUT"); 4531197ba5f4SPaul Zimmerman 4532197ba5f4SPaul Zimmerman switch (urb->dev->speed) { 4533197ba5f4SPaul Zimmerman case USB_SPEED_HIGH: 4534197ba5f4SPaul Zimmerman speed = "HIGH"; 4535197ba5f4SPaul Zimmerman break; 4536197ba5f4SPaul Zimmerman case USB_SPEED_FULL: 4537197ba5f4SPaul Zimmerman speed = "FULL"; 4538197ba5f4SPaul Zimmerman break; 4539197ba5f4SPaul Zimmerman case USB_SPEED_LOW: 4540197ba5f4SPaul Zimmerman speed = "LOW"; 4541197ba5f4SPaul Zimmerman break; 4542197ba5f4SPaul Zimmerman default: 4543197ba5f4SPaul Zimmerman speed = "UNKNOWN"; 4544197ba5f4SPaul Zimmerman break; 4545197ba5f4SPaul Zimmerman } 4546197ba5f4SPaul Zimmerman 4547197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " Speed: %s\n", speed); 4548197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " Max packet size: %d\n", 4549197ba5f4SPaul Zimmerman usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))); 4550197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " Data buffer length: %d\n", 4551197ba5f4SPaul Zimmerman urb->transfer_buffer_length); 4552197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n", 4553197ba5f4SPaul Zimmerman urb->transfer_buffer, (unsigned long)urb->transfer_dma); 4554197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n", 4555197ba5f4SPaul Zimmerman urb->setup_packet, (unsigned long)urb->setup_dma); 4556197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval); 4557197ba5f4SPaul Zimmerman 4558197ba5f4SPaul Zimmerman if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 4559197ba5f4SPaul Zimmerman int i; 4560197ba5f4SPaul Zimmerman 4561197ba5f4SPaul Zimmerman for (i = 0; i < urb->number_of_packets; i++) { 4562197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i); 4563197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, " offset: %d, length %d\n", 4564197ba5f4SPaul Zimmerman urb->iso_frame_desc[i].offset, 4565197ba5f4SPaul Zimmerman urb->iso_frame_desc[i].length); 4566197ba5f4SPaul Zimmerman } 4567197ba5f4SPaul Zimmerman } 4568197ba5f4SPaul Zimmerman #endif 4569197ba5f4SPaul Zimmerman } 4570197ba5f4SPaul Zimmerman 4571197ba5f4SPaul Zimmerman /* 4572197ba5f4SPaul Zimmerman * Starts processing a USB transfer request specified by a USB Request Block 4573197ba5f4SPaul Zimmerman * (URB). mem_flags indicates the type of memory allocation to use while 4574197ba5f4SPaul Zimmerman * processing this URB. 4575197ba5f4SPaul Zimmerman */ 4576197ba5f4SPaul Zimmerman static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, 4577197ba5f4SPaul Zimmerman gfp_t mem_flags) 4578197ba5f4SPaul Zimmerman { 4579197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4580197ba5f4SPaul Zimmerman struct usb_host_endpoint *ep = urb->ep; 4581197ba5f4SPaul Zimmerman struct dwc2_hcd_urb *dwc2_urb; 4582197ba5f4SPaul Zimmerman int i; 4583197ba5f4SPaul Zimmerman int retval; 4584197ba5f4SPaul Zimmerman int alloc_bandwidth = 0; 4585197ba5f4SPaul Zimmerman u8 ep_type = 0; 4586197ba5f4SPaul Zimmerman u32 tflags = 0; 4587197ba5f4SPaul Zimmerman void *buf; 4588197ba5f4SPaul Zimmerman unsigned long flags; 4589b58e6ceeSMian Yousaf Kaukab struct dwc2_qh *qh; 4590b58e6ceeSMian Yousaf Kaukab bool qh_allocated = false; 4591b5a468a6SMian Yousaf Kaukab struct dwc2_qtd *qtd; 4592197ba5f4SPaul Zimmerman 4593197ba5f4SPaul Zimmerman if (dbg_urb(urb)) { 4594197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n"); 4595197ba5f4SPaul Zimmerman dwc2_dump_urb_info(hcd, urb, "urb_enqueue"); 4596197ba5f4SPaul Zimmerman } 4597197ba5f4SPaul Zimmerman 45989da51974SJohn Youn if (!ep) 4599197ba5f4SPaul Zimmerman return -EINVAL; 4600197ba5f4SPaul Zimmerman 4601197ba5f4SPaul Zimmerman if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || 4602197ba5f4SPaul Zimmerman usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { 4603197ba5f4SPaul Zimmerman spin_lock_irqsave(&hsotg->lock, flags); 4604197ba5f4SPaul Zimmerman if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep)) 4605197ba5f4SPaul Zimmerman alloc_bandwidth = 1; 4606197ba5f4SPaul Zimmerman spin_unlock_irqrestore(&hsotg->lock, flags); 4607197ba5f4SPaul Zimmerman } 4608197ba5f4SPaul Zimmerman 4609197ba5f4SPaul Zimmerman switch (usb_pipetype(urb->pipe)) { 4610197ba5f4SPaul Zimmerman case PIPE_CONTROL: 4611197ba5f4SPaul Zimmerman ep_type = USB_ENDPOINT_XFER_CONTROL; 4612197ba5f4SPaul Zimmerman break; 4613197ba5f4SPaul Zimmerman case PIPE_ISOCHRONOUS: 4614197ba5f4SPaul Zimmerman ep_type = USB_ENDPOINT_XFER_ISOC; 4615197ba5f4SPaul Zimmerman break; 4616197ba5f4SPaul Zimmerman case PIPE_BULK: 4617197ba5f4SPaul Zimmerman ep_type = USB_ENDPOINT_XFER_BULK; 4618197ba5f4SPaul Zimmerman break; 4619197ba5f4SPaul Zimmerman case PIPE_INTERRUPT: 4620197ba5f4SPaul Zimmerman ep_type = USB_ENDPOINT_XFER_INT; 4621197ba5f4SPaul Zimmerman break; 4622197ba5f4SPaul Zimmerman } 4623197ba5f4SPaul Zimmerman 4624197ba5f4SPaul Zimmerman dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets, 4625197ba5f4SPaul Zimmerman mem_flags); 4626197ba5f4SPaul Zimmerman if (!dwc2_urb) 4627197ba5f4SPaul Zimmerman return -ENOMEM; 4628197ba5f4SPaul Zimmerman 4629197ba5f4SPaul Zimmerman dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe), 4630197ba5f4SPaul Zimmerman usb_pipeendpoint(urb->pipe), ep_type, 4631197ba5f4SPaul Zimmerman usb_pipein(urb->pipe), 4632197ba5f4SPaul Zimmerman usb_maxpacket(urb->dev, urb->pipe, 4633197ba5f4SPaul Zimmerman !(usb_pipein(urb->pipe)))); 4634197ba5f4SPaul Zimmerman 4635197ba5f4SPaul Zimmerman buf = urb->transfer_buffer; 4636197ba5f4SPaul Zimmerman 4637197ba5f4SPaul Zimmerman if (hcd->self.uses_dma) { 4638197ba5f4SPaul Zimmerman if (!buf && (urb->transfer_dma & 3)) { 4639197ba5f4SPaul Zimmerman dev_err(hsotg->dev, 4640197ba5f4SPaul Zimmerman "%s: unaligned transfer with no transfer_buffer", 4641197ba5f4SPaul Zimmerman __func__); 4642197ba5f4SPaul Zimmerman retval = -EINVAL; 464333ad261aSGregory Herrero goto fail0; 4644197ba5f4SPaul Zimmerman } 4645197ba5f4SPaul Zimmerman } 4646197ba5f4SPaul Zimmerman 4647197ba5f4SPaul Zimmerman if (!(urb->transfer_flags & URB_NO_INTERRUPT)) 4648197ba5f4SPaul Zimmerman tflags |= URB_GIVEBACK_ASAP; 4649197ba5f4SPaul Zimmerman if (urb->transfer_flags & URB_ZERO_PACKET) 4650197ba5f4SPaul Zimmerman tflags |= URB_SEND_ZERO_PACKET; 4651197ba5f4SPaul Zimmerman 4652197ba5f4SPaul Zimmerman dwc2_urb->priv = urb; 4653197ba5f4SPaul Zimmerman dwc2_urb->buf = buf; 4654197ba5f4SPaul Zimmerman dwc2_urb->dma = urb->transfer_dma; 4655197ba5f4SPaul Zimmerman dwc2_urb->length = urb->transfer_buffer_length; 4656197ba5f4SPaul Zimmerman dwc2_urb->setup_packet = urb->setup_packet; 4657197ba5f4SPaul Zimmerman dwc2_urb->setup_dma = urb->setup_dma; 4658197ba5f4SPaul Zimmerman dwc2_urb->flags = tflags; 4659197ba5f4SPaul Zimmerman dwc2_urb->interval = urb->interval; 4660197ba5f4SPaul Zimmerman dwc2_urb->status = -EINPROGRESS; 4661197ba5f4SPaul Zimmerman 4662197ba5f4SPaul Zimmerman for (i = 0; i < urb->number_of_packets; ++i) 4663197ba5f4SPaul Zimmerman dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i, 4664197ba5f4SPaul Zimmerman urb->iso_frame_desc[i].offset, 4665197ba5f4SPaul Zimmerman urb->iso_frame_desc[i].length); 4666197ba5f4SPaul Zimmerman 4667197ba5f4SPaul Zimmerman urb->hcpriv = dwc2_urb; 4668b58e6ceeSMian Yousaf Kaukab qh = (struct dwc2_qh *)ep->hcpriv; 4669b58e6ceeSMian Yousaf Kaukab /* Create QH for the endpoint if it doesn't exist */ 4670b58e6ceeSMian Yousaf Kaukab if (!qh) { 4671b58e6ceeSMian Yousaf Kaukab qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags); 4672b58e6ceeSMian Yousaf Kaukab if (!qh) { 4673b58e6ceeSMian Yousaf Kaukab retval = -ENOMEM; 4674b58e6ceeSMian Yousaf Kaukab goto fail0; 4675b58e6ceeSMian Yousaf Kaukab } 4676b58e6ceeSMian Yousaf Kaukab ep->hcpriv = qh; 4677b58e6ceeSMian Yousaf Kaukab qh_allocated = true; 4678b58e6ceeSMian Yousaf Kaukab } 4679197ba5f4SPaul Zimmerman 4680b5a468a6SMian Yousaf Kaukab qtd = kzalloc(sizeof(*qtd), mem_flags); 4681b5a468a6SMian Yousaf Kaukab if (!qtd) { 4682b5a468a6SMian Yousaf Kaukab retval = -ENOMEM; 4683b5a468a6SMian Yousaf Kaukab goto fail1; 4684b5a468a6SMian Yousaf Kaukab } 4685b5a468a6SMian Yousaf Kaukab 4686197ba5f4SPaul Zimmerman spin_lock_irqsave(&hsotg->lock, flags); 4687197ba5f4SPaul Zimmerman retval = usb_hcd_link_urb_to_ep(hcd, urb); 4688197ba5f4SPaul Zimmerman if (retval) 4689197ba5f4SPaul Zimmerman goto fail2; 4690197ba5f4SPaul Zimmerman 4691b5a468a6SMian Yousaf Kaukab retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd); 4692b5a468a6SMian Yousaf Kaukab if (retval) 4693b5a468a6SMian Yousaf Kaukab goto fail3; 4694b5a468a6SMian Yousaf Kaukab 4695197ba5f4SPaul Zimmerman if (alloc_bandwidth) { 4696197ba5f4SPaul Zimmerman dwc2_allocate_bus_bandwidth(hcd, 4697197ba5f4SPaul Zimmerman dwc2_hcd_get_ep_bandwidth(hsotg, ep), 4698197ba5f4SPaul Zimmerman urb); 4699197ba5f4SPaul Zimmerman } 4700197ba5f4SPaul Zimmerman 470133ad261aSGregory Herrero spin_unlock_irqrestore(&hsotg->lock, flags); 470233ad261aSGregory Herrero 4703197ba5f4SPaul Zimmerman return 0; 4704197ba5f4SPaul Zimmerman 4705b5a468a6SMian Yousaf Kaukab fail3: 4706197ba5f4SPaul Zimmerman dwc2_urb->priv = NULL; 4707197ba5f4SPaul Zimmerman usb_hcd_unlink_urb_from_ep(hcd, urb); 470816e80218SDouglas Anderson if (qh_allocated && qh->channel && qh->channel->qh == qh) 470916e80218SDouglas Anderson qh->channel->qh = NULL; 4710b5a468a6SMian Yousaf Kaukab fail2: 471133ad261aSGregory Herrero spin_unlock_irqrestore(&hsotg->lock, flags); 4712197ba5f4SPaul Zimmerman urb->hcpriv = NULL; 4713b5a468a6SMian Yousaf Kaukab kfree(qtd); 4714b0d65902SVardan Mikayelyan qtd = NULL; 4715b5a468a6SMian Yousaf Kaukab fail1: 4716b58e6ceeSMian Yousaf Kaukab if (qh_allocated) { 4717b58e6ceeSMian Yousaf Kaukab struct dwc2_qtd *qtd2, *qtd2_tmp; 4718b58e6ceeSMian Yousaf Kaukab 4719b58e6ceeSMian Yousaf Kaukab ep->hcpriv = NULL; 4720b58e6ceeSMian Yousaf Kaukab dwc2_hcd_qh_unlink(hsotg, qh); 4721b58e6ceeSMian Yousaf Kaukab /* Free each QTD in the QH's QTD list */ 4722b58e6ceeSMian Yousaf Kaukab list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list, 4723b58e6ceeSMian Yousaf Kaukab qtd_list_entry) 4724b58e6ceeSMian Yousaf Kaukab dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh); 4725b58e6ceeSMian Yousaf Kaukab dwc2_hcd_qh_free(hsotg, qh); 4726b58e6ceeSMian Yousaf Kaukab } 472733ad261aSGregory Herrero fail0: 4728197ba5f4SPaul Zimmerman kfree(dwc2_urb); 4729197ba5f4SPaul Zimmerman 4730197ba5f4SPaul Zimmerman return retval; 4731197ba5f4SPaul Zimmerman } 4732197ba5f4SPaul Zimmerman 4733197ba5f4SPaul Zimmerman /* 4734197ba5f4SPaul Zimmerman * Aborts/cancels a USB transfer request. Always returns 0 to indicate success. 4735197ba5f4SPaul Zimmerman */ 4736197ba5f4SPaul Zimmerman static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, 4737197ba5f4SPaul Zimmerman int status) 4738197ba5f4SPaul Zimmerman { 4739197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4740197ba5f4SPaul Zimmerman int rc; 4741197ba5f4SPaul Zimmerman unsigned long flags; 4742197ba5f4SPaul Zimmerman 4743197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n"); 4744197ba5f4SPaul Zimmerman dwc2_dump_urb_info(hcd, urb, "urb_dequeue"); 4745197ba5f4SPaul Zimmerman 4746197ba5f4SPaul Zimmerman spin_lock_irqsave(&hsotg->lock, flags); 4747197ba5f4SPaul Zimmerman 4748197ba5f4SPaul Zimmerman rc = usb_hcd_check_unlink_urb(hcd, urb, status); 4749197ba5f4SPaul Zimmerman if (rc) 4750197ba5f4SPaul Zimmerman goto out; 4751197ba5f4SPaul Zimmerman 4752197ba5f4SPaul Zimmerman if (!urb->hcpriv) { 4753197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n"); 4754197ba5f4SPaul Zimmerman goto out; 4755197ba5f4SPaul Zimmerman } 4756197ba5f4SPaul Zimmerman 4757197ba5f4SPaul Zimmerman rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv); 4758197ba5f4SPaul Zimmerman 4759197ba5f4SPaul Zimmerman usb_hcd_unlink_urb_from_ep(hcd, urb); 4760197ba5f4SPaul Zimmerman 4761197ba5f4SPaul Zimmerman kfree(urb->hcpriv); 4762197ba5f4SPaul Zimmerman urb->hcpriv = NULL; 4763197ba5f4SPaul Zimmerman 4764197ba5f4SPaul Zimmerman /* Higher layer software sets URB status */ 4765197ba5f4SPaul Zimmerman spin_unlock(&hsotg->lock); 4766197ba5f4SPaul Zimmerman usb_hcd_giveback_urb(hcd, urb, status); 4767197ba5f4SPaul Zimmerman spin_lock(&hsotg->lock); 4768197ba5f4SPaul Zimmerman 4769197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n"); 4770197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status); 4771197ba5f4SPaul Zimmerman out: 4772197ba5f4SPaul Zimmerman spin_unlock_irqrestore(&hsotg->lock, flags); 4773197ba5f4SPaul Zimmerman 4774197ba5f4SPaul Zimmerman return rc; 4775197ba5f4SPaul Zimmerman } 4776197ba5f4SPaul Zimmerman 4777197ba5f4SPaul Zimmerman /* 4778197ba5f4SPaul Zimmerman * Frees resources in the DWC_otg controller related to a given endpoint. Also 4779197ba5f4SPaul Zimmerman * clears state in the HCD related to the endpoint. Any URBs for the endpoint 4780197ba5f4SPaul Zimmerman * must already be dequeued. 4781197ba5f4SPaul Zimmerman */ 4782197ba5f4SPaul Zimmerman static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd, 4783197ba5f4SPaul Zimmerman struct usb_host_endpoint *ep) 4784197ba5f4SPaul Zimmerman { 4785197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4786197ba5f4SPaul Zimmerman 4787197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 4788197ba5f4SPaul Zimmerman "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n", 4789197ba5f4SPaul Zimmerman ep->desc.bEndpointAddress, ep->hcpriv); 4790197ba5f4SPaul Zimmerman dwc2_hcd_endpoint_disable(hsotg, ep, 250); 4791197ba5f4SPaul Zimmerman } 4792197ba5f4SPaul Zimmerman 4793197ba5f4SPaul Zimmerman /* 4794197ba5f4SPaul Zimmerman * Resets endpoint specific parameter values, in current version used to reset 4795197ba5f4SPaul Zimmerman * the data toggle (as a WA). This function can be called from usb_clear_halt 4796197ba5f4SPaul Zimmerman * routine. 4797197ba5f4SPaul Zimmerman */ 4798197ba5f4SPaul Zimmerman static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd, 4799197ba5f4SPaul Zimmerman struct usb_host_endpoint *ep) 4800197ba5f4SPaul Zimmerman { 4801197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4802197ba5f4SPaul Zimmerman unsigned long flags; 4803197ba5f4SPaul Zimmerman 4804197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, 4805197ba5f4SPaul Zimmerman "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n", 4806197ba5f4SPaul Zimmerman ep->desc.bEndpointAddress); 4807197ba5f4SPaul Zimmerman 4808197ba5f4SPaul Zimmerman spin_lock_irqsave(&hsotg->lock, flags); 4809197ba5f4SPaul Zimmerman dwc2_hcd_endpoint_reset(hsotg, ep); 4810197ba5f4SPaul Zimmerman spin_unlock_irqrestore(&hsotg->lock, flags); 4811197ba5f4SPaul Zimmerman } 4812197ba5f4SPaul Zimmerman 4813197ba5f4SPaul Zimmerman /* 4814197ba5f4SPaul Zimmerman * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if 4815197ba5f4SPaul Zimmerman * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid 4816197ba5f4SPaul Zimmerman * interrupt. 4817197ba5f4SPaul Zimmerman * 4818197ba5f4SPaul Zimmerman * This function is called by the USB core when an interrupt occurs 4819197ba5f4SPaul Zimmerman */ 4820197ba5f4SPaul Zimmerman static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd) 4821197ba5f4SPaul Zimmerman { 4822197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4823197ba5f4SPaul Zimmerman 4824197ba5f4SPaul Zimmerman return dwc2_handle_hcd_intr(hsotg); 4825197ba5f4SPaul Zimmerman } 4826197ba5f4SPaul Zimmerman 4827197ba5f4SPaul Zimmerman /* 4828197ba5f4SPaul Zimmerman * Creates Status Change bitmap for the root hub and root port. The bitmap is 4829197ba5f4SPaul Zimmerman * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1 4830197ba5f4SPaul Zimmerman * is the status change indicator for the single root port. Returns 1 if either 4831197ba5f4SPaul Zimmerman * change indicator is 1, otherwise returns 0. 4832197ba5f4SPaul Zimmerman */ 4833197ba5f4SPaul Zimmerman static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf) 4834197ba5f4SPaul Zimmerman { 4835197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4836197ba5f4SPaul Zimmerman 4837197ba5f4SPaul Zimmerman buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1; 4838197ba5f4SPaul Zimmerman return buf[0] != 0; 4839197ba5f4SPaul Zimmerman } 4840197ba5f4SPaul Zimmerman 4841197ba5f4SPaul Zimmerman /* Handles hub class-specific requests */ 4842197ba5f4SPaul Zimmerman static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue, 4843197ba5f4SPaul Zimmerman u16 windex, char *buf, u16 wlength) 4844197ba5f4SPaul Zimmerman { 4845197ba5f4SPaul Zimmerman int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq, 4846197ba5f4SPaul Zimmerman wvalue, windex, buf, wlength); 4847197ba5f4SPaul Zimmerman return retval; 4848197ba5f4SPaul Zimmerman } 4849197ba5f4SPaul Zimmerman 4850197ba5f4SPaul Zimmerman /* Handles hub TT buffer clear completions */ 4851197ba5f4SPaul Zimmerman static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd, 4852197ba5f4SPaul Zimmerman struct usb_host_endpoint *ep) 4853197ba5f4SPaul Zimmerman { 4854197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4855197ba5f4SPaul Zimmerman struct dwc2_qh *qh; 4856197ba5f4SPaul Zimmerman unsigned long flags; 4857197ba5f4SPaul Zimmerman 4858197ba5f4SPaul Zimmerman qh = ep->hcpriv; 4859197ba5f4SPaul Zimmerman if (!qh) 4860197ba5f4SPaul Zimmerman return; 4861197ba5f4SPaul Zimmerman 4862197ba5f4SPaul Zimmerman spin_lock_irqsave(&hsotg->lock, flags); 4863197ba5f4SPaul Zimmerman qh->tt_buffer_dirty = 0; 4864197ba5f4SPaul Zimmerman 4865197ba5f4SPaul Zimmerman if (hsotg->flags.b.port_connect_status) 4866197ba5f4SPaul Zimmerman dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL); 4867197ba5f4SPaul Zimmerman 4868197ba5f4SPaul Zimmerman spin_unlock_irqrestore(&hsotg->lock, flags); 4869197ba5f4SPaul Zimmerman } 4870197ba5f4SPaul Zimmerman 4871197ba5f4SPaul Zimmerman static struct hc_driver dwc2_hc_driver = { 4872197ba5f4SPaul Zimmerman .description = "dwc2_hsotg", 4873197ba5f4SPaul Zimmerman .product_desc = "DWC OTG Controller", 4874197ba5f4SPaul Zimmerman .hcd_priv_size = sizeof(struct wrapper_priv_data), 4875197ba5f4SPaul Zimmerman 4876197ba5f4SPaul Zimmerman .irq = _dwc2_hcd_irq, 48778add17cfSDouglas Anderson .flags = HCD_MEMORY | HCD_USB2 | HCD_BH, 4878197ba5f4SPaul Zimmerman 4879197ba5f4SPaul Zimmerman .start = _dwc2_hcd_start, 4880197ba5f4SPaul Zimmerman .stop = _dwc2_hcd_stop, 4881197ba5f4SPaul Zimmerman .urb_enqueue = _dwc2_hcd_urb_enqueue, 4882197ba5f4SPaul Zimmerman .urb_dequeue = _dwc2_hcd_urb_dequeue, 4883197ba5f4SPaul Zimmerman .endpoint_disable = _dwc2_hcd_endpoint_disable, 4884197ba5f4SPaul Zimmerman .endpoint_reset = _dwc2_hcd_endpoint_reset, 4885197ba5f4SPaul Zimmerman .get_frame_number = _dwc2_hcd_get_frame_number, 4886197ba5f4SPaul Zimmerman 4887197ba5f4SPaul Zimmerman .hub_status_data = _dwc2_hcd_hub_status_data, 4888197ba5f4SPaul Zimmerman .hub_control = _dwc2_hcd_hub_control, 4889197ba5f4SPaul Zimmerman .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete, 489099a65798SGregory Herrero 489199a65798SGregory Herrero .bus_suspend = _dwc2_hcd_suspend, 489299a65798SGregory Herrero .bus_resume = _dwc2_hcd_resume, 48933bc04e28SDouglas Anderson 48943bc04e28SDouglas Anderson .map_urb_for_dma = dwc2_map_urb_for_dma, 48953bc04e28SDouglas Anderson .unmap_urb_for_dma = dwc2_unmap_urb_for_dma, 4896197ba5f4SPaul Zimmerman }; 4897197ba5f4SPaul Zimmerman 4898197ba5f4SPaul Zimmerman /* 4899197ba5f4SPaul Zimmerman * Frees secondary storage associated with the dwc2_hsotg structure contained 4900197ba5f4SPaul Zimmerman * in the struct usb_hcd field 4901197ba5f4SPaul Zimmerman */ 4902197ba5f4SPaul Zimmerman static void dwc2_hcd_free(struct dwc2_hsotg *hsotg) 4903197ba5f4SPaul Zimmerman { 4904197ba5f4SPaul Zimmerman u32 ahbcfg; 4905197ba5f4SPaul Zimmerman u32 dctl; 4906197ba5f4SPaul Zimmerman int i; 4907197ba5f4SPaul Zimmerman 4908197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n"); 4909197ba5f4SPaul Zimmerman 4910197ba5f4SPaul Zimmerman /* Free memory for QH/QTD lists */ 4911197ba5f4SPaul Zimmerman dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive); 4912197ba5f4SPaul Zimmerman dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active); 4913197ba5f4SPaul Zimmerman dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive); 4914197ba5f4SPaul Zimmerman dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready); 4915197ba5f4SPaul Zimmerman dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned); 4916197ba5f4SPaul Zimmerman dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued); 4917197ba5f4SPaul Zimmerman 4918197ba5f4SPaul Zimmerman /* Free memory for the host channels */ 4919197ba5f4SPaul Zimmerman for (i = 0; i < MAX_EPS_CHANNELS; i++) { 4920197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 4921197ba5f4SPaul Zimmerman 49229da51974SJohn Youn if (chan) { 4923197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n", 4924197ba5f4SPaul Zimmerman i, chan); 4925197ba5f4SPaul Zimmerman hsotg->hc_ptr_array[i] = NULL; 4926197ba5f4SPaul Zimmerman kfree(chan); 4927197ba5f4SPaul Zimmerman } 4928197ba5f4SPaul Zimmerman } 4929197ba5f4SPaul Zimmerman 493095832c00SJohn Youn if (hsotg->params.host_dma) { 4931197ba5f4SPaul Zimmerman if (hsotg->status_buf) { 4932197ba5f4SPaul Zimmerman dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE, 4933197ba5f4SPaul Zimmerman hsotg->status_buf, 4934197ba5f4SPaul Zimmerman hsotg->status_buf_dma); 4935197ba5f4SPaul Zimmerman hsotg->status_buf = NULL; 4936197ba5f4SPaul Zimmerman } 4937197ba5f4SPaul Zimmerman } else { 4938197ba5f4SPaul Zimmerman kfree(hsotg->status_buf); 4939197ba5f4SPaul Zimmerman hsotg->status_buf = NULL; 4940197ba5f4SPaul Zimmerman } 4941197ba5f4SPaul Zimmerman 494295c8bc36SAntti Seppälä ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 4943197ba5f4SPaul Zimmerman 4944197ba5f4SPaul Zimmerman /* Disable all interrupts */ 4945197ba5f4SPaul Zimmerman ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 494695c8bc36SAntti Seppälä dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); 494795c8bc36SAntti Seppälä dwc2_writel(0, hsotg->regs + GINTMSK); 4948197ba5f4SPaul Zimmerman 4949197ba5f4SPaul Zimmerman if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) { 495095c8bc36SAntti Seppälä dctl = dwc2_readl(hsotg->regs + DCTL); 4951197ba5f4SPaul Zimmerman dctl |= DCTL_SFTDISCON; 495295c8bc36SAntti Seppälä dwc2_writel(dctl, hsotg->regs + DCTL); 4953197ba5f4SPaul Zimmerman } 4954197ba5f4SPaul Zimmerman 4955197ba5f4SPaul Zimmerman if (hsotg->wq_otg) { 4956197ba5f4SPaul Zimmerman if (!cancel_work_sync(&hsotg->wf_otg)) 4957197ba5f4SPaul Zimmerman flush_workqueue(hsotg->wq_otg); 4958197ba5f4SPaul Zimmerman destroy_workqueue(hsotg->wq_otg); 4959197ba5f4SPaul Zimmerman } 4960197ba5f4SPaul Zimmerman 4961197ba5f4SPaul Zimmerman del_timer(&hsotg->wkp_timer); 4962197ba5f4SPaul Zimmerman } 4963197ba5f4SPaul Zimmerman 4964197ba5f4SPaul Zimmerman static void dwc2_hcd_release(struct dwc2_hsotg *hsotg) 4965197ba5f4SPaul Zimmerman { 4966197ba5f4SPaul Zimmerman /* Turn off all host-specific interrupts */ 4967197ba5f4SPaul Zimmerman dwc2_disable_host_interrupts(hsotg); 4968197ba5f4SPaul Zimmerman 4969197ba5f4SPaul Zimmerman dwc2_hcd_free(hsotg); 4970197ba5f4SPaul Zimmerman } 4971197ba5f4SPaul Zimmerman 4972197ba5f4SPaul Zimmerman /* 4973197ba5f4SPaul Zimmerman * Initializes the HCD. This function allocates memory for and initializes the 4974197ba5f4SPaul Zimmerman * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the 4975197ba5f4SPaul Zimmerman * USB bus with the core and calls the hc_driver->start() function. It returns 4976197ba5f4SPaul Zimmerman * a negative error on failure. 4977197ba5f4SPaul Zimmerman */ 4978ecb176c6SMian Yousaf Kaukab int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq) 4979197ba5f4SPaul Zimmerman { 4980197ba5f4SPaul Zimmerman struct usb_hcd *hcd; 4981197ba5f4SPaul Zimmerman struct dwc2_host_chan *channel; 4982197ba5f4SPaul Zimmerman u32 hcfg; 4983197ba5f4SPaul Zimmerman int i, num_channels; 4984197ba5f4SPaul Zimmerman int retval; 4985197ba5f4SPaul Zimmerman 4986f5500eccSDinh Nguyen if (usb_disabled()) 4987f5500eccSDinh Nguyen return -ENODEV; 4988f5500eccSDinh Nguyen 4989197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n"); 4990197ba5f4SPaul Zimmerman 4991197ba5f4SPaul Zimmerman retval = -ENOMEM; 4992197ba5f4SPaul Zimmerman 499395c8bc36SAntti Seppälä hcfg = dwc2_readl(hsotg->regs + HCFG); 4994197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg); 4995197ba5f4SPaul Zimmerman 4996197ba5f4SPaul Zimmerman #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 4997197ba5f4SPaul Zimmerman hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) * 4998197ba5f4SPaul Zimmerman FRAME_NUM_ARRAY_SIZE, GFP_KERNEL); 4999197ba5f4SPaul Zimmerman if (!hsotg->frame_num_array) 5000197ba5f4SPaul Zimmerman goto error1; 5001197ba5f4SPaul Zimmerman hsotg->last_frame_num_array = kzalloc( 5002197ba5f4SPaul Zimmerman sizeof(*hsotg->last_frame_num_array) * 5003197ba5f4SPaul Zimmerman FRAME_NUM_ARRAY_SIZE, GFP_KERNEL); 5004197ba5f4SPaul Zimmerman if (!hsotg->last_frame_num_array) 5005197ba5f4SPaul Zimmerman goto error1; 5006197ba5f4SPaul Zimmerman #endif 5007483bb254SDouglas Anderson hsotg->last_frame_num = HFNUM_MAX_FRNUM; 5008197ba5f4SPaul Zimmerman 5009197ba5f4SPaul Zimmerman /* Check if the bus driver or platform code has setup a dma_mask */ 501095832c00SJohn Youn if (hsotg->params.host_dma && 50119da51974SJohn Youn !hsotg->dev->dma_mask) { 5012197ba5f4SPaul Zimmerman dev_warn(hsotg->dev, 5013197ba5f4SPaul Zimmerman "dma_mask not set, disabling DMA\n"); 5014fdb09b3eSNicholas Mc Guire hsotg->params.host_dma = false; 501595832c00SJohn Youn hsotg->params.dma_desc_enable = false; 5016197ba5f4SPaul Zimmerman } 5017197ba5f4SPaul Zimmerman 5018197ba5f4SPaul Zimmerman /* Set device flags indicating whether the HCD supports DMA */ 501995832c00SJohn Youn if (hsotg->params.host_dma) { 5020197ba5f4SPaul Zimmerman if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) 5021197ba5f4SPaul Zimmerman dev_warn(hsotg->dev, "can't set DMA mask\n"); 5022197ba5f4SPaul Zimmerman if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) 5023197ba5f4SPaul Zimmerman dev_warn(hsotg->dev, "can't set coherent DMA mask\n"); 5024197ba5f4SPaul Zimmerman } 5025197ba5f4SPaul Zimmerman 5026197ba5f4SPaul Zimmerman hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev)); 5027197ba5f4SPaul Zimmerman if (!hcd) 5028197ba5f4SPaul Zimmerman goto error1; 5029197ba5f4SPaul Zimmerman 503095832c00SJohn Youn if (!hsotg->params.host_dma) 5031197ba5f4SPaul Zimmerman hcd->self.uses_dma = 0; 5032197ba5f4SPaul Zimmerman 5033197ba5f4SPaul Zimmerman hcd->has_tt = 1; 5034197ba5f4SPaul Zimmerman 5035197ba5f4SPaul Zimmerman ((struct wrapper_priv_data *)&hcd->hcd_priv)->hsotg = hsotg; 5036197ba5f4SPaul Zimmerman hsotg->priv = hcd; 5037197ba5f4SPaul Zimmerman 5038197ba5f4SPaul Zimmerman /* 5039197ba5f4SPaul Zimmerman * Disable the global interrupt until all the interrupt handlers are 5040197ba5f4SPaul Zimmerman * installed 5041197ba5f4SPaul Zimmerman */ 5042197ba5f4SPaul Zimmerman dwc2_disable_global_interrupts(hsotg); 5043197ba5f4SPaul Zimmerman 5044197ba5f4SPaul Zimmerman /* Initialize the DWC_otg core, and select the Phy type */ 50450fe239bcSDouglas Anderson retval = dwc2_core_init(hsotg, true); 5046197ba5f4SPaul Zimmerman if (retval) 5047197ba5f4SPaul Zimmerman goto error2; 5048197ba5f4SPaul Zimmerman 5049197ba5f4SPaul Zimmerman /* Create new workqueue and init work */ 5050197ba5f4SPaul Zimmerman retval = -ENOMEM; 5051ec7b1268SBhaktipriya Shridhar hsotg->wq_otg = alloc_ordered_workqueue("dwc2", 0); 5052197ba5f4SPaul Zimmerman if (!hsotg->wq_otg) { 5053197ba5f4SPaul Zimmerman dev_err(hsotg->dev, "Failed to create workqueue\n"); 5054197ba5f4SPaul Zimmerman goto error2; 5055197ba5f4SPaul Zimmerman } 5056197ba5f4SPaul Zimmerman INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change); 5057197ba5f4SPaul Zimmerman 5058197ba5f4SPaul Zimmerman setup_timer(&hsotg->wkp_timer, dwc2_wakeup_detected, 5059197ba5f4SPaul Zimmerman (unsigned long)hsotg); 5060197ba5f4SPaul Zimmerman 5061197ba5f4SPaul Zimmerman /* Initialize the non-periodic schedule */ 5062197ba5f4SPaul Zimmerman INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive); 5063197ba5f4SPaul Zimmerman INIT_LIST_HEAD(&hsotg->non_periodic_sched_active); 5064197ba5f4SPaul Zimmerman 5065197ba5f4SPaul Zimmerman /* Initialize the periodic schedule */ 5066197ba5f4SPaul Zimmerman INIT_LIST_HEAD(&hsotg->periodic_sched_inactive); 5067197ba5f4SPaul Zimmerman INIT_LIST_HEAD(&hsotg->periodic_sched_ready); 5068197ba5f4SPaul Zimmerman INIT_LIST_HEAD(&hsotg->periodic_sched_assigned); 5069197ba5f4SPaul Zimmerman INIT_LIST_HEAD(&hsotg->periodic_sched_queued); 5070197ba5f4SPaul Zimmerman 5071c9c8ac01SDouglas Anderson INIT_LIST_HEAD(&hsotg->split_order); 5072c9c8ac01SDouglas Anderson 5073197ba5f4SPaul Zimmerman /* 5074197ba5f4SPaul Zimmerman * Create a host channel descriptor for each host channel implemented 5075197ba5f4SPaul Zimmerman * in the controller. Initialize the channel descriptor array. 5076197ba5f4SPaul Zimmerman */ 5077197ba5f4SPaul Zimmerman INIT_LIST_HEAD(&hsotg->free_hc_list); 5078bea8e86cSJohn Youn num_channels = hsotg->params.host_channels; 5079197ba5f4SPaul Zimmerman memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array)); 5080197ba5f4SPaul Zimmerman 5081197ba5f4SPaul Zimmerman for (i = 0; i < num_channels; i++) { 5082197ba5f4SPaul Zimmerman channel = kzalloc(sizeof(*channel), GFP_KERNEL); 50839da51974SJohn Youn if (!channel) 5084197ba5f4SPaul Zimmerman goto error3; 5085197ba5f4SPaul Zimmerman channel->hc_num = i; 5086c9c8ac01SDouglas Anderson INIT_LIST_HEAD(&channel->split_order_list_entry); 5087197ba5f4SPaul Zimmerman hsotg->hc_ptr_array[i] = channel; 5088197ba5f4SPaul Zimmerman } 5089197ba5f4SPaul Zimmerman 5090197ba5f4SPaul Zimmerman /* Initialize hsotg start work */ 5091197ba5f4SPaul Zimmerman INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func); 5092197ba5f4SPaul Zimmerman 5093197ba5f4SPaul Zimmerman /* Initialize port reset work */ 5094197ba5f4SPaul Zimmerman INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func); 5095197ba5f4SPaul Zimmerman 5096197ba5f4SPaul Zimmerman /* 5097197ba5f4SPaul Zimmerman * Allocate space for storing data on status transactions. Normally no 5098197ba5f4SPaul Zimmerman * data is sent, but this space acts as a bit bucket. This must be 5099197ba5f4SPaul Zimmerman * done after usb_add_hcd since that function allocates the DMA buffer 5100197ba5f4SPaul Zimmerman * pool. 5101197ba5f4SPaul Zimmerman */ 510295832c00SJohn Youn if (hsotg->params.host_dma) 5103197ba5f4SPaul Zimmerman hsotg->status_buf = dma_alloc_coherent(hsotg->dev, 5104197ba5f4SPaul Zimmerman DWC2_HCD_STATUS_BUF_SIZE, 5105197ba5f4SPaul Zimmerman &hsotg->status_buf_dma, GFP_KERNEL); 5106197ba5f4SPaul Zimmerman else 5107197ba5f4SPaul Zimmerman hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE, 5108197ba5f4SPaul Zimmerman GFP_KERNEL); 5109197ba5f4SPaul Zimmerman 5110197ba5f4SPaul Zimmerman if (!hsotg->status_buf) 5111197ba5f4SPaul Zimmerman goto error3; 5112197ba5f4SPaul Zimmerman 51133b5fcc9aSGregory Herrero /* 51143b5fcc9aSGregory Herrero * Create kmem caches to handle descriptor buffers in descriptor 51153b5fcc9aSGregory Herrero * DMA mode. 51163b5fcc9aSGregory Herrero * Alignment must be set to 512 bytes. 51173b5fcc9aSGregory Herrero */ 5118bea8e86cSJohn Youn if (hsotg->params.dma_desc_enable || 5119bea8e86cSJohn Youn hsotg->params.dma_desc_fs_enable) { 51203b5fcc9aSGregory Herrero hsotg->desc_gen_cache = kmem_cache_create("dwc2-gen-desc", 5121ec703251SVahram Aharonyan sizeof(struct dwc2_dma_desc) * 51223b5fcc9aSGregory Herrero MAX_DMA_DESC_NUM_GENERIC, 512, SLAB_CACHE_DMA, 51233b5fcc9aSGregory Herrero NULL); 51243b5fcc9aSGregory Herrero if (!hsotg->desc_gen_cache) { 51253b5fcc9aSGregory Herrero dev_err(hsotg->dev, 51263b5fcc9aSGregory Herrero "unable to create dwc2 generic desc cache\n"); 51273b5fcc9aSGregory Herrero 51283b5fcc9aSGregory Herrero /* 51293b5fcc9aSGregory Herrero * Disable descriptor dma mode since it will not be 51303b5fcc9aSGregory Herrero * usable. 51313b5fcc9aSGregory Herrero */ 513295832c00SJohn Youn hsotg->params.dma_desc_enable = false; 513395832c00SJohn Youn hsotg->params.dma_desc_fs_enable = false; 51343b5fcc9aSGregory Herrero } 51353b5fcc9aSGregory Herrero 51363b5fcc9aSGregory Herrero hsotg->desc_hsisoc_cache = kmem_cache_create("dwc2-hsisoc-desc", 5137ec703251SVahram Aharonyan sizeof(struct dwc2_dma_desc) * 51383b5fcc9aSGregory Herrero MAX_DMA_DESC_NUM_HS_ISOC, 512, 0, NULL); 51393b5fcc9aSGregory Herrero if (!hsotg->desc_hsisoc_cache) { 51403b5fcc9aSGregory Herrero dev_err(hsotg->dev, 51413b5fcc9aSGregory Herrero "unable to create dwc2 hs isoc desc cache\n"); 51423b5fcc9aSGregory Herrero 51433b5fcc9aSGregory Herrero kmem_cache_destroy(hsotg->desc_gen_cache); 51443b5fcc9aSGregory Herrero 51453b5fcc9aSGregory Herrero /* 51463b5fcc9aSGregory Herrero * Disable descriptor dma mode since it will not be 51473b5fcc9aSGregory Herrero * usable. 51483b5fcc9aSGregory Herrero */ 514995832c00SJohn Youn hsotg->params.dma_desc_enable = false; 515095832c00SJohn Youn hsotg->params.dma_desc_fs_enable = false; 51513b5fcc9aSGregory Herrero } 51523b5fcc9aSGregory Herrero } 51533b5fcc9aSGregory Herrero 5154197ba5f4SPaul Zimmerman hsotg->otg_port = 1; 5155197ba5f4SPaul Zimmerman hsotg->frame_list = NULL; 5156197ba5f4SPaul Zimmerman hsotg->frame_list_dma = 0; 5157197ba5f4SPaul Zimmerman hsotg->periodic_qh_count = 0; 5158197ba5f4SPaul Zimmerman 5159197ba5f4SPaul Zimmerman /* Initiate lx_state to L3 disconnected state */ 5160197ba5f4SPaul Zimmerman hsotg->lx_state = DWC2_L3; 5161197ba5f4SPaul Zimmerman 5162197ba5f4SPaul Zimmerman hcd->self.otg_port = hsotg->otg_port; 5163197ba5f4SPaul Zimmerman 5164197ba5f4SPaul Zimmerman /* Don't support SG list at this point */ 5165197ba5f4SPaul Zimmerman hcd->self.sg_tablesize = 0; 5166197ba5f4SPaul Zimmerman 51679df4ceacSMian Yousaf Kaukab if (!IS_ERR_OR_NULL(hsotg->uphy)) 51689df4ceacSMian Yousaf Kaukab otg_set_host(hsotg->uphy->otg, &hcd->self); 51699df4ceacSMian Yousaf Kaukab 5170197ba5f4SPaul Zimmerman /* 5171197ba5f4SPaul Zimmerman * Finish generic HCD initialization and start the HCD. This function 5172197ba5f4SPaul Zimmerman * allocates the DMA buffer pool, registers the USB bus, requests the 5173197ba5f4SPaul Zimmerman * IRQ line, and calls hcd_start method. 5174197ba5f4SPaul Zimmerman */ 5175197ba5f4SPaul Zimmerman retval = usb_add_hcd(hcd, irq, IRQF_SHARED); 5176197ba5f4SPaul Zimmerman if (retval < 0) 51773b5fcc9aSGregory Herrero goto error4; 5178197ba5f4SPaul Zimmerman 5179ec513b16SLinus Torvalds device_wakeup_enable(hcd->self.controller); 5180ec513b16SLinus Torvalds 5181197ba5f4SPaul Zimmerman dwc2_hcd_dump_state(hsotg); 5182197ba5f4SPaul Zimmerman 5183197ba5f4SPaul Zimmerman dwc2_enable_global_interrupts(hsotg); 5184197ba5f4SPaul Zimmerman 5185197ba5f4SPaul Zimmerman return 0; 5186197ba5f4SPaul Zimmerman 51873b5fcc9aSGregory Herrero error4: 51883b5fcc9aSGregory Herrero kmem_cache_destroy(hsotg->desc_gen_cache); 51893b5fcc9aSGregory Herrero kmem_cache_destroy(hsotg->desc_hsisoc_cache); 5190197ba5f4SPaul Zimmerman error3: 5191197ba5f4SPaul Zimmerman dwc2_hcd_release(hsotg); 5192197ba5f4SPaul Zimmerman error2: 5193197ba5f4SPaul Zimmerman usb_put_hcd(hcd); 5194197ba5f4SPaul Zimmerman error1: 5195197ba5f4SPaul Zimmerman 5196197ba5f4SPaul Zimmerman #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 5197197ba5f4SPaul Zimmerman kfree(hsotg->last_frame_num_array); 5198197ba5f4SPaul Zimmerman kfree(hsotg->frame_num_array); 5199197ba5f4SPaul Zimmerman #endif 5200197ba5f4SPaul Zimmerman 5201197ba5f4SPaul Zimmerman dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval); 5202197ba5f4SPaul Zimmerman return retval; 5203197ba5f4SPaul Zimmerman } 5204197ba5f4SPaul Zimmerman 5205197ba5f4SPaul Zimmerman /* 5206197ba5f4SPaul Zimmerman * Removes the HCD. 5207197ba5f4SPaul Zimmerman * Frees memory and resources associated with the HCD and deregisters the bus. 5208197ba5f4SPaul Zimmerman */ 5209197ba5f4SPaul Zimmerman void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) 5210197ba5f4SPaul Zimmerman { 5211197ba5f4SPaul Zimmerman struct usb_hcd *hcd; 5212197ba5f4SPaul Zimmerman 5213197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n"); 5214197ba5f4SPaul Zimmerman 5215197ba5f4SPaul Zimmerman hcd = dwc2_hsotg_to_hcd(hsotg); 5216197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd); 5217197ba5f4SPaul Zimmerman 5218197ba5f4SPaul Zimmerman if (!hcd) { 5219197ba5f4SPaul Zimmerman dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n", 5220197ba5f4SPaul Zimmerman __func__); 5221197ba5f4SPaul Zimmerman return; 5222197ba5f4SPaul Zimmerman } 5223197ba5f4SPaul Zimmerman 52249df4ceacSMian Yousaf Kaukab if (!IS_ERR_OR_NULL(hsotg->uphy)) 52259df4ceacSMian Yousaf Kaukab otg_set_host(hsotg->uphy->otg, NULL); 52269df4ceacSMian Yousaf Kaukab 5227197ba5f4SPaul Zimmerman usb_remove_hcd(hcd); 5228197ba5f4SPaul Zimmerman hsotg->priv = NULL; 52293b5fcc9aSGregory Herrero 52303b5fcc9aSGregory Herrero kmem_cache_destroy(hsotg->desc_gen_cache); 52313b5fcc9aSGregory Herrero kmem_cache_destroy(hsotg->desc_hsisoc_cache); 52323b5fcc9aSGregory Herrero 5233197ba5f4SPaul Zimmerman dwc2_hcd_release(hsotg); 5234197ba5f4SPaul Zimmerman usb_put_hcd(hcd); 5235197ba5f4SPaul Zimmerman 5236197ba5f4SPaul Zimmerman #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 5237197ba5f4SPaul Zimmerman kfree(hsotg->last_frame_num_array); 5238197ba5f4SPaul Zimmerman kfree(hsotg->frame_num_array); 5239197ba5f4SPaul Zimmerman #endif 5240197ba5f4SPaul Zimmerman } 524158e52ff6SJohn Youn 524258e52ff6SJohn Youn /** 524358e52ff6SJohn Youn * dwc2_backup_host_registers() - Backup controller host registers. 524458e52ff6SJohn Youn * When suspending usb bus, registers needs to be backuped 524558e52ff6SJohn Youn * if controller power is disabled once suspended. 524658e52ff6SJohn Youn * 524758e52ff6SJohn Youn * @hsotg: Programming view of the DWC_otg controller 524858e52ff6SJohn Youn */ 524958e52ff6SJohn Youn int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) 525058e52ff6SJohn Youn { 525158e52ff6SJohn Youn struct dwc2_hregs_backup *hr; 525258e52ff6SJohn Youn int i; 525358e52ff6SJohn Youn 525458e52ff6SJohn Youn dev_dbg(hsotg->dev, "%s\n", __func__); 525558e52ff6SJohn Youn 525658e52ff6SJohn Youn /* Backup Host regs */ 525758e52ff6SJohn Youn hr = &hsotg->hr_backup; 525858e52ff6SJohn Youn hr->hcfg = dwc2_readl(hsotg->regs + HCFG); 525958e52ff6SJohn Youn hr->haintmsk = dwc2_readl(hsotg->regs + HAINTMSK); 5260bea8e86cSJohn Youn for (i = 0; i < hsotg->params.host_channels; ++i) 526158e52ff6SJohn Youn hr->hcintmsk[i] = dwc2_readl(hsotg->regs + HCINTMSK(i)); 526258e52ff6SJohn Youn 526358e52ff6SJohn Youn hr->hprt0 = dwc2_read_hprt0(hsotg); 526458e52ff6SJohn Youn hr->hfir = dwc2_readl(hsotg->regs + HFIR); 526558e52ff6SJohn Youn hr->valid = true; 526658e52ff6SJohn Youn 526758e52ff6SJohn Youn return 0; 526858e52ff6SJohn Youn } 526958e52ff6SJohn Youn 527058e52ff6SJohn Youn /** 527158e52ff6SJohn Youn * dwc2_restore_host_registers() - Restore controller host registers. 527258e52ff6SJohn Youn * When resuming usb bus, device registers needs to be restored 527358e52ff6SJohn Youn * if controller power were disabled. 527458e52ff6SJohn Youn * 527558e52ff6SJohn Youn * @hsotg: Programming view of the DWC_otg controller 527658e52ff6SJohn Youn */ 527758e52ff6SJohn Youn int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) 527858e52ff6SJohn Youn { 527958e52ff6SJohn Youn struct dwc2_hregs_backup *hr; 528058e52ff6SJohn Youn int i; 528158e52ff6SJohn Youn 528258e52ff6SJohn Youn dev_dbg(hsotg->dev, "%s\n", __func__); 528358e52ff6SJohn Youn 528458e52ff6SJohn Youn /* Restore host regs */ 528558e52ff6SJohn Youn hr = &hsotg->hr_backup; 528658e52ff6SJohn Youn if (!hr->valid) { 528758e52ff6SJohn Youn dev_err(hsotg->dev, "%s: no host registers to restore\n", 528858e52ff6SJohn Youn __func__); 528958e52ff6SJohn Youn return -EINVAL; 529058e52ff6SJohn Youn } 529158e52ff6SJohn Youn hr->valid = false; 529258e52ff6SJohn Youn 529358e52ff6SJohn Youn dwc2_writel(hr->hcfg, hsotg->regs + HCFG); 529458e52ff6SJohn Youn dwc2_writel(hr->haintmsk, hsotg->regs + HAINTMSK); 529558e52ff6SJohn Youn 5296bea8e86cSJohn Youn for (i = 0; i < hsotg->params.host_channels; ++i) 529758e52ff6SJohn Youn dwc2_writel(hr->hcintmsk[i], hsotg->regs + HCINTMSK(i)); 529858e52ff6SJohn Youn 529958e52ff6SJohn Youn dwc2_writel(hr->hprt0, hsotg->regs + HPRT0); 530058e52ff6SJohn Youn dwc2_writel(hr->hfir, hsotg->regs + HFIR); 530158e52ff6SJohn Youn hsotg->frame_number = 0; 530258e52ff6SJohn Youn 530358e52ff6SJohn Youn return 0; 530458e52ff6SJohn Youn } 5305