15fd54aceSGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0 26fb914d7SGrigor Tovmasyan /* 347a1685fSDinh Nguyen * Copyright (c) 2011 Samsung Electronics Co., Ltd. 447a1685fSDinh Nguyen * http://www.samsung.com 547a1685fSDinh Nguyen * 647a1685fSDinh Nguyen * Copyright 2008 Openmoko, Inc. 747a1685fSDinh Nguyen * Copyright 2008 Simtec Electronics 847a1685fSDinh Nguyen * Ben Dooks <ben@simtec.co.uk> 947a1685fSDinh Nguyen * http://armlinux.simtec.co.uk/ 1047a1685fSDinh Nguyen * 1147a1685fSDinh Nguyen * S3C USB2.0 High-speed / OtG driver 1247a1685fSDinh Nguyen */ 1347a1685fSDinh Nguyen 1447a1685fSDinh Nguyen #include <linux/kernel.h> 1547a1685fSDinh Nguyen #include <linux/module.h> 1647a1685fSDinh Nguyen #include <linux/spinlock.h> 1747a1685fSDinh Nguyen #include <linux/interrupt.h> 1847a1685fSDinh Nguyen #include <linux/platform_device.h> 1947a1685fSDinh Nguyen #include <linux/dma-mapping.h> 207ad8096eSMarek Szyprowski #include <linux/mutex.h> 2147a1685fSDinh Nguyen #include <linux/seq_file.h> 2247a1685fSDinh Nguyen #include <linux/delay.h> 2347a1685fSDinh Nguyen #include <linux/io.h> 2447a1685fSDinh Nguyen #include <linux/slab.h> 2547a1685fSDinh Nguyen #include <linux/of_platform.h> 2647a1685fSDinh Nguyen 2747a1685fSDinh Nguyen #include <linux/usb/ch9.h> 2847a1685fSDinh Nguyen #include <linux/usb/gadget.h> 2947a1685fSDinh Nguyen #include <linux/usb/phy.h> 30b4c53b4aSMinas Harutyunyan #include <linux/usb/composite.h> 31b4c53b4aSMinas Harutyunyan 3247a1685fSDinh Nguyen 33f7c0b143SDinh Nguyen #include "core.h" 34941fcce4SDinh Nguyen #include "hw.h" 3547a1685fSDinh Nguyen 3647a1685fSDinh Nguyen /* conversion functions */ 371f91b4ccSFelipe Balbi static inline struct dwc2_hsotg_req *our_req(struct usb_request *req) 3847a1685fSDinh Nguyen { 391f91b4ccSFelipe Balbi return container_of(req, struct dwc2_hsotg_req, req); 4047a1685fSDinh Nguyen } 4147a1685fSDinh Nguyen 421f91b4ccSFelipe Balbi static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep) 4347a1685fSDinh Nguyen { 441f91b4ccSFelipe Balbi return container_of(ep, struct dwc2_hsotg_ep, ep); 4547a1685fSDinh Nguyen } 4647a1685fSDinh Nguyen 47941fcce4SDinh Nguyen static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget) 4847a1685fSDinh Nguyen { 49941fcce4SDinh Nguyen return container_of(gadget, struct dwc2_hsotg, gadget); 5047a1685fSDinh Nguyen } 5147a1685fSDinh Nguyen 52f25c42b8SGevorg Sahakyan static inline void dwc2_set_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val) 5347a1685fSDinh Nguyen { 54f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, dwc2_readl(hsotg, offset) | val, offset); 5547a1685fSDinh Nguyen } 5647a1685fSDinh Nguyen 57f25c42b8SGevorg Sahakyan static inline void dwc2_clear_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val) 5847a1685fSDinh Nguyen { 59f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, dwc2_readl(hsotg, offset) & ~val, offset); 6047a1685fSDinh Nguyen } 6147a1685fSDinh Nguyen 621f91b4ccSFelipe Balbi static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg, 63c6f5c050SMian Yousaf Kaukab u32 ep_index, u32 dir_in) 64c6f5c050SMian Yousaf Kaukab { 65c6f5c050SMian Yousaf Kaukab if (dir_in) 66c6f5c050SMian Yousaf Kaukab return hsotg->eps_in[ep_index]; 67c6f5c050SMian Yousaf Kaukab else 68c6f5c050SMian Yousaf Kaukab return hsotg->eps_out[ep_index]; 69c6f5c050SMian Yousaf Kaukab } 70c6f5c050SMian Yousaf Kaukab 71997f4f81SMickael Maison /* forward declaration of functions */ 721f91b4ccSFelipe Balbi static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg); 7347a1685fSDinh Nguyen 7447a1685fSDinh Nguyen /** 7547a1685fSDinh Nguyen * using_dma - return the DMA status of the driver. 7647a1685fSDinh Nguyen * @hsotg: The driver state. 7747a1685fSDinh Nguyen * 7847a1685fSDinh Nguyen * Return true if we're using DMA. 7947a1685fSDinh Nguyen * 8047a1685fSDinh Nguyen * Currently, we have the DMA support code worked into everywhere 8147a1685fSDinh Nguyen * that needs it, but the AMBA DMA implementation in the hardware can 8247a1685fSDinh Nguyen * only DMA from 32bit aligned addresses. This means that gadgets such 8347a1685fSDinh Nguyen * as the CDC Ethernet cannot work as they often pass packets which are 8447a1685fSDinh Nguyen * not 32bit aligned. 8547a1685fSDinh Nguyen * 8647a1685fSDinh Nguyen * Unfortunately the choice to use DMA or not is global to the controller 8747a1685fSDinh Nguyen * and seems to be only settable when the controller is being put through 8847a1685fSDinh Nguyen * a core reset. This means we either need to fix the gadgets to take 8947a1685fSDinh Nguyen * account of DMA alignment, or add bounce buffers (yuerk). 9047a1685fSDinh Nguyen * 91edd74be8SGregory Herrero * g_using_dma is set depending on dts flag. 9247a1685fSDinh Nguyen */ 93941fcce4SDinh Nguyen static inline bool using_dma(struct dwc2_hsotg *hsotg) 9447a1685fSDinh Nguyen { 9505ee799fSJohn Youn return hsotg->params.g_dma; 9647a1685fSDinh Nguyen } 9747a1685fSDinh Nguyen 98dec4b556SVahram Aharonyan /* 99dec4b556SVahram Aharonyan * using_desc_dma - return the descriptor DMA status of the driver. 100dec4b556SVahram Aharonyan * @hsotg: The driver state. 101dec4b556SVahram Aharonyan * 102dec4b556SVahram Aharonyan * Return true if we're using descriptor DMA. 103dec4b556SVahram Aharonyan */ 104dec4b556SVahram Aharonyan static inline bool using_desc_dma(struct dwc2_hsotg *hsotg) 105dec4b556SVahram Aharonyan { 106dec4b556SVahram Aharonyan return hsotg->params.g_dma_desc; 107dec4b556SVahram Aharonyan } 108dec4b556SVahram Aharonyan 10947a1685fSDinh Nguyen /** 11092d1635dSVardan Mikayelyan * dwc2_gadget_incr_frame_num - Increments the targeted frame number. 11192d1635dSVardan Mikayelyan * @hs_ep: The endpoint 11292d1635dSVardan Mikayelyan * 11392d1635dSVardan Mikayelyan * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT. 11492d1635dSVardan Mikayelyan * If an overrun occurs it will wrap the value and set the frame_overrun flag. 11592d1635dSVardan Mikayelyan */ 11692d1635dSVardan Mikayelyan static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep) 11792d1635dSVardan Mikayelyan { 118*91bb163eSMinas Harutyunyan struct dwc2_hsotg *hsotg = hs_ep->parent; 119*91bb163eSMinas Harutyunyan u16 limit = DSTS_SOFFN_LIMIT; 120*91bb163eSMinas Harutyunyan 121*91bb163eSMinas Harutyunyan if (hsotg->gadget.speed != USB_SPEED_HIGH) 122*91bb163eSMinas Harutyunyan limit >>= 3; 123*91bb163eSMinas Harutyunyan 12492d1635dSVardan Mikayelyan hs_ep->target_frame += hs_ep->interval; 125*91bb163eSMinas Harutyunyan if (hs_ep->target_frame > limit) { 126c1d5df69SGustavo A. R. Silva hs_ep->frame_overrun = true; 127*91bb163eSMinas Harutyunyan hs_ep->target_frame &= limit; 12892d1635dSVardan Mikayelyan } else { 129c1d5df69SGustavo A. R. Silva hs_ep->frame_overrun = false; 13092d1635dSVardan Mikayelyan } 13192d1635dSVardan Mikayelyan } 13292d1635dSVardan Mikayelyan 13392d1635dSVardan Mikayelyan /** 1349d630b9cSGrigor Tovmasyan * dwc2_gadget_dec_frame_num_by_one - Decrements the targeted frame number 1359d630b9cSGrigor Tovmasyan * by one. 1369d630b9cSGrigor Tovmasyan * @hs_ep: The endpoint. 1379d630b9cSGrigor Tovmasyan * 1389d630b9cSGrigor Tovmasyan * This function used in service interval based scheduling flow to calculate 1399d630b9cSGrigor Tovmasyan * descriptor frame number filed value. For service interval mode frame 1409d630b9cSGrigor Tovmasyan * number in descriptor should point to last (u)frame in the interval. 1419d630b9cSGrigor Tovmasyan * 1429d630b9cSGrigor Tovmasyan */ 1439d630b9cSGrigor Tovmasyan static inline void dwc2_gadget_dec_frame_num_by_one(struct dwc2_hsotg_ep *hs_ep) 1449d630b9cSGrigor Tovmasyan { 145*91bb163eSMinas Harutyunyan struct dwc2_hsotg *hsotg = hs_ep->parent; 146*91bb163eSMinas Harutyunyan u16 limit = DSTS_SOFFN_LIMIT; 147*91bb163eSMinas Harutyunyan 148*91bb163eSMinas Harutyunyan if (hsotg->gadget.speed != USB_SPEED_HIGH) 149*91bb163eSMinas Harutyunyan limit >>= 3; 150*91bb163eSMinas Harutyunyan 1519d630b9cSGrigor Tovmasyan if (hs_ep->target_frame) 1529d630b9cSGrigor Tovmasyan hs_ep->target_frame -= 1; 1539d630b9cSGrigor Tovmasyan else 154*91bb163eSMinas Harutyunyan hs_ep->target_frame = limit; 1559d630b9cSGrigor Tovmasyan } 1569d630b9cSGrigor Tovmasyan 1579d630b9cSGrigor Tovmasyan /** 1581f91b4ccSFelipe Balbi * dwc2_hsotg_en_gsint - enable one or more of the general interrupt 15947a1685fSDinh Nguyen * @hsotg: The device state 16047a1685fSDinh Nguyen * @ints: A bitmask of the interrupts to enable 16147a1685fSDinh Nguyen */ 1621f91b4ccSFelipe Balbi static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints) 16347a1685fSDinh Nguyen { 164f25c42b8SGevorg Sahakyan u32 gsintmsk = dwc2_readl(hsotg, GINTMSK); 16547a1685fSDinh Nguyen u32 new_gsintmsk; 16647a1685fSDinh Nguyen 16747a1685fSDinh Nguyen new_gsintmsk = gsintmsk | ints; 16847a1685fSDinh Nguyen 16947a1685fSDinh Nguyen if (new_gsintmsk != gsintmsk) { 17047a1685fSDinh Nguyen dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk); 171f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, new_gsintmsk, GINTMSK); 17247a1685fSDinh Nguyen } 17347a1685fSDinh Nguyen } 17447a1685fSDinh Nguyen 17547a1685fSDinh Nguyen /** 1761f91b4ccSFelipe Balbi * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt 17747a1685fSDinh Nguyen * @hsotg: The device state 17847a1685fSDinh Nguyen * @ints: A bitmask of the interrupts to enable 17947a1685fSDinh Nguyen */ 1801f91b4ccSFelipe Balbi static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints) 18147a1685fSDinh Nguyen { 182f25c42b8SGevorg Sahakyan u32 gsintmsk = dwc2_readl(hsotg, GINTMSK); 18347a1685fSDinh Nguyen u32 new_gsintmsk; 18447a1685fSDinh Nguyen 18547a1685fSDinh Nguyen new_gsintmsk = gsintmsk & ~ints; 18647a1685fSDinh Nguyen 18747a1685fSDinh Nguyen if (new_gsintmsk != gsintmsk) 188f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, new_gsintmsk, GINTMSK); 18947a1685fSDinh Nguyen } 19047a1685fSDinh Nguyen 19147a1685fSDinh Nguyen /** 1921f91b4ccSFelipe Balbi * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq 19347a1685fSDinh Nguyen * @hsotg: The device state 19447a1685fSDinh Nguyen * @ep: The endpoint index 19547a1685fSDinh Nguyen * @dir_in: True if direction is in. 19647a1685fSDinh Nguyen * @en: The enable value, true to enable 19747a1685fSDinh Nguyen * 19847a1685fSDinh Nguyen * Set or clear the mask for an individual endpoint's interrupt 19947a1685fSDinh Nguyen * request. 20047a1685fSDinh Nguyen */ 2011f91b4ccSFelipe Balbi static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg, 20247a1685fSDinh Nguyen unsigned int ep, unsigned int dir_in, 20347a1685fSDinh Nguyen unsigned int en) 20447a1685fSDinh Nguyen { 20547a1685fSDinh Nguyen unsigned long flags; 20647a1685fSDinh Nguyen u32 bit = 1 << ep; 20747a1685fSDinh Nguyen u32 daint; 20847a1685fSDinh Nguyen 20947a1685fSDinh Nguyen if (!dir_in) 21047a1685fSDinh Nguyen bit <<= 16; 21147a1685fSDinh Nguyen 21247a1685fSDinh Nguyen local_irq_save(flags); 213f25c42b8SGevorg Sahakyan daint = dwc2_readl(hsotg, DAINTMSK); 21447a1685fSDinh Nguyen if (en) 21547a1685fSDinh Nguyen daint |= bit; 21647a1685fSDinh Nguyen else 21747a1685fSDinh Nguyen daint &= ~bit; 218f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, daint, DAINTMSK); 21947a1685fSDinh Nguyen local_irq_restore(flags); 22047a1685fSDinh Nguyen } 22147a1685fSDinh Nguyen 22247a1685fSDinh Nguyen /** 223c138ecfaSSevak Arakelyan * dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode 2246fb914d7SGrigor Tovmasyan * 2256fb914d7SGrigor Tovmasyan * @hsotg: Programming view of the DWC_otg controller 226c138ecfaSSevak Arakelyan */ 227c138ecfaSSevak Arakelyan int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg) 228c138ecfaSSevak Arakelyan { 229c138ecfaSSevak Arakelyan if (hsotg->hw_params.en_multiple_tx_fifo) 230c138ecfaSSevak Arakelyan /* In dedicated FIFO mode we need count of IN EPs */ 2319273083aSMinas Harutyunyan return hsotg->hw_params.num_dev_in_eps; 232c138ecfaSSevak Arakelyan else 233c138ecfaSSevak Arakelyan /* In shared FIFO mode we need count of Periodic IN EPs */ 234c138ecfaSSevak Arakelyan return hsotg->hw_params.num_dev_perio_in_ep; 235c138ecfaSSevak Arakelyan } 236c138ecfaSSevak Arakelyan 237c138ecfaSSevak Arakelyan /** 238c138ecfaSSevak Arakelyan * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for 239c138ecfaSSevak Arakelyan * device mode TX FIFOs 2406fb914d7SGrigor Tovmasyan * 2416fb914d7SGrigor Tovmasyan * @hsotg: Programming view of the DWC_otg controller 242c138ecfaSSevak Arakelyan */ 243c138ecfaSSevak Arakelyan int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg) 244c138ecfaSSevak Arakelyan { 245c138ecfaSSevak Arakelyan int addr; 246c138ecfaSSevak Arakelyan int tx_addr_max; 247c138ecfaSSevak Arakelyan u32 np_tx_fifo_size; 248c138ecfaSSevak Arakelyan 249c138ecfaSSevak Arakelyan np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size, 250c138ecfaSSevak Arakelyan hsotg->params.g_np_tx_fifo_size); 251c138ecfaSSevak Arakelyan 252c138ecfaSSevak Arakelyan /* Get Endpoint Info Control block size in DWORDs. */ 2539273083aSMinas Harutyunyan tx_addr_max = hsotg->hw_params.total_fifo_size; 254c138ecfaSSevak Arakelyan 255c138ecfaSSevak Arakelyan addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size; 256c138ecfaSSevak Arakelyan if (tx_addr_max <= addr) 257c138ecfaSSevak Arakelyan return 0; 258c138ecfaSSevak Arakelyan 259c138ecfaSSevak Arakelyan return tx_addr_max - addr; 260c138ecfaSSevak Arakelyan } 261c138ecfaSSevak Arakelyan 262c138ecfaSSevak Arakelyan /** 263187c5298SGrigor Tovmasyan * dwc2_gadget_wkup_alert_handler - Handler for WKUP_ALERT interrupt 264187c5298SGrigor Tovmasyan * 265187c5298SGrigor Tovmasyan * @hsotg: Programming view of the DWC_otg controller 266187c5298SGrigor Tovmasyan * 267187c5298SGrigor Tovmasyan */ 268187c5298SGrigor Tovmasyan static void dwc2_gadget_wkup_alert_handler(struct dwc2_hsotg *hsotg) 269187c5298SGrigor Tovmasyan { 270187c5298SGrigor Tovmasyan u32 gintsts2; 271187c5298SGrigor Tovmasyan u32 gintmsk2; 272187c5298SGrigor Tovmasyan 273187c5298SGrigor Tovmasyan gintsts2 = dwc2_readl(hsotg, GINTSTS2); 274187c5298SGrigor Tovmasyan gintmsk2 = dwc2_readl(hsotg, GINTMSK2); 2759607f3cdSLee Jones gintsts2 &= gintmsk2; 276187c5298SGrigor Tovmasyan 277187c5298SGrigor Tovmasyan if (gintsts2 & GINTSTS2_WKUP_ALERT_INT) { 278187c5298SGrigor Tovmasyan dev_dbg(hsotg->dev, "%s: Wkup_Alert_Int\n", __func__); 27987b6d2c5SMinas Harutyunyan dwc2_set_bit(hsotg, GINTSTS2, GINTSTS2_WKUP_ALERT_INT); 280d64bc8eeSArtur Petrosyan dwc2_set_bit(hsotg, DCTL, DCTL_RMTWKUPSIG); 281187c5298SGrigor Tovmasyan } 282187c5298SGrigor Tovmasyan } 283187c5298SGrigor Tovmasyan 284187c5298SGrigor Tovmasyan /** 285c138ecfaSSevak Arakelyan * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode 286c138ecfaSSevak Arakelyan * TX FIFOs 2876fb914d7SGrigor Tovmasyan * 2886fb914d7SGrigor Tovmasyan * @hsotg: Programming view of the DWC_otg controller 289c138ecfaSSevak Arakelyan */ 290c138ecfaSSevak Arakelyan int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg) 291c138ecfaSSevak Arakelyan { 292c138ecfaSSevak Arakelyan int tx_fifo_count; 293c138ecfaSSevak Arakelyan int tx_fifo_depth; 294c138ecfaSSevak Arakelyan 295c138ecfaSSevak Arakelyan tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg); 296c138ecfaSSevak Arakelyan 297c138ecfaSSevak Arakelyan tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 298c138ecfaSSevak Arakelyan 299c138ecfaSSevak Arakelyan if (!tx_fifo_count) 300c138ecfaSSevak Arakelyan return tx_fifo_depth; 301c138ecfaSSevak Arakelyan else 302c138ecfaSSevak Arakelyan return tx_fifo_depth / tx_fifo_count; 303c138ecfaSSevak Arakelyan } 304c138ecfaSSevak Arakelyan 305c138ecfaSSevak Arakelyan /** 3061f91b4ccSFelipe Balbi * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs 30747a1685fSDinh Nguyen * @hsotg: The device instance. 30847a1685fSDinh Nguyen */ 3091f91b4ccSFelipe Balbi static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg) 31047a1685fSDinh Nguyen { 3112317eacdSJohn Youn unsigned int ep; 31247a1685fSDinh Nguyen unsigned int addr; 31347a1685fSDinh Nguyen int timeout; 31479d6b8c5SSevak Arakelyan 31547a1685fSDinh Nguyen u32 val; 31605ee799fSJohn Youn u32 *txfsz = hsotg->params.g_tx_fifo_size; 31747a1685fSDinh Nguyen 3187fcbc95cSGregory Herrero /* Reset fifo map if not correctly cleared during previous session */ 3197fcbc95cSGregory Herrero WARN_ON(hsotg->fifo_map); 3207fcbc95cSGregory Herrero hsotg->fifo_map = 0; 3217fcbc95cSGregory Herrero 3220a176279SGregory Herrero /* set RX/NPTX FIFO sizes */ 323f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, hsotg->params.g_rx_fifo_size, GRXFSIZ); 324f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, (hsotg->params.g_rx_fifo_size << 325f25c42b8SGevorg Sahakyan FIFOSIZE_STARTADDR_SHIFT) | 32605ee799fSJohn Youn (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT), 327f25c42b8SGevorg Sahakyan GNPTXFSIZ); 32847a1685fSDinh Nguyen 32947a1685fSDinh Nguyen /* 33047a1685fSDinh Nguyen * arange all the rest of the TX FIFOs, as some versions of this 33147a1685fSDinh Nguyen * block have overlapping default addresses. This also ensures 33247a1685fSDinh Nguyen * that if the settings have been changed, then they are set to 33347a1685fSDinh Nguyen * known values. 33447a1685fSDinh Nguyen */ 33547a1685fSDinh Nguyen 33647a1685fSDinh Nguyen /* start at the end of the GNPTXFSIZ, rounded up */ 33705ee799fSJohn Youn addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size; 33847a1685fSDinh Nguyen 33947a1685fSDinh Nguyen /* 3400a176279SGregory Herrero * Configure fifos sizes from provided configuration and assign 341b203d0a2SRobert Baldyga * them to endpoints dynamically according to maxpacket size value of 342b203d0a2SRobert Baldyga * given endpoint. 34347a1685fSDinh Nguyen */ 3442317eacdSJohn Youn for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) { 34505ee799fSJohn Youn if (!txfsz[ep]) 3463fa95385SJohn Youn continue; 3473fa95385SJohn Youn val = addr; 34805ee799fSJohn Youn val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT; 34905ee799fSJohn Youn WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem, 3503fa95385SJohn Youn "insufficient fifo memory"); 35105ee799fSJohn Youn addr += txfsz[ep]; 35247a1685fSDinh Nguyen 353f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, val, DPTXFSIZN(ep)); 354f25c42b8SGevorg Sahakyan val = dwc2_readl(hsotg, DPTXFSIZN(ep)); 35547a1685fSDinh Nguyen } 35647a1685fSDinh Nguyen 357f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, hsotg->hw_params.total_fifo_size | 358f87c842fSSevak Arakelyan addr << GDFIFOCFG_EPINFOBASE_SHIFT, 359f25c42b8SGevorg Sahakyan GDFIFOCFG); 36047a1685fSDinh Nguyen /* 36147a1685fSDinh Nguyen * according to p428 of the design guide, we need to ensure that 36247a1685fSDinh Nguyen * all fifos are flushed before continuing 36347a1685fSDinh Nguyen */ 36447a1685fSDinh Nguyen 365f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | 366f25c42b8SGevorg Sahakyan GRSTCTL_RXFFLSH, GRSTCTL); 36747a1685fSDinh Nguyen 36847a1685fSDinh Nguyen /* wait until the fifos are both flushed */ 36947a1685fSDinh Nguyen timeout = 100; 37047a1685fSDinh Nguyen while (1) { 371f25c42b8SGevorg Sahakyan val = dwc2_readl(hsotg, GRSTCTL); 37247a1685fSDinh Nguyen 37347a1685fSDinh Nguyen if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0) 37447a1685fSDinh Nguyen break; 37547a1685fSDinh Nguyen 37647a1685fSDinh Nguyen if (--timeout == 0) { 37747a1685fSDinh Nguyen dev_err(hsotg->dev, 37847a1685fSDinh Nguyen "%s: timeout flushing fifos (GRSTCTL=%08x)\n", 37947a1685fSDinh Nguyen __func__, val); 38048b20bcbSGregory Herrero break; 38147a1685fSDinh Nguyen } 38247a1685fSDinh Nguyen 38347a1685fSDinh Nguyen udelay(1); 38447a1685fSDinh Nguyen } 38547a1685fSDinh Nguyen 38647a1685fSDinh Nguyen dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout); 38747a1685fSDinh Nguyen } 38847a1685fSDinh Nguyen 38947a1685fSDinh Nguyen /** 3906fb914d7SGrigor Tovmasyan * dwc2_hsotg_ep_alloc_request - allocate USB rerequest structure 39147a1685fSDinh Nguyen * @ep: USB endpoint to allocate request for. 39247a1685fSDinh Nguyen * @flags: Allocation flags 39347a1685fSDinh Nguyen * 39447a1685fSDinh Nguyen * Allocate a new USB request structure appropriate for the specified endpoint 39547a1685fSDinh Nguyen */ 3961f91b4ccSFelipe Balbi static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep, 39747a1685fSDinh Nguyen gfp_t flags) 39847a1685fSDinh Nguyen { 3991f91b4ccSFelipe Balbi struct dwc2_hsotg_req *req; 40047a1685fSDinh Nguyen 401ec33efe2SJohn Youn req = kzalloc(sizeof(*req), flags); 40247a1685fSDinh Nguyen if (!req) 40347a1685fSDinh Nguyen return NULL; 40447a1685fSDinh Nguyen 40547a1685fSDinh Nguyen INIT_LIST_HEAD(&req->queue); 40647a1685fSDinh Nguyen 40747a1685fSDinh Nguyen return &req->req; 40847a1685fSDinh Nguyen } 40947a1685fSDinh Nguyen 41047a1685fSDinh Nguyen /** 41147a1685fSDinh Nguyen * is_ep_periodic - return true if the endpoint is in periodic mode. 41247a1685fSDinh Nguyen * @hs_ep: The endpoint to query. 41347a1685fSDinh Nguyen * 41447a1685fSDinh Nguyen * Returns true if the endpoint is in periodic mode, meaning it is being 41547a1685fSDinh Nguyen * used for an Interrupt or ISO transfer. 41647a1685fSDinh Nguyen */ 4171f91b4ccSFelipe Balbi static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep) 41847a1685fSDinh Nguyen { 41947a1685fSDinh Nguyen return hs_ep->periodic; 42047a1685fSDinh Nguyen } 42147a1685fSDinh Nguyen 42247a1685fSDinh Nguyen /** 4231f91b4ccSFelipe Balbi * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request 42447a1685fSDinh Nguyen * @hsotg: The device state. 42547a1685fSDinh Nguyen * @hs_ep: The endpoint for the request 42647a1685fSDinh Nguyen * @hs_req: The request being processed. 42747a1685fSDinh Nguyen * 4281f91b4ccSFelipe Balbi * This is the reverse of dwc2_hsotg_map_dma(), called for the completion 42947a1685fSDinh Nguyen * of a request to ensure the buffer is ready for access by the caller. 43047a1685fSDinh Nguyen */ 4311f91b4ccSFelipe Balbi static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg, 4321f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *hs_ep, 4331f91b4ccSFelipe Balbi struct dwc2_hsotg_req *hs_req) 43447a1685fSDinh Nguyen { 43547a1685fSDinh Nguyen struct usb_request *req = &hs_req->req; 4369da51974SJohn Youn 43775a41ce4SPhil Elwell usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->map_dir); 43847a1685fSDinh Nguyen } 43947a1685fSDinh Nguyen 4400f6b80c0SVahram Aharonyan /* 4410f6b80c0SVahram Aharonyan * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains 4420f6b80c0SVahram Aharonyan * for Control endpoint 4430f6b80c0SVahram Aharonyan * @hsotg: The device state. 4440f6b80c0SVahram Aharonyan * 4450f6b80c0SVahram Aharonyan * This function will allocate 4 descriptor chains for EP 0: 2 for 4460f6b80c0SVahram Aharonyan * Setup stage, per one for IN and OUT data/status transactions. 4470f6b80c0SVahram Aharonyan */ 4480f6b80c0SVahram Aharonyan static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg) 4490f6b80c0SVahram Aharonyan { 4500f6b80c0SVahram Aharonyan hsotg->setup_desc[0] = 4510f6b80c0SVahram Aharonyan dmam_alloc_coherent(hsotg->dev, 4520f6b80c0SVahram Aharonyan sizeof(struct dwc2_dma_desc), 4530f6b80c0SVahram Aharonyan &hsotg->setup_desc_dma[0], 4540f6b80c0SVahram Aharonyan GFP_KERNEL); 4550f6b80c0SVahram Aharonyan if (!hsotg->setup_desc[0]) 4560f6b80c0SVahram Aharonyan goto fail; 4570f6b80c0SVahram Aharonyan 4580f6b80c0SVahram Aharonyan hsotg->setup_desc[1] = 4590f6b80c0SVahram Aharonyan dmam_alloc_coherent(hsotg->dev, 4600f6b80c0SVahram Aharonyan sizeof(struct dwc2_dma_desc), 4610f6b80c0SVahram Aharonyan &hsotg->setup_desc_dma[1], 4620f6b80c0SVahram Aharonyan GFP_KERNEL); 4630f6b80c0SVahram Aharonyan if (!hsotg->setup_desc[1]) 4640f6b80c0SVahram Aharonyan goto fail; 4650f6b80c0SVahram Aharonyan 4660f6b80c0SVahram Aharonyan hsotg->ctrl_in_desc = 4670f6b80c0SVahram Aharonyan dmam_alloc_coherent(hsotg->dev, 4680f6b80c0SVahram Aharonyan sizeof(struct dwc2_dma_desc), 4690f6b80c0SVahram Aharonyan &hsotg->ctrl_in_desc_dma, 4700f6b80c0SVahram Aharonyan GFP_KERNEL); 4710f6b80c0SVahram Aharonyan if (!hsotg->ctrl_in_desc) 4720f6b80c0SVahram Aharonyan goto fail; 4730f6b80c0SVahram Aharonyan 4740f6b80c0SVahram Aharonyan hsotg->ctrl_out_desc = 4750f6b80c0SVahram Aharonyan dmam_alloc_coherent(hsotg->dev, 4760f6b80c0SVahram Aharonyan sizeof(struct dwc2_dma_desc), 4770f6b80c0SVahram Aharonyan &hsotg->ctrl_out_desc_dma, 4780f6b80c0SVahram Aharonyan GFP_KERNEL); 4790f6b80c0SVahram Aharonyan if (!hsotg->ctrl_out_desc) 4800f6b80c0SVahram Aharonyan goto fail; 4810f6b80c0SVahram Aharonyan 4820f6b80c0SVahram Aharonyan return 0; 4830f6b80c0SVahram Aharonyan 4840f6b80c0SVahram Aharonyan fail: 4850f6b80c0SVahram Aharonyan return -ENOMEM; 4860f6b80c0SVahram Aharonyan } 4870f6b80c0SVahram Aharonyan 48847a1685fSDinh Nguyen /** 4891f91b4ccSFelipe Balbi * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO 49047a1685fSDinh Nguyen * @hsotg: The controller state. 49147a1685fSDinh Nguyen * @hs_ep: The endpoint we're going to write for. 49247a1685fSDinh Nguyen * @hs_req: The request to write data for. 49347a1685fSDinh Nguyen * 49447a1685fSDinh Nguyen * This is called when the TxFIFO has some space in it to hold a new 49547a1685fSDinh Nguyen * transmission and we have something to give it. The actual setup of 49647a1685fSDinh Nguyen * the data size is done elsewhere, so all we have to do is to actually 49747a1685fSDinh Nguyen * write the data. 49847a1685fSDinh Nguyen * 49947a1685fSDinh Nguyen * The return value is zero if there is more space (or nothing was done) 50047a1685fSDinh Nguyen * otherwise -ENOSPC is returned if the FIFO space was used up. 50147a1685fSDinh Nguyen * 50247a1685fSDinh Nguyen * This routine is only needed for PIO 50347a1685fSDinh Nguyen */ 5041f91b4ccSFelipe Balbi static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg, 5051f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *hs_ep, 5061f91b4ccSFelipe Balbi struct dwc2_hsotg_req *hs_req) 50747a1685fSDinh Nguyen { 50847a1685fSDinh Nguyen bool periodic = is_ep_periodic(hs_ep); 509f25c42b8SGevorg Sahakyan u32 gnptxsts = dwc2_readl(hsotg, GNPTXSTS); 51047a1685fSDinh Nguyen int buf_pos = hs_req->req.actual; 51147a1685fSDinh Nguyen int to_write = hs_ep->size_loaded; 51247a1685fSDinh Nguyen void *data; 51347a1685fSDinh Nguyen int can_write; 51447a1685fSDinh Nguyen int pkt_round; 51547a1685fSDinh Nguyen int max_transfer; 51647a1685fSDinh Nguyen 51747a1685fSDinh Nguyen to_write -= (buf_pos - hs_ep->last_load); 51847a1685fSDinh Nguyen 51947a1685fSDinh Nguyen /* if there's nothing to write, get out early */ 52047a1685fSDinh Nguyen if (to_write == 0) 52147a1685fSDinh Nguyen return 0; 52247a1685fSDinh Nguyen 52347a1685fSDinh Nguyen if (periodic && !hsotg->dedicated_fifos) { 524f25c42b8SGevorg Sahakyan u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index)); 52547a1685fSDinh Nguyen int size_left; 52647a1685fSDinh Nguyen int size_done; 52747a1685fSDinh Nguyen 52847a1685fSDinh Nguyen /* 52947a1685fSDinh Nguyen * work out how much data was loaded so we can calculate 53047a1685fSDinh Nguyen * how much data is left in the fifo. 53147a1685fSDinh Nguyen */ 53247a1685fSDinh Nguyen 53347a1685fSDinh Nguyen size_left = DXEPTSIZ_XFERSIZE_GET(epsize); 53447a1685fSDinh Nguyen 53547a1685fSDinh Nguyen /* 53647a1685fSDinh Nguyen * if shared fifo, we cannot write anything until the 53747a1685fSDinh Nguyen * previous data has been completely sent. 53847a1685fSDinh Nguyen */ 53947a1685fSDinh Nguyen if (hs_ep->fifo_load != 0) { 5401f91b4ccSFelipe Balbi dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); 54147a1685fSDinh Nguyen return -ENOSPC; 54247a1685fSDinh Nguyen } 54347a1685fSDinh Nguyen 54447a1685fSDinh Nguyen dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n", 54547a1685fSDinh Nguyen __func__, size_left, 54647a1685fSDinh Nguyen hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size); 54747a1685fSDinh Nguyen 54847a1685fSDinh Nguyen /* how much of the data has moved */ 54947a1685fSDinh Nguyen size_done = hs_ep->size_loaded - size_left; 55047a1685fSDinh Nguyen 55147a1685fSDinh Nguyen /* how much data is left in the fifo */ 55247a1685fSDinh Nguyen can_write = hs_ep->fifo_load - size_done; 55347a1685fSDinh Nguyen dev_dbg(hsotg->dev, "%s: => can_write1=%d\n", 55447a1685fSDinh Nguyen __func__, can_write); 55547a1685fSDinh Nguyen 55647a1685fSDinh Nguyen can_write = hs_ep->fifo_size - can_write; 55747a1685fSDinh Nguyen dev_dbg(hsotg->dev, "%s: => can_write2=%d\n", 55847a1685fSDinh Nguyen __func__, can_write); 55947a1685fSDinh Nguyen 56047a1685fSDinh Nguyen if (can_write <= 0) { 5611f91b4ccSFelipe Balbi dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); 56247a1685fSDinh Nguyen return -ENOSPC; 56347a1685fSDinh Nguyen } 56447a1685fSDinh Nguyen } else if (hsotg->dedicated_fifos && hs_ep->index != 0) { 565f25c42b8SGevorg Sahakyan can_write = dwc2_readl(hsotg, 566ad674a15SRobert Baldyga DTXFSTS(hs_ep->fifo_index)); 56747a1685fSDinh Nguyen 56847a1685fSDinh Nguyen can_write &= 0xffff; 56947a1685fSDinh Nguyen can_write *= 4; 57047a1685fSDinh Nguyen } else { 57147a1685fSDinh Nguyen if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) { 57247a1685fSDinh Nguyen dev_dbg(hsotg->dev, 57347a1685fSDinh Nguyen "%s: no queue slots available (0x%08x)\n", 57447a1685fSDinh Nguyen __func__, gnptxsts); 57547a1685fSDinh Nguyen 5761f91b4ccSFelipe Balbi dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP); 57747a1685fSDinh Nguyen return -ENOSPC; 57847a1685fSDinh Nguyen } 57947a1685fSDinh Nguyen 58047a1685fSDinh Nguyen can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts); 58147a1685fSDinh Nguyen can_write *= 4; /* fifo size is in 32bit quantities. */ 58247a1685fSDinh Nguyen } 58347a1685fSDinh Nguyen 58447a1685fSDinh Nguyen max_transfer = hs_ep->ep.maxpacket * hs_ep->mc; 58547a1685fSDinh Nguyen 58647a1685fSDinh Nguyen dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n", 58747a1685fSDinh Nguyen __func__, gnptxsts, can_write, to_write, max_transfer); 58847a1685fSDinh Nguyen 58947a1685fSDinh Nguyen /* 59047a1685fSDinh Nguyen * limit to 512 bytes of data, it seems at least on the non-periodic 59147a1685fSDinh Nguyen * FIFO, requests of >512 cause the endpoint to get stuck with a 59247a1685fSDinh Nguyen * fragment of the end of the transfer in it. 59347a1685fSDinh Nguyen */ 59447a1685fSDinh Nguyen if (can_write > 512 && !periodic) 59547a1685fSDinh Nguyen can_write = 512; 59647a1685fSDinh Nguyen 59747a1685fSDinh Nguyen /* 59847a1685fSDinh Nguyen * limit the write to one max-packet size worth of data, but allow 59947a1685fSDinh Nguyen * the transfer to return that it did not run out of fifo space 60047a1685fSDinh Nguyen * doing it. 60147a1685fSDinh Nguyen */ 60247a1685fSDinh Nguyen if (to_write > max_transfer) { 60347a1685fSDinh Nguyen to_write = max_transfer; 60447a1685fSDinh Nguyen 60547a1685fSDinh Nguyen /* it's needed only when we do not use dedicated fifos */ 60647a1685fSDinh Nguyen if (!hsotg->dedicated_fifos) 6071f91b4ccSFelipe Balbi dwc2_hsotg_en_gsint(hsotg, 60847a1685fSDinh Nguyen periodic ? GINTSTS_PTXFEMP : 60947a1685fSDinh Nguyen GINTSTS_NPTXFEMP); 61047a1685fSDinh Nguyen } 61147a1685fSDinh Nguyen 61247a1685fSDinh Nguyen /* see if we can write data */ 61347a1685fSDinh Nguyen 61447a1685fSDinh Nguyen if (to_write > can_write) { 61547a1685fSDinh Nguyen to_write = can_write; 61647a1685fSDinh Nguyen pkt_round = to_write % max_transfer; 61747a1685fSDinh Nguyen 61847a1685fSDinh Nguyen /* 61947a1685fSDinh Nguyen * Round the write down to an 62047a1685fSDinh Nguyen * exact number of packets. 62147a1685fSDinh Nguyen * 62247a1685fSDinh Nguyen * Note, we do not currently check to see if we can ever 62347a1685fSDinh Nguyen * write a full packet or not to the FIFO. 62447a1685fSDinh Nguyen */ 62547a1685fSDinh Nguyen 62647a1685fSDinh Nguyen if (pkt_round) 62747a1685fSDinh Nguyen to_write -= pkt_round; 62847a1685fSDinh Nguyen 62947a1685fSDinh Nguyen /* 63047a1685fSDinh Nguyen * enable correct FIFO interrupt to alert us when there 63147a1685fSDinh Nguyen * is more room left. 63247a1685fSDinh Nguyen */ 63347a1685fSDinh Nguyen 63447a1685fSDinh Nguyen /* it's needed only when we do not use dedicated fifos */ 63547a1685fSDinh Nguyen if (!hsotg->dedicated_fifos) 6361f91b4ccSFelipe Balbi dwc2_hsotg_en_gsint(hsotg, 63747a1685fSDinh Nguyen periodic ? GINTSTS_PTXFEMP : 63847a1685fSDinh Nguyen GINTSTS_NPTXFEMP); 63947a1685fSDinh Nguyen } 64047a1685fSDinh Nguyen 64147a1685fSDinh Nguyen dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n", 64247a1685fSDinh Nguyen to_write, hs_req->req.length, can_write, buf_pos); 64347a1685fSDinh Nguyen 64447a1685fSDinh Nguyen if (to_write <= 0) 64547a1685fSDinh Nguyen return -ENOSPC; 64647a1685fSDinh Nguyen 64747a1685fSDinh Nguyen hs_req->req.actual = buf_pos + to_write; 64847a1685fSDinh Nguyen hs_ep->total_data += to_write; 64947a1685fSDinh Nguyen 65047a1685fSDinh Nguyen if (periodic) 65147a1685fSDinh Nguyen hs_ep->fifo_load += to_write; 65247a1685fSDinh Nguyen 65347a1685fSDinh Nguyen to_write = DIV_ROUND_UP(to_write, 4); 65447a1685fSDinh Nguyen data = hs_req->req.buf + buf_pos; 65547a1685fSDinh Nguyen 656342ccce1SGevorg Sahakyan dwc2_writel_rep(hsotg, EPFIFO(hs_ep->index), data, to_write); 65747a1685fSDinh Nguyen 65847a1685fSDinh Nguyen return (to_write >= can_write) ? -ENOSPC : 0; 65947a1685fSDinh Nguyen } 66047a1685fSDinh Nguyen 66147a1685fSDinh Nguyen /** 66247a1685fSDinh Nguyen * get_ep_limit - get the maximum data legnth for this endpoint 66347a1685fSDinh Nguyen * @hs_ep: The endpoint 66447a1685fSDinh Nguyen * 66547a1685fSDinh Nguyen * Return the maximum data that can be queued in one go on a given endpoint 66647a1685fSDinh Nguyen * so that transfers that are too long can be split. 66747a1685fSDinh Nguyen */ 6689da51974SJohn Youn static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep) 66947a1685fSDinh Nguyen { 67047a1685fSDinh Nguyen int index = hs_ep->index; 6719da51974SJohn Youn unsigned int maxsize; 6729da51974SJohn Youn unsigned int maxpkt; 67347a1685fSDinh Nguyen 67447a1685fSDinh Nguyen if (index != 0) { 67547a1685fSDinh Nguyen maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1; 67647a1685fSDinh Nguyen maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1; 67747a1685fSDinh Nguyen } else { 67847a1685fSDinh Nguyen maxsize = 64 + 64; 67947a1685fSDinh Nguyen if (hs_ep->dir_in) 68047a1685fSDinh Nguyen maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1; 68147a1685fSDinh Nguyen else 68247a1685fSDinh Nguyen maxpkt = 2; 68347a1685fSDinh Nguyen } 68447a1685fSDinh Nguyen 68547a1685fSDinh Nguyen /* we made the constant loading easier above by using +1 */ 68647a1685fSDinh Nguyen maxpkt--; 68747a1685fSDinh Nguyen maxsize--; 68847a1685fSDinh Nguyen 68947a1685fSDinh Nguyen /* 69047a1685fSDinh Nguyen * constrain by packet count if maxpkts*pktsize is greater 69147a1685fSDinh Nguyen * than the length register size. 69247a1685fSDinh Nguyen */ 69347a1685fSDinh Nguyen 69447a1685fSDinh Nguyen if ((maxpkt * hs_ep->ep.maxpacket) < maxsize) 69547a1685fSDinh Nguyen maxsize = maxpkt * hs_ep->ep.maxpacket; 69647a1685fSDinh Nguyen 69747a1685fSDinh Nguyen return maxsize; 69847a1685fSDinh Nguyen } 69947a1685fSDinh Nguyen 70047a1685fSDinh Nguyen /** 701381fc8f8SVardan Mikayelyan * dwc2_hsotg_read_frameno - read current frame number 702381fc8f8SVardan Mikayelyan * @hsotg: The device instance 703381fc8f8SVardan Mikayelyan * 704381fc8f8SVardan Mikayelyan * Return the current frame number 705381fc8f8SVardan Mikayelyan */ 706381fc8f8SVardan Mikayelyan static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg) 707381fc8f8SVardan Mikayelyan { 708381fc8f8SVardan Mikayelyan u32 dsts; 709381fc8f8SVardan Mikayelyan 710f25c42b8SGevorg Sahakyan dsts = dwc2_readl(hsotg, DSTS); 711381fc8f8SVardan Mikayelyan dsts &= DSTS_SOFFN_MASK; 712381fc8f8SVardan Mikayelyan dsts >>= DSTS_SOFFN_SHIFT; 713381fc8f8SVardan Mikayelyan 714381fc8f8SVardan Mikayelyan return dsts; 715381fc8f8SVardan Mikayelyan } 716381fc8f8SVardan Mikayelyan 717381fc8f8SVardan Mikayelyan /** 718cf77b5fbSVahram Aharonyan * dwc2_gadget_get_chain_limit - get the maximum data payload value of the 719cf77b5fbSVahram Aharonyan * DMA descriptor chain prepared for specific endpoint 720cf77b5fbSVahram Aharonyan * @hs_ep: The endpoint 721cf77b5fbSVahram Aharonyan * 722cf77b5fbSVahram Aharonyan * Return the maximum data that can be queued in one go on a given endpoint 723cf77b5fbSVahram Aharonyan * depending on its descriptor chain capacity so that transfers that 724cf77b5fbSVahram Aharonyan * are too long can be split. 725cf77b5fbSVahram Aharonyan */ 726cf77b5fbSVahram Aharonyan static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep) 727cf77b5fbSVahram Aharonyan { 728b2c586ebSMinas Harutyunyan const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc; 729cf77b5fbSVahram Aharonyan int is_isoc = hs_ep->isochronous; 730cf77b5fbSVahram Aharonyan unsigned int maxsize; 731b2c586ebSMinas Harutyunyan u32 mps = hs_ep->ep.maxpacket; 732b2c586ebSMinas Harutyunyan int dir_in = hs_ep->dir_in; 733cf77b5fbSVahram Aharonyan 734cf77b5fbSVahram Aharonyan if (is_isoc) 73554f37f56SMinas Harutyunyan maxsize = (hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT : 73654f37f56SMinas Harutyunyan DEV_DMA_ISOC_RX_NBYTES_LIMIT) * 73754f37f56SMinas Harutyunyan MAX_DMA_DESC_NUM_HS_ISOC; 738cf77b5fbSVahram Aharonyan else 73954f37f56SMinas Harutyunyan maxsize = DEV_DMA_NBYTES_LIMIT * MAX_DMA_DESC_NUM_GENERIC; 740cf77b5fbSVahram Aharonyan 741b2c586ebSMinas Harutyunyan /* Interrupt OUT EP with mps not multiple of 4 */ 742b2c586ebSMinas Harutyunyan if (hs_ep->index) 743b2c586ebSMinas Harutyunyan if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4)) 744b2c586ebSMinas Harutyunyan maxsize = mps * MAX_DMA_DESC_NUM_GENERIC; 745b2c586ebSMinas Harutyunyan 746cf77b5fbSVahram Aharonyan return maxsize; 747cf77b5fbSVahram Aharonyan } 748cf77b5fbSVahram Aharonyan 749e02f9aa6SVahram Aharonyan /* 750e02f9aa6SVahram Aharonyan * dwc2_gadget_get_desc_params - get DMA descriptor parameters. 751e02f9aa6SVahram Aharonyan * @hs_ep: The endpoint 752e02f9aa6SVahram Aharonyan * @mask: RX/TX bytes mask to be defined 753e02f9aa6SVahram Aharonyan * 754e02f9aa6SVahram Aharonyan * Returns maximum data payload for one descriptor after analyzing endpoint 755e02f9aa6SVahram Aharonyan * characteristics. 756e02f9aa6SVahram Aharonyan * DMA descriptor transfer bytes limit depends on EP type: 757e02f9aa6SVahram Aharonyan * Control out - MPS, 758e02f9aa6SVahram Aharonyan * Isochronous - descriptor rx/tx bytes bitfield limit, 759e02f9aa6SVahram Aharonyan * Control In/Bulk/Interrupt - multiple of mps. This will allow to not 760e02f9aa6SVahram Aharonyan * have concatenations from various descriptors within one packet. 761b2c586ebSMinas Harutyunyan * Interrupt OUT - if mps not multiple of 4 then a single packet corresponds 762b2c586ebSMinas Harutyunyan * to a single descriptor. 763e02f9aa6SVahram Aharonyan * 764e02f9aa6SVahram Aharonyan * Selects corresponding mask for RX/TX bytes as well. 765e02f9aa6SVahram Aharonyan */ 766e02f9aa6SVahram Aharonyan static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask) 767e02f9aa6SVahram Aharonyan { 768b2c586ebSMinas Harutyunyan const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc; 769e02f9aa6SVahram Aharonyan u32 mps = hs_ep->ep.maxpacket; 770e02f9aa6SVahram Aharonyan int dir_in = hs_ep->dir_in; 771e02f9aa6SVahram Aharonyan u32 desc_size = 0; 772e02f9aa6SVahram Aharonyan 773e02f9aa6SVahram Aharonyan if (!hs_ep->index && !dir_in) { 774e02f9aa6SVahram Aharonyan desc_size = mps; 775e02f9aa6SVahram Aharonyan *mask = DEV_DMA_NBYTES_MASK; 776e02f9aa6SVahram Aharonyan } else if (hs_ep->isochronous) { 777e02f9aa6SVahram Aharonyan if (dir_in) { 778e02f9aa6SVahram Aharonyan desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT; 779e02f9aa6SVahram Aharonyan *mask = DEV_DMA_ISOC_TX_NBYTES_MASK; 780e02f9aa6SVahram Aharonyan } else { 781e02f9aa6SVahram Aharonyan desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT; 782e02f9aa6SVahram Aharonyan *mask = DEV_DMA_ISOC_RX_NBYTES_MASK; 783e02f9aa6SVahram Aharonyan } 784e02f9aa6SVahram Aharonyan } else { 785e02f9aa6SVahram Aharonyan desc_size = DEV_DMA_NBYTES_LIMIT; 786e02f9aa6SVahram Aharonyan *mask = DEV_DMA_NBYTES_MASK; 787e02f9aa6SVahram Aharonyan 788e02f9aa6SVahram Aharonyan /* Round down desc_size to be mps multiple */ 789e02f9aa6SVahram Aharonyan desc_size -= desc_size % mps; 790e02f9aa6SVahram Aharonyan } 791e02f9aa6SVahram Aharonyan 792b2c586ebSMinas Harutyunyan /* Interrupt OUT EP with mps not multiple of 4 */ 793b2c586ebSMinas Harutyunyan if (hs_ep->index) 794b2c586ebSMinas Harutyunyan if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4)) { 795b2c586ebSMinas Harutyunyan desc_size = mps; 796b2c586ebSMinas Harutyunyan *mask = DEV_DMA_NBYTES_MASK; 797b2c586ebSMinas Harutyunyan } 798b2c586ebSMinas Harutyunyan 799e02f9aa6SVahram Aharonyan return desc_size; 800e02f9aa6SVahram Aharonyan } 801e02f9aa6SVahram Aharonyan 80210209abeSAndrzej Pietrasiewicz static void dwc2_gadget_fill_nonisoc_xfer_ddma_one(struct dwc2_hsotg_ep *hs_ep, 80310209abeSAndrzej Pietrasiewicz struct dwc2_dma_desc **desc, 804e02f9aa6SVahram Aharonyan dma_addr_t dma_buff, 80510209abeSAndrzej Pietrasiewicz unsigned int len, 80610209abeSAndrzej Pietrasiewicz bool true_last) 807e02f9aa6SVahram Aharonyan { 808e02f9aa6SVahram Aharonyan int dir_in = hs_ep->dir_in; 809e02f9aa6SVahram Aharonyan u32 mps = hs_ep->ep.maxpacket; 810e02f9aa6SVahram Aharonyan u32 maxsize = 0; 811e02f9aa6SVahram Aharonyan u32 offset = 0; 812e02f9aa6SVahram Aharonyan u32 mask = 0; 813e02f9aa6SVahram Aharonyan int i; 814e02f9aa6SVahram Aharonyan 815e02f9aa6SVahram Aharonyan maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask); 816e02f9aa6SVahram Aharonyan 817e02f9aa6SVahram Aharonyan hs_ep->desc_count = (len / maxsize) + 818e02f9aa6SVahram Aharonyan ((len % maxsize) ? 1 : 0); 819e02f9aa6SVahram Aharonyan if (len == 0) 820e02f9aa6SVahram Aharonyan hs_ep->desc_count = 1; 821e02f9aa6SVahram Aharonyan 822e02f9aa6SVahram Aharonyan for (i = 0; i < hs_ep->desc_count; ++i) { 82310209abeSAndrzej Pietrasiewicz (*desc)->status = 0; 82410209abeSAndrzej Pietrasiewicz (*desc)->status |= (DEV_DMA_BUFF_STS_HBUSY 825e02f9aa6SVahram Aharonyan << DEV_DMA_BUFF_STS_SHIFT); 826e02f9aa6SVahram Aharonyan 827e02f9aa6SVahram Aharonyan if (len > maxsize) { 828e02f9aa6SVahram Aharonyan if (!hs_ep->index && !dir_in) 82910209abeSAndrzej Pietrasiewicz (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC); 830e02f9aa6SVahram Aharonyan 83110209abeSAndrzej Pietrasiewicz (*desc)->status |= 83210209abeSAndrzej Pietrasiewicz maxsize << DEV_DMA_NBYTES_SHIFT & mask; 83310209abeSAndrzej Pietrasiewicz (*desc)->buf = dma_buff + offset; 834e02f9aa6SVahram Aharonyan 835e02f9aa6SVahram Aharonyan len -= maxsize; 836e02f9aa6SVahram Aharonyan offset += maxsize; 837e02f9aa6SVahram Aharonyan } else { 83810209abeSAndrzej Pietrasiewicz if (true_last) 83910209abeSAndrzej Pietrasiewicz (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC); 840e02f9aa6SVahram Aharonyan 841e02f9aa6SVahram Aharonyan if (dir_in) 84210209abeSAndrzej Pietrasiewicz (*desc)->status |= (len % mps) ? DEV_DMA_SHORT : 84310209abeSAndrzej Pietrasiewicz ((hs_ep->send_zlp && true_last) ? 84410209abeSAndrzej Pietrasiewicz DEV_DMA_SHORT : 0); 845e02f9aa6SVahram Aharonyan 84610209abeSAndrzej Pietrasiewicz (*desc)->status |= 847e02f9aa6SVahram Aharonyan len << DEV_DMA_NBYTES_SHIFT & mask; 84810209abeSAndrzej Pietrasiewicz (*desc)->buf = dma_buff + offset; 849e02f9aa6SVahram Aharonyan } 850e02f9aa6SVahram Aharonyan 85110209abeSAndrzej Pietrasiewicz (*desc)->status &= ~DEV_DMA_BUFF_STS_MASK; 85210209abeSAndrzej Pietrasiewicz (*desc)->status |= (DEV_DMA_BUFF_STS_HREADY 853e02f9aa6SVahram Aharonyan << DEV_DMA_BUFF_STS_SHIFT); 85410209abeSAndrzej Pietrasiewicz (*desc)++; 855e02f9aa6SVahram Aharonyan } 856e02f9aa6SVahram Aharonyan } 857e02f9aa6SVahram Aharonyan 858540ccba0SVahram Aharonyan /* 85910209abeSAndrzej Pietrasiewicz * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain. 86010209abeSAndrzej Pietrasiewicz * @hs_ep: The endpoint 86110209abeSAndrzej Pietrasiewicz * @ureq: Request to transfer 86210209abeSAndrzej Pietrasiewicz * @offset: offset in bytes 86310209abeSAndrzej Pietrasiewicz * @len: Length of the transfer 86410209abeSAndrzej Pietrasiewicz * 86510209abeSAndrzej Pietrasiewicz * This function will iterate over descriptor chain and fill its entries 86610209abeSAndrzej Pietrasiewicz * with corresponding information based on transfer data. 86710209abeSAndrzej Pietrasiewicz */ 86810209abeSAndrzej Pietrasiewicz static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep, 869066cfd07SAndrzej Pietrasiewicz dma_addr_t dma_buff, 87010209abeSAndrzej Pietrasiewicz unsigned int len) 87110209abeSAndrzej Pietrasiewicz { 872066cfd07SAndrzej Pietrasiewicz struct usb_request *ureq = NULL; 87310209abeSAndrzej Pietrasiewicz struct dwc2_dma_desc *desc = hs_ep->desc_list; 87410209abeSAndrzej Pietrasiewicz struct scatterlist *sg; 87510209abeSAndrzej Pietrasiewicz int i; 87610209abeSAndrzej Pietrasiewicz u8 desc_count = 0; 87710209abeSAndrzej Pietrasiewicz 878066cfd07SAndrzej Pietrasiewicz if (hs_ep->req) 879066cfd07SAndrzej Pietrasiewicz ureq = &hs_ep->req->req; 880066cfd07SAndrzej Pietrasiewicz 88110209abeSAndrzej Pietrasiewicz /* non-DMA sg buffer */ 882066cfd07SAndrzej Pietrasiewicz if (!ureq || !ureq->num_sgs) { 88310209abeSAndrzej Pietrasiewicz dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc, 884066cfd07SAndrzej Pietrasiewicz dma_buff, len, true); 88510209abeSAndrzej Pietrasiewicz return; 88610209abeSAndrzej Pietrasiewicz } 88710209abeSAndrzej Pietrasiewicz 88810209abeSAndrzej Pietrasiewicz /* DMA sg buffer */ 88910209abeSAndrzej Pietrasiewicz for_each_sg(ureq->sg, sg, ureq->num_sgs, i) { 89010209abeSAndrzej Pietrasiewicz dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc, 89110209abeSAndrzej Pietrasiewicz sg_dma_address(sg) + sg->offset, sg_dma_len(sg), 89210209abeSAndrzej Pietrasiewicz sg_is_last(sg)); 89310209abeSAndrzej Pietrasiewicz desc_count += hs_ep->desc_count; 89410209abeSAndrzej Pietrasiewicz } 89510209abeSAndrzej Pietrasiewicz 89610209abeSAndrzej Pietrasiewicz hs_ep->desc_count = desc_count; 89710209abeSAndrzej Pietrasiewicz } 89810209abeSAndrzej Pietrasiewicz 89910209abeSAndrzej Pietrasiewicz /* 900540ccba0SVahram Aharonyan * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain. 901540ccba0SVahram Aharonyan * @hs_ep: The isochronous endpoint. 902540ccba0SVahram Aharonyan * @dma_buff: usb requests dma buffer. 903540ccba0SVahram Aharonyan * @len: usb request transfer length. 904540ccba0SVahram Aharonyan * 905729cac69SMinas Harutyunyan * Fills next free descriptor with the data of the arrived usb request, 906540ccba0SVahram Aharonyan * frame info, sets Last and IOC bits increments next_desc. If filled 907540ccba0SVahram Aharonyan * descriptor is not the first one, removes L bit from the previous descriptor 908540ccba0SVahram Aharonyan * status. 909540ccba0SVahram Aharonyan */ 910540ccba0SVahram Aharonyan static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep, 911540ccba0SVahram Aharonyan dma_addr_t dma_buff, unsigned int len) 912540ccba0SVahram Aharonyan { 913540ccba0SVahram Aharonyan struct dwc2_dma_desc *desc; 914540ccba0SVahram Aharonyan struct dwc2_hsotg *hsotg = hs_ep->parent; 915540ccba0SVahram Aharonyan u32 index; 916540ccba0SVahram Aharonyan u32 mask = 0; 9171d8e5c00SMinas Harutyunyan u8 pid = 0; 918540ccba0SVahram Aharonyan 919768a0741SLee Jones dwc2_gadget_get_desc_params(hs_ep, &mask); 920540ccba0SVahram Aharonyan 921729cac69SMinas Harutyunyan index = hs_ep->next_desc; 922540ccba0SVahram Aharonyan desc = &hs_ep->desc_list[index]; 923540ccba0SVahram Aharonyan 924729cac69SMinas Harutyunyan /* Check if descriptor chain full */ 925729cac69SMinas Harutyunyan if ((desc->status >> DEV_DMA_BUFF_STS_SHIFT) == 926729cac69SMinas Harutyunyan DEV_DMA_BUFF_STS_HREADY) { 927729cac69SMinas Harutyunyan dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__); 928729cac69SMinas Harutyunyan return 1; 929729cac69SMinas Harutyunyan } 930729cac69SMinas Harutyunyan 931540ccba0SVahram Aharonyan /* Clear L bit of previous desc if more than one entries in the chain */ 932540ccba0SVahram Aharonyan if (hs_ep->next_desc) 933540ccba0SVahram Aharonyan hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L; 934540ccba0SVahram Aharonyan 935540ccba0SVahram Aharonyan dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n", 936540ccba0SVahram Aharonyan __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index); 937540ccba0SVahram Aharonyan 938540ccba0SVahram Aharonyan desc->status = 0; 939540ccba0SVahram Aharonyan desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT); 940540ccba0SVahram Aharonyan 941540ccba0SVahram Aharonyan desc->buf = dma_buff; 942540ccba0SVahram Aharonyan desc->status |= (DEV_DMA_L | DEV_DMA_IOC | 943540ccba0SVahram Aharonyan ((len << DEV_DMA_NBYTES_SHIFT) & mask)); 944540ccba0SVahram Aharonyan 945540ccba0SVahram Aharonyan if (hs_ep->dir_in) { 9461d8e5c00SMinas Harutyunyan if (len) 9471d8e5c00SMinas Harutyunyan pid = DIV_ROUND_UP(len, hs_ep->ep.maxpacket); 9481d8e5c00SMinas Harutyunyan else 9491d8e5c00SMinas Harutyunyan pid = 1; 9501d8e5c00SMinas Harutyunyan desc->status |= ((pid << DEV_DMA_ISOC_PID_SHIFT) & 951540ccba0SVahram Aharonyan DEV_DMA_ISOC_PID_MASK) | 952540ccba0SVahram Aharonyan ((len % hs_ep->ep.maxpacket) ? 953540ccba0SVahram Aharonyan DEV_DMA_SHORT : 0) | 954540ccba0SVahram Aharonyan ((hs_ep->target_frame << 955540ccba0SVahram Aharonyan DEV_DMA_ISOC_FRNUM_SHIFT) & 956540ccba0SVahram Aharonyan DEV_DMA_ISOC_FRNUM_MASK); 957540ccba0SVahram Aharonyan } 958540ccba0SVahram Aharonyan 959540ccba0SVahram Aharonyan desc->status &= ~DEV_DMA_BUFF_STS_MASK; 960540ccba0SVahram Aharonyan desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT); 961540ccba0SVahram Aharonyan 962729cac69SMinas Harutyunyan /* Increment frame number by interval for IN */ 963729cac69SMinas Harutyunyan if (hs_ep->dir_in) 964729cac69SMinas Harutyunyan dwc2_gadget_incr_frame_num(hs_ep); 965729cac69SMinas Harutyunyan 966540ccba0SVahram Aharonyan /* Update index of last configured entry in the chain */ 967540ccba0SVahram Aharonyan hs_ep->next_desc++; 96854f37f56SMinas Harutyunyan if (hs_ep->next_desc >= MAX_DMA_DESC_NUM_HS_ISOC) 969729cac69SMinas Harutyunyan hs_ep->next_desc = 0; 970540ccba0SVahram Aharonyan 971540ccba0SVahram Aharonyan return 0; 972540ccba0SVahram Aharonyan } 973540ccba0SVahram Aharonyan 974540ccba0SVahram Aharonyan /* 975540ccba0SVahram Aharonyan * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA 976540ccba0SVahram Aharonyan * @hs_ep: The isochronous endpoint. 977540ccba0SVahram Aharonyan * 978729cac69SMinas Harutyunyan * Prepare descriptor chain for isochronous endpoints. Afterwards 979540ccba0SVahram Aharonyan * write DMA address to HW and enable the endpoint. 980540ccba0SVahram Aharonyan */ 981540ccba0SVahram Aharonyan static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep) 982540ccba0SVahram Aharonyan { 983540ccba0SVahram Aharonyan struct dwc2_hsotg *hsotg = hs_ep->parent; 984540ccba0SVahram Aharonyan struct dwc2_hsotg_req *hs_req, *treq; 985540ccba0SVahram Aharonyan int index = hs_ep->index; 986540ccba0SVahram Aharonyan int ret; 987729cac69SMinas Harutyunyan int i; 988540ccba0SVahram Aharonyan u32 dma_reg; 989540ccba0SVahram Aharonyan u32 depctl; 990540ccba0SVahram Aharonyan u32 ctrl; 991729cac69SMinas Harutyunyan struct dwc2_dma_desc *desc; 992540ccba0SVahram Aharonyan 993540ccba0SVahram Aharonyan if (list_empty(&hs_ep->queue)) { 9941ffba905SMinas Harutyunyan hs_ep->target_frame = TARGET_FRAME_INITIAL; 995540ccba0SVahram Aharonyan dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__); 996540ccba0SVahram Aharonyan return; 997540ccba0SVahram Aharonyan } 998540ccba0SVahram Aharonyan 999729cac69SMinas Harutyunyan /* Initialize descriptor chain by Host Busy status */ 100054f37f56SMinas Harutyunyan for (i = 0; i < MAX_DMA_DESC_NUM_HS_ISOC; i++) { 1001729cac69SMinas Harutyunyan desc = &hs_ep->desc_list[i]; 1002729cac69SMinas Harutyunyan desc->status = 0; 1003729cac69SMinas Harutyunyan desc->status |= (DEV_DMA_BUFF_STS_HBUSY 1004729cac69SMinas Harutyunyan << DEV_DMA_BUFF_STS_SHIFT); 1005729cac69SMinas Harutyunyan } 1006729cac69SMinas Harutyunyan 1007729cac69SMinas Harutyunyan hs_ep->next_desc = 0; 1008540ccba0SVahram Aharonyan list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) { 100910209abeSAndrzej Pietrasiewicz dma_addr_t dma_addr = hs_req->req.dma; 101010209abeSAndrzej Pietrasiewicz 101110209abeSAndrzej Pietrasiewicz if (hs_req->req.num_sgs) { 101210209abeSAndrzej Pietrasiewicz WARN_ON(hs_req->req.num_sgs > 1); 101310209abeSAndrzej Pietrasiewicz dma_addr = sg_dma_address(hs_req->req.sg); 101410209abeSAndrzej Pietrasiewicz } 101510209abeSAndrzej Pietrasiewicz ret = dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr, 1016540ccba0SVahram Aharonyan hs_req->req.length); 1017729cac69SMinas Harutyunyan if (ret) 1018540ccba0SVahram Aharonyan break; 1019540ccba0SVahram Aharonyan } 1020540ccba0SVahram Aharonyan 1021729cac69SMinas Harutyunyan hs_ep->compl_desc = 0; 1022540ccba0SVahram Aharonyan depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index); 1023540ccba0SVahram Aharonyan dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index); 1024540ccba0SVahram Aharonyan 1025540ccba0SVahram Aharonyan /* write descriptor chain address to control register */ 1026f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg); 1027540ccba0SVahram Aharonyan 1028f25c42b8SGevorg Sahakyan ctrl = dwc2_readl(hsotg, depctl); 1029540ccba0SVahram Aharonyan ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK; 1030f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, ctrl, depctl); 1031540ccba0SVahram Aharonyan } 1032540ccba0SVahram Aharonyan 1033*91bb163eSMinas Harutyunyan static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep); 1034*91bb163eSMinas Harutyunyan static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg, 1035*91bb163eSMinas Harutyunyan struct dwc2_hsotg_ep *hs_ep, 1036*91bb163eSMinas Harutyunyan struct dwc2_hsotg_req *hs_req, 1037*91bb163eSMinas Harutyunyan int result); 1038*91bb163eSMinas Harutyunyan 1039cf77b5fbSVahram Aharonyan /** 10401f91b4ccSFelipe Balbi * dwc2_hsotg_start_req - start a USB request from an endpoint's queue 104147a1685fSDinh Nguyen * @hsotg: The controller state. 104247a1685fSDinh Nguyen * @hs_ep: The endpoint to process a request for 104347a1685fSDinh Nguyen * @hs_req: The request to start. 104447a1685fSDinh Nguyen * @continuing: True if we are doing more for the current request. 104547a1685fSDinh Nguyen * 104647a1685fSDinh Nguyen * Start the given request running by setting the endpoint registers 104747a1685fSDinh Nguyen * appropriately, and writing any data to the FIFOs. 104847a1685fSDinh Nguyen */ 10491f91b4ccSFelipe Balbi static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg, 10501f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *hs_ep, 10511f91b4ccSFelipe Balbi struct dwc2_hsotg_req *hs_req, 105247a1685fSDinh Nguyen bool continuing) 105347a1685fSDinh Nguyen { 105447a1685fSDinh Nguyen struct usb_request *ureq = &hs_req->req; 105547a1685fSDinh Nguyen int index = hs_ep->index; 105647a1685fSDinh Nguyen int dir_in = hs_ep->dir_in; 105747a1685fSDinh Nguyen u32 epctrl_reg; 105847a1685fSDinh Nguyen u32 epsize_reg; 105947a1685fSDinh Nguyen u32 epsize; 106047a1685fSDinh Nguyen u32 ctrl; 10619da51974SJohn Youn unsigned int length; 10629da51974SJohn Youn unsigned int packets; 10639da51974SJohn Youn unsigned int maxreq; 1064aa3e8bc8SVahram Aharonyan unsigned int dma_reg; 106547a1685fSDinh Nguyen 106647a1685fSDinh Nguyen if (index != 0) { 106747a1685fSDinh Nguyen if (hs_ep->req && !continuing) { 106847a1685fSDinh Nguyen dev_err(hsotg->dev, "%s: active request\n", __func__); 106947a1685fSDinh Nguyen WARN_ON(1); 107047a1685fSDinh Nguyen return; 107147a1685fSDinh Nguyen } else if (hs_ep->req != hs_req && continuing) { 107247a1685fSDinh Nguyen dev_err(hsotg->dev, 107347a1685fSDinh Nguyen "%s: continue different req\n", __func__); 107447a1685fSDinh Nguyen WARN_ON(1); 107547a1685fSDinh Nguyen return; 107647a1685fSDinh Nguyen } 107747a1685fSDinh Nguyen } 107847a1685fSDinh Nguyen 1079aa3e8bc8SVahram Aharonyan dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index); 108047a1685fSDinh Nguyen epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); 108147a1685fSDinh Nguyen epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); 108247a1685fSDinh Nguyen 108347a1685fSDinh Nguyen dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n", 1084f25c42b8SGevorg Sahakyan __func__, dwc2_readl(hsotg, epctrl_reg), index, 108547a1685fSDinh Nguyen hs_ep->dir_in ? "in" : "out"); 108647a1685fSDinh Nguyen 108747a1685fSDinh Nguyen /* If endpoint is stalled, we will restart request later */ 1088f25c42b8SGevorg Sahakyan ctrl = dwc2_readl(hsotg, epctrl_reg); 108947a1685fSDinh Nguyen 1090b2d4c54eSMian Yousaf Kaukab if (index && ctrl & DXEPCTL_STALL) { 109147a1685fSDinh Nguyen dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index); 109247a1685fSDinh Nguyen return; 109347a1685fSDinh Nguyen } 109447a1685fSDinh Nguyen 109547a1685fSDinh Nguyen length = ureq->length - ureq->actual; 109647a1685fSDinh Nguyen dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n", 109747a1685fSDinh Nguyen ureq->length, ureq->actual); 109847a1685fSDinh Nguyen 1099cf77b5fbSVahram Aharonyan if (!using_desc_dma(hsotg)) 110047a1685fSDinh Nguyen maxreq = get_ep_limit(hs_ep); 1101cf77b5fbSVahram Aharonyan else 1102cf77b5fbSVahram Aharonyan maxreq = dwc2_gadget_get_chain_limit(hs_ep); 1103cf77b5fbSVahram Aharonyan 110447a1685fSDinh Nguyen if (length > maxreq) { 110547a1685fSDinh Nguyen int round = maxreq % hs_ep->ep.maxpacket; 110647a1685fSDinh Nguyen 110747a1685fSDinh Nguyen dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n", 110847a1685fSDinh Nguyen __func__, length, maxreq, round); 110947a1685fSDinh Nguyen 111047a1685fSDinh Nguyen /* round down to multiple of packets */ 111147a1685fSDinh Nguyen if (round) 111247a1685fSDinh Nguyen maxreq -= round; 111347a1685fSDinh Nguyen 111447a1685fSDinh Nguyen length = maxreq; 111547a1685fSDinh Nguyen } 111647a1685fSDinh Nguyen 111747a1685fSDinh Nguyen if (length) 111847a1685fSDinh Nguyen packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket); 111947a1685fSDinh Nguyen else 112047a1685fSDinh Nguyen packets = 1; /* send one packet if length is zero. */ 112147a1685fSDinh Nguyen 112247a1685fSDinh Nguyen if (dir_in && index != 0) 112347a1685fSDinh Nguyen if (hs_ep->isochronous) 112447a1685fSDinh Nguyen epsize = DXEPTSIZ_MC(packets); 112547a1685fSDinh Nguyen else 112647a1685fSDinh Nguyen epsize = DXEPTSIZ_MC(1); 112747a1685fSDinh Nguyen else 112847a1685fSDinh Nguyen epsize = 0; 112947a1685fSDinh Nguyen 113047a1685fSDinh Nguyen /* 1131f71b5e25SMian Yousaf Kaukab * zero length packet should be programmed on its own and should not 1132f71b5e25SMian Yousaf Kaukab * be counted in DIEPTSIZ.PktCnt with other packets. 113347a1685fSDinh Nguyen */ 1134f71b5e25SMian Yousaf Kaukab if (dir_in && ureq->zero && !continuing) { 1135f71b5e25SMian Yousaf Kaukab /* Test if zlp is actually required. */ 1136f71b5e25SMian Yousaf Kaukab if ((ureq->length >= hs_ep->ep.maxpacket) && 1137f71b5e25SMian Yousaf Kaukab !(ureq->length % hs_ep->ep.maxpacket)) 11388a20fa45SMian Yousaf Kaukab hs_ep->send_zlp = 1; 113947a1685fSDinh Nguyen } 114047a1685fSDinh Nguyen 114147a1685fSDinh Nguyen epsize |= DXEPTSIZ_PKTCNT(packets); 114247a1685fSDinh Nguyen epsize |= DXEPTSIZ_XFERSIZE(length); 114347a1685fSDinh Nguyen 114447a1685fSDinh Nguyen dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n", 114547a1685fSDinh Nguyen __func__, packets, length, ureq->length, epsize, epsize_reg); 114647a1685fSDinh Nguyen 114747a1685fSDinh Nguyen /* store the request as the current one we're doing */ 114847a1685fSDinh Nguyen hs_ep->req = hs_req; 114947a1685fSDinh Nguyen 1150aa3e8bc8SVahram Aharonyan if (using_desc_dma(hsotg)) { 1151aa3e8bc8SVahram Aharonyan u32 offset = 0; 1152aa3e8bc8SVahram Aharonyan u32 mps = hs_ep->ep.maxpacket; 1153aa3e8bc8SVahram Aharonyan 1154aa3e8bc8SVahram Aharonyan /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */ 1155aa3e8bc8SVahram Aharonyan if (!dir_in) { 1156aa3e8bc8SVahram Aharonyan if (!index) 1157aa3e8bc8SVahram Aharonyan length = mps; 1158aa3e8bc8SVahram Aharonyan else if (length % mps) 1159aa3e8bc8SVahram Aharonyan length += (mps - (length % mps)); 1160aa3e8bc8SVahram Aharonyan } 1161aa3e8bc8SVahram Aharonyan 1162b2c586ebSMinas Harutyunyan if (continuing) 1163aa3e8bc8SVahram Aharonyan offset = ureq->actual; 1164aa3e8bc8SVahram Aharonyan 1165aa3e8bc8SVahram Aharonyan /* Fill DDMA chain entries */ 1166066cfd07SAndrzej Pietrasiewicz dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset, 1167aa3e8bc8SVahram Aharonyan length); 1168aa3e8bc8SVahram Aharonyan 1169aa3e8bc8SVahram Aharonyan /* write descriptor chain address to control register */ 1170f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg); 1171aa3e8bc8SVahram Aharonyan 1172aa3e8bc8SVahram Aharonyan dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n", 1173aa3e8bc8SVahram Aharonyan __func__, (u32)hs_ep->desc_list_dma, dma_reg); 1174aa3e8bc8SVahram Aharonyan } else { 117547a1685fSDinh Nguyen /* write size / packets */ 1176f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, epsize, epsize_reg); 117747a1685fSDinh Nguyen 1178729e6574SRazmik Karapetyan if (using_dma(hsotg) && !continuing && (length != 0)) { 117947a1685fSDinh Nguyen /* 1180aa3e8bc8SVahram Aharonyan * write DMA address to control register, buffer 1181aa3e8bc8SVahram Aharonyan * already synced by dwc2_hsotg_ep_queue(). 118247a1685fSDinh Nguyen */ 118347a1685fSDinh Nguyen 1184f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, ureq->dma, dma_reg); 118547a1685fSDinh Nguyen 11860cc4cf6fSFabio Estevam dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n", 118747a1685fSDinh Nguyen __func__, &ureq->dma, dma_reg); 118847a1685fSDinh Nguyen } 1189aa3e8bc8SVahram Aharonyan } 119047a1685fSDinh Nguyen 1191*91bb163eSMinas Harutyunyan if (hs_ep->isochronous) { 1192*91bb163eSMinas Harutyunyan if (!dwc2_gadget_target_frame_elapsed(hs_ep)) { 1193*91bb163eSMinas Harutyunyan if (hs_ep->interval == 1) { 1194837e9f00SVardan Mikayelyan if (hs_ep->target_frame & 0x1) 1195837e9f00SVardan Mikayelyan ctrl |= DXEPCTL_SETODDFR; 1196837e9f00SVardan Mikayelyan else 1197837e9f00SVardan Mikayelyan ctrl |= DXEPCTL_SETEVENFR; 1198837e9f00SVardan Mikayelyan } 1199*91bb163eSMinas Harutyunyan ctrl |= DXEPCTL_CNAK; 1200*91bb163eSMinas Harutyunyan } else { 1201*91bb163eSMinas Harutyunyan dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, -ENODATA); 1202*91bb163eSMinas Harutyunyan return; 1203*91bb163eSMinas Harutyunyan } 1204*91bb163eSMinas Harutyunyan } 1205837e9f00SVardan Mikayelyan 120647a1685fSDinh Nguyen ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ 120747a1685fSDinh Nguyen 1208fe0b94abSMian Yousaf Kaukab dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state); 120947a1685fSDinh Nguyen 121047a1685fSDinh Nguyen /* For Setup request do not clear NAK */ 1211fe0b94abSMian Yousaf Kaukab if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP)) 121247a1685fSDinh Nguyen ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ 121347a1685fSDinh Nguyen 121447a1685fSDinh Nguyen dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); 1215f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, ctrl, epctrl_reg); 121647a1685fSDinh Nguyen 121747a1685fSDinh Nguyen /* 121847a1685fSDinh Nguyen * set these, it seems that DMA support increments past the end 121947a1685fSDinh Nguyen * of the packet buffer so we need to calculate the length from 122047a1685fSDinh Nguyen * this information. 122147a1685fSDinh Nguyen */ 122247a1685fSDinh Nguyen hs_ep->size_loaded = length; 122347a1685fSDinh Nguyen hs_ep->last_load = ureq->actual; 122447a1685fSDinh Nguyen 122547a1685fSDinh Nguyen if (dir_in && !using_dma(hsotg)) { 122647a1685fSDinh Nguyen /* set these anyway, we may need them for non-periodic in */ 122747a1685fSDinh Nguyen hs_ep->fifo_load = 0; 122847a1685fSDinh Nguyen 12291f91b4ccSFelipe Balbi dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req); 123047a1685fSDinh Nguyen } 123147a1685fSDinh Nguyen 123247a1685fSDinh Nguyen /* 123347a1685fSDinh Nguyen * Note, trying to clear the NAK here causes problems with transmit 123447a1685fSDinh Nguyen * on the S3C6400 ending up with the TXFIFO becoming full. 123547a1685fSDinh Nguyen */ 123647a1685fSDinh Nguyen 123747a1685fSDinh Nguyen /* check ep is enabled */ 1238f25c42b8SGevorg Sahakyan if (!(dwc2_readl(hsotg, epctrl_reg) & DXEPCTL_EPENA)) 12391a0ed863SMian Yousaf Kaukab dev_dbg(hsotg->dev, 124047a1685fSDinh Nguyen "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n", 1241f25c42b8SGevorg Sahakyan index, dwc2_readl(hsotg, epctrl_reg)); 124247a1685fSDinh Nguyen 124347a1685fSDinh Nguyen dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n", 1244f25c42b8SGevorg Sahakyan __func__, dwc2_readl(hsotg, epctrl_reg)); 124547a1685fSDinh Nguyen 124647a1685fSDinh Nguyen /* enable ep interrupts */ 12471f91b4ccSFelipe Balbi dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1); 124847a1685fSDinh Nguyen } 124947a1685fSDinh Nguyen 125047a1685fSDinh Nguyen /** 12511f91b4ccSFelipe Balbi * dwc2_hsotg_map_dma - map the DMA memory being used for the request 125247a1685fSDinh Nguyen * @hsotg: The device state. 125347a1685fSDinh Nguyen * @hs_ep: The endpoint the request is on. 125447a1685fSDinh Nguyen * @req: The request being processed. 125547a1685fSDinh Nguyen * 125647a1685fSDinh Nguyen * We've been asked to queue a request, so ensure that the memory buffer 125747a1685fSDinh Nguyen * is correctly setup for DMA. If we've been passed an extant DMA address 125847a1685fSDinh Nguyen * then ensure the buffer has been synced to memory. If our buffer has no 125947a1685fSDinh Nguyen * DMA memory, then we map the memory and mark our request to allow us to 126047a1685fSDinh Nguyen * cleanup on completion. 126147a1685fSDinh Nguyen */ 12621f91b4ccSFelipe Balbi static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg, 12631f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *hs_ep, 126447a1685fSDinh Nguyen struct usb_request *req) 126547a1685fSDinh Nguyen { 126647a1685fSDinh Nguyen int ret; 126747a1685fSDinh Nguyen 126875a41ce4SPhil Elwell hs_ep->map_dir = hs_ep->dir_in; 126947a1685fSDinh Nguyen ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in); 127047a1685fSDinh Nguyen if (ret) 127147a1685fSDinh Nguyen goto dma_error; 127247a1685fSDinh Nguyen 127347a1685fSDinh Nguyen return 0; 127447a1685fSDinh Nguyen 127547a1685fSDinh Nguyen dma_error: 127647a1685fSDinh Nguyen dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n", 127747a1685fSDinh Nguyen __func__, req->buf, req->length); 127847a1685fSDinh Nguyen 127947a1685fSDinh Nguyen return -EIO; 128047a1685fSDinh Nguyen } 128147a1685fSDinh Nguyen 12821f91b4ccSFelipe Balbi static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg, 1283b98866c2SJohn Youn struct dwc2_hsotg_ep *hs_ep, 1284b98866c2SJohn Youn struct dwc2_hsotg_req *hs_req) 12857d24c1b5SMian Yousaf Kaukab { 12867d24c1b5SMian Yousaf Kaukab void *req_buf = hs_req->req.buf; 12877d24c1b5SMian Yousaf Kaukab 12887d24c1b5SMian Yousaf Kaukab /* If dma is not being used or buffer is aligned */ 12897d24c1b5SMian Yousaf Kaukab if (!using_dma(hsotg) || !((long)req_buf & 3)) 12907d24c1b5SMian Yousaf Kaukab return 0; 12917d24c1b5SMian Yousaf Kaukab 12927d24c1b5SMian Yousaf Kaukab WARN_ON(hs_req->saved_req_buf); 12937d24c1b5SMian Yousaf Kaukab 12947d24c1b5SMian Yousaf Kaukab dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__, 12957d24c1b5SMian Yousaf Kaukab hs_ep->ep.name, req_buf, hs_req->req.length); 12967d24c1b5SMian Yousaf Kaukab 12977d24c1b5SMian Yousaf Kaukab hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC); 12987d24c1b5SMian Yousaf Kaukab if (!hs_req->req.buf) { 12997d24c1b5SMian Yousaf Kaukab hs_req->req.buf = req_buf; 13007d24c1b5SMian Yousaf Kaukab dev_err(hsotg->dev, 13017d24c1b5SMian Yousaf Kaukab "%s: unable to allocate memory for bounce buffer\n", 13027d24c1b5SMian Yousaf Kaukab __func__); 13037d24c1b5SMian Yousaf Kaukab return -ENOMEM; 13047d24c1b5SMian Yousaf Kaukab } 13057d24c1b5SMian Yousaf Kaukab 13067d24c1b5SMian Yousaf Kaukab /* Save actual buffer */ 13077d24c1b5SMian Yousaf Kaukab hs_req->saved_req_buf = req_buf; 13087d24c1b5SMian Yousaf Kaukab 13097d24c1b5SMian Yousaf Kaukab if (hs_ep->dir_in) 13107d24c1b5SMian Yousaf Kaukab memcpy(hs_req->req.buf, req_buf, hs_req->req.length); 13117d24c1b5SMian Yousaf Kaukab return 0; 13127d24c1b5SMian Yousaf Kaukab } 13137d24c1b5SMian Yousaf Kaukab 1314b98866c2SJohn Youn static void 1315b98866c2SJohn Youn dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg, 1316b98866c2SJohn Youn struct dwc2_hsotg_ep *hs_ep, 1317b98866c2SJohn Youn struct dwc2_hsotg_req *hs_req) 13187d24c1b5SMian Yousaf Kaukab { 13197d24c1b5SMian Yousaf Kaukab /* If dma is not being used or buffer was aligned */ 13207d24c1b5SMian Yousaf Kaukab if (!using_dma(hsotg) || !hs_req->saved_req_buf) 13217d24c1b5SMian Yousaf Kaukab return; 13227d24c1b5SMian Yousaf Kaukab 13237d24c1b5SMian Yousaf Kaukab dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__, 13247d24c1b5SMian Yousaf Kaukab hs_ep->ep.name, hs_req->req.status, hs_req->req.actual); 13257d24c1b5SMian Yousaf Kaukab 13267d24c1b5SMian Yousaf Kaukab /* Copy data from bounce buffer on successful out transfer */ 13277d24c1b5SMian Yousaf Kaukab if (!hs_ep->dir_in && !hs_req->req.status) 13287d24c1b5SMian Yousaf Kaukab memcpy(hs_req->saved_req_buf, hs_req->req.buf, 13297d24c1b5SMian Yousaf Kaukab hs_req->req.actual); 13307d24c1b5SMian Yousaf Kaukab 13317d24c1b5SMian Yousaf Kaukab /* Free bounce buffer */ 13327d24c1b5SMian Yousaf Kaukab kfree(hs_req->req.buf); 13337d24c1b5SMian Yousaf Kaukab 13347d24c1b5SMian Yousaf Kaukab hs_req->req.buf = hs_req->saved_req_buf; 13357d24c1b5SMian Yousaf Kaukab hs_req->saved_req_buf = NULL; 13367d24c1b5SMian Yousaf Kaukab } 13377d24c1b5SMian Yousaf Kaukab 1338381fc8f8SVardan Mikayelyan /** 1339381fc8f8SVardan Mikayelyan * dwc2_gadget_target_frame_elapsed - Checks target frame 1340381fc8f8SVardan Mikayelyan * @hs_ep: The driver endpoint to check 1341381fc8f8SVardan Mikayelyan * 1342381fc8f8SVardan Mikayelyan * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop 1343381fc8f8SVardan Mikayelyan * corresponding transfer. 1344381fc8f8SVardan Mikayelyan */ 1345381fc8f8SVardan Mikayelyan static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep) 1346381fc8f8SVardan Mikayelyan { 1347381fc8f8SVardan Mikayelyan struct dwc2_hsotg *hsotg = hs_ep->parent; 1348381fc8f8SVardan Mikayelyan u32 target_frame = hs_ep->target_frame; 1349c7c24e7aSArtur Petrosyan u32 current_frame = hsotg->frame_number; 1350381fc8f8SVardan Mikayelyan bool frame_overrun = hs_ep->frame_overrun; 1351*91bb163eSMinas Harutyunyan u16 limit = DSTS_SOFFN_LIMIT; 1352*91bb163eSMinas Harutyunyan 1353*91bb163eSMinas Harutyunyan if (hsotg->gadget.speed != USB_SPEED_HIGH) 1354*91bb163eSMinas Harutyunyan limit >>= 3; 1355381fc8f8SVardan Mikayelyan 1356381fc8f8SVardan Mikayelyan if (!frame_overrun && current_frame >= target_frame) 1357381fc8f8SVardan Mikayelyan return true; 1358381fc8f8SVardan Mikayelyan 1359381fc8f8SVardan Mikayelyan if (frame_overrun && current_frame >= target_frame && 1360*91bb163eSMinas Harutyunyan ((current_frame - target_frame) < limit / 2)) 1361381fc8f8SVardan Mikayelyan return true; 1362381fc8f8SVardan Mikayelyan 1363381fc8f8SVardan Mikayelyan return false; 1364381fc8f8SVardan Mikayelyan } 1365381fc8f8SVardan Mikayelyan 1366e02f9aa6SVahram Aharonyan /* 1367e02f9aa6SVahram Aharonyan * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers 1368e02f9aa6SVahram Aharonyan * @hsotg: The driver state 1369e02f9aa6SVahram Aharonyan * @hs_ep: the ep descriptor chain is for 1370e02f9aa6SVahram Aharonyan * 1371e02f9aa6SVahram Aharonyan * Called to update EP0 structure's pointers depend on stage of 1372e02f9aa6SVahram Aharonyan * control transfer. 1373e02f9aa6SVahram Aharonyan */ 1374e02f9aa6SVahram Aharonyan static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg, 1375e02f9aa6SVahram Aharonyan struct dwc2_hsotg_ep *hs_ep) 1376e02f9aa6SVahram Aharonyan { 1377e02f9aa6SVahram Aharonyan switch (hsotg->ep0_state) { 1378e02f9aa6SVahram Aharonyan case DWC2_EP0_SETUP: 1379e02f9aa6SVahram Aharonyan case DWC2_EP0_STATUS_OUT: 1380e02f9aa6SVahram Aharonyan hs_ep->desc_list = hsotg->setup_desc[0]; 1381e02f9aa6SVahram Aharonyan hs_ep->desc_list_dma = hsotg->setup_desc_dma[0]; 1382e02f9aa6SVahram Aharonyan break; 1383e02f9aa6SVahram Aharonyan case DWC2_EP0_DATA_IN: 1384e02f9aa6SVahram Aharonyan case DWC2_EP0_STATUS_IN: 1385e02f9aa6SVahram Aharonyan hs_ep->desc_list = hsotg->ctrl_in_desc; 1386e02f9aa6SVahram Aharonyan hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma; 1387e02f9aa6SVahram Aharonyan break; 1388e02f9aa6SVahram Aharonyan case DWC2_EP0_DATA_OUT: 1389e02f9aa6SVahram Aharonyan hs_ep->desc_list = hsotg->ctrl_out_desc; 1390e02f9aa6SVahram Aharonyan hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma; 1391e02f9aa6SVahram Aharonyan break; 1392e02f9aa6SVahram Aharonyan default: 1393e02f9aa6SVahram Aharonyan dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n", 1394e02f9aa6SVahram Aharonyan hsotg->ep0_state); 1395e02f9aa6SVahram Aharonyan return -EINVAL; 1396e02f9aa6SVahram Aharonyan } 1397e02f9aa6SVahram Aharonyan 1398e02f9aa6SVahram Aharonyan return 0; 1399e02f9aa6SVahram Aharonyan } 1400e02f9aa6SVahram Aharonyan 14011f91b4ccSFelipe Balbi static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req, 140247a1685fSDinh Nguyen gfp_t gfp_flags) 140347a1685fSDinh Nguyen { 14041f91b4ccSFelipe Balbi struct dwc2_hsotg_req *hs_req = our_req(req); 14051f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *hs_ep = our_ep(ep); 1406941fcce4SDinh Nguyen struct dwc2_hsotg *hs = hs_ep->parent; 140747a1685fSDinh Nguyen bool first; 14087d24c1b5SMian Yousaf Kaukab int ret; 1409729cac69SMinas Harutyunyan u32 maxsize = 0; 1410729cac69SMinas Harutyunyan u32 mask = 0; 1411729cac69SMinas Harutyunyan 141247a1685fSDinh Nguyen 141347a1685fSDinh Nguyen dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n", 141447a1685fSDinh Nguyen ep->name, req, req->length, req->buf, req->no_interrupt, 141547a1685fSDinh Nguyen req->zero, req->short_not_ok); 141647a1685fSDinh Nguyen 14177ababa92SGregory Herrero /* Prevent new request submission when controller is suspended */ 141888b02f2cSGrigor Tovmasyan if (hs->lx_state != DWC2_L0) { 141988b02f2cSGrigor Tovmasyan dev_dbg(hs->dev, "%s: submit request only in active state\n", 14207ababa92SGregory Herrero __func__); 14217ababa92SGregory Herrero return -EAGAIN; 14227ababa92SGregory Herrero } 14237ababa92SGregory Herrero 142447a1685fSDinh Nguyen /* initialise status of the request */ 142547a1685fSDinh Nguyen INIT_LIST_HEAD(&hs_req->queue); 142647a1685fSDinh Nguyen req->actual = 0; 142747a1685fSDinh Nguyen req->status = -EINPROGRESS; 142847a1685fSDinh Nguyen 1429860ef6cdSMinas Harutyunyan /* Don't queue ISOC request if length greater than mps*mc */ 1430860ef6cdSMinas Harutyunyan if (hs_ep->isochronous && 1431860ef6cdSMinas Harutyunyan req->length > (hs_ep->mc * hs_ep->ep.maxpacket)) { 1432860ef6cdSMinas Harutyunyan dev_err(hs->dev, "req length > maxpacket*mc\n"); 1433860ef6cdSMinas Harutyunyan return -EINVAL; 1434860ef6cdSMinas Harutyunyan } 1435860ef6cdSMinas Harutyunyan 1436729cac69SMinas Harutyunyan /* In DDMA mode for ISOC's don't queue request if length greater 1437729cac69SMinas Harutyunyan * than descriptor limits. 1438729cac69SMinas Harutyunyan */ 1439729cac69SMinas Harutyunyan if (using_desc_dma(hs) && hs_ep->isochronous) { 1440729cac69SMinas Harutyunyan maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask); 1441729cac69SMinas Harutyunyan if (hs_ep->dir_in && req->length > maxsize) { 1442729cac69SMinas Harutyunyan dev_err(hs->dev, "wrong length %d (maxsize=%d)\n", 1443729cac69SMinas Harutyunyan req->length, maxsize); 1444729cac69SMinas Harutyunyan return -EINVAL; 1445729cac69SMinas Harutyunyan } 1446729cac69SMinas Harutyunyan 1447729cac69SMinas Harutyunyan if (!hs_ep->dir_in && req->length > hs_ep->ep.maxpacket) { 1448729cac69SMinas Harutyunyan dev_err(hs->dev, "ISOC OUT: wrong length %d (mps=%d)\n", 1449729cac69SMinas Harutyunyan req->length, hs_ep->ep.maxpacket); 1450729cac69SMinas Harutyunyan return -EINVAL; 1451729cac69SMinas Harutyunyan } 1452729cac69SMinas Harutyunyan } 1453729cac69SMinas Harutyunyan 14541f91b4ccSFelipe Balbi ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req); 14557d24c1b5SMian Yousaf Kaukab if (ret) 14567d24c1b5SMian Yousaf Kaukab return ret; 14577d24c1b5SMian Yousaf Kaukab 145847a1685fSDinh Nguyen /* if we're using DMA, sync the buffers as necessary */ 145947a1685fSDinh Nguyen if (using_dma(hs)) { 14601f91b4ccSFelipe Balbi ret = dwc2_hsotg_map_dma(hs, hs_ep, req); 146147a1685fSDinh Nguyen if (ret) 146247a1685fSDinh Nguyen return ret; 146347a1685fSDinh Nguyen } 1464e02f9aa6SVahram Aharonyan /* If using descriptor DMA configure EP0 descriptor chain pointers */ 1465e02f9aa6SVahram Aharonyan if (using_desc_dma(hs) && !hs_ep->index) { 1466e02f9aa6SVahram Aharonyan ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep); 1467e02f9aa6SVahram Aharonyan if (ret) 1468e02f9aa6SVahram Aharonyan return ret; 1469e02f9aa6SVahram Aharonyan } 147047a1685fSDinh Nguyen 147147a1685fSDinh Nguyen first = list_empty(&hs_ep->queue); 147247a1685fSDinh Nguyen list_add_tail(&hs_req->queue, &hs_ep->queue); 147347a1685fSDinh Nguyen 1474540ccba0SVahram Aharonyan /* 1475540ccba0SVahram Aharonyan * Handle DDMA isochronous transfers separately - just add new entry 1476729cac69SMinas Harutyunyan * to the descriptor chain. 1477540ccba0SVahram Aharonyan * Transfer will be started once SW gets either one of NAK or 1478540ccba0SVahram Aharonyan * OutTknEpDis interrupts. 1479540ccba0SVahram Aharonyan */ 1480729cac69SMinas Harutyunyan if (using_desc_dma(hs) && hs_ep->isochronous) { 1481729cac69SMinas Harutyunyan if (hs_ep->target_frame != TARGET_FRAME_INITIAL) { 148210209abeSAndrzej Pietrasiewicz dma_addr_t dma_addr = hs_req->req.dma; 148310209abeSAndrzej Pietrasiewicz 148410209abeSAndrzej Pietrasiewicz if (hs_req->req.num_sgs) { 148510209abeSAndrzej Pietrasiewicz WARN_ON(hs_req->req.num_sgs > 1); 148610209abeSAndrzej Pietrasiewicz dma_addr = sg_dma_address(hs_req->req.sg); 148710209abeSAndrzej Pietrasiewicz } 148810209abeSAndrzej Pietrasiewicz dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr, 1489540ccba0SVahram Aharonyan hs_req->req.length); 1490729cac69SMinas Harutyunyan } 1491540ccba0SVahram Aharonyan return 0; 1492540ccba0SVahram Aharonyan } 1493540ccba0SVahram Aharonyan 1494b4c53b4aSMinas Harutyunyan /* Change EP direction if status phase request is after data out */ 1495b4c53b4aSMinas Harutyunyan if (!hs_ep->index && !req->length && !hs_ep->dir_in && 1496b4c53b4aSMinas Harutyunyan hs->ep0_state == DWC2_EP0_DATA_OUT) 1497b4c53b4aSMinas Harutyunyan hs_ep->dir_in = 1; 1498b4c53b4aSMinas Harutyunyan 1499837e9f00SVardan Mikayelyan if (first) { 1500837e9f00SVardan Mikayelyan if (!hs_ep->isochronous) { 15011f91b4ccSFelipe Balbi dwc2_hsotg_start_req(hs, hs_ep, hs_req, false); 1502837e9f00SVardan Mikayelyan return 0; 1503837e9f00SVardan Mikayelyan } 150447a1685fSDinh Nguyen 1505c7c24e7aSArtur Petrosyan /* Update current frame number value. */ 1506c7c24e7aSArtur Petrosyan hs->frame_number = dwc2_hsotg_read_frameno(hs); 1507c7c24e7aSArtur Petrosyan while (dwc2_gadget_target_frame_elapsed(hs_ep)) { 1508837e9f00SVardan Mikayelyan dwc2_gadget_incr_frame_num(hs_ep); 1509c7c24e7aSArtur Petrosyan /* Update current frame number value once more as it 1510c7c24e7aSArtur Petrosyan * changes here. 1511c7c24e7aSArtur Petrosyan */ 1512c7c24e7aSArtur Petrosyan hs->frame_number = dwc2_hsotg_read_frameno(hs); 1513c7c24e7aSArtur Petrosyan } 1514837e9f00SVardan Mikayelyan 1515837e9f00SVardan Mikayelyan if (hs_ep->target_frame != TARGET_FRAME_INITIAL) 1516837e9f00SVardan Mikayelyan dwc2_hsotg_start_req(hs, hs_ep, hs_req, false); 1517837e9f00SVardan Mikayelyan } 151847a1685fSDinh Nguyen return 0; 151947a1685fSDinh Nguyen } 152047a1685fSDinh Nguyen 15211f91b4ccSFelipe Balbi static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req, 152247a1685fSDinh Nguyen gfp_t gfp_flags) 152347a1685fSDinh Nguyen { 15241f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *hs_ep = our_ep(ep); 1525941fcce4SDinh Nguyen struct dwc2_hsotg *hs = hs_ep->parent; 15268879904bSJohan Hovold unsigned long flags; 15278879904bSJohan Hovold int ret; 152847a1685fSDinh Nguyen 152947a1685fSDinh Nguyen spin_lock_irqsave(&hs->lock, flags); 15301f91b4ccSFelipe Balbi ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags); 153147a1685fSDinh Nguyen spin_unlock_irqrestore(&hs->lock, flags); 153247a1685fSDinh Nguyen 153347a1685fSDinh Nguyen return ret; 153447a1685fSDinh Nguyen } 153547a1685fSDinh Nguyen 15361f91b4ccSFelipe Balbi static void dwc2_hsotg_ep_free_request(struct usb_ep *ep, 153747a1685fSDinh Nguyen struct usb_request *req) 153847a1685fSDinh Nguyen { 15391f91b4ccSFelipe Balbi struct dwc2_hsotg_req *hs_req = our_req(req); 154047a1685fSDinh Nguyen 154147a1685fSDinh Nguyen kfree(hs_req); 154247a1685fSDinh Nguyen } 154347a1685fSDinh Nguyen 154447a1685fSDinh Nguyen /** 15451f91b4ccSFelipe Balbi * dwc2_hsotg_complete_oursetup - setup completion callback 154647a1685fSDinh Nguyen * @ep: The endpoint the request was on. 154747a1685fSDinh Nguyen * @req: The request completed. 154847a1685fSDinh Nguyen * 154947a1685fSDinh Nguyen * Called on completion of any requests the driver itself 155047a1685fSDinh Nguyen * submitted that need cleaning up. 155147a1685fSDinh Nguyen */ 15521f91b4ccSFelipe Balbi static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep, 155347a1685fSDinh Nguyen struct usb_request *req) 155447a1685fSDinh Nguyen { 15551f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *hs_ep = our_ep(ep); 1556941fcce4SDinh Nguyen struct dwc2_hsotg *hsotg = hs_ep->parent; 155747a1685fSDinh Nguyen 155847a1685fSDinh Nguyen dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req); 155947a1685fSDinh Nguyen 15601f91b4ccSFelipe Balbi dwc2_hsotg_ep_free_request(ep, req); 156147a1685fSDinh Nguyen } 156247a1685fSDinh Nguyen 156347a1685fSDinh Nguyen /** 156447a1685fSDinh Nguyen * ep_from_windex - convert control wIndex value to endpoint 156547a1685fSDinh Nguyen * @hsotg: The driver state. 156647a1685fSDinh Nguyen * @windex: The control request wIndex field (in host order). 156747a1685fSDinh Nguyen * 156847a1685fSDinh Nguyen * Convert the given wIndex into a pointer to an driver endpoint 156947a1685fSDinh Nguyen * structure, or return NULL if it is not a valid endpoint. 157047a1685fSDinh Nguyen */ 15711f91b4ccSFelipe Balbi static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg, 157247a1685fSDinh Nguyen u32 windex) 157347a1685fSDinh Nguyen { 157447a1685fSDinh Nguyen int dir = (windex & USB_DIR_IN) ? 1 : 0; 157547a1685fSDinh Nguyen int idx = windex & 0x7F; 157647a1685fSDinh Nguyen 157747a1685fSDinh Nguyen if (windex >= 0x100) 157847a1685fSDinh Nguyen return NULL; 157947a1685fSDinh Nguyen 158047a1685fSDinh Nguyen if (idx > hsotg->num_of_eps) 158147a1685fSDinh Nguyen return NULL; 158247a1685fSDinh Nguyen 1583f670e9f9SHeiko Stuebner return index_to_ep(hsotg, idx, dir); 158447a1685fSDinh Nguyen } 158547a1685fSDinh Nguyen 158647a1685fSDinh Nguyen /** 15871f91b4ccSFelipe Balbi * dwc2_hsotg_set_test_mode - Enable usb Test Modes 15889e14d0a5SGregory Herrero * @hsotg: The driver state. 15899e14d0a5SGregory Herrero * @testmode: requested usb test mode 15909e14d0a5SGregory Herrero * Enable usb Test Mode requested by the Host. 15919e14d0a5SGregory Herrero */ 15921f91b4ccSFelipe Balbi int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode) 15939e14d0a5SGregory Herrero { 1594f25c42b8SGevorg Sahakyan int dctl = dwc2_readl(hsotg, DCTL); 15959e14d0a5SGregory Herrero 15969e14d0a5SGregory Herrero dctl &= ~DCTL_TSTCTL_MASK; 15979e14d0a5SGregory Herrero switch (testmode) { 159862fb45d3SGreg Kroah-Hartman case USB_TEST_J: 159962fb45d3SGreg Kroah-Hartman case USB_TEST_K: 160062fb45d3SGreg Kroah-Hartman case USB_TEST_SE0_NAK: 160162fb45d3SGreg Kroah-Hartman case USB_TEST_PACKET: 160262fb45d3SGreg Kroah-Hartman case USB_TEST_FORCE_ENABLE: 16039e14d0a5SGregory Herrero dctl |= testmode << DCTL_TSTCTL_SHIFT; 16049e14d0a5SGregory Herrero break; 16059e14d0a5SGregory Herrero default: 16069e14d0a5SGregory Herrero return -EINVAL; 16079e14d0a5SGregory Herrero } 1608f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, dctl, DCTL); 16099e14d0a5SGregory Herrero return 0; 16109e14d0a5SGregory Herrero } 16119e14d0a5SGregory Herrero 16129e14d0a5SGregory Herrero /** 16131f91b4ccSFelipe Balbi * dwc2_hsotg_send_reply - send reply to control request 161447a1685fSDinh Nguyen * @hsotg: The device state 161547a1685fSDinh Nguyen * @ep: Endpoint 0 161647a1685fSDinh Nguyen * @buff: Buffer for request 161747a1685fSDinh Nguyen * @length: Length of reply. 161847a1685fSDinh Nguyen * 161947a1685fSDinh Nguyen * Create a request and queue it on the given endpoint. This is useful as 162047a1685fSDinh Nguyen * an internal method of sending replies to certain control requests, etc. 162147a1685fSDinh Nguyen */ 16221f91b4ccSFelipe Balbi static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg, 16231f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *ep, 162447a1685fSDinh Nguyen void *buff, 162547a1685fSDinh Nguyen int length) 162647a1685fSDinh Nguyen { 162747a1685fSDinh Nguyen struct usb_request *req; 162847a1685fSDinh Nguyen int ret; 162947a1685fSDinh Nguyen 163047a1685fSDinh Nguyen dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length); 163147a1685fSDinh Nguyen 16321f91b4ccSFelipe Balbi req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC); 163347a1685fSDinh Nguyen hsotg->ep0_reply = req; 163447a1685fSDinh Nguyen if (!req) { 163547a1685fSDinh Nguyen dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__); 163647a1685fSDinh Nguyen return -ENOMEM; 163747a1685fSDinh Nguyen } 163847a1685fSDinh Nguyen 163947a1685fSDinh Nguyen req->buf = hsotg->ep0_buff; 164047a1685fSDinh Nguyen req->length = length; 1641f71b5e25SMian Yousaf Kaukab /* 1642f71b5e25SMian Yousaf Kaukab * zero flag is for sending zlp in DATA IN stage. It has no impact on 1643f71b5e25SMian Yousaf Kaukab * STATUS stage. 1644f71b5e25SMian Yousaf Kaukab */ 1645f71b5e25SMian Yousaf Kaukab req->zero = 0; 16461f91b4ccSFelipe Balbi req->complete = dwc2_hsotg_complete_oursetup; 164747a1685fSDinh Nguyen 164847a1685fSDinh Nguyen if (length) 164947a1685fSDinh Nguyen memcpy(req->buf, buff, length); 165047a1685fSDinh Nguyen 16511f91b4ccSFelipe Balbi ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC); 165247a1685fSDinh Nguyen if (ret) { 165347a1685fSDinh Nguyen dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__); 165447a1685fSDinh Nguyen return ret; 165547a1685fSDinh Nguyen } 165647a1685fSDinh Nguyen 165747a1685fSDinh Nguyen return 0; 165847a1685fSDinh Nguyen } 165947a1685fSDinh Nguyen 166047a1685fSDinh Nguyen /** 16611f91b4ccSFelipe Balbi * dwc2_hsotg_process_req_status - process request GET_STATUS 166247a1685fSDinh Nguyen * @hsotg: The device state 166347a1685fSDinh Nguyen * @ctrl: USB control request 166447a1685fSDinh Nguyen */ 16651f91b4ccSFelipe Balbi static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg, 166647a1685fSDinh Nguyen struct usb_ctrlrequest *ctrl) 166747a1685fSDinh Nguyen { 16681f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; 16691f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *ep; 167047a1685fSDinh Nguyen __le16 reply; 16719a0d6f7cSMinas Harutyunyan u16 status; 167247a1685fSDinh Nguyen int ret; 167347a1685fSDinh Nguyen 167447a1685fSDinh Nguyen dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__); 167547a1685fSDinh Nguyen 167647a1685fSDinh Nguyen if (!ep0->dir_in) { 167747a1685fSDinh Nguyen dev_warn(hsotg->dev, "%s: direction out?\n", __func__); 167847a1685fSDinh Nguyen return -EINVAL; 167947a1685fSDinh Nguyen } 168047a1685fSDinh Nguyen 168147a1685fSDinh Nguyen switch (ctrl->bRequestType & USB_RECIP_MASK) { 168247a1685fSDinh Nguyen case USB_RECIP_DEVICE: 16831a0808cbSJohn Keeping status = hsotg->gadget.is_selfpowered << 16841a0808cbSJohn Keeping USB_DEVICE_SELF_POWERED; 16859a0d6f7cSMinas Harutyunyan status |= hsotg->remote_wakeup_allowed << 16869a0d6f7cSMinas Harutyunyan USB_DEVICE_REMOTE_WAKEUP; 16879a0d6f7cSMinas Harutyunyan reply = cpu_to_le16(status); 168847a1685fSDinh Nguyen break; 168947a1685fSDinh Nguyen 169047a1685fSDinh Nguyen case USB_RECIP_INTERFACE: 169147a1685fSDinh Nguyen /* currently, the data result should be zero */ 169247a1685fSDinh Nguyen reply = cpu_to_le16(0); 169347a1685fSDinh Nguyen break; 169447a1685fSDinh Nguyen 169547a1685fSDinh Nguyen case USB_RECIP_ENDPOINT: 169647a1685fSDinh Nguyen ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex)); 169747a1685fSDinh Nguyen if (!ep) 169847a1685fSDinh Nguyen return -ENOENT; 169947a1685fSDinh Nguyen 170047a1685fSDinh Nguyen reply = cpu_to_le16(ep->halted ? 1 : 0); 170147a1685fSDinh Nguyen break; 170247a1685fSDinh Nguyen 170347a1685fSDinh Nguyen default: 170447a1685fSDinh Nguyen return 0; 170547a1685fSDinh Nguyen } 170647a1685fSDinh Nguyen 170747a1685fSDinh Nguyen if (le16_to_cpu(ctrl->wLength) != 2) 170847a1685fSDinh Nguyen return -EINVAL; 170947a1685fSDinh Nguyen 17101f91b4ccSFelipe Balbi ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2); 171147a1685fSDinh Nguyen if (ret) { 171247a1685fSDinh Nguyen dev_err(hsotg->dev, "%s: failed to send reply\n", __func__); 171347a1685fSDinh Nguyen return ret; 171447a1685fSDinh Nguyen } 171547a1685fSDinh Nguyen 171647a1685fSDinh Nguyen return 1; 171747a1685fSDinh Nguyen } 171847a1685fSDinh Nguyen 171951da43b5SVahram Aharonyan static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now); 172047a1685fSDinh Nguyen 172147a1685fSDinh Nguyen /** 172247a1685fSDinh Nguyen * get_ep_head - return the first request on the endpoint 172347a1685fSDinh Nguyen * @hs_ep: The controller endpoint to get 172447a1685fSDinh Nguyen * 172547a1685fSDinh Nguyen * Get the first request on the endpoint. 172647a1685fSDinh Nguyen */ 17271f91b4ccSFelipe Balbi static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep) 172847a1685fSDinh Nguyen { 1729ffc4b406SMasahiro Yamada return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req, 1730ffc4b406SMasahiro Yamada queue); 173147a1685fSDinh Nguyen } 173247a1685fSDinh Nguyen 173347a1685fSDinh Nguyen /** 173441cc4cd2SVardan Mikayelyan * dwc2_gadget_start_next_request - Starts next request from ep queue 173541cc4cd2SVardan Mikayelyan * @hs_ep: Endpoint structure 173641cc4cd2SVardan Mikayelyan * 173741cc4cd2SVardan Mikayelyan * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked 173841cc4cd2SVardan Mikayelyan * in its handler. Hence we need to unmask it here to be able to do 173941cc4cd2SVardan Mikayelyan * resynchronization. 174041cc4cd2SVardan Mikayelyan */ 174141cc4cd2SVardan Mikayelyan static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep) 174241cc4cd2SVardan Mikayelyan { 174341cc4cd2SVardan Mikayelyan struct dwc2_hsotg *hsotg = hs_ep->parent; 174441cc4cd2SVardan Mikayelyan int dir_in = hs_ep->dir_in; 174541cc4cd2SVardan Mikayelyan struct dwc2_hsotg_req *hs_req; 174641cc4cd2SVardan Mikayelyan 174741cc4cd2SVardan Mikayelyan if (!list_empty(&hs_ep->queue)) { 174841cc4cd2SVardan Mikayelyan hs_req = get_ep_head(hs_ep); 174941cc4cd2SVardan Mikayelyan dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false); 175041cc4cd2SVardan Mikayelyan return; 175141cc4cd2SVardan Mikayelyan } 175241cc4cd2SVardan Mikayelyan if (!hs_ep->isochronous) 175341cc4cd2SVardan Mikayelyan return; 175441cc4cd2SVardan Mikayelyan 175541cc4cd2SVardan Mikayelyan if (dir_in) { 175641cc4cd2SVardan Mikayelyan dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n", 175741cc4cd2SVardan Mikayelyan __func__); 175841cc4cd2SVardan Mikayelyan } else { 175941cc4cd2SVardan Mikayelyan dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n", 176041cc4cd2SVardan Mikayelyan __func__); 176141cc4cd2SVardan Mikayelyan } 176241cc4cd2SVardan Mikayelyan } 176341cc4cd2SVardan Mikayelyan 176441cc4cd2SVardan Mikayelyan /** 17651f91b4ccSFelipe Balbi * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE 176647a1685fSDinh Nguyen * @hsotg: The device state 176747a1685fSDinh Nguyen * @ctrl: USB control request 176847a1685fSDinh Nguyen */ 17691f91b4ccSFelipe Balbi static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg, 177047a1685fSDinh Nguyen struct usb_ctrlrequest *ctrl) 177147a1685fSDinh Nguyen { 17721f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; 17731f91b4ccSFelipe Balbi struct dwc2_hsotg_req *hs_req; 177447a1685fSDinh Nguyen bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE); 17751f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *ep; 177647a1685fSDinh Nguyen int ret; 177747a1685fSDinh Nguyen bool halted; 17789e14d0a5SGregory Herrero u32 recip; 17799e14d0a5SGregory Herrero u32 wValue; 17809e14d0a5SGregory Herrero u32 wIndex; 178147a1685fSDinh Nguyen 178247a1685fSDinh Nguyen dev_dbg(hsotg->dev, "%s: %s_FEATURE\n", 178347a1685fSDinh Nguyen __func__, set ? "SET" : "CLEAR"); 178447a1685fSDinh Nguyen 17859e14d0a5SGregory Herrero wValue = le16_to_cpu(ctrl->wValue); 17869e14d0a5SGregory Herrero wIndex = le16_to_cpu(ctrl->wIndex); 17879e14d0a5SGregory Herrero recip = ctrl->bRequestType & USB_RECIP_MASK; 17889e14d0a5SGregory Herrero 17899e14d0a5SGregory Herrero switch (recip) { 17909e14d0a5SGregory Herrero case USB_RECIP_DEVICE: 17919e14d0a5SGregory Herrero switch (wValue) { 1792fa389a6dSVardan Mikayelyan case USB_DEVICE_REMOTE_WAKEUP: 17939a0d6f7cSMinas Harutyunyan if (set) 1794fa389a6dSVardan Mikayelyan hsotg->remote_wakeup_allowed = 1; 17959a0d6f7cSMinas Harutyunyan else 17969a0d6f7cSMinas Harutyunyan hsotg->remote_wakeup_allowed = 0; 1797fa389a6dSVardan Mikayelyan break; 1798fa389a6dSVardan Mikayelyan 17999e14d0a5SGregory Herrero case USB_DEVICE_TEST_MODE: 18009e14d0a5SGregory Herrero if ((wIndex & 0xff) != 0) 18019e14d0a5SGregory Herrero return -EINVAL; 18029e14d0a5SGregory Herrero if (!set) 18039e14d0a5SGregory Herrero return -EINVAL; 18049e14d0a5SGregory Herrero 18059e14d0a5SGregory Herrero hsotg->test_mode = wIndex >> 8; 18069a0d6f7cSMinas Harutyunyan break; 18079a0d6f7cSMinas Harutyunyan default: 18089a0d6f7cSMinas Harutyunyan return -ENOENT; 18099a0d6f7cSMinas Harutyunyan } 18109a0d6f7cSMinas Harutyunyan 18111f91b4ccSFelipe Balbi ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); 18129e14d0a5SGregory Herrero if (ret) { 18139e14d0a5SGregory Herrero dev_err(hsotg->dev, 18149e14d0a5SGregory Herrero "%s: failed to send reply\n", __func__); 18159e14d0a5SGregory Herrero return ret; 18169e14d0a5SGregory Herrero } 18179e14d0a5SGregory Herrero break; 18189e14d0a5SGregory Herrero 18199e14d0a5SGregory Herrero case USB_RECIP_ENDPOINT: 18209e14d0a5SGregory Herrero ep = ep_from_windex(hsotg, wIndex); 182147a1685fSDinh Nguyen if (!ep) { 182247a1685fSDinh Nguyen dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n", 18239e14d0a5SGregory Herrero __func__, wIndex); 182447a1685fSDinh Nguyen return -ENOENT; 182547a1685fSDinh Nguyen } 182647a1685fSDinh Nguyen 18279e14d0a5SGregory Herrero switch (wValue) { 182847a1685fSDinh Nguyen case USB_ENDPOINT_HALT: 182947a1685fSDinh Nguyen halted = ep->halted; 183047a1685fSDinh Nguyen 1831b833ce15SMinas Harutyunyan if (!ep->wedged) 183251da43b5SVahram Aharonyan dwc2_hsotg_ep_sethalt(&ep->ep, set, true); 183347a1685fSDinh Nguyen 18341f91b4ccSFelipe Balbi ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); 183547a1685fSDinh Nguyen if (ret) { 183647a1685fSDinh Nguyen dev_err(hsotg->dev, 183747a1685fSDinh Nguyen "%s: failed to send reply\n", __func__); 183847a1685fSDinh Nguyen return ret; 183947a1685fSDinh Nguyen } 184047a1685fSDinh Nguyen 184147a1685fSDinh Nguyen /* 184247a1685fSDinh Nguyen * we have to complete all requests for ep if it was 184347a1685fSDinh Nguyen * halted, and the halt was cleared by CLEAR_FEATURE 184447a1685fSDinh Nguyen */ 184547a1685fSDinh Nguyen 184647a1685fSDinh Nguyen if (!set && halted) { 184747a1685fSDinh Nguyen /* 184847a1685fSDinh Nguyen * If we have request in progress, 184947a1685fSDinh Nguyen * then complete it 185047a1685fSDinh Nguyen */ 185147a1685fSDinh Nguyen if (ep->req) { 185247a1685fSDinh Nguyen hs_req = ep->req; 185347a1685fSDinh Nguyen ep->req = NULL; 185447a1685fSDinh Nguyen list_del_init(&hs_req->queue); 1855c00dd4a6SGregory Herrero if (hs_req->req.complete) { 1856c00dd4a6SGregory Herrero spin_unlock(&hsotg->lock); 1857c00dd4a6SGregory Herrero usb_gadget_giveback_request( 1858c00dd4a6SGregory Herrero &ep->ep, &hs_req->req); 1859c00dd4a6SGregory Herrero spin_lock(&hsotg->lock); 1860c00dd4a6SGregory Herrero } 186147a1685fSDinh Nguyen } 186247a1685fSDinh Nguyen 186347a1685fSDinh Nguyen /* If we have pending request, then start it */ 186434c0887fSJohn Youn if (!ep->req) 186541cc4cd2SVardan Mikayelyan dwc2_gadget_start_next_request(ep); 186647a1685fSDinh Nguyen } 186747a1685fSDinh Nguyen 186847a1685fSDinh Nguyen break; 186947a1685fSDinh Nguyen 187047a1685fSDinh Nguyen default: 187147a1685fSDinh Nguyen return -ENOENT; 187247a1685fSDinh Nguyen } 18739e14d0a5SGregory Herrero break; 18749e14d0a5SGregory Herrero default: 18759e14d0a5SGregory Herrero return -ENOENT; 18769e14d0a5SGregory Herrero } 187747a1685fSDinh Nguyen return 1; 187847a1685fSDinh Nguyen } 187947a1685fSDinh Nguyen 18801f91b4ccSFelipe Balbi static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg); 188147a1685fSDinh Nguyen 188247a1685fSDinh Nguyen /** 18831f91b4ccSFelipe Balbi * dwc2_hsotg_stall_ep0 - stall ep0 188447a1685fSDinh Nguyen * @hsotg: The device state 188547a1685fSDinh Nguyen * 188647a1685fSDinh Nguyen * Set stall for ep0 as response for setup request. 188747a1685fSDinh Nguyen */ 18881f91b4ccSFelipe Balbi static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg) 1889e9ebe7c3SJingoo Han { 18901f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; 189147a1685fSDinh Nguyen u32 reg; 189247a1685fSDinh Nguyen u32 ctrl; 189347a1685fSDinh Nguyen 189447a1685fSDinh Nguyen dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in); 189547a1685fSDinh Nguyen reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0; 189647a1685fSDinh Nguyen 189747a1685fSDinh Nguyen /* 189847a1685fSDinh Nguyen * DxEPCTL_Stall will be cleared by EP once it has 189947a1685fSDinh Nguyen * taken effect, so no need to clear later. 190047a1685fSDinh Nguyen */ 190147a1685fSDinh Nguyen 1902f25c42b8SGevorg Sahakyan ctrl = dwc2_readl(hsotg, reg); 190347a1685fSDinh Nguyen ctrl |= DXEPCTL_STALL; 190447a1685fSDinh Nguyen ctrl |= DXEPCTL_CNAK; 1905f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, ctrl, reg); 190647a1685fSDinh Nguyen 190747a1685fSDinh Nguyen dev_dbg(hsotg->dev, 190847a1685fSDinh Nguyen "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n", 1909f25c42b8SGevorg Sahakyan ctrl, reg, dwc2_readl(hsotg, reg)); 191047a1685fSDinh Nguyen 191147a1685fSDinh Nguyen /* 191247a1685fSDinh Nguyen * complete won't be called, so we enqueue 191347a1685fSDinh Nguyen * setup request here 191447a1685fSDinh Nguyen */ 19151f91b4ccSFelipe Balbi dwc2_hsotg_enqueue_setup(hsotg); 191647a1685fSDinh Nguyen } 191747a1685fSDinh Nguyen 191847a1685fSDinh Nguyen /** 19191f91b4ccSFelipe Balbi * dwc2_hsotg_process_control - process a control request 192047a1685fSDinh Nguyen * @hsotg: The device state 192147a1685fSDinh Nguyen * @ctrl: The control request received 192247a1685fSDinh Nguyen * 192347a1685fSDinh Nguyen * The controller has received the SETUP phase of a control request, and 192447a1685fSDinh Nguyen * needs to work out what to do next (and whether to pass it on to the 192547a1685fSDinh Nguyen * gadget driver). 192647a1685fSDinh Nguyen */ 19271f91b4ccSFelipe Balbi static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg, 192847a1685fSDinh Nguyen struct usb_ctrlrequest *ctrl) 192947a1685fSDinh Nguyen { 19301f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; 193147a1685fSDinh Nguyen int ret = 0; 193247a1685fSDinh Nguyen u32 dcfg; 193347a1685fSDinh Nguyen 1934e525e743SMian Yousaf Kaukab dev_dbg(hsotg->dev, 1935e525e743SMian Yousaf Kaukab "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n", 1936e525e743SMian Yousaf Kaukab ctrl->bRequestType, ctrl->bRequest, ctrl->wValue, 1937e525e743SMian Yousaf Kaukab ctrl->wIndex, ctrl->wLength); 193847a1685fSDinh Nguyen 1939fe0b94abSMian Yousaf Kaukab if (ctrl->wLength == 0) { 194047a1685fSDinh Nguyen ep0->dir_in = 1; 1941fe0b94abSMian Yousaf Kaukab hsotg->ep0_state = DWC2_EP0_STATUS_IN; 1942fe0b94abSMian Yousaf Kaukab } else if (ctrl->bRequestType & USB_DIR_IN) { 1943fe0b94abSMian Yousaf Kaukab ep0->dir_in = 1; 1944fe0b94abSMian Yousaf Kaukab hsotg->ep0_state = DWC2_EP0_DATA_IN; 1945fe0b94abSMian Yousaf Kaukab } else { 1946fe0b94abSMian Yousaf Kaukab ep0->dir_in = 0; 1947fe0b94abSMian Yousaf Kaukab hsotg->ep0_state = DWC2_EP0_DATA_OUT; 1948fe0b94abSMian Yousaf Kaukab } 194947a1685fSDinh Nguyen 195047a1685fSDinh Nguyen if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { 195147a1685fSDinh Nguyen switch (ctrl->bRequest) { 195247a1685fSDinh Nguyen case USB_REQ_SET_ADDRESS: 19536d713c15SMian Yousaf Kaukab hsotg->connected = 1; 1954f25c42b8SGevorg Sahakyan dcfg = dwc2_readl(hsotg, DCFG); 195547a1685fSDinh Nguyen dcfg &= ~DCFG_DEVADDR_MASK; 1956d5dbd3f7SPaul Zimmerman dcfg |= (le16_to_cpu(ctrl->wValue) << 1957d5dbd3f7SPaul Zimmerman DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK; 1958f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, dcfg, DCFG); 195947a1685fSDinh Nguyen 196047a1685fSDinh Nguyen dev_info(hsotg->dev, "new address %d\n", ctrl->wValue); 196147a1685fSDinh Nguyen 19621f91b4ccSFelipe Balbi ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); 196347a1685fSDinh Nguyen return; 196447a1685fSDinh Nguyen 196547a1685fSDinh Nguyen case USB_REQ_GET_STATUS: 19661f91b4ccSFelipe Balbi ret = dwc2_hsotg_process_req_status(hsotg, ctrl); 196747a1685fSDinh Nguyen break; 196847a1685fSDinh Nguyen 196947a1685fSDinh Nguyen case USB_REQ_CLEAR_FEATURE: 197047a1685fSDinh Nguyen case USB_REQ_SET_FEATURE: 19711f91b4ccSFelipe Balbi ret = dwc2_hsotg_process_req_feature(hsotg, ctrl); 197247a1685fSDinh Nguyen break; 197347a1685fSDinh Nguyen } 197447a1685fSDinh Nguyen } 197547a1685fSDinh Nguyen 197647a1685fSDinh Nguyen /* as a fallback, try delivering it to the driver to deal with */ 197747a1685fSDinh Nguyen 197847a1685fSDinh Nguyen if (ret == 0 && hsotg->driver) { 197947a1685fSDinh Nguyen spin_unlock(&hsotg->lock); 198047a1685fSDinh Nguyen ret = hsotg->driver->setup(&hsotg->gadget, ctrl); 198147a1685fSDinh Nguyen spin_lock(&hsotg->lock); 198247a1685fSDinh Nguyen if (ret < 0) 198347a1685fSDinh Nguyen dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret); 198447a1685fSDinh Nguyen } 198547a1685fSDinh Nguyen 1986b4c53b4aSMinas Harutyunyan hsotg->delayed_status = false; 1987b4c53b4aSMinas Harutyunyan if (ret == USB_GADGET_DELAYED_STATUS) 1988b4c53b4aSMinas Harutyunyan hsotg->delayed_status = true; 1989b4c53b4aSMinas Harutyunyan 199047a1685fSDinh Nguyen /* 199147a1685fSDinh Nguyen * the request is either unhandlable, or is not formatted correctly 199247a1685fSDinh Nguyen * so respond with a STALL for the status stage to indicate failure. 199347a1685fSDinh Nguyen */ 199447a1685fSDinh Nguyen 199547a1685fSDinh Nguyen if (ret < 0) 19961f91b4ccSFelipe Balbi dwc2_hsotg_stall_ep0(hsotg); 199747a1685fSDinh Nguyen } 199847a1685fSDinh Nguyen 199947a1685fSDinh Nguyen /** 20001f91b4ccSFelipe Balbi * dwc2_hsotg_complete_setup - completion of a setup transfer 200147a1685fSDinh Nguyen * @ep: The endpoint the request was on. 200247a1685fSDinh Nguyen * @req: The request completed. 200347a1685fSDinh Nguyen * 200447a1685fSDinh Nguyen * Called on completion of any requests the driver itself submitted for 200547a1685fSDinh Nguyen * EP0 setup packets 200647a1685fSDinh Nguyen */ 20071f91b4ccSFelipe Balbi static void dwc2_hsotg_complete_setup(struct usb_ep *ep, 200847a1685fSDinh Nguyen struct usb_request *req) 200947a1685fSDinh Nguyen { 20101f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *hs_ep = our_ep(ep); 2011941fcce4SDinh Nguyen struct dwc2_hsotg *hsotg = hs_ep->parent; 201247a1685fSDinh Nguyen 201347a1685fSDinh Nguyen if (req->status < 0) { 201447a1685fSDinh Nguyen dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status); 201547a1685fSDinh Nguyen return; 201647a1685fSDinh Nguyen } 201747a1685fSDinh Nguyen 201847a1685fSDinh Nguyen spin_lock(&hsotg->lock); 201947a1685fSDinh Nguyen if (req->actual == 0) 20201f91b4ccSFelipe Balbi dwc2_hsotg_enqueue_setup(hsotg); 202147a1685fSDinh Nguyen else 20221f91b4ccSFelipe Balbi dwc2_hsotg_process_control(hsotg, req->buf); 202347a1685fSDinh Nguyen spin_unlock(&hsotg->lock); 202447a1685fSDinh Nguyen } 202547a1685fSDinh Nguyen 202647a1685fSDinh Nguyen /** 20271f91b4ccSFelipe Balbi * dwc2_hsotg_enqueue_setup - start a request for EP0 packets 202847a1685fSDinh Nguyen * @hsotg: The device state. 202947a1685fSDinh Nguyen * 203047a1685fSDinh Nguyen * Enqueue a request on EP0 if necessary to received any SETUP packets 203147a1685fSDinh Nguyen * received from the host. 203247a1685fSDinh Nguyen */ 20331f91b4ccSFelipe Balbi static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg) 203447a1685fSDinh Nguyen { 203547a1685fSDinh Nguyen struct usb_request *req = hsotg->ctrl_req; 20361f91b4ccSFelipe Balbi struct dwc2_hsotg_req *hs_req = our_req(req); 203747a1685fSDinh Nguyen int ret; 203847a1685fSDinh Nguyen 203947a1685fSDinh Nguyen dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__); 204047a1685fSDinh Nguyen 204147a1685fSDinh Nguyen req->zero = 0; 204247a1685fSDinh Nguyen req->length = 8; 204347a1685fSDinh Nguyen req->buf = hsotg->ctrl_buff; 20441f91b4ccSFelipe Balbi req->complete = dwc2_hsotg_complete_setup; 204547a1685fSDinh Nguyen 204647a1685fSDinh Nguyen if (!list_empty(&hs_req->queue)) { 204747a1685fSDinh Nguyen dev_dbg(hsotg->dev, "%s already queued???\n", __func__); 204847a1685fSDinh Nguyen return; 204947a1685fSDinh Nguyen } 205047a1685fSDinh Nguyen 2051c6f5c050SMian Yousaf Kaukab hsotg->eps_out[0]->dir_in = 0; 20528a20fa45SMian Yousaf Kaukab hsotg->eps_out[0]->send_zlp = 0; 2053fe0b94abSMian Yousaf Kaukab hsotg->ep0_state = DWC2_EP0_SETUP; 205447a1685fSDinh Nguyen 20551f91b4ccSFelipe Balbi ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC); 205647a1685fSDinh Nguyen if (ret < 0) { 205747a1685fSDinh Nguyen dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret); 205847a1685fSDinh Nguyen /* 205947a1685fSDinh Nguyen * Don't think there's much we can do other than watch the 206047a1685fSDinh Nguyen * driver fail. 206147a1685fSDinh Nguyen */ 206247a1685fSDinh Nguyen } 206347a1685fSDinh Nguyen } 206447a1685fSDinh Nguyen 20651f91b4ccSFelipe Balbi static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg, 20661f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *hs_ep) 2067fe0b94abSMian Yousaf Kaukab { 2068fe0b94abSMian Yousaf Kaukab u32 ctrl; 2069fe0b94abSMian Yousaf Kaukab u8 index = hs_ep->index; 2070fe0b94abSMian Yousaf Kaukab u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index); 2071fe0b94abSMian Yousaf Kaukab u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); 2072fe0b94abSMian Yousaf Kaukab 2073ccb34a91SMian Yousaf Kaukab if (hs_ep->dir_in) 2074ccb34a91SMian Yousaf Kaukab dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n", 2075ccb34a91SMian Yousaf Kaukab index); 2076ccb34a91SMian Yousaf Kaukab else 2077ccb34a91SMian Yousaf Kaukab dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n", 2078ccb34a91SMian Yousaf Kaukab index); 2079e02f9aa6SVahram Aharonyan if (using_desc_dma(hsotg)) { 2080066cfd07SAndrzej Pietrasiewicz /* Not specific buffer needed for ep0 ZLP */ 2081066cfd07SAndrzej Pietrasiewicz dma_addr_t dma = hs_ep->desc_list_dma; 2082066cfd07SAndrzej Pietrasiewicz 2083201ec568SMinas Harutyunyan if (!index) 2084e02f9aa6SVahram Aharonyan dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep); 2085201ec568SMinas Harutyunyan 2086066cfd07SAndrzej Pietrasiewicz dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0); 2087e02f9aa6SVahram Aharonyan } else { 2088f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | 2089f25c42b8SGevorg Sahakyan DXEPTSIZ_XFERSIZE(0), 2090fe0b94abSMian Yousaf Kaukab epsiz_reg); 2091e02f9aa6SVahram Aharonyan } 2092fe0b94abSMian Yousaf Kaukab 2093f25c42b8SGevorg Sahakyan ctrl = dwc2_readl(hsotg, epctl_reg); 2094fe0b94abSMian Yousaf Kaukab ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ 2095fe0b94abSMian Yousaf Kaukab ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ 2096fe0b94abSMian Yousaf Kaukab ctrl |= DXEPCTL_USBACTEP; 2097f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, ctrl, epctl_reg); 2098fe0b94abSMian Yousaf Kaukab } 2099fe0b94abSMian Yousaf Kaukab 210047a1685fSDinh Nguyen /** 21011f91b4ccSFelipe Balbi * dwc2_hsotg_complete_request - complete a request given to us 210247a1685fSDinh Nguyen * @hsotg: The device state. 210347a1685fSDinh Nguyen * @hs_ep: The endpoint the request was on. 210447a1685fSDinh Nguyen * @hs_req: The request to complete. 210547a1685fSDinh Nguyen * @result: The result code (0 => Ok, otherwise errno) 210647a1685fSDinh Nguyen * 210747a1685fSDinh Nguyen * The given request has finished, so call the necessary completion 210847a1685fSDinh Nguyen * if it has one and then look to see if we can start a new request 210947a1685fSDinh Nguyen * on the endpoint. 211047a1685fSDinh Nguyen * 211147a1685fSDinh Nguyen * Note, expects the ep to already be locked as appropriate. 211247a1685fSDinh Nguyen */ 21131f91b4ccSFelipe Balbi static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg, 21141f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *hs_ep, 21151f91b4ccSFelipe Balbi struct dwc2_hsotg_req *hs_req, 211647a1685fSDinh Nguyen int result) 211747a1685fSDinh Nguyen { 211847a1685fSDinh Nguyen if (!hs_req) { 211947a1685fSDinh Nguyen dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__); 212047a1685fSDinh Nguyen return; 212147a1685fSDinh Nguyen } 212247a1685fSDinh Nguyen 212347a1685fSDinh Nguyen dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n", 212447a1685fSDinh Nguyen hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete); 212547a1685fSDinh Nguyen 212647a1685fSDinh Nguyen /* 212747a1685fSDinh Nguyen * only replace the status if we've not already set an error 212847a1685fSDinh Nguyen * from a previous transaction 212947a1685fSDinh Nguyen */ 213047a1685fSDinh Nguyen 213147a1685fSDinh Nguyen if (hs_req->req.status == -EINPROGRESS) 213247a1685fSDinh Nguyen hs_req->req.status = result; 213347a1685fSDinh Nguyen 213444583fecSYunzhi Li if (using_dma(hsotg)) 213544583fecSYunzhi Li dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req); 213644583fecSYunzhi Li 21371f91b4ccSFelipe Balbi dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req); 21387d24c1b5SMian Yousaf Kaukab 213947a1685fSDinh Nguyen hs_ep->req = NULL; 214047a1685fSDinh Nguyen list_del_init(&hs_req->queue); 214147a1685fSDinh Nguyen 214247a1685fSDinh Nguyen /* 214347a1685fSDinh Nguyen * call the complete request with the locks off, just in case the 214447a1685fSDinh Nguyen * request tries to queue more work for this endpoint. 214547a1685fSDinh Nguyen */ 214647a1685fSDinh Nguyen 214747a1685fSDinh Nguyen if (hs_req->req.complete) { 214847a1685fSDinh Nguyen spin_unlock(&hsotg->lock); 2149304f7e5eSMichal Sojka usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req); 215047a1685fSDinh Nguyen spin_lock(&hsotg->lock); 215147a1685fSDinh Nguyen } 215247a1685fSDinh Nguyen 2153540ccba0SVahram Aharonyan /* In DDMA don't need to proceed to starting of next ISOC request */ 2154540ccba0SVahram Aharonyan if (using_desc_dma(hsotg) && hs_ep->isochronous) 2155540ccba0SVahram Aharonyan return; 2156540ccba0SVahram Aharonyan 215747a1685fSDinh Nguyen /* 215847a1685fSDinh Nguyen * Look to see if there is anything else to do. Note, the completion 215947a1685fSDinh Nguyen * of the previous request may have caused a new request to be started 216047a1685fSDinh Nguyen * so be careful when doing this. 216147a1685fSDinh Nguyen */ 216247a1685fSDinh Nguyen 216334c0887fSJohn Youn if (!hs_ep->req && result >= 0) 216441cc4cd2SVardan Mikayelyan dwc2_gadget_start_next_request(hs_ep); 216547a1685fSDinh Nguyen } 216647a1685fSDinh Nguyen 2167540ccba0SVahram Aharonyan /* 2168540ccba0SVahram Aharonyan * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA 2169540ccba0SVahram Aharonyan * @hs_ep: The endpoint the request was on. 2170540ccba0SVahram Aharonyan * 2171540ccba0SVahram Aharonyan * Get first request from the ep queue, determine descriptor on which complete 2172729cac69SMinas Harutyunyan * happened. SW discovers which descriptor currently in use by HW, adjusts 2173729cac69SMinas Harutyunyan * dma_address and calculates index of completed descriptor based on the value 2174729cac69SMinas Harutyunyan * of DEPDMA register. Update actual length of request, giveback to gadget. 2175540ccba0SVahram Aharonyan */ 2176540ccba0SVahram Aharonyan static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep) 2177540ccba0SVahram Aharonyan { 2178540ccba0SVahram Aharonyan struct dwc2_hsotg *hsotg = hs_ep->parent; 2179540ccba0SVahram Aharonyan struct dwc2_hsotg_req *hs_req; 2180540ccba0SVahram Aharonyan struct usb_request *ureq; 2181540ccba0SVahram Aharonyan u32 desc_sts; 2182540ccba0SVahram Aharonyan u32 mask; 2183540ccba0SVahram Aharonyan 2184729cac69SMinas Harutyunyan desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status; 2185729cac69SMinas Harutyunyan 2186729cac69SMinas Harutyunyan /* Process only descriptors with buffer status set to DMA done */ 2187729cac69SMinas Harutyunyan while ((desc_sts & DEV_DMA_BUFF_STS_MASK) >> 2188729cac69SMinas Harutyunyan DEV_DMA_BUFF_STS_SHIFT == DEV_DMA_BUFF_STS_DMADONE) { 2189729cac69SMinas Harutyunyan 2190540ccba0SVahram Aharonyan hs_req = get_ep_head(hs_ep); 2191540ccba0SVahram Aharonyan if (!hs_req) { 2192540ccba0SVahram Aharonyan dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__); 2193540ccba0SVahram Aharonyan return; 2194540ccba0SVahram Aharonyan } 2195540ccba0SVahram Aharonyan ureq = &hs_req->req; 2196540ccba0SVahram Aharonyan 2197729cac69SMinas Harutyunyan /* Check completion status */ 2198729cac69SMinas Harutyunyan if ((desc_sts & DEV_DMA_STS_MASK) >> DEV_DMA_STS_SHIFT == 2199729cac69SMinas Harutyunyan DEV_DMA_STS_SUCC) { 2200540ccba0SVahram Aharonyan mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK : 2201540ccba0SVahram Aharonyan DEV_DMA_ISOC_RX_NBYTES_MASK; 2202729cac69SMinas Harutyunyan ureq->actual = ureq->length - ((desc_sts & mask) >> 2203729cac69SMinas Harutyunyan DEV_DMA_ISOC_NBYTES_SHIFT); 2204540ccba0SVahram Aharonyan 2205729cac69SMinas Harutyunyan /* Adjust actual len for ISOC Out if len is 2206729cac69SMinas Harutyunyan * not align of 4 2207729cac69SMinas Harutyunyan */ 220895d2b037SVahram Aharonyan if (!hs_ep->dir_in && ureq->length & 0x3) 220995d2b037SVahram Aharonyan ureq->actual += 4 - (ureq->length & 0x3); 2210c8006f67SMinas Harutyunyan 2211c8006f67SMinas Harutyunyan /* Set actual frame number for completed transfers */ 2212c8006f67SMinas Harutyunyan ureq->frame_number = 2213c8006f67SMinas Harutyunyan (desc_sts & DEV_DMA_ISOC_FRNUM_MASK) >> 2214c8006f67SMinas Harutyunyan DEV_DMA_ISOC_FRNUM_SHIFT; 2215729cac69SMinas Harutyunyan } 221695d2b037SVahram Aharonyan 2217540ccba0SVahram Aharonyan dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); 2218729cac69SMinas Harutyunyan 2219729cac69SMinas Harutyunyan hs_ep->compl_desc++; 222054f37f56SMinas Harutyunyan if (hs_ep->compl_desc > (MAX_DMA_DESC_NUM_HS_ISOC - 1)) 2221729cac69SMinas Harutyunyan hs_ep->compl_desc = 0; 2222729cac69SMinas Harutyunyan desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status; 2223729cac69SMinas Harutyunyan } 2224540ccba0SVahram Aharonyan } 2225540ccba0SVahram Aharonyan 2226540ccba0SVahram Aharonyan /* 2227729cac69SMinas Harutyunyan * dwc2_gadget_handle_isoc_bna - handle BNA interrupt for ISOC. 2228729cac69SMinas Harutyunyan * @hs_ep: The isochronous endpoint. 2229540ccba0SVahram Aharonyan * 2230729cac69SMinas Harutyunyan * If EP ISOC OUT then need to flush RX FIFO to remove source of BNA 2231729cac69SMinas Harutyunyan * interrupt. Reset target frame and next_desc to allow to start 2232729cac69SMinas Harutyunyan * ISOC's on NAK interrupt for IN direction or on OUTTKNEPDIS 2233729cac69SMinas Harutyunyan * interrupt for OUT direction. 2234540ccba0SVahram Aharonyan */ 2235729cac69SMinas Harutyunyan static void dwc2_gadget_handle_isoc_bna(struct dwc2_hsotg_ep *hs_ep) 2236540ccba0SVahram Aharonyan { 2237540ccba0SVahram Aharonyan struct dwc2_hsotg *hsotg = hs_ep->parent; 2238540ccba0SVahram Aharonyan 2239729cac69SMinas Harutyunyan if (!hs_ep->dir_in) 2240729cac69SMinas Harutyunyan dwc2_flush_rx_fifo(hsotg); 2241729cac69SMinas Harutyunyan dwc2_hsotg_complete_request(hsotg, hs_ep, get_ep_head(hs_ep), 0); 2242540ccba0SVahram Aharonyan 2243729cac69SMinas Harutyunyan hs_ep->target_frame = TARGET_FRAME_INITIAL; 2244540ccba0SVahram Aharonyan hs_ep->next_desc = 0; 2245729cac69SMinas Harutyunyan hs_ep->compl_desc = 0; 2246540ccba0SVahram Aharonyan } 2247540ccba0SVahram Aharonyan 224847a1685fSDinh Nguyen /** 22491f91b4ccSFelipe Balbi * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint 225047a1685fSDinh Nguyen * @hsotg: The device state. 225147a1685fSDinh Nguyen * @ep_idx: The endpoint index for the data 225247a1685fSDinh Nguyen * @size: The size of data in the fifo, in bytes 225347a1685fSDinh Nguyen * 225447a1685fSDinh Nguyen * The FIFO status shows there is data to read from the FIFO for a given 225547a1685fSDinh Nguyen * endpoint, so sort out whether we need to read the data into a request 225647a1685fSDinh Nguyen * that has been made for that endpoint. 225747a1685fSDinh Nguyen */ 22581f91b4ccSFelipe Balbi static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size) 225947a1685fSDinh Nguyen { 22601f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx]; 22611f91b4ccSFelipe Balbi struct dwc2_hsotg_req *hs_req = hs_ep->req; 226247a1685fSDinh Nguyen int to_read; 226347a1685fSDinh Nguyen int max_req; 226447a1685fSDinh Nguyen int read_ptr; 226547a1685fSDinh Nguyen 226647a1685fSDinh Nguyen if (!hs_req) { 2267f25c42b8SGevorg Sahakyan u32 epctl = dwc2_readl(hsotg, DOEPCTL(ep_idx)); 226847a1685fSDinh Nguyen int ptr; 226947a1685fSDinh Nguyen 22706b448af4SRobert Baldyga dev_dbg(hsotg->dev, 227147a1685fSDinh Nguyen "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n", 227247a1685fSDinh Nguyen __func__, size, ep_idx, epctl); 227347a1685fSDinh Nguyen 227447a1685fSDinh Nguyen /* dump the data from the FIFO, we've nothing we can do */ 227547a1685fSDinh Nguyen for (ptr = 0; ptr < size; ptr += 4) 2276f25c42b8SGevorg Sahakyan (void)dwc2_readl(hsotg, EPFIFO(ep_idx)); 227747a1685fSDinh Nguyen 227847a1685fSDinh Nguyen return; 227947a1685fSDinh Nguyen } 228047a1685fSDinh Nguyen 228147a1685fSDinh Nguyen to_read = size; 228247a1685fSDinh Nguyen read_ptr = hs_req->req.actual; 228347a1685fSDinh Nguyen max_req = hs_req->req.length - read_ptr; 228447a1685fSDinh Nguyen 228547a1685fSDinh Nguyen dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n", 228647a1685fSDinh Nguyen __func__, to_read, max_req, read_ptr, hs_req->req.length); 228747a1685fSDinh Nguyen 228847a1685fSDinh Nguyen if (to_read > max_req) { 228947a1685fSDinh Nguyen /* 229047a1685fSDinh Nguyen * more data appeared than we where willing 229147a1685fSDinh Nguyen * to deal with in this request. 229247a1685fSDinh Nguyen */ 229347a1685fSDinh Nguyen 229447a1685fSDinh Nguyen /* currently we don't deal this */ 229547a1685fSDinh Nguyen WARN_ON_ONCE(1); 229647a1685fSDinh Nguyen } 229747a1685fSDinh Nguyen 229847a1685fSDinh Nguyen hs_ep->total_data += to_read; 229947a1685fSDinh Nguyen hs_req->req.actual += to_read; 230047a1685fSDinh Nguyen to_read = DIV_ROUND_UP(to_read, 4); 230147a1685fSDinh Nguyen 230247a1685fSDinh Nguyen /* 230347a1685fSDinh Nguyen * note, we might over-write the buffer end by 3 bytes depending on 230447a1685fSDinh Nguyen * alignment of the data. 230547a1685fSDinh Nguyen */ 2306342ccce1SGevorg Sahakyan dwc2_readl_rep(hsotg, EPFIFO(ep_idx), 2307f25c42b8SGevorg Sahakyan hs_req->req.buf + read_ptr, to_read); 230847a1685fSDinh Nguyen } 230947a1685fSDinh Nguyen 231047a1685fSDinh Nguyen /** 23111f91b4ccSFelipe Balbi * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint 231247a1685fSDinh Nguyen * @hsotg: The device instance 2313fe0b94abSMian Yousaf Kaukab * @dir_in: If IN zlp 231447a1685fSDinh Nguyen * 231547a1685fSDinh Nguyen * Generate a zero-length IN packet request for terminating a SETUP 231647a1685fSDinh Nguyen * transaction. 231747a1685fSDinh Nguyen * 231847a1685fSDinh Nguyen * Note, since we don't write any data to the TxFIFO, then it is 231947a1685fSDinh Nguyen * currently believed that we do not need to wait for any space in 232047a1685fSDinh Nguyen * the TxFIFO. 232147a1685fSDinh Nguyen */ 23221f91b4ccSFelipe Balbi static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in) 232347a1685fSDinh Nguyen { 2324c6f5c050SMian Yousaf Kaukab /* eps_out[0] is used in both directions */ 2325fe0b94abSMian Yousaf Kaukab hsotg->eps_out[0]->dir_in = dir_in; 2326fe0b94abSMian Yousaf Kaukab hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT; 232747a1685fSDinh Nguyen 23281f91b4ccSFelipe Balbi dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]); 232947a1685fSDinh Nguyen } 233047a1685fSDinh Nguyen 2331aa3e8bc8SVahram Aharonyan /* 2332aa3e8bc8SVahram Aharonyan * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc 2333aa3e8bc8SVahram Aharonyan * @hs_ep - The endpoint on which transfer went 2334aa3e8bc8SVahram Aharonyan * 2335aa3e8bc8SVahram Aharonyan * Iterate over endpoints descriptor chain and get info on bytes remained 2336aa3e8bc8SVahram Aharonyan * in DMA descriptors after transfer has completed. Used for non isoc EPs. 2337aa3e8bc8SVahram Aharonyan */ 2338aa3e8bc8SVahram Aharonyan static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep) 2339aa3e8bc8SVahram Aharonyan { 2340b2c586ebSMinas Harutyunyan const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc; 2341aa3e8bc8SVahram Aharonyan struct dwc2_hsotg *hsotg = hs_ep->parent; 2342aa3e8bc8SVahram Aharonyan unsigned int bytes_rem = 0; 2343b2c586ebSMinas Harutyunyan unsigned int bytes_rem_correction = 0; 2344aa3e8bc8SVahram Aharonyan struct dwc2_dma_desc *desc = hs_ep->desc_list; 2345aa3e8bc8SVahram Aharonyan int i; 2346aa3e8bc8SVahram Aharonyan u32 status; 2347b2c586ebSMinas Harutyunyan u32 mps = hs_ep->ep.maxpacket; 2348b2c586ebSMinas Harutyunyan int dir_in = hs_ep->dir_in; 2349aa3e8bc8SVahram Aharonyan 2350aa3e8bc8SVahram Aharonyan if (!desc) 2351aa3e8bc8SVahram Aharonyan return -EINVAL; 2352aa3e8bc8SVahram Aharonyan 2353b2c586ebSMinas Harutyunyan /* Interrupt OUT EP with mps not multiple of 4 */ 2354b2c586ebSMinas Harutyunyan if (hs_ep->index) 2355b2c586ebSMinas Harutyunyan if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4)) 2356b2c586ebSMinas Harutyunyan bytes_rem_correction = 4 - (mps % 4); 2357b2c586ebSMinas Harutyunyan 2358aa3e8bc8SVahram Aharonyan for (i = 0; i < hs_ep->desc_count; ++i) { 2359aa3e8bc8SVahram Aharonyan status = desc->status; 2360aa3e8bc8SVahram Aharonyan bytes_rem += status & DEV_DMA_NBYTES_MASK; 2361b2c586ebSMinas Harutyunyan bytes_rem -= bytes_rem_correction; 2362aa3e8bc8SVahram Aharonyan 2363aa3e8bc8SVahram Aharonyan if (status & DEV_DMA_STS_MASK) 2364aa3e8bc8SVahram Aharonyan dev_err(hsotg->dev, "descriptor %d closed with %x\n", 2365aa3e8bc8SVahram Aharonyan i, status & DEV_DMA_STS_MASK); 2366b2c586ebSMinas Harutyunyan 2367b2c586ebSMinas Harutyunyan if (status & DEV_DMA_L) 2368b2c586ebSMinas Harutyunyan break; 2369b2c586ebSMinas Harutyunyan 23705acb4b97SMinas Harutyunyan desc++; 2371aa3e8bc8SVahram Aharonyan } 2372aa3e8bc8SVahram Aharonyan 2373aa3e8bc8SVahram Aharonyan return bytes_rem; 2374aa3e8bc8SVahram Aharonyan } 2375aa3e8bc8SVahram Aharonyan 237647a1685fSDinh Nguyen /** 23771f91b4ccSFelipe Balbi * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO 237847a1685fSDinh Nguyen * @hsotg: The device instance 237947a1685fSDinh Nguyen * @epnum: The endpoint received from 238047a1685fSDinh Nguyen * 238147a1685fSDinh Nguyen * The RXFIFO has delivered an OutDone event, which means that the data 238247a1685fSDinh Nguyen * transfer for an OUT endpoint has been completed, either by a short 238347a1685fSDinh Nguyen * packet or by the finish of a transfer. 238447a1685fSDinh Nguyen */ 23851f91b4ccSFelipe Balbi static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum) 238647a1685fSDinh Nguyen { 2387f25c42b8SGevorg Sahakyan u32 epsize = dwc2_readl(hsotg, DOEPTSIZ(epnum)); 23881f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum]; 23891f91b4ccSFelipe Balbi struct dwc2_hsotg_req *hs_req = hs_ep->req; 239047a1685fSDinh Nguyen struct usb_request *req = &hs_req->req; 23919da51974SJohn Youn unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize); 239247a1685fSDinh Nguyen int result = 0; 239347a1685fSDinh Nguyen 239447a1685fSDinh Nguyen if (!hs_req) { 239547a1685fSDinh Nguyen dev_dbg(hsotg->dev, "%s: no request active\n", __func__); 239647a1685fSDinh Nguyen return; 239747a1685fSDinh Nguyen } 239847a1685fSDinh Nguyen 2399fe0b94abSMian Yousaf Kaukab if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) { 2400fe0b94abSMian Yousaf Kaukab dev_dbg(hsotg->dev, "zlp packet received\n"); 24011f91b4ccSFelipe Balbi dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); 24021f91b4ccSFelipe Balbi dwc2_hsotg_enqueue_setup(hsotg); 2403fe0b94abSMian Yousaf Kaukab return; 2404fe0b94abSMian Yousaf Kaukab } 2405fe0b94abSMian Yousaf Kaukab 2406aa3e8bc8SVahram Aharonyan if (using_desc_dma(hsotg)) 2407aa3e8bc8SVahram Aharonyan size_left = dwc2_gadget_get_xfersize_ddma(hs_ep); 2408aa3e8bc8SVahram Aharonyan 240947a1685fSDinh Nguyen if (using_dma(hsotg)) { 24109da51974SJohn Youn unsigned int size_done; 241147a1685fSDinh Nguyen 241247a1685fSDinh Nguyen /* 241347a1685fSDinh Nguyen * Calculate the size of the transfer by checking how much 241447a1685fSDinh Nguyen * is left in the endpoint size register and then working it 241547a1685fSDinh Nguyen * out from the amount we loaded for the transfer. 241647a1685fSDinh Nguyen * 241747a1685fSDinh Nguyen * We need to do this as DMA pointers are always 32bit aligned 241847a1685fSDinh Nguyen * so may overshoot/undershoot the transfer. 241947a1685fSDinh Nguyen */ 242047a1685fSDinh Nguyen 242147a1685fSDinh Nguyen size_done = hs_ep->size_loaded - size_left; 242247a1685fSDinh Nguyen size_done += hs_ep->last_load; 242347a1685fSDinh Nguyen 242447a1685fSDinh Nguyen req->actual = size_done; 242547a1685fSDinh Nguyen } 242647a1685fSDinh Nguyen 242747a1685fSDinh Nguyen /* if there is more request to do, schedule new transfer */ 242847a1685fSDinh Nguyen if (req->actual < req->length && size_left == 0) { 24291f91b4ccSFelipe Balbi dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true); 243047a1685fSDinh Nguyen return; 243147a1685fSDinh Nguyen } 243247a1685fSDinh Nguyen 243347a1685fSDinh Nguyen if (req->actual < req->length && req->short_not_ok) { 243447a1685fSDinh Nguyen dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n", 243547a1685fSDinh Nguyen __func__, req->actual, req->length); 243647a1685fSDinh Nguyen 243747a1685fSDinh Nguyen /* 243847a1685fSDinh Nguyen * todo - what should we return here? there's no one else 243947a1685fSDinh Nguyen * even bothering to check the status. 244047a1685fSDinh Nguyen */ 244147a1685fSDinh Nguyen } 244247a1685fSDinh Nguyen 2443ef750c71SVahram Aharonyan /* DDMA IN status phase will start from StsPhseRcvd interrupt */ 2444ef750c71SVahram Aharonyan if (!using_desc_dma(hsotg) && epnum == 0 && 2445ef750c71SVahram Aharonyan hsotg->ep0_state == DWC2_EP0_DATA_OUT) { 2446fe0b94abSMian Yousaf Kaukab /* Move to STATUS IN */ 2447b4c53b4aSMinas Harutyunyan if (!hsotg->delayed_status) 24481f91b4ccSFelipe Balbi dwc2_hsotg_ep0_zlp(hsotg, true); 244947a1685fSDinh Nguyen } 245047a1685fSDinh Nguyen 2451*91bb163eSMinas Harutyunyan /* Set actual frame number for completed transfers */ 2452*91bb163eSMinas Harutyunyan if (!using_desc_dma(hsotg) && hs_ep->isochronous) { 2453*91bb163eSMinas Harutyunyan req->frame_number = hs_ep->target_frame; 2454837e9f00SVardan Mikayelyan dwc2_gadget_incr_frame_num(hs_ep); 2455ec1f9d9fSRoman Bacik } 2456ec1f9d9fSRoman Bacik 24571f91b4ccSFelipe Balbi dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result); 245847a1685fSDinh Nguyen } 245947a1685fSDinh Nguyen 246047a1685fSDinh Nguyen /** 24611f91b4ccSFelipe Balbi * dwc2_hsotg_handle_rx - RX FIFO has data 246247a1685fSDinh Nguyen * @hsotg: The device instance 246347a1685fSDinh Nguyen * 246447a1685fSDinh Nguyen * The IRQ handler has detected that the RX FIFO has some data in it 246547a1685fSDinh Nguyen * that requires processing, so find out what is in there and do the 246647a1685fSDinh Nguyen * appropriate read. 246747a1685fSDinh Nguyen * 246847a1685fSDinh Nguyen * The RXFIFO is a true FIFO, the packets coming out are still in packet 246947a1685fSDinh Nguyen * chunks, so if you have x packets received on an endpoint you'll get x 247047a1685fSDinh Nguyen * FIFO events delivered, each with a packet's worth of data in it. 247147a1685fSDinh Nguyen * 247247a1685fSDinh Nguyen * When using DMA, we should not be processing events from the RXFIFO 247347a1685fSDinh Nguyen * as the actual data should be sent to the memory directly and we turn 247447a1685fSDinh Nguyen * on the completion interrupts to get notifications of transfer completion. 247547a1685fSDinh Nguyen */ 24761f91b4ccSFelipe Balbi static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg) 247747a1685fSDinh Nguyen { 2478f25c42b8SGevorg Sahakyan u32 grxstsr = dwc2_readl(hsotg, GRXSTSP); 247947a1685fSDinh Nguyen u32 epnum, status, size; 248047a1685fSDinh Nguyen 248147a1685fSDinh Nguyen WARN_ON(using_dma(hsotg)); 248247a1685fSDinh Nguyen 248347a1685fSDinh Nguyen epnum = grxstsr & GRXSTS_EPNUM_MASK; 248447a1685fSDinh Nguyen status = grxstsr & GRXSTS_PKTSTS_MASK; 248547a1685fSDinh Nguyen 248647a1685fSDinh Nguyen size = grxstsr & GRXSTS_BYTECNT_MASK; 248747a1685fSDinh Nguyen size >>= GRXSTS_BYTECNT_SHIFT; 248847a1685fSDinh Nguyen 248947a1685fSDinh Nguyen dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n", 249047a1685fSDinh Nguyen __func__, grxstsr, size, epnum); 249147a1685fSDinh Nguyen 249247a1685fSDinh Nguyen switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) { 249347a1685fSDinh Nguyen case GRXSTS_PKTSTS_GLOBALOUTNAK: 249447a1685fSDinh Nguyen dev_dbg(hsotg->dev, "GLOBALOUTNAK\n"); 249547a1685fSDinh Nguyen break; 249647a1685fSDinh Nguyen 249747a1685fSDinh Nguyen case GRXSTS_PKTSTS_OUTDONE: 249847a1685fSDinh Nguyen dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n", 24991f91b4ccSFelipe Balbi dwc2_hsotg_read_frameno(hsotg)); 250047a1685fSDinh Nguyen 250147a1685fSDinh Nguyen if (!using_dma(hsotg)) 25021f91b4ccSFelipe Balbi dwc2_hsotg_handle_outdone(hsotg, epnum); 250347a1685fSDinh Nguyen break; 250447a1685fSDinh Nguyen 250547a1685fSDinh Nguyen case GRXSTS_PKTSTS_SETUPDONE: 250647a1685fSDinh Nguyen dev_dbg(hsotg->dev, 250747a1685fSDinh Nguyen "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n", 25081f91b4ccSFelipe Balbi dwc2_hsotg_read_frameno(hsotg), 2509f25c42b8SGevorg Sahakyan dwc2_readl(hsotg, DOEPCTL(0))); 2510fe0b94abSMian Yousaf Kaukab /* 25111f91b4ccSFelipe Balbi * Call dwc2_hsotg_handle_outdone here if it was not called from 2512fe0b94abSMian Yousaf Kaukab * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't 2513fe0b94abSMian Yousaf Kaukab * generate GRXSTS_PKTSTS_OUTDONE for setup packet. 2514fe0b94abSMian Yousaf Kaukab */ 2515fe0b94abSMian Yousaf Kaukab if (hsotg->ep0_state == DWC2_EP0_SETUP) 25161f91b4ccSFelipe Balbi dwc2_hsotg_handle_outdone(hsotg, epnum); 251747a1685fSDinh Nguyen break; 251847a1685fSDinh Nguyen 251947a1685fSDinh Nguyen case GRXSTS_PKTSTS_OUTRX: 25201f91b4ccSFelipe Balbi dwc2_hsotg_rx_data(hsotg, epnum, size); 252147a1685fSDinh Nguyen break; 252247a1685fSDinh Nguyen 252347a1685fSDinh Nguyen case GRXSTS_PKTSTS_SETUPRX: 252447a1685fSDinh Nguyen dev_dbg(hsotg->dev, 252547a1685fSDinh Nguyen "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n", 25261f91b4ccSFelipe Balbi dwc2_hsotg_read_frameno(hsotg), 2527f25c42b8SGevorg Sahakyan dwc2_readl(hsotg, DOEPCTL(0))); 252847a1685fSDinh Nguyen 2529fe0b94abSMian Yousaf Kaukab WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP); 2530fe0b94abSMian Yousaf Kaukab 25311f91b4ccSFelipe Balbi dwc2_hsotg_rx_data(hsotg, epnum, size); 253247a1685fSDinh Nguyen break; 253347a1685fSDinh Nguyen 253447a1685fSDinh Nguyen default: 253547a1685fSDinh Nguyen dev_warn(hsotg->dev, "%s: unknown status %08x\n", 253647a1685fSDinh Nguyen __func__, grxstsr); 253747a1685fSDinh Nguyen 25381f91b4ccSFelipe Balbi dwc2_hsotg_dump(hsotg); 253947a1685fSDinh Nguyen break; 254047a1685fSDinh Nguyen } 254147a1685fSDinh Nguyen } 254247a1685fSDinh Nguyen 254347a1685fSDinh Nguyen /** 25441f91b4ccSFelipe Balbi * dwc2_hsotg_ep0_mps - turn max packet size into register setting 254547a1685fSDinh Nguyen * @mps: The maximum packet size in bytes. 254647a1685fSDinh Nguyen */ 25471f91b4ccSFelipe Balbi static u32 dwc2_hsotg_ep0_mps(unsigned int mps) 254847a1685fSDinh Nguyen { 254947a1685fSDinh Nguyen switch (mps) { 255047a1685fSDinh Nguyen case 64: 255147a1685fSDinh Nguyen return D0EPCTL_MPS_64; 255247a1685fSDinh Nguyen case 32: 255347a1685fSDinh Nguyen return D0EPCTL_MPS_32; 255447a1685fSDinh Nguyen case 16: 255547a1685fSDinh Nguyen return D0EPCTL_MPS_16; 255647a1685fSDinh Nguyen case 8: 255747a1685fSDinh Nguyen return D0EPCTL_MPS_8; 255847a1685fSDinh Nguyen } 255947a1685fSDinh Nguyen 256047a1685fSDinh Nguyen /* bad max packet size, warn and return invalid result */ 256147a1685fSDinh Nguyen WARN_ON(1); 256247a1685fSDinh Nguyen return (u32)-1; 256347a1685fSDinh Nguyen } 256447a1685fSDinh Nguyen 256547a1685fSDinh Nguyen /** 25661f91b4ccSFelipe Balbi * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field 256747a1685fSDinh Nguyen * @hsotg: The driver state. 256847a1685fSDinh Nguyen * @ep: The index number of the endpoint 256947a1685fSDinh Nguyen * @mps: The maximum packet size in bytes 2570ee2c40deSVardan Mikayelyan * @mc: The multicount value 25716fb914d7SGrigor Tovmasyan * @dir_in: True if direction is in. 257247a1685fSDinh Nguyen * 257347a1685fSDinh Nguyen * Configure the maximum packet size for the given endpoint, updating 257447a1685fSDinh Nguyen * the hardware control registers to reflect this. 257547a1685fSDinh Nguyen */ 25761f91b4ccSFelipe Balbi static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg, 2577ee2c40deSVardan Mikayelyan unsigned int ep, unsigned int mps, 2578ee2c40deSVardan Mikayelyan unsigned int mc, unsigned int dir_in) 257947a1685fSDinh Nguyen { 25801f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *hs_ep; 258147a1685fSDinh Nguyen u32 reg; 258247a1685fSDinh Nguyen 2583c6f5c050SMian Yousaf Kaukab hs_ep = index_to_ep(hsotg, ep, dir_in); 2584c6f5c050SMian Yousaf Kaukab if (!hs_ep) 2585c6f5c050SMian Yousaf Kaukab return; 2586c6f5c050SMian Yousaf Kaukab 258747a1685fSDinh Nguyen if (ep == 0) { 2588ee2c40deSVardan Mikayelyan u32 mps_bytes = mps; 2589ee2c40deSVardan Mikayelyan 259047a1685fSDinh Nguyen /* EP0 is a special case */ 2591ee2c40deSVardan Mikayelyan mps = dwc2_hsotg_ep0_mps(mps_bytes); 2592ee2c40deSVardan Mikayelyan if (mps > 3) 259347a1685fSDinh Nguyen goto bad_mps; 2594ee2c40deSVardan Mikayelyan hs_ep->ep.maxpacket = mps_bytes; 259547a1685fSDinh Nguyen hs_ep->mc = 1; 259647a1685fSDinh Nguyen } else { 2597ee2c40deSVardan Mikayelyan if (mps > 1024) 259847a1685fSDinh Nguyen goto bad_mps; 2599ee2c40deSVardan Mikayelyan hs_ep->mc = mc; 2600ee2c40deSVardan Mikayelyan if (mc > 3) 260147a1685fSDinh Nguyen goto bad_mps; 2602ee2c40deSVardan Mikayelyan hs_ep->ep.maxpacket = mps; 260347a1685fSDinh Nguyen } 260447a1685fSDinh Nguyen 2605c6f5c050SMian Yousaf Kaukab if (dir_in) { 2606f25c42b8SGevorg Sahakyan reg = dwc2_readl(hsotg, DIEPCTL(ep)); 260747a1685fSDinh Nguyen reg &= ~DXEPCTL_MPS_MASK; 2608ee2c40deSVardan Mikayelyan reg |= mps; 2609f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, reg, DIEPCTL(ep)); 2610c6f5c050SMian Yousaf Kaukab } else { 2611f25c42b8SGevorg Sahakyan reg = dwc2_readl(hsotg, DOEPCTL(ep)); 261247a1685fSDinh Nguyen reg &= ~DXEPCTL_MPS_MASK; 2613ee2c40deSVardan Mikayelyan reg |= mps; 2614f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, reg, DOEPCTL(ep)); 261547a1685fSDinh Nguyen } 261647a1685fSDinh Nguyen 261747a1685fSDinh Nguyen return; 261847a1685fSDinh Nguyen 261947a1685fSDinh Nguyen bad_mps: 262047a1685fSDinh Nguyen dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps); 262147a1685fSDinh Nguyen } 262247a1685fSDinh Nguyen 262347a1685fSDinh Nguyen /** 26241f91b4ccSFelipe Balbi * dwc2_hsotg_txfifo_flush - flush Tx FIFO 262547a1685fSDinh Nguyen * @hsotg: The driver state 262647a1685fSDinh Nguyen * @idx: The index for the endpoint (0..15) 262747a1685fSDinh Nguyen */ 26281f91b4ccSFelipe Balbi static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx) 262947a1685fSDinh Nguyen { 2630f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH, 2631f25c42b8SGevorg Sahakyan GRSTCTL); 263247a1685fSDinh Nguyen 263347a1685fSDinh Nguyen /* wait until the fifo is flushed */ 263479d6b8c5SSevak Arakelyan if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100)) 263579d6b8c5SSevak Arakelyan dev_warn(hsotg->dev, "%s: timeout flushing fifo GRSTCTL_TXFFLSH\n", 263679d6b8c5SSevak Arakelyan __func__); 263747a1685fSDinh Nguyen } 263847a1685fSDinh Nguyen 263947a1685fSDinh Nguyen /** 26401f91b4ccSFelipe Balbi * dwc2_hsotg_trytx - check to see if anything needs transmitting 264147a1685fSDinh Nguyen * @hsotg: The driver state 264247a1685fSDinh Nguyen * @hs_ep: The driver endpoint to check. 264347a1685fSDinh Nguyen * 264447a1685fSDinh Nguyen * Check to see if there is a request that has data to send, and if so 264547a1685fSDinh Nguyen * make an attempt to write data into the FIFO. 264647a1685fSDinh Nguyen */ 26471f91b4ccSFelipe Balbi static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg, 26481f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *hs_ep) 264947a1685fSDinh Nguyen { 26501f91b4ccSFelipe Balbi struct dwc2_hsotg_req *hs_req = hs_ep->req; 265147a1685fSDinh Nguyen 265247a1685fSDinh Nguyen if (!hs_ep->dir_in || !hs_req) { 265347a1685fSDinh Nguyen /** 265447a1685fSDinh Nguyen * if request is not enqueued, we disable interrupts 265547a1685fSDinh Nguyen * for endpoints, excepting ep0 265647a1685fSDinh Nguyen */ 265747a1685fSDinh Nguyen if (hs_ep->index != 0) 26581f91b4ccSFelipe Balbi dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, 265947a1685fSDinh Nguyen hs_ep->dir_in, 0); 266047a1685fSDinh Nguyen return 0; 266147a1685fSDinh Nguyen } 266247a1685fSDinh Nguyen 266347a1685fSDinh Nguyen if (hs_req->req.actual < hs_req->req.length) { 266447a1685fSDinh Nguyen dev_dbg(hsotg->dev, "trying to write more for ep%d\n", 266547a1685fSDinh Nguyen hs_ep->index); 26661f91b4ccSFelipe Balbi return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req); 266747a1685fSDinh Nguyen } 266847a1685fSDinh Nguyen 266947a1685fSDinh Nguyen return 0; 267047a1685fSDinh Nguyen } 267147a1685fSDinh Nguyen 267247a1685fSDinh Nguyen /** 26731f91b4ccSFelipe Balbi * dwc2_hsotg_complete_in - complete IN transfer 267447a1685fSDinh Nguyen * @hsotg: The device state. 267547a1685fSDinh Nguyen * @hs_ep: The endpoint that has just completed. 267647a1685fSDinh Nguyen * 267747a1685fSDinh Nguyen * An IN transfer has been completed, update the transfer's state and then 267847a1685fSDinh Nguyen * call the relevant completion routines. 267947a1685fSDinh Nguyen */ 26801f91b4ccSFelipe Balbi static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg, 26811f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *hs_ep) 268247a1685fSDinh Nguyen { 26831f91b4ccSFelipe Balbi struct dwc2_hsotg_req *hs_req = hs_ep->req; 2684f25c42b8SGevorg Sahakyan u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index)); 268547a1685fSDinh Nguyen int size_left, size_done; 268647a1685fSDinh Nguyen 268747a1685fSDinh Nguyen if (!hs_req) { 268847a1685fSDinh Nguyen dev_dbg(hsotg->dev, "XferCompl but no req\n"); 268947a1685fSDinh Nguyen return; 269047a1685fSDinh Nguyen } 269147a1685fSDinh Nguyen 269247a1685fSDinh Nguyen /* Finish ZLP handling for IN EP0 transactions */ 2693fe0b94abSMian Yousaf Kaukab if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) { 2694fe0b94abSMian Yousaf Kaukab dev_dbg(hsotg->dev, "zlp packet sent\n"); 2695c3b22fe2SRazmik Karapetyan 2696c3b22fe2SRazmik Karapetyan /* 2697c3b22fe2SRazmik Karapetyan * While send zlp for DWC2_EP0_STATUS_IN EP direction was 2698c3b22fe2SRazmik Karapetyan * changed to IN. Change back to complete OUT transfer request 2699c3b22fe2SRazmik Karapetyan */ 2700c3b22fe2SRazmik Karapetyan hs_ep->dir_in = 0; 2701c3b22fe2SRazmik Karapetyan 27021f91b4ccSFelipe Balbi dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); 27039e14d0a5SGregory Herrero if (hsotg->test_mode) { 27049e14d0a5SGregory Herrero int ret; 27059e14d0a5SGregory Herrero 27061f91b4ccSFelipe Balbi ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode); 27079e14d0a5SGregory Herrero if (ret < 0) { 27089e14d0a5SGregory Herrero dev_dbg(hsotg->dev, "Invalid Test #%d\n", 27099e14d0a5SGregory Herrero hsotg->test_mode); 27101f91b4ccSFelipe Balbi dwc2_hsotg_stall_ep0(hsotg); 27119e14d0a5SGregory Herrero return; 27129e14d0a5SGregory Herrero } 27139e14d0a5SGregory Herrero } 27141f91b4ccSFelipe Balbi dwc2_hsotg_enqueue_setup(hsotg); 271547a1685fSDinh Nguyen return; 271647a1685fSDinh Nguyen } 271747a1685fSDinh Nguyen 271847a1685fSDinh Nguyen /* 271947a1685fSDinh Nguyen * Calculate the size of the transfer by checking how much is left 272047a1685fSDinh Nguyen * in the endpoint size register and then working it out from 272147a1685fSDinh Nguyen * the amount we loaded for the transfer. 272247a1685fSDinh Nguyen * 272347a1685fSDinh Nguyen * We do this even for DMA, as the transfer may have incremented 272447a1685fSDinh Nguyen * past the end of the buffer (DMA transfers are always 32bit 272547a1685fSDinh Nguyen * aligned). 272647a1685fSDinh Nguyen */ 2727aa3e8bc8SVahram Aharonyan if (using_desc_dma(hsotg)) { 2728aa3e8bc8SVahram Aharonyan size_left = dwc2_gadget_get_xfersize_ddma(hs_ep); 2729aa3e8bc8SVahram Aharonyan if (size_left < 0) 2730aa3e8bc8SVahram Aharonyan dev_err(hsotg->dev, "error parsing DDMA results %d\n", 2731aa3e8bc8SVahram Aharonyan size_left); 2732aa3e8bc8SVahram Aharonyan } else { 273347a1685fSDinh Nguyen size_left = DXEPTSIZ_XFERSIZE_GET(epsize); 2734aa3e8bc8SVahram Aharonyan } 273547a1685fSDinh Nguyen 273647a1685fSDinh Nguyen size_done = hs_ep->size_loaded - size_left; 273747a1685fSDinh Nguyen size_done += hs_ep->last_load; 273847a1685fSDinh Nguyen 273947a1685fSDinh Nguyen if (hs_req->req.actual != size_done) 274047a1685fSDinh Nguyen dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n", 274147a1685fSDinh Nguyen __func__, hs_req->req.actual, size_done); 274247a1685fSDinh Nguyen 274347a1685fSDinh Nguyen hs_req->req.actual = size_done; 274447a1685fSDinh Nguyen dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n", 274547a1685fSDinh Nguyen hs_req->req.length, hs_req->req.actual, hs_req->req.zero); 274647a1685fSDinh Nguyen 274747a1685fSDinh Nguyen if (!size_left && hs_req->req.actual < hs_req->req.length) { 274847a1685fSDinh Nguyen dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__); 27491f91b4ccSFelipe Balbi dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true); 2750fe0b94abSMian Yousaf Kaukab return; 2751fe0b94abSMian Yousaf Kaukab } 2752fe0b94abSMian Yousaf Kaukab 2753d53dc388SMinas Harutyunyan /* Zlp for all endpoints in non DDMA, for ep0 only in DATA IN stage */ 27548a20fa45SMian Yousaf Kaukab if (hs_ep->send_zlp) { 27558a20fa45SMian Yousaf Kaukab hs_ep->send_zlp = 0; 2756d53dc388SMinas Harutyunyan if (!using_desc_dma(hsotg)) { 2757d53dc388SMinas Harutyunyan dwc2_hsotg_program_zlp(hsotg, hs_ep); 2758f71b5e25SMian Yousaf Kaukab /* transfer will be completed on next complete interrupt */ 2759f71b5e25SMian Yousaf Kaukab return; 2760f71b5e25SMian Yousaf Kaukab } 2761d53dc388SMinas Harutyunyan } 2762f71b5e25SMian Yousaf Kaukab 2763fe0b94abSMian Yousaf Kaukab if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) { 2764fe0b94abSMian Yousaf Kaukab /* Move to STATUS OUT */ 27651f91b4ccSFelipe Balbi dwc2_hsotg_ep0_zlp(hsotg, false); 2766fe0b94abSMian Yousaf Kaukab return; 2767fe0b94abSMian Yousaf Kaukab } 2768fe0b94abSMian Yousaf Kaukab 2769*91bb163eSMinas Harutyunyan /* Set actual frame number for completed transfers */ 2770*91bb163eSMinas Harutyunyan if (!using_desc_dma(hsotg) && hs_ep->isochronous) { 2771*91bb163eSMinas Harutyunyan hs_req->req.frame_number = hs_ep->target_frame; 2772*91bb163eSMinas Harutyunyan dwc2_gadget_incr_frame_num(hs_ep); 2773*91bb163eSMinas Harutyunyan } 2774*91bb163eSMinas Harutyunyan 27751f91b4ccSFelipe Balbi dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); 277647a1685fSDinh Nguyen } 277747a1685fSDinh Nguyen 277847a1685fSDinh Nguyen /** 277932601588SVardan Mikayelyan * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep 278032601588SVardan Mikayelyan * @hsotg: The device state. 278132601588SVardan Mikayelyan * @idx: Index of ep. 278232601588SVardan Mikayelyan * @dir_in: Endpoint direction 1-in 0-out. 278332601588SVardan Mikayelyan * 278432601588SVardan Mikayelyan * Reads for endpoint with given index and direction, by masking 278532601588SVardan Mikayelyan * epint_reg with coresponding mask. 278632601588SVardan Mikayelyan */ 278732601588SVardan Mikayelyan static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg, 278832601588SVardan Mikayelyan unsigned int idx, int dir_in) 278932601588SVardan Mikayelyan { 279032601588SVardan Mikayelyan u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK; 279132601588SVardan Mikayelyan u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); 279232601588SVardan Mikayelyan u32 ints; 279332601588SVardan Mikayelyan u32 mask; 279432601588SVardan Mikayelyan u32 diepempmsk; 279532601588SVardan Mikayelyan 2796f25c42b8SGevorg Sahakyan mask = dwc2_readl(hsotg, epmsk_reg); 2797f25c42b8SGevorg Sahakyan diepempmsk = dwc2_readl(hsotg, DIEPEMPMSK); 279832601588SVardan Mikayelyan mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0; 279932601588SVardan Mikayelyan mask |= DXEPINT_SETUP_RCVD; 280032601588SVardan Mikayelyan 2801f25c42b8SGevorg Sahakyan ints = dwc2_readl(hsotg, epint_reg); 280232601588SVardan Mikayelyan ints &= mask; 280332601588SVardan Mikayelyan return ints; 280432601588SVardan Mikayelyan } 280532601588SVardan Mikayelyan 280632601588SVardan Mikayelyan /** 2807bd9971f0SVardan Mikayelyan * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD 2808bd9971f0SVardan Mikayelyan * @hs_ep: The endpoint on which interrupt is asserted. 2809bd9971f0SVardan Mikayelyan * 2810bd9971f0SVardan Mikayelyan * This interrupt indicates that the endpoint has been disabled per the 2811bd9971f0SVardan Mikayelyan * application's request. 2812bd9971f0SVardan Mikayelyan * 2813bd9971f0SVardan Mikayelyan * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK, 2814bd9971f0SVardan Mikayelyan * in case of ISOC completes current request. 2815bd9971f0SVardan Mikayelyan * 2816bd9971f0SVardan Mikayelyan * For ISOC-OUT endpoints completes expired requests. If there is remaining 2817bd9971f0SVardan Mikayelyan * request starts it. 2818bd9971f0SVardan Mikayelyan */ 2819bd9971f0SVardan Mikayelyan static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep) 2820bd9971f0SVardan Mikayelyan { 2821bd9971f0SVardan Mikayelyan struct dwc2_hsotg *hsotg = hs_ep->parent; 2822bd9971f0SVardan Mikayelyan struct dwc2_hsotg_req *hs_req; 2823bd9971f0SVardan Mikayelyan unsigned char idx = hs_ep->index; 2824bd9971f0SVardan Mikayelyan int dir_in = hs_ep->dir_in; 2825bd9971f0SVardan Mikayelyan u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); 2826f25c42b8SGevorg Sahakyan int dctl = dwc2_readl(hsotg, DCTL); 2827bd9971f0SVardan Mikayelyan 2828bd9971f0SVardan Mikayelyan dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__); 2829bd9971f0SVardan Mikayelyan 2830bd9971f0SVardan Mikayelyan if (dir_in) { 2831f25c42b8SGevorg Sahakyan int epctl = dwc2_readl(hsotg, epctl_reg); 2832bd9971f0SVardan Mikayelyan 2833bd9971f0SVardan Mikayelyan dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index); 2834bd9971f0SVardan Mikayelyan 2835bd9971f0SVardan Mikayelyan if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) { 2836f25c42b8SGevorg Sahakyan int dctl = dwc2_readl(hsotg, DCTL); 2837bd9971f0SVardan Mikayelyan 2838bd9971f0SVardan Mikayelyan dctl |= DCTL_CGNPINNAK; 2839f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, dctl, DCTL); 2840bd9971f0SVardan Mikayelyan } 2841*91bb163eSMinas Harutyunyan } else { 2842bd9971f0SVardan Mikayelyan 2843bd9971f0SVardan Mikayelyan if (dctl & DCTL_GOUTNAKSTS) { 2844bd9971f0SVardan Mikayelyan dctl |= DCTL_CGOUTNAK; 2845f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, dctl, DCTL); 2846bd9971f0SVardan Mikayelyan } 2847*91bb163eSMinas Harutyunyan } 2848bd9971f0SVardan Mikayelyan 2849bd9971f0SVardan Mikayelyan if (!hs_ep->isochronous) 2850bd9971f0SVardan Mikayelyan return; 2851bd9971f0SVardan Mikayelyan 2852bd9971f0SVardan Mikayelyan if (list_empty(&hs_ep->queue)) { 2853bd9971f0SVardan Mikayelyan dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n", 2854bd9971f0SVardan Mikayelyan __func__, hs_ep); 2855bd9971f0SVardan Mikayelyan return; 2856bd9971f0SVardan Mikayelyan } 2857bd9971f0SVardan Mikayelyan 2858bd9971f0SVardan Mikayelyan do { 2859bd9971f0SVardan Mikayelyan hs_req = get_ep_head(hs_ep); 2860bd9971f0SVardan Mikayelyan if (hs_req) 2861bd9971f0SVardan Mikayelyan dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 2862bd9971f0SVardan Mikayelyan -ENODATA); 2863bd9971f0SVardan Mikayelyan dwc2_gadget_incr_frame_num(hs_ep); 2864c7c24e7aSArtur Petrosyan /* Update current frame number value. */ 2865c7c24e7aSArtur Petrosyan hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg); 2866bd9971f0SVardan Mikayelyan } while (dwc2_gadget_target_frame_elapsed(hs_ep)); 2867bd9971f0SVardan Mikayelyan } 2868bd9971f0SVardan Mikayelyan 2869bd9971f0SVardan Mikayelyan /** 28705321922cSVardan Mikayelyan * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS 28716fb914d7SGrigor Tovmasyan * @ep: The endpoint on which interrupt is asserted. 28725321922cSVardan Mikayelyan * 28735321922cSVardan Mikayelyan * This is starting point for ISOC-OUT transfer, synchronization done with 28745321922cSVardan Mikayelyan * first out token received from host while corresponding EP is disabled. 28755321922cSVardan Mikayelyan * 28765321922cSVardan Mikayelyan * Device does not know initial frame in which out token will come. For this 28775321922cSVardan Mikayelyan * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon 28785321922cSVardan Mikayelyan * getting this interrupt SW starts calculation for next transfer frame. 28795321922cSVardan Mikayelyan */ 28805321922cSVardan Mikayelyan static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep) 28815321922cSVardan Mikayelyan { 28825321922cSVardan Mikayelyan struct dwc2_hsotg *hsotg = ep->parent; 2883*91bb163eSMinas Harutyunyan struct dwc2_hsotg_req *hs_req; 28845321922cSVardan Mikayelyan int dir_in = ep->dir_in; 28855321922cSVardan Mikayelyan 28865321922cSVardan Mikayelyan if (dir_in || !ep->isochronous) 28875321922cSVardan Mikayelyan return; 28885321922cSVardan Mikayelyan 2889540ccba0SVahram Aharonyan if (using_desc_dma(hsotg)) { 2890540ccba0SVahram Aharonyan if (ep->target_frame == TARGET_FRAME_INITIAL) { 2891540ccba0SVahram Aharonyan /* Start first ISO Out */ 28924d4f1e79SMinas Harutyunyan ep->target_frame = hsotg->frame_number; 2893540ccba0SVahram Aharonyan dwc2_gadget_start_isoc_ddma(ep); 2894540ccba0SVahram Aharonyan } 2895540ccba0SVahram Aharonyan return; 2896540ccba0SVahram Aharonyan } 2897540ccba0SVahram Aharonyan 2898*91bb163eSMinas Harutyunyan if (ep->target_frame == TARGET_FRAME_INITIAL) { 28995321922cSVardan Mikayelyan u32 ctrl; 29005321922cSVardan Mikayelyan 29014d4f1e79SMinas Harutyunyan ep->target_frame = hsotg->frame_number; 2902*91bb163eSMinas Harutyunyan if (ep->interval > 1) { 2903f25c42b8SGevorg Sahakyan ctrl = dwc2_readl(hsotg, DOEPCTL(ep->index)); 29045321922cSVardan Mikayelyan if (ep->target_frame & 0x1) 29055321922cSVardan Mikayelyan ctrl |= DXEPCTL_SETODDFR; 29065321922cSVardan Mikayelyan else 29075321922cSVardan Mikayelyan ctrl |= DXEPCTL_SETEVENFR; 29085321922cSVardan Mikayelyan 2909f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, ctrl, DOEPCTL(ep->index)); 29105321922cSVardan Mikayelyan } 29115321922cSVardan Mikayelyan } 29125321922cSVardan Mikayelyan 2913*91bb163eSMinas Harutyunyan while (dwc2_gadget_target_frame_elapsed(ep)) { 2914*91bb163eSMinas Harutyunyan hs_req = get_ep_head(ep); 2915*91bb163eSMinas Harutyunyan if (hs_req) 2916*91bb163eSMinas Harutyunyan dwc2_hsotg_complete_request(hsotg, ep, hs_req, -ENODATA); 2917*91bb163eSMinas Harutyunyan 2918*91bb163eSMinas Harutyunyan dwc2_gadget_incr_frame_num(ep); 2919*91bb163eSMinas Harutyunyan /* Update current frame number value. */ 2920*91bb163eSMinas Harutyunyan hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg); 2921*91bb163eSMinas Harutyunyan } 2922*91bb163eSMinas Harutyunyan 2923*91bb163eSMinas Harutyunyan if (!ep->req) 2924*91bb163eSMinas Harutyunyan dwc2_gadget_start_next_request(ep); 2925*91bb163eSMinas Harutyunyan 2926*91bb163eSMinas Harutyunyan } 2927*91bb163eSMinas Harutyunyan 2928*91bb163eSMinas Harutyunyan static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg, 2929*91bb163eSMinas Harutyunyan struct dwc2_hsotg_ep *hs_ep); 2930*91bb163eSMinas Harutyunyan 29315321922cSVardan Mikayelyan /** 29325321922cSVardan Mikayelyan * dwc2_gadget_handle_nak - handle NAK interrupt 29335321922cSVardan Mikayelyan * @hs_ep: The endpoint on which interrupt is asserted. 29345321922cSVardan Mikayelyan * 29355321922cSVardan Mikayelyan * This is starting point for ISOC-IN transfer, synchronization done with 29365321922cSVardan Mikayelyan * first IN token received from host while corresponding EP is disabled. 29375321922cSVardan Mikayelyan * 29385321922cSVardan Mikayelyan * Device does not know when first one token will arrive from host. On first 29395321922cSVardan Mikayelyan * token arrival HW generates 2 interrupts: 'in token received while FIFO empty' 29405321922cSVardan Mikayelyan * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was 29415321922cSVardan Mikayelyan * sent in response to that as there was no data in FIFO. SW is basing on this 29425321922cSVardan Mikayelyan * interrupt to obtain frame in which token has come and then based on the 29435321922cSVardan Mikayelyan * interval calculates next frame for transfer. 29445321922cSVardan Mikayelyan */ 29455321922cSVardan Mikayelyan static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep) 29465321922cSVardan Mikayelyan { 29475321922cSVardan Mikayelyan struct dwc2_hsotg *hsotg = hs_ep->parent; 2948*91bb163eSMinas Harutyunyan struct dwc2_hsotg_req *hs_req; 29495321922cSVardan Mikayelyan int dir_in = hs_ep->dir_in; 2950*91bb163eSMinas Harutyunyan u32 ctrl; 29515321922cSVardan Mikayelyan 29525321922cSVardan Mikayelyan if (!dir_in || !hs_ep->isochronous) 29535321922cSVardan Mikayelyan return; 29545321922cSVardan Mikayelyan 29555321922cSVardan Mikayelyan if (hs_ep->target_frame == TARGET_FRAME_INITIAL) { 2956540ccba0SVahram Aharonyan 2957540ccba0SVahram Aharonyan if (using_desc_dma(hsotg)) { 29584d4f1e79SMinas Harutyunyan hs_ep->target_frame = hsotg->frame_number; 2959729cac69SMinas Harutyunyan dwc2_gadget_incr_frame_num(hs_ep); 296048dac4e4SGrigor Tovmasyan 296148dac4e4SGrigor Tovmasyan /* In service interval mode target_frame must 296248dac4e4SGrigor Tovmasyan * be set to last (u)frame of the service interval. 296348dac4e4SGrigor Tovmasyan */ 296448dac4e4SGrigor Tovmasyan if (hsotg->params.service_interval) { 296548dac4e4SGrigor Tovmasyan /* Set target_frame to the first (u)frame of 296648dac4e4SGrigor Tovmasyan * the service interval 296748dac4e4SGrigor Tovmasyan */ 296848dac4e4SGrigor Tovmasyan hs_ep->target_frame &= ~hs_ep->interval + 1; 296948dac4e4SGrigor Tovmasyan 297048dac4e4SGrigor Tovmasyan /* Set target_frame to the last (u)frame of 297148dac4e4SGrigor Tovmasyan * the service interval 297248dac4e4SGrigor Tovmasyan */ 297348dac4e4SGrigor Tovmasyan dwc2_gadget_incr_frame_num(hs_ep); 297448dac4e4SGrigor Tovmasyan dwc2_gadget_dec_frame_num_by_one(hs_ep); 297548dac4e4SGrigor Tovmasyan } 297648dac4e4SGrigor Tovmasyan 2977540ccba0SVahram Aharonyan dwc2_gadget_start_isoc_ddma(hs_ep); 2978540ccba0SVahram Aharonyan return; 2979540ccba0SVahram Aharonyan } 2980540ccba0SVahram Aharonyan 29814d4f1e79SMinas Harutyunyan hs_ep->target_frame = hsotg->frame_number; 29825321922cSVardan Mikayelyan if (hs_ep->interval > 1) { 2983f25c42b8SGevorg Sahakyan u32 ctrl = dwc2_readl(hsotg, 29845321922cSVardan Mikayelyan DIEPCTL(hs_ep->index)); 29855321922cSVardan Mikayelyan if (hs_ep->target_frame & 0x1) 29865321922cSVardan Mikayelyan ctrl |= DXEPCTL_SETODDFR; 29875321922cSVardan Mikayelyan else 29885321922cSVardan Mikayelyan ctrl |= DXEPCTL_SETEVENFR; 29895321922cSVardan Mikayelyan 2990f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, ctrl, DIEPCTL(hs_ep->index)); 29915321922cSVardan Mikayelyan } 29925321922cSVardan Mikayelyan } 29935321922cSVardan Mikayelyan 2994*91bb163eSMinas Harutyunyan if (using_desc_dma(hsotg)) 2995*91bb163eSMinas Harutyunyan return; 2996*91bb163eSMinas Harutyunyan 2997*91bb163eSMinas Harutyunyan ctrl = dwc2_readl(hsotg, DIEPCTL(hs_ep->index)); 2998*91bb163eSMinas Harutyunyan if (ctrl & DXEPCTL_EPENA) 2999*91bb163eSMinas Harutyunyan dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep); 3000*91bb163eSMinas Harutyunyan else 3001*91bb163eSMinas Harutyunyan dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index); 3002*91bb163eSMinas Harutyunyan 3003*91bb163eSMinas Harutyunyan while (dwc2_gadget_target_frame_elapsed(hs_ep)) { 3004*91bb163eSMinas Harutyunyan hs_req = get_ep_head(hs_ep); 3005*91bb163eSMinas Harutyunyan if (hs_req) 3006*91bb163eSMinas Harutyunyan dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, -ENODATA); 3007*91bb163eSMinas Harutyunyan 30085321922cSVardan Mikayelyan dwc2_gadget_incr_frame_num(hs_ep); 3009*91bb163eSMinas Harutyunyan /* Update current frame number value. */ 3010*91bb163eSMinas Harutyunyan hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg); 3011*91bb163eSMinas Harutyunyan } 3012*91bb163eSMinas Harutyunyan 3013*91bb163eSMinas Harutyunyan if (!hs_ep->req) 3014*91bb163eSMinas Harutyunyan dwc2_gadget_start_next_request(hs_ep); 30155321922cSVardan Mikayelyan } 30165321922cSVardan Mikayelyan 30175321922cSVardan Mikayelyan /** 30181f91b4ccSFelipe Balbi * dwc2_hsotg_epint - handle an in/out endpoint interrupt 301947a1685fSDinh Nguyen * @hsotg: The driver state 302047a1685fSDinh Nguyen * @idx: The index for the endpoint (0..15) 302147a1685fSDinh Nguyen * @dir_in: Set if this is an IN endpoint 302247a1685fSDinh Nguyen * 302347a1685fSDinh Nguyen * Process and clear any interrupt pending for an individual endpoint 302447a1685fSDinh Nguyen */ 30251f91b4ccSFelipe Balbi static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx, 302647a1685fSDinh Nguyen int dir_in) 302747a1685fSDinh Nguyen { 30281f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in); 302947a1685fSDinh Nguyen u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); 303047a1685fSDinh Nguyen u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); 303147a1685fSDinh Nguyen u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx); 303247a1685fSDinh Nguyen u32 ints; 303347a1685fSDinh Nguyen 303432601588SVardan Mikayelyan ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in); 303547a1685fSDinh Nguyen 303647a1685fSDinh Nguyen /* Clear endpoint interrupts */ 3037f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, ints, epint_reg); 303847a1685fSDinh Nguyen 3039c6f5c050SMian Yousaf Kaukab if (!hs_ep) { 3040c6f5c050SMian Yousaf Kaukab dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n", 3041c6f5c050SMian Yousaf Kaukab __func__, idx, dir_in ? "in" : "out"); 3042c6f5c050SMian Yousaf Kaukab return; 3043c6f5c050SMian Yousaf Kaukab } 3044c6f5c050SMian Yousaf Kaukab 304547a1685fSDinh Nguyen dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n", 304647a1685fSDinh Nguyen __func__, idx, dir_in ? "in" : "out", ints); 304747a1685fSDinh Nguyen 3048b787d755SMian Yousaf Kaukab /* Don't process XferCompl interrupt if it is a setup packet */ 3049b787d755SMian Yousaf Kaukab if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD))) 3050b787d755SMian Yousaf Kaukab ints &= ~DXEPINT_XFERCOMPL; 3051b787d755SMian Yousaf Kaukab 3052f0afdb42SVahram Aharonyan /* 3053f0afdb42SVahram Aharonyan * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP 3054f0afdb42SVahram Aharonyan * stage and xfercomplete was generated without SETUP phase done 3055f0afdb42SVahram Aharonyan * interrupt. SW should parse received setup packet only after host's 3056f0afdb42SVahram Aharonyan * exit from setup phase of control transfer. 3057f0afdb42SVahram Aharonyan */ 3058f0afdb42SVahram Aharonyan if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in && 3059f0afdb42SVahram Aharonyan hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP)) 3060f0afdb42SVahram Aharonyan ints &= ~DXEPINT_XFERCOMPL; 3061f0afdb42SVahram Aharonyan 3062837e9f00SVardan Mikayelyan if (ints & DXEPINT_XFERCOMPL) { 306347a1685fSDinh Nguyen dev_dbg(hsotg->dev, 306447a1685fSDinh Nguyen "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n", 3065f25c42b8SGevorg Sahakyan __func__, dwc2_readl(hsotg, epctl_reg), 3066f25c42b8SGevorg Sahakyan dwc2_readl(hsotg, epsiz_reg)); 306747a1685fSDinh Nguyen 3068540ccba0SVahram Aharonyan /* In DDMA handle isochronous requests separately */ 3069540ccba0SVahram Aharonyan if (using_desc_dma(hsotg) && hs_ep->isochronous) { 3070729cac69SMinas Harutyunyan /* XferCompl set along with BNA */ 3071729cac69SMinas Harutyunyan if (!(ints & DXEPINT_BNAINTR)) 3072540ccba0SVahram Aharonyan dwc2_gadget_complete_isoc_request_ddma(hs_ep); 3073540ccba0SVahram Aharonyan } else if (dir_in) { 307447a1685fSDinh Nguyen /* 3075540ccba0SVahram Aharonyan * We get OutDone from the FIFO, so we only 3076540ccba0SVahram Aharonyan * need to look at completing IN requests here 3077540ccba0SVahram Aharonyan * if operating slave mode 307847a1685fSDinh Nguyen */ 3079*91bb163eSMinas Harutyunyan if (!hs_ep->isochronous || !(ints & DXEPINT_NAKINTRPT)) 30801f91b4ccSFelipe Balbi dwc2_hsotg_complete_in(hsotg, hs_ep); 308147a1685fSDinh Nguyen 308247a1685fSDinh Nguyen if (idx == 0 && !hs_ep->req) 30831f91b4ccSFelipe Balbi dwc2_hsotg_enqueue_setup(hsotg); 308447a1685fSDinh Nguyen } else if (using_dma(hsotg)) { 308547a1685fSDinh Nguyen /* 308647a1685fSDinh Nguyen * We're using DMA, we need to fire an OutDone here 308747a1685fSDinh Nguyen * as we ignore the RXFIFO. 308847a1685fSDinh Nguyen */ 3089*91bb163eSMinas Harutyunyan if (!hs_ep->isochronous || !(ints & DXEPINT_OUTTKNEPDIS)) 30901f91b4ccSFelipe Balbi dwc2_hsotg_handle_outdone(hsotg, idx); 309147a1685fSDinh Nguyen } 309247a1685fSDinh Nguyen } 309347a1685fSDinh Nguyen 3094bd9971f0SVardan Mikayelyan if (ints & DXEPINT_EPDISBLD) 3095bd9971f0SVardan Mikayelyan dwc2_gadget_handle_ep_disabled(hs_ep); 309647a1685fSDinh Nguyen 30975321922cSVardan Mikayelyan if (ints & DXEPINT_OUTTKNEPDIS) 30985321922cSVardan Mikayelyan dwc2_gadget_handle_out_token_ep_disabled(hs_ep); 30995321922cSVardan Mikayelyan 31005321922cSVardan Mikayelyan if (ints & DXEPINT_NAKINTRPT) 31015321922cSVardan Mikayelyan dwc2_gadget_handle_nak(hs_ep); 31025321922cSVardan Mikayelyan 310347a1685fSDinh Nguyen if (ints & DXEPINT_AHBERR) 310447a1685fSDinh Nguyen dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__); 310547a1685fSDinh Nguyen 310647a1685fSDinh Nguyen if (ints & DXEPINT_SETUP) { /* Setup or Timeout */ 310747a1685fSDinh Nguyen dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__); 310847a1685fSDinh Nguyen 310947a1685fSDinh Nguyen if (using_dma(hsotg) && idx == 0) { 311047a1685fSDinh Nguyen /* 311147a1685fSDinh Nguyen * this is the notification we've received a 311247a1685fSDinh Nguyen * setup packet. In non-DMA mode we'd get this 311347a1685fSDinh Nguyen * from the RXFIFO, instead we need to process 311447a1685fSDinh Nguyen * the setup here. 311547a1685fSDinh Nguyen */ 311647a1685fSDinh Nguyen 311747a1685fSDinh Nguyen if (dir_in) 311847a1685fSDinh Nguyen WARN_ON_ONCE(1); 311947a1685fSDinh Nguyen else 31201f91b4ccSFelipe Balbi dwc2_hsotg_handle_outdone(hsotg, 0); 312147a1685fSDinh Nguyen } 312247a1685fSDinh Nguyen } 312347a1685fSDinh Nguyen 3124ef750c71SVahram Aharonyan if (ints & DXEPINT_STSPHSERCVD) { 31259d9a6b07SVahram Aharonyan dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__); 31269d9a6b07SVahram Aharonyan 31279e95a66cSMinas Harutyunyan /* Safety check EP0 state when STSPHSERCVD asserted */ 31289e95a66cSMinas Harutyunyan if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) { 3129ef750c71SVahram Aharonyan /* Move to STATUS IN for DDMA */ 3130b4c53b4aSMinas Harutyunyan if (using_desc_dma(hsotg)) { 3131b4c53b4aSMinas Harutyunyan if (!hsotg->delayed_status) 3132ef750c71SVahram Aharonyan dwc2_hsotg_ep0_zlp(hsotg, true); 3133b4c53b4aSMinas Harutyunyan else 3134b4c53b4aSMinas Harutyunyan /* In case of 3 stage Control Write with delayed 3135b4c53b4aSMinas Harutyunyan * status, when Status IN transfer started 3136b4c53b4aSMinas Harutyunyan * before STSPHSERCVD asserted, NAKSTS bit not 3137b4c53b4aSMinas Harutyunyan * cleared by CNAK in dwc2_hsotg_start_req() 3138b4c53b4aSMinas Harutyunyan * function. Clear now NAKSTS to allow complete 3139b4c53b4aSMinas Harutyunyan * transfer. 3140b4c53b4aSMinas Harutyunyan */ 3141b4c53b4aSMinas Harutyunyan dwc2_set_bit(hsotg, DIEPCTL(0), 3142b4c53b4aSMinas Harutyunyan DXEPCTL_CNAK); 3143b4c53b4aSMinas Harutyunyan } 3144ef750c71SVahram Aharonyan } 3145ef750c71SVahram Aharonyan 31469e95a66cSMinas Harutyunyan } 31479e95a66cSMinas Harutyunyan 314847a1685fSDinh Nguyen if (ints & DXEPINT_BACK2BACKSETUP) 314947a1685fSDinh Nguyen dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__); 315047a1685fSDinh Nguyen 3151540ccba0SVahram Aharonyan if (ints & DXEPINT_BNAINTR) { 3152540ccba0SVahram Aharonyan dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__); 3153540ccba0SVahram Aharonyan if (hs_ep->isochronous) 3154729cac69SMinas Harutyunyan dwc2_gadget_handle_isoc_bna(hs_ep); 3155540ccba0SVahram Aharonyan } 3156540ccba0SVahram Aharonyan 315747a1685fSDinh Nguyen if (dir_in && !hs_ep->isochronous) { 315847a1685fSDinh Nguyen /* not sure if this is important, but we'll clear it anyway */ 315926ddef5dSVardan Mikayelyan if (ints & DXEPINT_INTKNTXFEMP) { 316047a1685fSDinh Nguyen dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n", 316147a1685fSDinh Nguyen __func__, idx); 316247a1685fSDinh Nguyen } 316347a1685fSDinh Nguyen 316447a1685fSDinh Nguyen /* this probably means something bad is happening */ 316526ddef5dSVardan Mikayelyan if (ints & DXEPINT_INTKNEPMIS) { 316647a1685fSDinh Nguyen dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n", 316747a1685fSDinh Nguyen __func__, idx); 316847a1685fSDinh Nguyen } 316947a1685fSDinh Nguyen 317047a1685fSDinh Nguyen /* FIFO has space or is empty (see GAHBCFG) */ 317147a1685fSDinh Nguyen if (hsotg->dedicated_fifos && 317226ddef5dSVardan Mikayelyan ints & DXEPINT_TXFEMP) { 317347a1685fSDinh Nguyen dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n", 317447a1685fSDinh Nguyen __func__, idx); 317547a1685fSDinh Nguyen if (!using_dma(hsotg)) 31761f91b4ccSFelipe Balbi dwc2_hsotg_trytx(hsotg, hs_ep); 317747a1685fSDinh Nguyen } 317847a1685fSDinh Nguyen } 317947a1685fSDinh Nguyen } 318047a1685fSDinh Nguyen 318147a1685fSDinh Nguyen /** 31821f91b4ccSFelipe Balbi * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done) 318347a1685fSDinh Nguyen * @hsotg: The device state. 318447a1685fSDinh Nguyen * 318547a1685fSDinh Nguyen * Handle updating the device settings after the enumeration phase has 318647a1685fSDinh Nguyen * been completed. 318747a1685fSDinh Nguyen */ 31881f91b4ccSFelipe Balbi static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg) 318947a1685fSDinh Nguyen { 3190f25c42b8SGevorg Sahakyan u32 dsts = dwc2_readl(hsotg, DSTS); 31919b2667f1SJingoo Han int ep0_mps = 0, ep_mps = 8; 319247a1685fSDinh Nguyen 319347a1685fSDinh Nguyen /* 319447a1685fSDinh Nguyen * This should signal the finish of the enumeration phase 319547a1685fSDinh Nguyen * of the USB handshaking, so we should now know what rate 319647a1685fSDinh Nguyen * we connected at. 319747a1685fSDinh Nguyen */ 319847a1685fSDinh Nguyen 319947a1685fSDinh Nguyen dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts); 320047a1685fSDinh Nguyen 320147a1685fSDinh Nguyen /* 320247a1685fSDinh Nguyen * note, since we're limited by the size of transfer on EP0, and 320347a1685fSDinh Nguyen * it seems IN transfers must be a even number of packets we do 320447a1685fSDinh Nguyen * not advertise a 64byte MPS on EP0. 320547a1685fSDinh Nguyen */ 320647a1685fSDinh Nguyen 320747a1685fSDinh Nguyen /* catch both EnumSpd_FS and EnumSpd_FS48 */ 32086d76c92cSMarek Vasut switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) { 320947a1685fSDinh Nguyen case DSTS_ENUMSPD_FS: 321047a1685fSDinh Nguyen case DSTS_ENUMSPD_FS48: 321147a1685fSDinh Nguyen hsotg->gadget.speed = USB_SPEED_FULL; 321247a1685fSDinh Nguyen ep0_mps = EP0_MPS_LIMIT; 321347a1685fSDinh Nguyen ep_mps = 1023; 321447a1685fSDinh Nguyen break; 321547a1685fSDinh Nguyen 321647a1685fSDinh Nguyen case DSTS_ENUMSPD_HS: 321747a1685fSDinh Nguyen hsotg->gadget.speed = USB_SPEED_HIGH; 321847a1685fSDinh Nguyen ep0_mps = EP0_MPS_LIMIT; 321947a1685fSDinh Nguyen ep_mps = 1024; 322047a1685fSDinh Nguyen break; 322147a1685fSDinh Nguyen 322247a1685fSDinh Nguyen case DSTS_ENUMSPD_LS: 322347a1685fSDinh Nguyen hsotg->gadget.speed = USB_SPEED_LOW; 3224552d940fSVardan Mikayelyan ep0_mps = 8; 3225552d940fSVardan Mikayelyan ep_mps = 8; 322647a1685fSDinh Nguyen /* 322747a1685fSDinh Nguyen * note, we don't actually support LS in this driver at the 322847a1685fSDinh Nguyen * moment, and the documentation seems to imply that it isn't 322947a1685fSDinh Nguyen * supported by the PHYs on some of the devices. 323047a1685fSDinh Nguyen */ 323147a1685fSDinh Nguyen break; 323247a1685fSDinh Nguyen } 323347a1685fSDinh Nguyen dev_info(hsotg->dev, "new device is %s\n", 323447a1685fSDinh Nguyen usb_speed_string(hsotg->gadget.speed)); 323547a1685fSDinh Nguyen 323647a1685fSDinh Nguyen /* 323747a1685fSDinh Nguyen * we should now know the maximum packet size for an 323847a1685fSDinh Nguyen * endpoint, so set the endpoints to a default value. 323947a1685fSDinh Nguyen */ 324047a1685fSDinh Nguyen 324147a1685fSDinh Nguyen if (ep0_mps) { 324247a1685fSDinh Nguyen int i; 3243c6f5c050SMian Yousaf Kaukab /* Initialize ep0 for both in and out directions */ 3244ee2c40deSVardan Mikayelyan dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1); 3245ee2c40deSVardan Mikayelyan dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0); 3246c6f5c050SMian Yousaf Kaukab for (i = 1; i < hsotg->num_of_eps; i++) { 3247c6f5c050SMian Yousaf Kaukab if (hsotg->eps_in[i]) 3248ee2c40deSVardan Mikayelyan dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 3249ee2c40deSVardan Mikayelyan 0, 1); 3250c6f5c050SMian Yousaf Kaukab if (hsotg->eps_out[i]) 3251ee2c40deSVardan Mikayelyan dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 3252ee2c40deSVardan Mikayelyan 0, 0); 3253c6f5c050SMian Yousaf Kaukab } 325447a1685fSDinh Nguyen } 325547a1685fSDinh Nguyen 325647a1685fSDinh Nguyen /* ensure after enumeration our EP0 is active */ 325747a1685fSDinh Nguyen 32581f91b4ccSFelipe Balbi dwc2_hsotg_enqueue_setup(hsotg); 325947a1685fSDinh Nguyen 326047a1685fSDinh Nguyen dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", 3261f25c42b8SGevorg Sahakyan dwc2_readl(hsotg, DIEPCTL0), 3262f25c42b8SGevorg Sahakyan dwc2_readl(hsotg, DOEPCTL0)); 326347a1685fSDinh Nguyen } 326447a1685fSDinh Nguyen 326547a1685fSDinh Nguyen /** 326647a1685fSDinh Nguyen * kill_all_requests - remove all requests from the endpoint's queue 326747a1685fSDinh Nguyen * @hsotg: The device state. 326847a1685fSDinh Nguyen * @ep: The endpoint the requests may be on. 326947a1685fSDinh Nguyen * @result: The result code to use. 327047a1685fSDinh Nguyen * 327147a1685fSDinh Nguyen * Go through the requests on the given endpoint and mark them 327247a1685fSDinh Nguyen * completed with the given result code. 327347a1685fSDinh Nguyen */ 3274941fcce4SDinh Nguyen static void kill_all_requests(struct dwc2_hsotg *hsotg, 32751f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *ep, 32766b448af4SRobert Baldyga int result) 327747a1685fSDinh Nguyen { 32789da51974SJohn Youn unsigned int size; 327947a1685fSDinh Nguyen 32806b448af4SRobert Baldyga ep->req = NULL; 328147a1685fSDinh Nguyen 328237bea42fSJohn Keeping while (!list_empty(&ep->queue)) { 328337bea42fSJohn Keeping struct dwc2_hsotg_req *req = get_ep_head(ep); 328437bea42fSJohn Keeping 328537bea42fSJohn Keeping dwc2_hsotg_complete_request(hsotg, ep, req, result); 328637bea42fSJohn Keeping } 32876b448af4SRobert Baldyga 3288b203d0a2SRobert Baldyga if (!hsotg->dedicated_fifos) 3289b203d0a2SRobert Baldyga return; 3290f25c42b8SGevorg Sahakyan size = (dwc2_readl(hsotg, DTXFSTS(ep->fifo_index)) & 0xffff) * 4; 3291b203d0a2SRobert Baldyga if (size < ep->fifo_size) 32921f91b4ccSFelipe Balbi dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index); 329347a1685fSDinh Nguyen } 329447a1685fSDinh Nguyen 329547a1685fSDinh Nguyen /** 32961f91b4ccSFelipe Balbi * dwc2_hsotg_disconnect - disconnect service 329747a1685fSDinh Nguyen * @hsotg: The device state. 329847a1685fSDinh Nguyen * 329947a1685fSDinh Nguyen * The device has been disconnected. Remove all current 330047a1685fSDinh Nguyen * transactions and signal the gadget driver that this 330147a1685fSDinh Nguyen * has happened. 330247a1685fSDinh Nguyen */ 33031f91b4ccSFelipe Balbi void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg) 330447a1685fSDinh Nguyen { 33059da51974SJohn Youn unsigned int ep; 330647a1685fSDinh Nguyen 33074ace06e8SMarek Szyprowski if (!hsotg->connected) 33084ace06e8SMarek Szyprowski return; 33094ace06e8SMarek Szyprowski 33104ace06e8SMarek Szyprowski hsotg->connected = 0; 33119e14d0a5SGregory Herrero hsotg->test_mode = 0; 3312c6f5c050SMian Yousaf Kaukab 3313dccf1badSMinas Harutyunyan /* all endpoints should be shutdown */ 3314c6f5c050SMian Yousaf Kaukab for (ep = 0; ep < hsotg->num_of_eps; ep++) { 3315c6f5c050SMian Yousaf Kaukab if (hsotg->eps_in[ep]) 33164fe4f9feSMinas Harutyunyan kill_all_requests(hsotg, hsotg->eps_in[ep], 33174fe4f9feSMinas Harutyunyan -ESHUTDOWN); 3318c6f5c050SMian Yousaf Kaukab if (hsotg->eps_out[ep]) 33194fe4f9feSMinas Harutyunyan kill_all_requests(hsotg, hsotg->eps_out[ep], 33204fe4f9feSMinas Harutyunyan -ESHUTDOWN); 3321c6f5c050SMian Yousaf Kaukab } 332247a1685fSDinh Nguyen 332347a1685fSDinh Nguyen call_gadget(hsotg, disconnect); 3324065d3931SGregory Herrero hsotg->lx_state = DWC2_L3; 3325ce2b21a4SJohn Stultz 3326ce2b21a4SJohn Stultz usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED); 332747a1685fSDinh Nguyen } 332847a1685fSDinh Nguyen 332947a1685fSDinh Nguyen /** 33301f91b4ccSFelipe Balbi * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler 333147a1685fSDinh Nguyen * @hsotg: The device state: 333247a1685fSDinh Nguyen * @periodic: True if this is a periodic FIFO interrupt 333347a1685fSDinh Nguyen */ 33341f91b4ccSFelipe Balbi static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic) 333547a1685fSDinh Nguyen { 33361f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *ep; 333747a1685fSDinh Nguyen int epno, ret; 333847a1685fSDinh Nguyen 333947a1685fSDinh Nguyen /* look through for any more data to transmit */ 334047a1685fSDinh Nguyen for (epno = 0; epno < hsotg->num_of_eps; epno++) { 3341c6f5c050SMian Yousaf Kaukab ep = index_to_ep(hsotg, epno, 1); 3342c6f5c050SMian Yousaf Kaukab 3343c6f5c050SMian Yousaf Kaukab if (!ep) 3344c6f5c050SMian Yousaf Kaukab continue; 334547a1685fSDinh Nguyen 334647a1685fSDinh Nguyen if (!ep->dir_in) 334747a1685fSDinh Nguyen continue; 334847a1685fSDinh Nguyen 334947a1685fSDinh Nguyen if ((periodic && !ep->periodic) || 335047a1685fSDinh Nguyen (!periodic && ep->periodic)) 335147a1685fSDinh Nguyen continue; 335247a1685fSDinh Nguyen 33531f91b4ccSFelipe Balbi ret = dwc2_hsotg_trytx(hsotg, ep); 335447a1685fSDinh Nguyen if (ret < 0) 335547a1685fSDinh Nguyen break; 335647a1685fSDinh Nguyen } 335747a1685fSDinh Nguyen } 335847a1685fSDinh Nguyen 335947a1685fSDinh Nguyen /* IRQ flags which will trigger a retry around the IRQ loop */ 336047a1685fSDinh Nguyen #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \ 336147a1685fSDinh Nguyen GINTSTS_PTXFEMP | \ 336247a1685fSDinh Nguyen GINTSTS_RXFLVL) 336347a1685fSDinh Nguyen 33644fe4f9feSMinas Harutyunyan static int dwc2_hsotg_ep_disable(struct usb_ep *ep); 336547a1685fSDinh Nguyen /** 336658aff959SLee Jones * dwc2_hsotg_core_init_disconnected - issue softreset to the core 336747a1685fSDinh Nguyen * @hsotg: The device state 33686fb914d7SGrigor Tovmasyan * @is_usb_reset: Usb resetting flag 336947a1685fSDinh Nguyen * 337047a1685fSDinh Nguyen * Issue a soft reset to the core, and await the core finishing it. 337147a1685fSDinh Nguyen */ 33721f91b4ccSFelipe Balbi void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, 3373643cc4deSGregory Herrero bool is_usb_reset) 337447a1685fSDinh Nguyen { 33751ee6903bSGregory Herrero u32 intmsk; 3376643cc4deSGregory Herrero u32 val; 3377ecd9a7adSPrzemek Rudy u32 usbcfg; 337879c3b5bbSVahram Aharonyan u32 dcfg = 0; 3379dccf1badSMinas Harutyunyan int ep; 3380643cc4deSGregory Herrero 33815390d438SMian Yousaf Kaukab /* Kill any ep0 requests as controller will be reinitialized */ 33825390d438SMian Yousaf Kaukab kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET); 33835390d438SMian Yousaf Kaukab 3384dccf1badSMinas Harutyunyan if (!is_usb_reset) { 33856e6360b6SJohn Stultz if (dwc2_core_reset(hsotg, true)) 338686de4895SGregory Herrero return; 3387dccf1badSMinas Harutyunyan } else { 3388dccf1badSMinas Harutyunyan /* all endpoints should be shutdown */ 3389dccf1badSMinas Harutyunyan for (ep = 1; ep < hsotg->num_of_eps; ep++) { 3390dccf1badSMinas Harutyunyan if (hsotg->eps_in[ep]) 3391dccf1badSMinas Harutyunyan dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); 3392dccf1badSMinas Harutyunyan if (hsotg->eps_out[ep]) 3393dccf1badSMinas Harutyunyan dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); 3394dccf1badSMinas Harutyunyan } 3395dccf1badSMinas Harutyunyan } 339647a1685fSDinh Nguyen 339747a1685fSDinh Nguyen /* 339847a1685fSDinh Nguyen * we must now enable ep0 ready for host detection and then 339947a1685fSDinh Nguyen * set configuration. 340047a1685fSDinh Nguyen */ 340147a1685fSDinh Nguyen 3402ecd9a7adSPrzemek Rudy /* keep other bits untouched (so e.g. forced modes are not lost) */ 3403f25c42b8SGevorg Sahakyan usbcfg = dwc2_readl(hsotg, GUSBCFG); 34041e868545SJules Maselbas usbcfg &= ~GUSBCFG_TOUTCAL_MASK; 3405707d80f0SJules Maselbas usbcfg |= GUSBCFG_TOUTCAL(7); 3406ecd9a7adSPrzemek Rudy 34071e868545SJules Maselbas /* remove the HNP/SRP and set the PHY */ 34081e868545SJules Maselbas usbcfg &= ~(GUSBCFG_SRPCAP | GUSBCFG_HNPCAP); 3409f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, usbcfg, GUSBCFG); 341047a1685fSDinh Nguyen 34111e868545SJules Maselbas dwc2_phy_init(hsotg, true); 34121e868545SJules Maselbas 34131f91b4ccSFelipe Balbi dwc2_hsotg_init_fifo(hsotg); 341447a1685fSDinh Nguyen 3415643cc4deSGregory Herrero if (!is_usb_reset) 3416f25c42b8SGevorg Sahakyan dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON); 341747a1685fSDinh Nguyen 341879c3b5bbSVahram Aharonyan dcfg |= DCFG_EPMISCNT(1); 341938e9002bSVardan Mikayelyan 342038e9002bSVardan Mikayelyan switch (hsotg->params.speed) { 342138e9002bSVardan Mikayelyan case DWC2_SPEED_PARAM_LOW: 342238e9002bSVardan Mikayelyan dcfg |= DCFG_DEVSPD_LS; 342338e9002bSVardan Mikayelyan break; 342438e9002bSVardan Mikayelyan case DWC2_SPEED_PARAM_FULL: 342579c3b5bbSVahram Aharonyan if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) 342679c3b5bbSVahram Aharonyan dcfg |= DCFG_DEVSPD_FS48; 342779c3b5bbSVahram Aharonyan else 342879c3b5bbSVahram Aharonyan dcfg |= DCFG_DEVSPD_FS; 342938e9002bSVardan Mikayelyan break; 343038e9002bSVardan Mikayelyan default: 343179c3b5bbSVahram Aharonyan dcfg |= DCFG_DEVSPD_HS; 343279c3b5bbSVahram Aharonyan } 343338e9002bSVardan Mikayelyan 3434b43ebc96SGrigor Tovmasyan if (hsotg->params.ipg_isoc_en) 3435b43ebc96SGrigor Tovmasyan dcfg |= DCFG_IPG_ISOC_SUPPORDED; 3436b43ebc96SGrigor Tovmasyan 3437f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, dcfg, DCFG); 343847a1685fSDinh Nguyen 343947a1685fSDinh Nguyen /* Clear any pending OTG interrupts */ 3440f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, 0xffffffff, GOTGINT); 344147a1685fSDinh Nguyen 344247a1685fSDinh Nguyen /* Clear any pending interrupts */ 3443f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, 0xffffffff, GINTSTS); 34441ee6903bSGregory Herrero intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT | 344547a1685fSDinh Nguyen GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF | 34461ee6903bSGregory Herrero GINTSTS_USBRST | GINTSTS_RESETDET | 34471ee6903bSGregory Herrero GINTSTS_ENUMDONE | GINTSTS_OTGINT | 3448376f0401SSevak Arakelyan GINTSTS_USBSUSP | GINTSTS_WKUPINT | 3449376f0401SSevak Arakelyan GINTSTS_LPMTRANRCVD; 3450f4736701SVahram Aharonyan 3451f4736701SVahram Aharonyan if (!using_desc_dma(hsotg)) 3452f4736701SVahram Aharonyan intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT; 34531ee6903bSGregory Herrero 345495832c00SJohn Youn if (!hsotg->params.external_id_pin_ctl) 34551ee6903bSGregory Herrero intmsk |= GINTSTS_CONIDSTSCHNG; 34561ee6903bSGregory Herrero 3457f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, intmsk, GINTMSK); 345847a1685fSDinh Nguyen 3459a5c18f11SVahram Aharonyan if (using_dma(hsotg)) { 3460f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN | 3461d1ac8c80SRazmik Karapetyan hsotg->params.ahbcfg, 3462f25c42b8SGevorg Sahakyan GAHBCFG); 3463a5c18f11SVahram Aharonyan 3464a5c18f11SVahram Aharonyan /* Set DDMA mode support in the core if needed */ 3465a5c18f11SVahram Aharonyan if (using_desc_dma(hsotg)) 3466f25c42b8SGevorg Sahakyan dwc2_set_bit(hsotg, DCFG, DCFG_DESCDMA_EN); 3467a5c18f11SVahram Aharonyan 3468a5c18f11SVahram Aharonyan } else { 3469f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, ((hsotg->dedicated_fifos) ? 347095c8bc36SAntti Seppälä (GAHBCFG_NP_TXF_EMP_LVL | 347147a1685fSDinh Nguyen GAHBCFG_P_TXF_EMP_LVL) : 0) | 3472f25c42b8SGevorg Sahakyan GAHBCFG_GLBL_INTR_EN, GAHBCFG); 3473a5c18f11SVahram Aharonyan } 347447a1685fSDinh Nguyen 347547a1685fSDinh Nguyen /* 347647a1685fSDinh Nguyen * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts 347747a1685fSDinh Nguyen * when we have no data to transfer. Otherwise we get being flooded by 347847a1685fSDinh Nguyen * interrupts. 347947a1685fSDinh Nguyen */ 348047a1685fSDinh Nguyen 3481f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, ((hsotg->dedicated_fifos && !using_dma(hsotg)) ? 34826ff2e832SMian Yousaf Kaukab DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) | 348347a1685fSDinh Nguyen DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK | 3484837e9f00SVardan Mikayelyan DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK, 3485f25c42b8SGevorg Sahakyan DIEPMSK); 348647a1685fSDinh Nguyen 348747a1685fSDinh Nguyen /* 348847a1685fSDinh Nguyen * don't need XferCompl, we get that from RXFIFO in slave mode. In 34899d9a6b07SVahram Aharonyan * DMA mode we may need this and StsPhseRcvd. 349047a1685fSDinh Nguyen */ 3491f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, (using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK | 34929d9a6b07SVahram Aharonyan DOEPMSK_STSPHSERCVDMSK) : 0) | 349347a1685fSDinh Nguyen DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK | 34949d9a6b07SVahram Aharonyan DOEPMSK_SETUPMSK, 3495f25c42b8SGevorg Sahakyan DOEPMSK); 349647a1685fSDinh Nguyen 3497ec01f0b2SVahram Aharonyan /* Enable BNA interrupt for DDMA */ 349837981e00SMinas Harutyunyan if (using_desc_dma(hsotg)) { 3499f25c42b8SGevorg Sahakyan dwc2_set_bit(hsotg, DOEPMSK, DOEPMSK_BNAMSK); 3500f25c42b8SGevorg Sahakyan dwc2_set_bit(hsotg, DIEPMSK, DIEPMSK_BNAININTRMSK); 350137981e00SMinas Harutyunyan } 3502ec01f0b2SVahram Aharonyan 3503ca531bc2SGrigor Tovmasyan /* Enable Service Interval mode if supported */ 3504ca531bc2SGrigor Tovmasyan if (using_desc_dma(hsotg) && hsotg->params.service_interval) 3505ca531bc2SGrigor Tovmasyan dwc2_set_bit(hsotg, DCTL, DCTL_SERVICE_INTERVAL_SUPPORTED); 3506ca531bc2SGrigor Tovmasyan 3507f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, 0, DAINTMSK); 350847a1685fSDinh Nguyen 350947a1685fSDinh Nguyen dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", 3510f25c42b8SGevorg Sahakyan dwc2_readl(hsotg, DIEPCTL0), 3511f25c42b8SGevorg Sahakyan dwc2_readl(hsotg, DOEPCTL0)); 351247a1685fSDinh Nguyen 351347a1685fSDinh Nguyen /* enable in and out endpoint interrupts */ 35141f91b4ccSFelipe Balbi dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT); 351547a1685fSDinh Nguyen 351647a1685fSDinh Nguyen /* 351747a1685fSDinh Nguyen * Enable the RXFIFO when in slave mode, as this is how we collect 351847a1685fSDinh Nguyen * the data. In DMA mode, we get events from the FIFO but also 351947a1685fSDinh Nguyen * things we cannot process, so do not use it. 352047a1685fSDinh Nguyen */ 352147a1685fSDinh Nguyen if (!using_dma(hsotg)) 35221f91b4ccSFelipe Balbi dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL); 352347a1685fSDinh Nguyen 352447a1685fSDinh Nguyen /* Enable interrupts for EP0 in and out */ 35251f91b4ccSFelipe Balbi dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1); 35261f91b4ccSFelipe Balbi dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1); 352747a1685fSDinh Nguyen 3528643cc4deSGregory Herrero if (!is_usb_reset) { 3529f25c42b8SGevorg Sahakyan dwc2_set_bit(hsotg, DCTL, DCTL_PWRONPRGDONE); 353047a1685fSDinh Nguyen udelay(10); /* see openiboot */ 3531f25c42b8SGevorg Sahakyan dwc2_clear_bit(hsotg, DCTL, DCTL_PWRONPRGDONE); 3532643cc4deSGregory Herrero } 353347a1685fSDinh Nguyen 3534f25c42b8SGevorg Sahakyan dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg, DCTL)); 353547a1685fSDinh Nguyen 353647a1685fSDinh Nguyen /* 353747a1685fSDinh Nguyen * DxEPCTL_USBActEp says RO in manual, but seems to be set by 353847a1685fSDinh Nguyen * writing to the EPCTL register.. 353947a1685fSDinh Nguyen */ 354047a1685fSDinh Nguyen 354147a1685fSDinh Nguyen /* set to read 1 8byte packet */ 3542f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | 3543f25c42b8SGevorg Sahakyan DXEPTSIZ_XFERSIZE(8), DOEPTSIZ0); 354447a1685fSDinh Nguyen 3545f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | 354647a1685fSDinh Nguyen DXEPCTL_CNAK | DXEPCTL_EPENA | 354747a1685fSDinh Nguyen DXEPCTL_USBACTEP, 3548f25c42b8SGevorg Sahakyan DOEPCTL0); 354947a1685fSDinh Nguyen 355047a1685fSDinh Nguyen /* enable, but don't activate EP0in */ 3551f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | 3552f25c42b8SGevorg Sahakyan DXEPCTL_USBACTEP, DIEPCTL0); 355347a1685fSDinh Nguyen 355447a1685fSDinh Nguyen /* clear global NAKs */ 3555643cc4deSGregory Herrero val = DCTL_CGOUTNAK | DCTL_CGNPINNAK; 3556643cc4deSGregory Herrero if (!is_usb_reset) 3557643cc4deSGregory Herrero val |= DCTL_SFTDISCON; 3558f25c42b8SGevorg Sahakyan dwc2_set_bit(hsotg, DCTL, val); 355947a1685fSDinh Nguyen 356021b03405SSevak Arakelyan /* configure the core to support LPM */ 356121b03405SSevak Arakelyan dwc2_gadget_init_lpm(hsotg); 356221b03405SSevak Arakelyan 356315d9dbf8SGrigor Tovmasyan /* program GREFCLK register if needed */ 356415d9dbf8SGrigor Tovmasyan if (using_desc_dma(hsotg) && hsotg->params.service_interval) 356515d9dbf8SGrigor Tovmasyan dwc2_gadget_program_ref_clk(hsotg); 356615d9dbf8SGrigor Tovmasyan 356747a1685fSDinh Nguyen /* must be at-least 3ms to allow bus to see disconnect */ 356847a1685fSDinh Nguyen mdelay(3); 356947a1685fSDinh Nguyen 3570065d3931SGregory Herrero hsotg->lx_state = DWC2_L0; 3571755d7395SVardan Mikayelyan 3572755d7395SVardan Mikayelyan dwc2_hsotg_enqueue_setup(hsotg); 3573755d7395SVardan Mikayelyan 3574755d7395SVardan Mikayelyan dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", 3575f25c42b8SGevorg Sahakyan dwc2_readl(hsotg, DIEPCTL0), 3576f25c42b8SGevorg Sahakyan dwc2_readl(hsotg, DOEPCTL0)); 3577ad38dc5dSMarek Szyprowski } 3578ac3c81f3SMarek Szyprowski 357917f93402SAmelie Delaunay void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) 3580ad38dc5dSMarek Szyprowski { 3581ad38dc5dSMarek Szyprowski /* set the soft-disconnect bit */ 3582f25c42b8SGevorg Sahakyan dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON); 3583ad38dc5dSMarek Szyprowski } 3584ad38dc5dSMarek Szyprowski 35851f91b4ccSFelipe Balbi void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) 3586ad38dc5dSMarek Szyprowski { 358747a1685fSDinh Nguyen /* remove the soft-disconnect and let's go */ 3588f25c42b8SGevorg Sahakyan dwc2_clear_bit(hsotg, DCTL, DCTL_SFTDISCON); 358947a1685fSDinh Nguyen } 359047a1685fSDinh Nguyen 359147a1685fSDinh Nguyen /** 3592381fc8f8SVardan Mikayelyan * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt. 3593381fc8f8SVardan Mikayelyan * @hsotg: The device state: 3594381fc8f8SVardan Mikayelyan * 3595381fc8f8SVardan Mikayelyan * This interrupt indicates one of the following conditions occurred while 3596381fc8f8SVardan Mikayelyan * transmitting an ISOC transaction. 3597381fc8f8SVardan Mikayelyan * - Corrupted IN Token for ISOC EP. 3598381fc8f8SVardan Mikayelyan * - Packet not complete in FIFO. 3599381fc8f8SVardan Mikayelyan * 3600381fc8f8SVardan Mikayelyan * The following actions will be taken: 3601381fc8f8SVardan Mikayelyan * - Determine the EP 3602381fc8f8SVardan Mikayelyan * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO 3603381fc8f8SVardan Mikayelyan */ 3604381fc8f8SVardan Mikayelyan static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg) 3605381fc8f8SVardan Mikayelyan { 3606381fc8f8SVardan Mikayelyan struct dwc2_hsotg_ep *hs_ep; 3607381fc8f8SVardan Mikayelyan u32 epctrl; 36081b4977c7SRazmik Karapetyan u32 daintmsk; 3609381fc8f8SVardan Mikayelyan u32 idx; 3610381fc8f8SVardan Mikayelyan 3611381fc8f8SVardan Mikayelyan dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n"); 3612381fc8f8SVardan Mikayelyan 3613f25c42b8SGevorg Sahakyan daintmsk = dwc2_readl(hsotg, DAINTMSK); 36141b4977c7SRazmik Karapetyan 3615d5d5f079SArtur Petrosyan for (idx = 1; idx < hsotg->num_of_eps; idx++) { 3616381fc8f8SVardan Mikayelyan hs_ep = hsotg->eps_in[idx]; 36171b4977c7SRazmik Karapetyan /* Proceed only unmasked ISOC EPs */ 361889066b36SJohn Keeping if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous) 36191b4977c7SRazmik Karapetyan continue; 36201b4977c7SRazmik Karapetyan 3621f25c42b8SGevorg Sahakyan epctrl = dwc2_readl(hsotg, DIEPCTL(idx)); 36221b4977c7SRazmik Karapetyan if ((epctrl & DXEPCTL_EPENA) && 3623381fc8f8SVardan Mikayelyan dwc2_gadget_target_frame_elapsed(hs_ep)) { 3624381fc8f8SVardan Mikayelyan epctrl |= DXEPCTL_SNAK; 3625381fc8f8SVardan Mikayelyan epctrl |= DXEPCTL_EPDIS; 3626f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, epctrl, DIEPCTL(idx)); 3627381fc8f8SVardan Mikayelyan } 3628381fc8f8SVardan Mikayelyan } 3629381fc8f8SVardan Mikayelyan 3630381fc8f8SVardan Mikayelyan /* Clear interrupt */ 3631f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, GINTSTS_INCOMPL_SOIN, GINTSTS); 3632381fc8f8SVardan Mikayelyan } 3633381fc8f8SVardan Mikayelyan 3634381fc8f8SVardan Mikayelyan /** 3635381fc8f8SVardan Mikayelyan * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt 3636381fc8f8SVardan Mikayelyan * @hsotg: The device state: 3637381fc8f8SVardan Mikayelyan * 3638381fc8f8SVardan Mikayelyan * This interrupt indicates one of the following conditions occurred while 3639381fc8f8SVardan Mikayelyan * transmitting an ISOC transaction. 3640381fc8f8SVardan Mikayelyan * - Corrupted OUT Token for ISOC EP. 3641381fc8f8SVardan Mikayelyan * - Packet not complete in FIFO. 3642381fc8f8SVardan Mikayelyan * 3643381fc8f8SVardan Mikayelyan * The following actions will be taken: 3644381fc8f8SVardan Mikayelyan * - Determine the EP 3645381fc8f8SVardan Mikayelyan * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed. 3646381fc8f8SVardan Mikayelyan */ 3647381fc8f8SVardan Mikayelyan static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg) 3648381fc8f8SVardan Mikayelyan { 3649381fc8f8SVardan Mikayelyan u32 gintsts; 3650381fc8f8SVardan Mikayelyan u32 gintmsk; 3651689efb26SRazmik Karapetyan u32 daintmsk; 3652381fc8f8SVardan Mikayelyan u32 epctrl; 3653381fc8f8SVardan Mikayelyan struct dwc2_hsotg_ep *hs_ep; 3654381fc8f8SVardan Mikayelyan int idx; 3655381fc8f8SVardan Mikayelyan 3656381fc8f8SVardan Mikayelyan dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__); 3657381fc8f8SVardan Mikayelyan 3658f25c42b8SGevorg Sahakyan daintmsk = dwc2_readl(hsotg, DAINTMSK); 3659689efb26SRazmik Karapetyan daintmsk >>= DAINT_OUTEP_SHIFT; 3660689efb26SRazmik Karapetyan 3661d5d5f079SArtur Petrosyan for (idx = 1; idx < hsotg->num_of_eps; idx++) { 3662381fc8f8SVardan Mikayelyan hs_ep = hsotg->eps_out[idx]; 3663689efb26SRazmik Karapetyan /* Proceed only unmasked ISOC EPs */ 366489066b36SJohn Keeping if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous) 3665689efb26SRazmik Karapetyan continue; 3666689efb26SRazmik Karapetyan 3667f25c42b8SGevorg Sahakyan epctrl = dwc2_readl(hsotg, DOEPCTL(idx)); 3668689efb26SRazmik Karapetyan if ((epctrl & DXEPCTL_EPENA) && 3669381fc8f8SVardan Mikayelyan dwc2_gadget_target_frame_elapsed(hs_ep)) { 3670381fc8f8SVardan Mikayelyan /* Unmask GOUTNAKEFF interrupt */ 3671f25c42b8SGevorg Sahakyan gintmsk = dwc2_readl(hsotg, GINTMSK); 3672381fc8f8SVardan Mikayelyan gintmsk |= GINTSTS_GOUTNAKEFF; 3673f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, gintmsk, GINTMSK); 3674381fc8f8SVardan Mikayelyan 3675f25c42b8SGevorg Sahakyan gintsts = dwc2_readl(hsotg, GINTSTS); 3676689efb26SRazmik Karapetyan if (!(gintsts & GINTSTS_GOUTNAKEFF)) { 3677f25c42b8SGevorg Sahakyan dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK); 3678689efb26SRazmik Karapetyan break; 3679689efb26SRazmik Karapetyan } 3680381fc8f8SVardan Mikayelyan } 3681381fc8f8SVardan Mikayelyan } 3682381fc8f8SVardan Mikayelyan 3683381fc8f8SVardan Mikayelyan /* Clear interrupt */ 3684f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, GINTSTS_INCOMPL_SOOUT, GINTSTS); 3685381fc8f8SVardan Mikayelyan } 3686381fc8f8SVardan Mikayelyan 3687381fc8f8SVardan Mikayelyan /** 36881f91b4ccSFelipe Balbi * dwc2_hsotg_irq - handle device interrupt 368947a1685fSDinh Nguyen * @irq: The IRQ number triggered 369047a1685fSDinh Nguyen * @pw: The pw value when registered the handler. 369147a1685fSDinh Nguyen */ 36921f91b4ccSFelipe Balbi static irqreturn_t dwc2_hsotg_irq(int irq, void *pw) 369347a1685fSDinh Nguyen { 3694941fcce4SDinh Nguyen struct dwc2_hsotg *hsotg = pw; 369547a1685fSDinh Nguyen int retry_count = 8; 369647a1685fSDinh Nguyen u32 gintsts; 369747a1685fSDinh Nguyen u32 gintmsk; 369847a1685fSDinh Nguyen 3699ee3de8d7SVardan Mikayelyan if (!dwc2_is_device_mode(hsotg)) 3700ee3de8d7SVardan Mikayelyan return IRQ_NONE; 3701ee3de8d7SVardan Mikayelyan 370247a1685fSDinh Nguyen spin_lock(&hsotg->lock); 370347a1685fSDinh Nguyen irq_retry: 3704f25c42b8SGevorg Sahakyan gintsts = dwc2_readl(hsotg, GINTSTS); 3705f25c42b8SGevorg Sahakyan gintmsk = dwc2_readl(hsotg, GINTMSK); 370647a1685fSDinh Nguyen 370747a1685fSDinh Nguyen dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n", 370847a1685fSDinh Nguyen __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count); 370947a1685fSDinh Nguyen 371047a1685fSDinh Nguyen gintsts &= gintmsk; 371147a1685fSDinh Nguyen 37128fc37b82SMian Yousaf Kaukab if (gintsts & GINTSTS_RESETDET) { 37138fc37b82SMian Yousaf Kaukab dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__); 37148fc37b82SMian Yousaf Kaukab 3715f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, GINTSTS_RESETDET, GINTSTS); 37168fc37b82SMian Yousaf Kaukab 37178fc37b82SMian Yousaf Kaukab /* This event must be used only if controller is suspended */ 3718c9c394abSArtur Petrosyan if (hsotg->in_ppd && hsotg->lx_state == DWC2_L2) 3719c9c394abSArtur Petrosyan dwc2_exit_partial_power_down(hsotg, 0, true); 3720c9c394abSArtur Petrosyan 37218fc37b82SMian Yousaf Kaukab hsotg->lx_state = DWC2_L0; 37228fc37b82SMian Yousaf Kaukab } 37238fc37b82SMian Yousaf Kaukab 37248fc37b82SMian Yousaf Kaukab if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) { 3725f25c42b8SGevorg Sahakyan u32 usb_status = dwc2_readl(hsotg, GOTGCTL); 37268fc37b82SMian Yousaf Kaukab u32 connected = hsotg->connected; 37278fc37b82SMian Yousaf Kaukab 37288fc37b82SMian Yousaf Kaukab dev_dbg(hsotg->dev, "%s: USBRst\n", __func__); 37298fc37b82SMian Yousaf Kaukab dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n", 3730f25c42b8SGevorg Sahakyan dwc2_readl(hsotg, GNPTXSTS)); 37318fc37b82SMian Yousaf Kaukab 3732f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, GINTSTS_USBRST, GINTSTS); 37338fc37b82SMian Yousaf Kaukab 37348fc37b82SMian Yousaf Kaukab /* Report disconnection if it is not already done. */ 37358fc37b82SMian Yousaf Kaukab dwc2_hsotg_disconnect(hsotg); 37368fc37b82SMian Yousaf Kaukab 3737307bc11fSMinas Harutyunyan /* Reset device address to zero */ 3738f25c42b8SGevorg Sahakyan dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK); 3739307bc11fSMinas Harutyunyan 37408fc37b82SMian Yousaf Kaukab if (usb_status & GOTGCTL_BSESVLD && connected) 37418fc37b82SMian Yousaf Kaukab dwc2_hsotg_core_init_disconnected(hsotg, true); 37428fc37b82SMian Yousaf Kaukab } 37438fc37b82SMian Yousaf Kaukab 374447a1685fSDinh Nguyen if (gintsts & GINTSTS_ENUMDONE) { 3745f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, GINTSTS_ENUMDONE, GINTSTS); 374647a1685fSDinh Nguyen 37471f91b4ccSFelipe Balbi dwc2_hsotg_irq_enumdone(hsotg); 374847a1685fSDinh Nguyen } 374947a1685fSDinh Nguyen 375047a1685fSDinh Nguyen if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) { 3751f25c42b8SGevorg Sahakyan u32 daint = dwc2_readl(hsotg, DAINT); 3752f25c42b8SGevorg Sahakyan u32 daintmsk = dwc2_readl(hsotg, DAINTMSK); 375347a1685fSDinh Nguyen u32 daint_out, daint_in; 375447a1685fSDinh Nguyen int ep; 375547a1685fSDinh Nguyen 375647a1685fSDinh Nguyen daint &= daintmsk; 375747a1685fSDinh Nguyen daint_out = daint >> DAINT_OUTEP_SHIFT; 375847a1685fSDinh Nguyen daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT); 375947a1685fSDinh Nguyen 376047a1685fSDinh Nguyen dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint); 376147a1685fSDinh Nguyen 3762cec87f1dSMian Yousaf Kaukab for (ep = 0; ep < hsotg->num_of_eps && daint_out; 3763cec87f1dSMian Yousaf Kaukab ep++, daint_out >>= 1) { 376447a1685fSDinh Nguyen if (daint_out & 1) 37651f91b4ccSFelipe Balbi dwc2_hsotg_epint(hsotg, ep, 0); 376647a1685fSDinh Nguyen } 376747a1685fSDinh Nguyen 3768cec87f1dSMian Yousaf Kaukab for (ep = 0; ep < hsotg->num_of_eps && daint_in; 3769cec87f1dSMian Yousaf Kaukab ep++, daint_in >>= 1) { 377047a1685fSDinh Nguyen if (daint_in & 1) 37711f91b4ccSFelipe Balbi dwc2_hsotg_epint(hsotg, ep, 1); 377247a1685fSDinh Nguyen } 377347a1685fSDinh Nguyen } 377447a1685fSDinh Nguyen 377547a1685fSDinh Nguyen /* check both FIFOs */ 377647a1685fSDinh Nguyen 377747a1685fSDinh Nguyen if (gintsts & GINTSTS_NPTXFEMP) { 377847a1685fSDinh Nguyen dev_dbg(hsotg->dev, "NPTxFEmp\n"); 377947a1685fSDinh Nguyen 378047a1685fSDinh Nguyen /* 378147a1685fSDinh Nguyen * Disable the interrupt to stop it happening again 378247a1685fSDinh Nguyen * unless one of these endpoint routines decides that 378347a1685fSDinh Nguyen * it needs re-enabling 378447a1685fSDinh Nguyen */ 378547a1685fSDinh Nguyen 37861f91b4ccSFelipe Balbi dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP); 37871f91b4ccSFelipe Balbi dwc2_hsotg_irq_fifoempty(hsotg, false); 378847a1685fSDinh Nguyen } 378947a1685fSDinh Nguyen 379047a1685fSDinh Nguyen if (gintsts & GINTSTS_PTXFEMP) { 379147a1685fSDinh Nguyen dev_dbg(hsotg->dev, "PTxFEmp\n"); 379247a1685fSDinh Nguyen 379347a1685fSDinh Nguyen /* See note in GINTSTS_NPTxFEmp */ 379447a1685fSDinh Nguyen 37951f91b4ccSFelipe Balbi dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP); 37961f91b4ccSFelipe Balbi dwc2_hsotg_irq_fifoempty(hsotg, true); 379747a1685fSDinh Nguyen } 379847a1685fSDinh Nguyen 379947a1685fSDinh Nguyen if (gintsts & GINTSTS_RXFLVL) { 380047a1685fSDinh Nguyen /* 380147a1685fSDinh Nguyen * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty, 38021f91b4ccSFelipe Balbi * we need to retry dwc2_hsotg_handle_rx if this is still 380347a1685fSDinh Nguyen * set. 380447a1685fSDinh Nguyen */ 380547a1685fSDinh Nguyen 38061f91b4ccSFelipe Balbi dwc2_hsotg_handle_rx(hsotg); 380747a1685fSDinh Nguyen } 380847a1685fSDinh Nguyen 380947a1685fSDinh Nguyen if (gintsts & GINTSTS_ERLYSUSP) { 381047a1685fSDinh Nguyen dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n"); 3811f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, GINTSTS_ERLYSUSP, GINTSTS); 381247a1685fSDinh Nguyen } 381347a1685fSDinh Nguyen 381447a1685fSDinh Nguyen /* 381547a1685fSDinh Nguyen * these next two seem to crop-up occasionally causing the core 381647a1685fSDinh Nguyen * to shutdown the USB transfer, so try clearing them and logging 381747a1685fSDinh Nguyen * the occurrence. 381847a1685fSDinh Nguyen */ 381947a1685fSDinh Nguyen 382047a1685fSDinh Nguyen if (gintsts & GINTSTS_GOUTNAKEFF) { 3821837e9f00SVardan Mikayelyan u8 idx; 3822837e9f00SVardan Mikayelyan u32 epctrl; 3823837e9f00SVardan Mikayelyan u32 gintmsk; 3824d8484552SRazmik Karapetyan u32 daintmsk; 3825837e9f00SVardan Mikayelyan struct dwc2_hsotg_ep *hs_ep; 382647a1685fSDinh Nguyen 3827f25c42b8SGevorg Sahakyan daintmsk = dwc2_readl(hsotg, DAINTMSK); 3828d8484552SRazmik Karapetyan daintmsk >>= DAINT_OUTEP_SHIFT; 3829837e9f00SVardan Mikayelyan /* Mask this interrupt */ 3830f25c42b8SGevorg Sahakyan gintmsk = dwc2_readl(hsotg, GINTMSK); 3831837e9f00SVardan Mikayelyan gintmsk &= ~GINTSTS_GOUTNAKEFF; 3832f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, gintmsk, GINTMSK); 383347a1685fSDinh Nguyen 3834837e9f00SVardan Mikayelyan dev_dbg(hsotg->dev, "GOUTNakEff triggered\n"); 3835d5d5f079SArtur Petrosyan for (idx = 1; idx < hsotg->num_of_eps; idx++) { 3836837e9f00SVardan Mikayelyan hs_ep = hsotg->eps_out[idx]; 3837d8484552SRazmik Karapetyan /* Proceed only unmasked ISOC EPs */ 38386070636cSMinas Harutyunyan if (BIT(idx) & ~daintmsk) 3839d8484552SRazmik Karapetyan continue; 3840d8484552SRazmik Karapetyan 3841f25c42b8SGevorg Sahakyan epctrl = dwc2_readl(hsotg, DOEPCTL(idx)); 3842837e9f00SVardan Mikayelyan 38436070636cSMinas Harutyunyan //ISOC Ep's only 38446070636cSMinas Harutyunyan if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous) { 3845837e9f00SVardan Mikayelyan epctrl |= DXEPCTL_SNAK; 3846837e9f00SVardan Mikayelyan epctrl |= DXEPCTL_EPDIS; 3847f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, epctrl, DOEPCTL(idx)); 38486070636cSMinas Harutyunyan continue; 38496070636cSMinas Harutyunyan } 38506070636cSMinas Harutyunyan 38516070636cSMinas Harutyunyan //Non-ISOC EP's 38526070636cSMinas Harutyunyan if (hs_ep->halted) { 38536070636cSMinas Harutyunyan if (!(epctrl & DXEPCTL_EPENA)) 38546070636cSMinas Harutyunyan epctrl |= DXEPCTL_EPENA; 38556070636cSMinas Harutyunyan epctrl |= DXEPCTL_EPDIS; 38566070636cSMinas Harutyunyan epctrl |= DXEPCTL_STALL; 38576070636cSMinas Harutyunyan dwc2_writel(hsotg, epctrl, DOEPCTL(idx)); 3858837e9f00SVardan Mikayelyan } 3859837e9f00SVardan Mikayelyan } 3860837e9f00SVardan Mikayelyan 3861837e9f00SVardan Mikayelyan /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */ 386247a1685fSDinh Nguyen } 386347a1685fSDinh Nguyen 386447a1685fSDinh Nguyen if (gintsts & GINTSTS_GINNAKEFF) { 386547a1685fSDinh Nguyen dev_info(hsotg->dev, "GINNakEff triggered\n"); 386647a1685fSDinh Nguyen 3867f25c42b8SGevorg Sahakyan dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK); 386847a1685fSDinh Nguyen 38691f91b4ccSFelipe Balbi dwc2_hsotg_dump(hsotg); 387047a1685fSDinh Nguyen } 387147a1685fSDinh Nguyen 3872381fc8f8SVardan Mikayelyan if (gintsts & GINTSTS_INCOMPL_SOIN) 3873381fc8f8SVardan Mikayelyan dwc2_gadget_handle_incomplete_isoc_in(hsotg); 3874ec1f9d9fSRoman Bacik 3875381fc8f8SVardan Mikayelyan if (gintsts & GINTSTS_INCOMPL_SOOUT) 3876381fc8f8SVardan Mikayelyan dwc2_gadget_handle_incomplete_isoc_out(hsotg); 3877ec1f9d9fSRoman Bacik 387847a1685fSDinh Nguyen /* 387947a1685fSDinh Nguyen * if we've had fifo events, we should try and go around the 388047a1685fSDinh Nguyen * loop again to see if there's any point in returning yet. 388147a1685fSDinh Nguyen */ 388247a1685fSDinh Nguyen 388347a1685fSDinh Nguyen if (gintsts & IRQ_RETRY_MASK && --retry_count > 0) 388447a1685fSDinh Nguyen goto irq_retry; 388547a1685fSDinh Nguyen 3886187c5298SGrigor Tovmasyan /* Check WKUP_ALERT interrupt*/ 3887187c5298SGrigor Tovmasyan if (hsotg->params.service_interval) 3888187c5298SGrigor Tovmasyan dwc2_gadget_wkup_alert_handler(hsotg); 3889187c5298SGrigor Tovmasyan 389047a1685fSDinh Nguyen spin_unlock(&hsotg->lock); 389147a1685fSDinh Nguyen 389247a1685fSDinh Nguyen return IRQ_HANDLED; 389347a1685fSDinh Nguyen } 389447a1685fSDinh Nguyen 3895a4f82771SVahram Aharonyan static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg, 3896a4f82771SVahram Aharonyan struct dwc2_hsotg_ep *hs_ep) 3897a4f82771SVahram Aharonyan { 3898a4f82771SVahram Aharonyan u32 epctrl_reg; 3899a4f82771SVahram Aharonyan u32 epint_reg; 3900a4f82771SVahram Aharonyan 3901a4f82771SVahram Aharonyan epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) : 3902a4f82771SVahram Aharonyan DOEPCTL(hs_ep->index); 3903a4f82771SVahram Aharonyan epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) : 3904a4f82771SVahram Aharonyan DOEPINT(hs_ep->index); 3905a4f82771SVahram Aharonyan 3906a4f82771SVahram Aharonyan dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__, 3907a4f82771SVahram Aharonyan hs_ep->name); 3908a4f82771SVahram Aharonyan 3909a4f82771SVahram Aharonyan if (hs_ep->dir_in) { 3910a4f82771SVahram Aharonyan if (hsotg->dedicated_fifos || hs_ep->periodic) { 3911f25c42b8SGevorg Sahakyan dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_SNAK); 3912a4f82771SVahram Aharonyan /* Wait for Nak effect */ 3913a4f82771SVahram Aharonyan if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, 3914a4f82771SVahram Aharonyan DXEPINT_INEPNAKEFF, 100)) 3915a4f82771SVahram Aharonyan dev_warn(hsotg->dev, 3916a4f82771SVahram Aharonyan "%s: timeout DIEPINT.NAKEFF\n", 3917a4f82771SVahram Aharonyan __func__); 3918a4f82771SVahram Aharonyan } else { 3919f25c42b8SGevorg Sahakyan dwc2_set_bit(hsotg, DCTL, DCTL_SGNPINNAK); 3920a4f82771SVahram Aharonyan /* Wait for Nak effect */ 3921a4f82771SVahram Aharonyan if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, 3922a4f82771SVahram Aharonyan GINTSTS_GINNAKEFF, 100)) 3923a4f82771SVahram Aharonyan dev_warn(hsotg->dev, 3924a4f82771SVahram Aharonyan "%s: timeout GINTSTS.GINNAKEFF\n", 3925a4f82771SVahram Aharonyan __func__); 3926a4f82771SVahram Aharonyan } 3927a4f82771SVahram Aharonyan } else { 3928fecb3a17SMinas Harutyunyan /* Mask GINTSTS_GOUTNAKEFF interrupt */ 3929fecb3a17SMinas Harutyunyan dwc2_hsotg_disable_gsint(hsotg, GINTSTS_GOUTNAKEFF); 3930fecb3a17SMinas Harutyunyan 3931f25c42b8SGevorg Sahakyan if (!(dwc2_readl(hsotg, GINTSTS) & GINTSTS_GOUTNAKEFF)) 3932f25c42b8SGevorg Sahakyan dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK); 3933a4f82771SVahram Aharonyan 3934fecb3a17SMinas Harutyunyan if (!using_dma(hsotg)) { 3935fecb3a17SMinas Harutyunyan /* Wait for GINTSTS_RXFLVL interrupt */ 3936fecb3a17SMinas Harutyunyan if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, 3937fecb3a17SMinas Harutyunyan GINTSTS_RXFLVL, 100)) { 3938fecb3a17SMinas Harutyunyan dev_warn(hsotg->dev, "%s: timeout GINTSTS.RXFLVL\n", 3939fecb3a17SMinas Harutyunyan __func__); 3940fecb3a17SMinas Harutyunyan } else { 3941fecb3a17SMinas Harutyunyan /* 3942fecb3a17SMinas Harutyunyan * Pop GLOBAL OUT NAK status packet from RxFIFO 3943fecb3a17SMinas Harutyunyan * to assert GOUTNAKEFF interrupt 3944fecb3a17SMinas Harutyunyan */ 3945fecb3a17SMinas Harutyunyan dwc2_readl(hsotg, GRXSTSP); 3946fecb3a17SMinas Harutyunyan } 3947fecb3a17SMinas Harutyunyan } 3948fecb3a17SMinas Harutyunyan 3949a4f82771SVahram Aharonyan /* Wait for global nak to take effect */ 3950a4f82771SVahram Aharonyan if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, 3951a4f82771SVahram Aharonyan GINTSTS_GOUTNAKEFF, 100)) 3952a4f82771SVahram Aharonyan dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n", 3953a4f82771SVahram Aharonyan __func__); 3954a4f82771SVahram Aharonyan } 3955a4f82771SVahram Aharonyan 3956a4f82771SVahram Aharonyan /* Disable ep */ 3957f25c42b8SGevorg Sahakyan dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK); 3958a4f82771SVahram Aharonyan 3959a4f82771SVahram Aharonyan /* Wait for ep to be disabled */ 3960a4f82771SVahram Aharonyan if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100)) 3961a4f82771SVahram Aharonyan dev_warn(hsotg->dev, 3962a4f82771SVahram Aharonyan "%s: timeout DOEPCTL.EPDisable\n", __func__); 3963a4f82771SVahram Aharonyan 3964a4f82771SVahram Aharonyan /* Clear EPDISBLD interrupt */ 3965f25c42b8SGevorg Sahakyan dwc2_set_bit(hsotg, epint_reg, DXEPINT_EPDISBLD); 3966a4f82771SVahram Aharonyan 3967a4f82771SVahram Aharonyan if (hs_ep->dir_in) { 3968a4f82771SVahram Aharonyan unsigned short fifo_index; 3969a4f82771SVahram Aharonyan 3970a4f82771SVahram Aharonyan if (hsotg->dedicated_fifos || hs_ep->periodic) 3971a4f82771SVahram Aharonyan fifo_index = hs_ep->fifo_index; 3972a4f82771SVahram Aharonyan else 3973a4f82771SVahram Aharonyan fifo_index = 0; 3974a4f82771SVahram Aharonyan 3975a4f82771SVahram Aharonyan /* Flush TX FIFO */ 3976a4f82771SVahram Aharonyan dwc2_flush_tx_fifo(hsotg, fifo_index); 3977a4f82771SVahram Aharonyan 3978a4f82771SVahram Aharonyan /* Clear Global In NP NAK in Shared FIFO for non periodic ep */ 3979a4f82771SVahram Aharonyan if (!hsotg->dedicated_fifos && !hs_ep->periodic) 3980f25c42b8SGevorg Sahakyan dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK); 3981a4f82771SVahram Aharonyan 3982a4f82771SVahram Aharonyan } else { 3983a4f82771SVahram Aharonyan /* Remove global NAKs */ 3984f25c42b8SGevorg Sahakyan dwc2_set_bit(hsotg, DCTL, DCTL_CGOUTNAK); 3985a4f82771SVahram Aharonyan } 3986a4f82771SVahram Aharonyan } 3987a4f82771SVahram Aharonyan 398847a1685fSDinh Nguyen /** 39891f91b4ccSFelipe Balbi * dwc2_hsotg_ep_enable - enable the given endpoint 399047a1685fSDinh Nguyen * @ep: The USB endpint to configure 399147a1685fSDinh Nguyen * @desc: The USB endpoint descriptor to configure with. 399247a1685fSDinh Nguyen * 399347a1685fSDinh Nguyen * This is called from the USB gadget code's usb_ep_enable(). 399447a1685fSDinh Nguyen */ 39951f91b4ccSFelipe Balbi static int dwc2_hsotg_ep_enable(struct usb_ep *ep, 399647a1685fSDinh Nguyen const struct usb_endpoint_descriptor *desc) 399747a1685fSDinh Nguyen { 39981f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *hs_ep = our_ep(ep); 3999941fcce4SDinh Nguyen struct dwc2_hsotg *hsotg = hs_ep->parent; 400047a1685fSDinh Nguyen unsigned long flags; 4001ca4c55adSMian Yousaf Kaukab unsigned int index = hs_ep->index; 400247a1685fSDinh Nguyen u32 epctrl_reg; 400347a1685fSDinh Nguyen u32 epctrl; 400447a1685fSDinh Nguyen u32 mps; 4005ee2c40deSVardan Mikayelyan u32 mc; 4006837e9f00SVardan Mikayelyan u32 mask; 4007ca4c55adSMian Yousaf Kaukab unsigned int dir_in; 4008ca4c55adSMian Yousaf Kaukab unsigned int i, val, size; 400947a1685fSDinh Nguyen int ret = 0; 4010729cac69SMinas Harutyunyan unsigned char ep_type; 401154f37f56SMinas Harutyunyan int desc_num; 401247a1685fSDinh Nguyen 401347a1685fSDinh Nguyen dev_dbg(hsotg->dev, 401447a1685fSDinh Nguyen "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n", 401547a1685fSDinh Nguyen __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes, 401647a1685fSDinh Nguyen desc->wMaxPacketSize, desc->bInterval); 401747a1685fSDinh Nguyen 401847a1685fSDinh Nguyen /* not to be called for EP0 */ 40198c3d6092SVahram Aharonyan if (index == 0) { 40208c3d6092SVahram Aharonyan dev_err(hsotg->dev, "%s: called for EP 0\n", __func__); 40218c3d6092SVahram Aharonyan return -EINVAL; 40228c3d6092SVahram Aharonyan } 402347a1685fSDinh Nguyen 402447a1685fSDinh Nguyen dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0; 402547a1685fSDinh Nguyen if (dir_in != hs_ep->dir_in) { 402647a1685fSDinh Nguyen dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__); 402747a1685fSDinh Nguyen return -EINVAL; 402847a1685fSDinh Nguyen } 402947a1685fSDinh Nguyen 4030729cac69SMinas Harutyunyan ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; 403147a1685fSDinh Nguyen mps = usb_endpoint_maxp(desc); 4032ee2c40deSVardan Mikayelyan mc = usb_endpoint_maxp_mult(desc); 403347a1685fSDinh Nguyen 4034729cac69SMinas Harutyunyan /* ISOC IN in DDMA supported bInterval up to 10 */ 4035729cac69SMinas Harutyunyan if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC && 4036729cac69SMinas Harutyunyan dir_in && desc->bInterval > 10) { 4037729cac69SMinas Harutyunyan dev_err(hsotg->dev, 4038729cac69SMinas Harutyunyan "%s: ISOC IN, DDMA: bInterval>10 not supported!\n", __func__); 4039729cac69SMinas Harutyunyan return -EINVAL; 4040729cac69SMinas Harutyunyan } 4041729cac69SMinas Harutyunyan 4042729cac69SMinas Harutyunyan /* High bandwidth ISOC OUT in DDMA not supported */ 4043729cac69SMinas Harutyunyan if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC && 4044729cac69SMinas Harutyunyan !dir_in && mc > 1) { 4045729cac69SMinas Harutyunyan dev_err(hsotg->dev, 4046729cac69SMinas Harutyunyan "%s: ISOC OUT, DDMA: HB not supported!\n", __func__); 4047729cac69SMinas Harutyunyan return -EINVAL; 4048729cac69SMinas Harutyunyan } 4049729cac69SMinas Harutyunyan 40501f91b4ccSFelipe Balbi /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */ 405147a1685fSDinh Nguyen 405247a1685fSDinh Nguyen epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); 4053f25c42b8SGevorg Sahakyan epctrl = dwc2_readl(hsotg, epctrl_reg); 405447a1685fSDinh Nguyen 405547a1685fSDinh Nguyen dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n", 405647a1685fSDinh Nguyen __func__, epctrl, epctrl_reg); 405747a1685fSDinh Nguyen 405854f37f56SMinas Harutyunyan if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC) 405954f37f56SMinas Harutyunyan desc_num = MAX_DMA_DESC_NUM_HS_ISOC; 406054f37f56SMinas Harutyunyan else 406154f37f56SMinas Harutyunyan desc_num = MAX_DMA_DESC_NUM_GENERIC; 406254f37f56SMinas Harutyunyan 40635f54c54bSVahram Aharonyan /* Allocate DMA descriptor chain for non-ctrl endpoints */ 40649383e084SVardan Mikayelyan if (using_desc_dma(hsotg) && !hs_ep->desc_list) { 40659383e084SVardan Mikayelyan hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev, 406654f37f56SMinas Harutyunyan desc_num * sizeof(struct dwc2_dma_desc), 406786e881e7SMarek Szyprowski &hs_ep->desc_list_dma, GFP_ATOMIC); 40685f54c54bSVahram Aharonyan if (!hs_ep->desc_list) { 40695f54c54bSVahram Aharonyan ret = -ENOMEM; 40705f54c54bSVahram Aharonyan goto error2; 40715f54c54bSVahram Aharonyan } 40725f54c54bSVahram Aharonyan } 40735f54c54bSVahram Aharonyan 407447a1685fSDinh Nguyen spin_lock_irqsave(&hsotg->lock, flags); 407547a1685fSDinh Nguyen 407647a1685fSDinh Nguyen epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK); 407747a1685fSDinh Nguyen epctrl |= DXEPCTL_MPS(mps); 407847a1685fSDinh Nguyen 407947a1685fSDinh Nguyen /* 408047a1685fSDinh Nguyen * mark the endpoint as active, otherwise the core may ignore 408147a1685fSDinh Nguyen * transactions entirely for this endpoint 408247a1685fSDinh Nguyen */ 408347a1685fSDinh Nguyen epctrl |= DXEPCTL_USBACTEP; 408447a1685fSDinh Nguyen 408547a1685fSDinh Nguyen /* update the endpoint state */ 4086ee2c40deSVardan Mikayelyan dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in); 408747a1685fSDinh Nguyen 408847a1685fSDinh Nguyen /* default, set to non-periodic */ 408947a1685fSDinh Nguyen hs_ep->isochronous = 0; 409047a1685fSDinh Nguyen hs_ep->periodic = 0; 409147a1685fSDinh Nguyen hs_ep->halted = 0; 4092b833ce15SMinas Harutyunyan hs_ep->wedged = 0; 409347a1685fSDinh Nguyen hs_ep->interval = desc->bInterval; 409447a1685fSDinh Nguyen 4095729cac69SMinas Harutyunyan switch (ep_type) { 409647a1685fSDinh Nguyen case USB_ENDPOINT_XFER_ISOC: 409747a1685fSDinh Nguyen epctrl |= DXEPCTL_EPTYPE_ISO; 409847a1685fSDinh Nguyen epctrl |= DXEPCTL_SETEVENFR; 409947a1685fSDinh Nguyen hs_ep->isochronous = 1; 4100142bd33fSVardan Mikayelyan hs_ep->interval = 1 << (desc->bInterval - 1); 4101837e9f00SVardan Mikayelyan hs_ep->target_frame = TARGET_FRAME_INITIAL; 4102ab7d2192SVahram Aharonyan hs_ep->next_desc = 0; 4103729cac69SMinas Harutyunyan hs_ep->compl_desc = 0; 4104837e9f00SVardan Mikayelyan if (dir_in) { 410547a1685fSDinh Nguyen hs_ep->periodic = 1; 4106f25c42b8SGevorg Sahakyan mask = dwc2_readl(hsotg, DIEPMSK); 4107837e9f00SVardan Mikayelyan mask |= DIEPMSK_NAKMSK; 4108f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, mask, DIEPMSK); 4109837e9f00SVardan Mikayelyan } else { 4110*91bb163eSMinas Harutyunyan epctrl |= DXEPCTL_SNAK; 4111f25c42b8SGevorg Sahakyan mask = dwc2_readl(hsotg, DOEPMSK); 4112837e9f00SVardan Mikayelyan mask |= DOEPMSK_OUTTKNEPDISMSK; 4113f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, mask, DOEPMSK); 4114837e9f00SVardan Mikayelyan } 411547a1685fSDinh Nguyen break; 411647a1685fSDinh Nguyen 411747a1685fSDinh Nguyen case USB_ENDPOINT_XFER_BULK: 411847a1685fSDinh Nguyen epctrl |= DXEPCTL_EPTYPE_BULK; 411947a1685fSDinh Nguyen break; 412047a1685fSDinh Nguyen 412147a1685fSDinh Nguyen case USB_ENDPOINT_XFER_INT: 4122b203d0a2SRobert Baldyga if (dir_in) 412347a1685fSDinh Nguyen hs_ep->periodic = 1; 412447a1685fSDinh Nguyen 4125142bd33fSVardan Mikayelyan if (hsotg->gadget.speed == USB_SPEED_HIGH) 4126142bd33fSVardan Mikayelyan hs_ep->interval = 1 << (desc->bInterval - 1); 4127142bd33fSVardan Mikayelyan 412847a1685fSDinh Nguyen epctrl |= DXEPCTL_EPTYPE_INTERRUPT; 412947a1685fSDinh Nguyen break; 413047a1685fSDinh Nguyen 413147a1685fSDinh Nguyen case USB_ENDPOINT_XFER_CONTROL: 413247a1685fSDinh Nguyen epctrl |= DXEPCTL_EPTYPE_CONTROL; 413347a1685fSDinh Nguyen break; 413447a1685fSDinh Nguyen } 413547a1685fSDinh Nguyen 413647a1685fSDinh Nguyen /* 413747a1685fSDinh Nguyen * if the hardware has dedicated fifos, we must give each IN EP 413847a1685fSDinh Nguyen * a unique tx-fifo even if it is non-periodic. 413947a1685fSDinh Nguyen */ 414021f3bb52SRobert Baldyga if (dir_in && hsotg->dedicated_fifos) { 4141644139f8SJohn Keeping unsigned fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 4142ca4c55adSMian Yousaf Kaukab u32 fifo_index = 0; 4143ca4c55adSMian Yousaf Kaukab u32 fifo_size = UINT_MAX; 41449da51974SJohn Youn 4145b203d0a2SRobert Baldyga size = hs_ep->ep.maxpacket * hs_ep->mc; 4146644139f8SJohn Keeping for (i = 1; i <= fifo_count; ++i) { 4147b203d0a2SRobert Baldyga if (hsotg->fifo_map & (1 << i)) 4148b203d0a2SRobert Baldyga continue; 4149f25c42b8SGevorg Sahakyan val = dwc2_readl(hsotg, DPTXFSIZN(i)); 4150b203d0a2SRobert Baldyga val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4; 4151b203d0a2SRobert Baldyga if (val < size) 4152b203d0a2SRobert Baldyga continue; 4153ca4c55adSMian Yousaf Kaukab /* Search for smallest acceptable fifo */ 4154ca4c55adSMian Yousaf Kaukab if (val < fifo_size) { 4155ca4c55adSMian Yousaf Kaukab fifo_size = val; 4156ca4c55adSMian Yousaf Kaukab fifo_index = i; 4157b203d0a2SRobert Baldyga } 4158ca4c55adSMian Yousaf Kaukab } 4159ca4c55adSMian Yousaf Kaukab if (!fifo_index) { 41605f2196bdSMian Yousaf Kaukab dev_err(hsotg->dev, 41615f2196bdSMian Yousaf Kaukab "%s: No suitable fifo found\n", __func__); 4162b585a48bSSudip Mukherjee ret = -ENOMEM; 41635f54c54bSVahram Aharonyan goto error1; 4164b585a48bSSudip Mukherjee } 416597311c8fSMinas Harutyunyan epctrl &= ~(DXEPCTL_TXFNUM_LIMIT << DXEPCTL_TXFNUM_SHIFT); 4166ca4c55adSMian Yousaf Kaukab hsotg->fifo_map |= 1 << fifo_index; 4167ca4c55adSMian Yousaf Kaukab epctrl |= DXEPCTL_TXFNUM(fifo_index); 4168ca4c55adSMian Yousaf Kaukab hs_ep->fifo_index = fifo_index; 4169ca4c55adSMian Yousaf Kaukab hs_ep->fifo_size = fifo_size; 4170b203d0a2SRobert Baldyga } 417147a1685fSDinh Nguyen 417247a1685fSDinh Nguyen /* for non control endpoints, set PID to D0 */ 4173837e9f00SVardan Mikayelyan if (index && !hs_ep->isochronous) 417447a1685fSDinh Nguyen epctrl |= DXEPCTL_SETD0PID; 417547a1685fSDinh Nguyen 41765295322aSArtur Petrosyan /* WA for Full speed ISOC IN in DDMA mode. 41775295322aSArtur Petrosyan * By Clear NAK status of EP, core will send ZLP 41785295322aSArtur Petrosyan * to IN token and assert NAK interrupt relying 41795295322aSArtur Petrosyan * on TxFIFO status only 41805295322aSArtur Petrosyan */ 41815295322aSArtur Petrosyan 41825295322aSArtur Petrosyan if (hsotg->gadget.speed == USB_SPEED_FULL && 41835295322aSArtur Petrosyan hs_ep->isochronous && dir_in) { 41845295322aSArtur Petrosyan /* The WA applies only to core versions from 2.72a 41855295322aSArtur Petrosyan * to 4.00a (including both). Also for FS_IOT_1.00a 41865295322aSArtur Petrosyan * and HS_IOT_1.00a. 41875295322aSArtur Petrosyan */ 4188f25c42b8SGevorg Sahakyan u32 gsnpsid = dwc2_readl(hsotg, GSNPSID); 41895295322aSArtur Petrosyan 41905295322aSArtur Petrosyan if ((gsnpsid >= DWC2_CORE_REV_2_72a && 41915295322aSArtur Petrosyan gsnpsid <= DWC2_CORE_REV_4_00a) || 41925295322aSArtur Petrosyan gsnpsid == DWC2_FS_IOT_REV_1_00a || 41935295322aSArtur Petrosyan gsnpsid == DWC2_HS_IOT_REV_1_00a) 41945295322aSArtur Petrosyan epctrl |= DXEPCTL_CNAK; 41955295322aSArtur Petrosyan } 41965295322aSArtur Petrosyan 419747a1685fSDinh Nguyen dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n", 419847a1685fSDinh Nguyen __func__, epctrl); 419947a1685fSDinh Nguyen 4200f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, epctrl, epctrl_reg); 420147a1685fSDinh Nguyen dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n", 4202f25c42b8SGevorg Sahakyan __func__, dwc2_readl(hsotg, epctrl_reg)); 420347a1685fSDinh Nguyen 420447a1685fSDinh Nguyen /* enable the endpoint interrupt */ 42051f91b4ccSFelipe Balbi dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1); 420647a1685fSDinh Nguyen 42075f54c54bSVahram Aharonyan error1: 420847a1685fSDinh Nguyen spin_unlock_irqrestore(&hsotg->lock, flags); 42095f54c54bSVahram Aharonyan 42105f54c54bSVahram Aharonyan error2: 42115f54c54bSVahram Aharonyan if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) { 421254f37f56SMinas Harutyunyan dmam_free_coherent(hsotg->dev, desc_num * 42135f54c54bSVahram Aharonyan sizeof(struct dwc2_dma_desc), 42145f54c54bSVahram Aharonyan hs_ep->desc_list, hs_ep->desc_list_dma); 42155f54c54bSVahram Aharonyan hs_ep->desc_list = NULL; 42165f54c54bSVahram Aharonyan } 42175f54c54bSVahram Aharonyan 421847a1685fSDinh Nguyen return ret; 421947a1685fSDinh Nguyen } 422047a1685fSDinh Nguyen 422147a1685fSDinh Nguyen /** 42221f91b4ccSFelipe Balbi * dwc2_hsotg_ep_disable - disable given endpoint 422347a1685fSDinh Nguyen * @ep: The endpoint to disable. 422447a1685fSDinh Nguyen */ 42251f91b4ccSFelipe Balbi static int dwc2_hsotg_ep_disable(struct usb_ep *ep) 422647a1685fSDinh Nguyen { 42271f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *hs_ep = our_ep(ep); 4228941fcce4SDinh Nguyen struct dwc2_hsotg *hsotg = hs_ep->parent; 422947a1685fSDinh Nguyen int dir_in = hs_ep->dir_in; 423047a1685fSDinh Nguyen int index = hs_ep->index; 423147a1685fSDinh Nguyen u32 epctrl_reg; 423247a1685fSDinh Nguyen u32 ctrl; 423347a1685fSDinh Nguyen 42341e011293SMarek Szyprowski dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep); 423547a1685fSDinh Nguyen 4236c6f5c050SMian Yousaf Kaukab if (ep == &hsotg->eps_out[0]->ep) { 423747a1685fSDinh Nguyen dev_err(hsotg->dev, "%s: called for ep0\n", __func__); 423847a1685fSDinh Nguyen return -EINVAL; 423947a1685fSDinh Nguyen } 424047a1685fSDinh Nguyen 42419b481092SJohn Stultz if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) { 42429b481092SJohn Stultz dev_err(hsotg->dev, "%s: called in host mode?\n", __func__); 42439b481092SJohn Stultz return -EINVAL; 42449b481092SJohn Stultz } 42459b481092SJohn Stultz 424647a1685fSDinh Nguyen epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); 424747a1685fSDinh Nguyen 4248f25c42b8SGevorg Sahakyan ctrl = dwc2_readl(hsotg, epctrl_reg); 4249a4f82771SVahram Aharonyan 4250a4f82771SVahram Aharonyan if (ctrl & DXEPCTL_EPENA) 4251a4f82771SVahram Aharonyan dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep); 4252a4f82771SVahram Aharonyan 425347a1685fSDinh Nguyen ctrl &= ~DXEPCTL_EPENA; 425447a1685fSDinh Nguyen ctrl &= ~DXEPCTL_USBACTEP; 425547a1685fSDinh Nguyen ctrl |= DXEPCTL_SNAK; 425647a1685fSDinh Nguyen 425747a1685fSDinh Nguyen dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); 4258f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, ctrl, epctrl_reg); 425947a1685fSDinh Nguyen 426047a1685fSDinh Nguyen /* disable endpoint interrupts */ 42611f91b4ccSFelipe Balbi dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0); 426247a1685fSDinh Nguyen 42631141ea01SMian Yousaf Kaukab /* terminate all requests with shutdown */ 42641141ea01SMian Yousaf Kaukab kill_all_requests(hsotg, hs_ep, -ESHUTDOWN); 42651141ea01SMian Yousaf Kaukab 42661c07b20eSRobert Baldyga hsotg->fifo_map &= ~(1 << hs_ep->fifo_index); 42671c07b20eSRobert Baldyga hs_ep->fifo_index = 0; 42681c07b20eSRobert Baldyga hs_ep->fifo_size = 0; 42691c07b20eSRobert Baldyga 427047a1685fSDinh Nguyen return 0; 427147a1685fSDinh Nguyen } 427247a1685fSDinh Nguyen 42734fe4f9feSMinas Harutyunyan static int dwc2_hsotg_ep_disable_lock(struct usb_ep *ep) 42744fe4f9feSMinas Harutyunyan { 42754fe4f9feSMinas Harutyunyan struct dwc2_hsotg_ep *hs_ep = our_ep(ep); 42764fe4f9feSMinas Harutyunyan struct dwc2_hsotg *hsotg = hs_ep->parent; 42774fe4f9feSMinas Harutyunyan unsigned long flags; 42784fe4f9feSMinas Harutyunyan int ret; 42794fe4f9feSMinas Harutyunyan 42804fe4f9feSMinas Harutyunyan spin_lock_irqsave(&hsotg->lock, flags); 42814fe4f9feSMinas Harutyunyan ret = dwc2_hsotg_ep_disable(ep); 42824fe4f9feSMinas Harutyunyan spin_unlock_irqrestore(&hsotg->lock, flags); 42834fe4f9feSMinas Harutyunyan return ret; 42844fe4f9feSMinas Harutyunyan } 42854fe4f9feSMinas Harutyunyan 428647a1685fSDinh Nguyen /** 428747a1685fSDinh Nguyen * on_list - check request is on the given endpoint 428847a1685fSDinh Nguyen * @ep: The endpoint to check. 428947a1685fSDinh Nguyen * @test: The request to test if it is on the endpoint. 429047a1685fSDinh Nguyen */ 42911f91b4ccSFelipe Balbi static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test) 429247a1685fSDinh Nguyen { 42931f91b4ccSFelipe Balbi struct dwc2_hsotg_req *req, *treq; 429447a1685fSDinh Nguyen 429547a1685fSDinh Nguyen list_for_each_entry_safe(req, treq, &ep->queue, queue) { 429647a1685fSDinh Nguyen if (req == test) 429747a1685fSDinh Nguyen return true; 429847a1685fSDinh Nguyen } 429947a1685fSDinh Nguyen 430047a1685fSDinh Nguyen return false; 430147a1685fSDinh Nguyen } 430247a1685fSDinh Nguyen 430347a1685fSDinh Nguyen /** 43041f91b4ccSFelipe Balbi * dwc2_hsotg_ep_dequeue - dequeue given endpoint 430547a1685fSDinh Nguyen * @ep: The endpoint to dequeue. 430647a1685fSDinh Nguyen * @req: The request to be removed from a queue. 430747a1685fSDinh Nguyen */ 43081f91b4ccSFelipe Balbi static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req) 430947a1685fSDinh Nguyen { 43101f91b4ccSFelipe Balbi struct dwc2_hsotg_req *hs_req = our_req(req); 43111f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *hs_ep = our_ep(ep); 4312941fcce4SDinh Nguyen struct dwc2_hsotg *hs = hs_ep->parent; 431347a1685fSDinh Nguyen unsigned long flags; 431447a1685fSDinh Nguyen 43151e011293SMarek Szyprowski dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req); 431647a1685fSDinh Nguyen 431747a1685fSDinh Nguyen spin_lock_irqsave(&hs->lock, flags); 431847a1685fSDinh Nguyen 431947a1685fSDinh Nguyen if (!on_list(hs_ep, hs_req)) { 432047a1685fSDinh Nguyen spin_unlock_irqrestore(&hs->lock, flags); 432147a1685fSDinh Nguyen return -EINVAL; 432247a1685fSDinh Nguyen } 432347a1685fSDinh Nguyen 4324c524dd5fSMian Yousaf Kaukab /* Dequeue already started request */ 4325c524dd5fSMian Yousaf Kaukab if (req == &hs_ep->req->req) 4326c524dd5fSMian Yousaf Kaukab dwc2_hsotg_ep_stop_xfr(hs, hs_ep); 4327c524dd5fSMian Yousaf Kaukab 43281f91b4ccSFelipe Balbi dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET); 432947a1685fSDinh Nguyen spin_unlock_irqrestore(&hs->lock, flags); 433047a1685fSDinh Nguyen 433147a1685fSDinh Nguyen return 0; 433247a1685fSDinh Nguyen } 433347a1685fSDinh Nguyen 433447a1685fSDinh Nguyen /** 4335b833ce15SMinas Harutyunyan * dwc2_gadget_ep_set_wedge - set wedge on a given endpoint 4336b833ce15SMinas Harutyunyan * @ep: The endpoint to be wedged. 4337b833ce15SMinas Harutyunyan * 4338b833ce15SMinas Harutyunyan */ 4339b833ce15SMinas Harutyunyan static int dwc2_gadget_ep_set_wedge(struct usb_ep *ep) 4340b833ce15SMinas Harutyunyan { 4341b833ce15SMinas Harutyunyan struct dwc2_hsotg_ep *hs_ep = our_ep(ep); 4342b833ce15SMinas Harutyunyan struct dwc2_hsotg *hs = hs_ep->parent; 4343b833ce15SMinas Harutyunyan 4344b833ce15SMinas Harutyunyan unsigned long flags; 4345b833ce15SMinas Harutyunyan int ret; 4346b833ce15SMinas Harutyunyan 4347b833ce15SMinas Harutyunyan spin_lock_irqsave(&hs->lock, flags); 4348b833ce15SMinas Harutyunyan hs_ep->wedged = 1; 4349b833ce15SMinas Harutyunyan ret = dwc2_hsotg_ep_sethalt(ep, 1, false); 4350b833ce15SMinas Harutyunyan spin_unlock_irqrestore(&hs->lock, flags); 4351b833ce15SMinas Harutyunyan 4352b833ce15SMinas Harutyunyan return ret; 4353b833ce15SMinas Harutyunyan } 4354b833ce15SMinas Harutyunyan 4355b833ce15SMinas Harutyunyan /** 43561f91b4ccSFelipe Balbi * dwc2_hsotg_ep_sethalt - set halt on a given endpoint 435747a1685fSDinh Nguyen * @ep: The endpoint to set halt. 435847a1685fSDinh Nguyen * @value: Set or unset the halt. 435951da43b5SVahram Aharonyan * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if 436051da43b5SVahram Aharonyan * the endpoint is busy processing requests. 436151da43b5SVahram Aharonyan * 436251da43b5SVahram Aharonyan * We need to stall the endpoint immediately if request comes from set_feature 436351da43b5SVahram Aharonyan * protocol command handler. 436447a1685fSDinh Nguyen */ 436551da43b5SVahram Aharonyan static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now) 436647a1685fSDinh Nguyen { 43671f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *hs_ep = our_ep(ep); 4368941fcce4SDinh Nguyen struct dwc2_hsotg *hs = hs_ep->parent; 436947a1685fSDinh Nguyen int index = hs_ep->index; 437047a1685fSDinh Nguyen u32 epreg; 437147a1685fSDinh Nguyen u32 epctl; 437247a1685fSDinh Nguyen u32 xfertype; 437347a1685fSDinh Nguyen 437447a1685fSDinh Nguyen dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value); 437547a1685fSDinh Nguyen 437647a1685fSDinh Nguyen if (index == 0) { 437747a1685fSDinh Nguyen if (value) 43781f91b4ccSFelipe Balbi dwc2_hsotg_stall_ep0(hs); 437947a1685fSDinh Nguyen else 438047a1685fSDinh Nguyen dev_warn(hs->dev, 438147a1685fSDinh Nguyen "%s: can't clear halt on ep0\n", __func__); 438247a1685fSDinh Nguyen return 0; 438347a1685fSDinh Nguyen } 438447a1685fSDinh Nguyen 438515186f10SVahram Aharonyan if (hs_ep->isochronous) { 438615186f10SVahram Aharonyan dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name); 438715186f10SVahram Aharonyan return -EINVAL; 438815186f10SVahram Aharonyan } 438915186f10SVahram Aharonyan 439051da43b5SVahram Aharonyan if (!now && value && !list_empty(&hs_ep->queue)) { 439151da43b5SVahram Aharonyan dev_dbg(hs->dev, "%s request is pending, cannot halt\n", 439251da43b5SVahram Aharonyan ep->name); 439351da43b5SVahram Aharonyan return -EAGAIN; 439451da43b5SVahram Aharonyan } 439551da43b5SVahram Aharonyan 4396c6f5c050SMian Yousaf Kaukab if (hs_ep->dir_in) { 439747a1685fSDinh Nguyen epreg = DIEPCTL(index); 4398f25c42b8SGevorg Sahakyan epctl = dwc2_readl(hs, epreg); 439947a1685fSDinh Nguyen 440047a1685fSDinh Nguyen if (value) { 44015a350d53SFelipe Balbi epctl |= DXEPCTL_STALL | DXEPCTL_SNAK; 440247a1685fSDinh Nguyen if (epctl & DXEPCTL_EPENA) 440347a1685fSDinh Nguyen epctl |= DXEPCTL_EPDIS; 440447a1685fSDinh Nguyen } else { 440547a1685fSDinh Nguyen epctl &= ~DXEPCTL_STALL; 4406b833ce15SMinas Harutyunyan hs_ep->wedged = 0; 440747a1685fSDinh Nguyen xfertype = epctl & DXEPCTL_EPTYPE_MASK; 440847a1685fSDinh Nguyen if (xfertype == DXEPCTL_EPTYPE_BULK || 440947a1685fSDinh Nguyen xfertype == DXEPCTL_EPTYPE_INTERRUPT) 441047a1685fSDinh Nguyen epctl |= DXEPCTL_SETD0PID; 441147a1685fSDinh Nguyen } 4412f25c42b8SGevorg Sahakyan dwc2_writel(hs, epctl, epreg); 4413c6f5c050SMian Yousaf Kaukab } else { 441447a1685fSDinh Nguyen epreg = DOEPCTL(index); 4415f25c42b8SGevorg Sahakyan epctl = dwc2_readl(hs, epreg); 441647a1685fSDinh Nguyen 441734c0887fSJohn Youn if (value) { 4418fecb3a17SMinas Harutyunyan /* Unmask GOUTNAKEFF interrupt */ 4419fecb3a17SMinas Harutyunyan dwc2_hsotg_en_gsint(hs, GINTSTS_GOUTNAKEFF); 4420fecb3a17SMinas Harutyunyan 44216070636cSMinas Harutyunyan if (!(dwc2_readl(hs, GINTSTS) & GINTSTS_GOUTNAKEFF)) 44226070636cSMinas Harutyunyan dwc2_set_bit(hs, DCTL, DCTL_SGOUTNAK); 44236070636cSMinas Harutyunyan // STALL bit will be set in GOUTNAKEFF interrupt handler 442434c0887fSJohn Youn } else { 442547a1685fSDinh Nguyen epctl &= ~DXEPCTL_STALL; 4426b833ce15SMinas Harutyunyan hs_ep->wedged = 0; 442747a1685fSDinh Nguyen xfertype = epctl & DXEPCTL_EPTYPE_MASK; 442847a1685fSDinh Nguyen if (xfertype == DXEPCTL_EPTYPE_BULK || 442947a1685fSDinh Nguyen xfertype == DXEPCTL_EPTYPE_INTERRUPT) 443047a1685fSDinh Nguyen epctl |= DXEPCTL_SETD0PID; 4431f25c42b8SGevorg Sahakyan dwc2_writel(hs, epctl, epreg); 4432c6f5c050SMian Yousaf Kaukab } 44336070636cSMinas Harutyunyan } 443447a1685fSDinh Nguyen 443547a1685fSDinh Nguyen hs_ep->halted = value; 443647a1685fSDinh Nguyen return 0; 443747a1685fSDinh Nguyen } 443847a1685fSDinh Nguyen 443947a1685fSDinh Nguyen /** 44401f91b4ccSFelipe Balbi * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held 444147a1685fSDinh Nguyen * @ep: The endpoint to set halt. 444247a1685fSDinh Nguyen * @value: Set or unset the halt. 444347a1685fSDinh Nguyen */ 44441f91b4ccSFelipe Balbi static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value) 444547a1685fSDinh Nguyen { 44461f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *hs_ep = our_ep(ep); 4447941fcce4SDinh Nguyen struct dwc2_hsotg *hs = hs_ep->parent; 44488879904bSJohan Hovold unsigned long flags; 44498879904bSJohan Hovold int ret; 445047a1685fSDinh Nguyen 445147a1685fSDinh Nguyen spin_lock_irqsave(&hs->lock, flags); 445251da43b5SVahram Aharonyan ret = dwc2_hsotg_ep_sethalt(ep, value, false); 445347a1685fSDinh Nguyen spin_unlock_irqrestore(&hs->lock, flags); 445447a1685fSDinh Nguyen 445547a1685fSDinh Nguyen return ret; 445647a1685fSDinh Nguyen } 445747a1685fSDinh Nguyen 4458ebce561aSBhumika Goyal static const struct usb_ep_ops dwc2_hsotg_ep_ops = { 44591f91b4ccSFelipe Balbi .enable = dwc2_hsotg_ep_enable, 44604fe4f9feSMinas Harutyunyan .disable = dwc2_hsotg_ep_disable_lock, 44611f91b4ccSFelipe Balbi .alloc_request = dwc2_hsotg_ep_alloc_request, 44621f91b4ccSFelipe Balbi .free_request = dwc2_hsotg_ep_free_request, 44631f91b4ccSFelipe Balbi .queue = dwc2_hsotg_ep_queue_lock, 44641f91b4ccSFelipe Balbi .dequeue = dwc2_hsotg_ep_dequeue, 44651f91b4ccSFelipe Balbi .set_halt = dwc2_hsotg_ep_sethalt_lock, 4466b833ce15SMinas Harutyunyan .set_wedge = dwc2_gadget_ep_set_wedge, 446747a1685fSDinh Nguyen /* note, don't believe we have any call for the fifo routines */ 446847a1685fSDinh Nguyen }; 446947a1685fSDinh Nguyen 447047a1685fSDinh Nguyen /** 44719da51974SJohn Youn * dwc2_hsotg_init - initialize the usb core 447247a1685fSDinh Nguyen * @hsotg: The driver state 447347a1685fSDinh Nguyen */ 44741f91b4ccSFelipe Balbi static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg) 447547a1685fSDinh Nguyen { 447647a1685fSDinh Nguyen /* unmask subset of endpoint interrupts */ 447747a1685fSDinh Nguyen 4478f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | 447947a1685fSDinh Nguyen DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK, 4480f25c42b8SGevorg Sahakyan DIEPMSK); 448147a1685fSDinh Nguyen 4482f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK | 448347a1685fSDinh Nguyen DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK, 4484f25c42b8SGevorg Sahakyan DOEPMSK); 448547a1685fSDinh Nguyen 4486f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, 0, DAINTMSK); 448747a1685fSDinh Nguyen 448847a1685fSDinh Nguyen /* Be in disconnected state until gadget is registered */ 4489f25c42b8SGevorg Sahakyan dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON); 449047a1685fSDinh Nguyen 449147a1685fSDinh Nguyen /* setup fifos */ 449247a1685fSDinh Nguyen 449347a1685fSDinh Nguyen dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", 4494f25c42b8SGevorg Sahakyan dwc2_readl(hsotg, GRXFSIZ), 4495f25c42b8SGevorg Sahakyan dwc2_readl(hsotg, GNPTXFSIZ)); 449647a1685fSDinh Nguyen 44971f91b4ccSFelipe Balbi dwc2_hsotg_init_fifo(hsotg); 449847a1685fSDinh Nguyen 4499f5090044SGregory Herrero if (using_dma(hsotg)) 4500f25c42b8SGevorg Sahakyan dwc2_set_bit(hsotg, GAHBCFG, GAHBCFG_DMA_EN); 450147a1685fSDinh Nguyen } 450247a1685fSDinh Nguyen 450347a1685fSDinh Nguyen /** 45041f91b4ccSFelipe Balbi * dwc2_hsotg_udc_start - prepare the udc for work 450547a1685fSDinh Nguyen * @gadget: The usb gadget state 450647a1685fSDinh Nguyen * @driver: The usb gadget driver 450747a1685fSDinh Nguyen * 450847a1685fSDinh Nguyen * Perform initialization to prepare udc device and driver 450947a1685fSDinh Nguyen * to work. 451047a1685fSDinh Nguyen */ 45111f91b4ccSFelipe Balbi static int dwc2_hsotg_udc_start(struct usb_gadget *gadget, 451247a1685fSDinh Nguyen struct usb_gadget_driver *driver) 451347a1685fSDinh Nguyen { 4514941fcce4SDinh Nguyen struct dwc2_hsotg *hsotg = to_hsotg(gadget); 45155b9451f8SMarek Szyprowski unsigned long flags; 451647a1685fSDinh Nguyen int ret; 451747a1685fSDinh Nguyen 451847a1685fSDinh Nguyen if (!hsotg) { 451947a1685fSDinh Nguyen pr_err("%s: called with no device\n", __func__); 452047a1685fSDinh Nguyen return -ENODEV; 452147a1685fSDinh Nguyen } 452247a1685fSDinh Nguyen 452347a1685fSDinh Nguyen if (!driver) { 452447a1685fSDinh Nguyen dev_err(hsotg->dev, "%s: no driver\n", __func__); 452547a1685fSDinh Nguyen return -EINVAL; 452647a1685fSDinh Nguyen } 452747a1685fSDinh Nguyen 452847a1685fSDinh Nguyen if (driver->max_speed < USB_SPEED_FULL) 452947a1685fSDinh Nguyen dev_err(hsotg->dev, "%s: bad speed\n", __func__); 453047a1685fSDinh Nguyen 453147a1685fSDinh Nguyen if (!driver->setup) { 453247a1685fSDinh Nguyen dev_err(hsotg->dev, "%s: missing entry points\n", __func__); 453347a1685fSDinh Nguyen return -EINVAL; 453447a1685fSDinh Nguyen } 453547a1685fSDinh Nguyen 453647a1685fSDinh Nguyen WARN_ON(hsotg->driver); 453747a1685fSDinh Nguyen 453847a1685fSDinh Nguyen driver->driver.bus = NULL; 453947a1685fSDinh Nguyen hsotg->driver = driver; 454047a1685fSDinh Nguyen hsotg->gadget.dev.of_node = hsotg->dev->of_node; 454147a1685fSDinh Nguyen hsotg->gadget.speed = USB_SPEED_UNKNOWN; 454247a1685fSDinh Nguyen 454309a75e85SMarek Szyprowski if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) { 454409a75e85SMarek Szyprowski ret = dwc2_lowlevel_hw_enable(hsotg); 454509a75e85SMarek Szyprowski if (ret) 454647a1685fSDinh Nguyen goto err; 454747a1685fSDinh Nguyen } 454847a1685fSDinh Nguyen 4549f6c01592SGregory Herrero if (!IS_ERR_OR_NULL(hsotg->uphy)) 4550f6c01592SGregory Herrero otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget); 4551c816c47fSMarek Szyprowski 45525b9451f8SMarek Szyprowski spin_lock_irqsave(&hsotg->lock, flags); 4553d0f0ac56SJohn Youn if (dwc2_hw_is_device(hsotg)) { 45541f91b4ccSFelipe Balbi dwc2_hsotg_init(hsotg); 45551f91b4ccSFelipe Balbi dwc2_hsotg_core_init_disconnected(hsotg, false); 4556d0f0ac56SJohn Youn } 4557d0f0ac56SJohn Youn 4558dc6e69e6SMarek Szyprowski hsotg->enabled = 0; 45595b9451f8SMarek Szyprowski spin_unlock_irqrestore(&hsotg->lock, flags); 45605b9451f8SMarek Szyprowski 456110209abeSAndrzej Pietrasiewicz gadget->sg_supported = using_desc_dma(hsotg); 456247a1685fSDinh Nguyen dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name); 45635b9451f8SMarek Szyprowski 456447a1685fSDinh Nguyen return 0; 456547a1685fSDinh Nguyen 456647a1685fSDinh Nguyen err: 456747a1685fSDinh Nguyen hsotg->driver = NULL; 456847a1685fSDinh Nguyen return ret; 456947a1685fSDinh Nguyen } 457047a1685fSDinh Nguyen 457147a1685fSDinh Nguyen /** 45721f91b4ccSFelipe Balbi * dwc2_hsotg_udc_stop - stop the udc 457347a1685fSDinh Nguyen * @gadget: The usb gadget state 457447a1685fSDinh Nguyen * 457547a1685fSDinh Nguyen * Stop udc hw block and stay tunned for future transmissions 457647a1685fSDinh Nguyen */ 45771f91b4ccSFelipe Balbi static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget) 457847a1685fSDinh Nguyen { 4579941fcce4SDinh Nguyen struct dwc2_hsotg *hsotg = to_hsotg(gadget); 45808879904bSJohan Hovold unsigned long flags; 458147a1685fSDinh Nguyen int ep; 458247a1685fSDinh Nguyen 458347a1685fSDinh Nguyen if (!hsotg) 458447a1685fSDinh Nguyen return -ENODEV; 458547a1685fSDinh Nguyen 458647a1685fSDinh Nguyen /* all endpoints should be shutdown */ 4587c6f5c050SMian Yousaf Kaukab for (ep = 1; ep < hsotg->num_of_eps; ep++) { 4588c6f5c050SMian Yousaf Kaukab if (hsotg->eps_in[ep]) 45894fe4f9feSMinas Harutyunyan dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep); 4590c6f5c050SMian Yousaf Kaukab if (hsotg->eps_out[ep]) 45914fe4f9feSMinas Harutyunyan dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep); 4592c6f5c050SMian Yousaf Kaukab } 459347a1685fSDinh Nguyen 459447a1685fSDinh Nguyen spin_lock_irqsave(&hsotg->lock, flags); 459547a1685fSDinh Nguyen 459647a1685fSDinh Nguyen hsotg->driver = NULL; 459747a1685fSDinh Nguyen hsotg->gadget.speed = USB_SPEED_UNKNOWN; 4598dc6e69e6SMarek Szyprowski hsotg->enabled = 0; 459947a1685fSDinh Nguyen 460047a1685fSDinh Nguyen spin_unlock_irqrestore(&hsotg->lock, flags); 460147a1685fSDinh Nguyen 4602f6c01592SGregory Herrero if (!IS_ERR_OR_NULL(hsotg->uphy)) 4603f6c01592SGregory Herrero otg_set_peripheral(hsotg->uphy->otg, NULL); 4604c816c47fSMarek Szyprowski 460509a75e85SMarek Szyprowski if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) 460609a75e85SMarek Szyprowski dwc2_lowlevel_hw_disable(hsotg); 460747a1685fSDinh Nguyen 460847a1685fSDinh Nguyen return 0; 460947a1685fSDinh Nguyen } 461047a1685fSDinh Nguyen 461147a1685fSDinh Nguyen /** 46121f91b4ccSFelipe Balbi * dwc2_hsotg_gadget_getframe - read the frame number 461347a1685fSDinh Nguyen * @gadget: The usb gadget state 461447a1685fSDinh Nguyen * 461547a1685fSDinh Nguyen * Read the {micro} frame number 461647a1685fSDinh Nguyen */ 46171f91b4ccSFelipe Balbi static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget) 461847a1685fSDinh Nguyen { 46191f91b4ccSFelipe Balbi return dwc2_hsotg_read_frameno(to_hsotg(gadget)); 462047a1685fSDinh Nguyen } 462147a1685fSDinh Nguyen 462247a1685fSDinh Nguyen /** 46231a0808cbSJohn Keeping * dwc2_hsotg_set_selfpowered - set if device is self/bus powered 46241a0808cbSJohn Keeping * @gadget: The usb gadget state 46251a0808cbSJohn Keeping * @is_selfpowered: Whether the device is self-powered 46261a0808cbSJohn Keeping * 46271a0808cbSJohn Keeping * Set if the device is self or bus powered. 46281a0808cbSJohn Keeping */ 46291a0808cbSJohn Keeping static int dwc2_hsotg_set_selfpowered(struct usb_gadget *gadget, 46301a0808cbSJohn Keeping int is_selfpowered) 46311a0808cbSJohn Keeping { 46321a0808cbSJohn Keeping struct dwc2_hsotg *hsotg = to_hsotg(gadget); 46331a0808cbSJohn Keeping unsigned long flags; 46341a0808cbSJohn Keeping 46351a0808cbSJohn Keeping spin_lock_irqsave(&hsotg->lock, flags); 46361a0808cbSJohn Keeping gadget->is_selfpowered = !!is_selfpowered; 46371a0808cbSJohn Keeping spin_unlock_irqrestore(&hsotg->lock, flags); 46381a0808cbSJohn Keeping 46391a0808cbSJohn Keeping return 0; 46401a0808cbSJohn Keeping } 46411a0808cbSJohn Keeping 46421a0808cbSJohn Keeping /** 46431f91b4ccSFelipe Balbi * dwc2_hsotg_pullup - connect/disconnect the USB PHY 464447a1685fSDinh Nguyen * @gadget: The usb gadget state 464547a1685fSDinh Nguyen * @is_on: Current state of the USB PHY 464647a1685fSDinh Nguyen * 464747a1685fSDinh Nguyen * Connect/Disconnect the USB PHY pullup 464847a1685fSDinh Nguyen */ 46491f91b4ccSFelipe Balbi static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on) 465047a1685fSDinh Nguyen { 4651941fcce4SDinh Nguyen struct dwc2_hsotg *hsotg = to_hsotg(gadget); 46528879904bSJohan Hovold unsigned long flags; 465347a1685fSDinh Nguyen 465477ba9119SGregory Herrero dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on, 465577ba9119SGregory Herrero hsotg->op_state); 465677ba9119SGregory Herrero 465777ba9119SGregory Herrero /* Don't modify pullup state while in host mode */ 465877ba9119SGregory Herrero if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) { 465977ba9119SGregory Herrero hsotg->enabled = is_on; 466077ba9119SGregory Herrero return 0; 466177ba9119SGregory Herrero } 466247a1685fSDinh Nguyen 466347a1685fSDinh Nguyen spin_lock_irqsave(&hsotg->lock, flags); 466447a1685fSDinh Nguyen if (is_on) { 4665dc6e69e6SMarek Szyprowski hsotg->enabled = 1; 46661f91b4ccSFelipe Balbi dwc2_hsotg_core_init_disconnected(hsotg, false); 466766e77a24SRazmik Karapetyan /* Enable ACG feature in device mode,if supported */ 466866e77a24SRazmik Karapetyan dwc2_enable_acg(hsotg); 46691f91b4ccSFelipe Balbi dwc2_hsotg_core_connect(hsotg); 467047a1685fSDinh Nguyen } else { 46711f91b4ccSFelipe Balbi dwc2_hsotg_core_disconnect(hsotg); 46721f91b4ccSFelipe Balbi dwc2_hsotg_disconnect(hsotg); 4673dc6e69e6SMarek Szyprowski hsotg->enabled = 0; 467447a1685fSDinh Nguyen } 467547a1685fSDinh Nguyen 467647a1685fSDinh Nguyen hsotg->gadget.speed = USB_SPEED_UNKNOWN; 467747a1685fSDinh Nguyen spin_unlock_irqrestore(&hsotg->lock, flags); 467847a1685fSDinh Nguyen 467947a1685fSDinh Nguyen return 0; 468047a1685fSDinh Nguyen } 468147a1685fSDinh Nguyen 46821f91b4ccSFelipe Balbi static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active) 468383d98223SGregory Herrero { 468483d98223SGregory Herrero struct dwc2_hsotg *hsotg = to_hsotg(gadget); 468583d98223SGregory Herrero unsigned long flags; 468683d98223SGregory Herrero 468783d98223SGregory Herrero dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active); 468883d98223SGregory Herrero spin_lock_irqsave(&hsotg->lock, flags); 468983d98223SGregory Herrero 469018b2b37cSGregory Herrero /* 4691c9c394abSArtur Petrosyan * If controller is in partial power down state, it must exit from 4692c9c394abSArtur Petrosyan * that state before being initialized / de-initialized 469318b2b37cSGregory Herrero */ 4694c9c394abSArtur Petrosyan if (hsotg->lx_state == DWC2_L2 && hsotg->in_ppd) 4695c9c394abSArtur Petrosyan /* 4696c9c394abSArtur Petrosyan * No need to check the return value as 4697c9c394abSArtur Petrosyan * registers are not being restored. 4698c9c394abSArtur Petrosyan */ 4699c9c394abSArtur Petrosyan dwc2_exit_partial_power_down(hsotg, 0, false); 4700065d3931SGregory Herrero 470161f7223bSGregory Herrero if (is_active) { 470261f7223bSGregory Herrero hsotg->op_state = OTG_STATE_B_PERIPHERAL; 470361f7223bSGregory Herrero 47041f91b4ccSFelipe Balbi dwc2_hsotg_core_init_disconnected(hsotg, false); 470566e77a24SRazmik Karapetyan if (hsotg->enabled) { 470666e77a24SRazmik Karapetyan /* Enable ACG feature in device mode,if supported */ 470766e77a24SRazmik Karapetyan dwc2_enable_acg(hsotg); 47081f91b4ccSFelipe Balbi dwc2_hsotg_core_connect(hsotg); 470966e77a24SRazmik Karapetyan } 471083d98223SGregory Herrero } else { 47111f91b4ccSFelipe Balbi dwc2_hsotg_core_disconnect(hsotg); 47121f91b4ccSFelipe Balbi dwc2_hsotg_disconnect(hsotg); 471383d98223SGregory Herrero } 471483d98223SGregory Herrero 471583d98223SGregory Herrero spin_unlock_irqrestore(&hsotg->lock, flags); 471683d98223SGregory Herrero return 0; 471783d98223SGregory Herrero } 471883d98223SGregory Herrero 4719596d696aSGregory Herrero /** 47201f91b4ccSFelipe Balbi * dwc2_hsotg_vbus_draw - report bMaxPower field 4721596d696aSGregory Herrero * @gadget: The usb gadget state 4722596d696aSGregory Herrero * @mA: Amount of current 4723596d696aSGregory Herrero * 4724596d696aSGregory Herrero * Report how much power the device may consume to the phy. 4725596d696aSGregory Herrero */ 47269da51974SJohn Youn static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA) 4727596d696aSGregory Herrero { 4728596d696aSGregory Herrero struct dwc2_hsotg *hsotg = to_hsotg(gadget); 4729596d696aSGregory Herrero 4730596d696aSGregory Herrero if (IS_ERR_OR_NULL(hsotg->uphy)) 4731596d696aSGregory Herrero return -ENOTSUPP; 4732596d696aSGregory Herrero return usb_phy_set_power(hsotg->uphy, mA); 4733596d696aSGregory Herrero } 4734596d696aSGregory Herrero 47355324bad6SArgishti Aleksanyan static void dwc2_gadget_set_speed(struct usb_gadget *g, enum usb_device_speed speed) 47365324bad6SArgishti Aleksanyan { 47375324bad6SArgishti Aleksanyan struct dwc2_hsotg *hsotg = to_hsotg(g); 47385324bad6SArgishti Aleksanyan unsigned long flags; 47395324bad6SArgishti Aleksanyan 47405324bad6SArgishti Aleksanyan spin_lock_irqsave(&hsotg->lock, flags); 47415324bad6SArgishti Aleksanyan switch (speed) { 47425324bad6SArgishti Aleksanyan case USB_SPEED_HIGH: 47435324bad6SArgishti Aleksanyan hsotg->params.speed = DWC2_SPEED_PARAM_HIGH; 47445324bad6SArgishti Aleksanyan break; 47455324bad6SArgishti Aleksanyan case USB_SPEED_FULL: 47465324bad6SArgishti Aleksanyan hsotg->params.speed = DWC2_SPEED_PARAM_FULL; 47475324bad6SArgishti Aleksanyan break; 47485324bad6SArgishti Aleksanyan case USB_SPEED_LOW: 47495324bad6SArgishti Aleksanyan hsotg->params.speed = DWC2_SPEED_PARAM_LOW; 47505324bad6SArgishti Aleksanyan break; 47515324bad6SArgishti Aleksanyan default: 47525324bad6SArgishti Aleksanyan dev_err(hsotg->dev, "invalid speed (%d)\n", speed); 47535324bad6SArgishti Aleksanyan } 47545324bad6SArgishti Aleksanyan spin_unlock_irqrestore(&hsotg->lock, flags); 47555324bad6SArgishti Aleksanyan } 47565324bad6SArgishti Aleksanyan 47571f91b4ccSFelipe Balbi static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = { 47581f91b4ccSFelipe Balbi .get_frame = dwc2_hsotg_gadget_getframe, 47591a0808cbSJohn Keeping .set_selfpowered = dwc2_hsotg_set_selfpowered, 47601f91b4ccSFelipe Balbi .udc_start = dwc2_hsotg_udc_start, 47611f91b4ccSFelipe Balbi .udc_stop = dwc2_hsotg_udc_stop, 47621f91b4ccSFelipe Balbi .pullup = dwc2_hsotg_pullup, 47635324bad6SArgishti Aleksanyan .udc_set_speed = dwc2_gadget_set_speed, 47641f91b4ccSFelipe Balbi .vbus_session = dwc2_hsotg_vbus_session, 47651f91b4ccSFelipe Balbi .vbus_draw = dwc2_hsotg_vbus_draw, 476647a1685fSDinh Nguyen }; 476747a1685fSDinh Nguyen 476847a1685fSDinh Nguyen /** 47691f91b4ccSFelipe Balbi * dwc2_hsotg_initep - initialise a single endpoint 477047a1685fSDinh Nguyen * @hsotg: The device state. 477147a1685fSDinh Nguyen * @hs_ep: The endpoint to be initialised. 477247a1685fSDinh Nguyen * @epnum: The endpoint number 47736fb914d7SGrigor Tovmasyan * @dir_in: True if direction is in. 477447a1685fSDinh Nguyen * 477547a1685fSDinh Nguyen * Initialise the given endpoint (as part of the probe and device state 477647a1685fSDinh Nguyen * creation) to give to the gadget driver. Setup the endpoint name, any 477747a1685fSDinh Nguyen * direction information and other state that may be required. 477847a1685fSDinh Nguyen */ 47791f91b4ccSFelipe Balbi static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg, 47801f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *hs_ep, 4781c6f5c050SMian Yousaf Kaukab int epnum, 4782c6f5c050SMian Yousaf Kaukab bool dir_in) 478347a1685fSDinh Nguyen { 478447a1685fSDinh Nguyen char *dir; 478547a1685fSDinh Nguyen 478647a1685fSDinh Nguyen if (epnum == 0) 478747a1685fSDinh Nguyen dir = ""; 4788c6f5c050SMian Yousaf Kaukab else if (dir_in) 478947a1685fSDinh Nguyen dir = "in"; 4790c6f5c050SMian Yousaf Kaukab else 4791c6f5c050SMian Yousaf Kaukab dir = "out"; 479247a1685fSDinh Nguyen 4793c6f5c050SMian Yousaf Kaukab hs_ep->dir_in = dir_in; 479447a1685fSDinh Nguyen hs_ep->index = epnum; 479547a1685fSDinh Nguyen 479647a1685fSDinh Nguyen snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir); 479747a1685fSDinh Nguyen 479847a1685fSDinh Nguyen INIT_LIST_HEAD(&hs_ep->queue); 479947a1685fSDinh Nguyen INIT_LIST_HEAD(&hs_ep->ep.ep_list); 480047a1685fSDinh Nguyen 480147a1685fSDinh Nguyen /* add to the list of endpoints known by the gadget driver */ 480247a1685fSDinh Nguyen if (epnum) 480347a1685fSDinh Nguyen list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list); 480447a1685fSDinh Nguyen 480547a1685fSDinh Nguyen hs_ep->parent = hsotg; 480647a1685fSDinh Nguyen hs_ep->ep.name = hs_ep->name; 480738e9002bSVardan Mikayelyan 480838e9002bSVardan Mikayelyan if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW) 480938e9002bSVardan Mikayelyan usb_ep_set_maxpacket_limit(&hs_ep->ep, 8); 481038e9002bSVardan Mikayelyan else 481138e9002bSVardan Mikayelyan usb_ep_set_maxpacket_limit(&hs_ep->ep, 481238e9002bSVardan Mikayelyan epnum ? 1024 : EP0_MPS_LIMIT); 48131f91b4ccSFelipe Balbi hs_ep->ep.ops = &dwc2_hsotg_ep_ops; 481447a1685fSDinh Nguyen 48152954522fSRobert Baldyga if (epnum == 0) { 48162954522fSRobert Baldyga hs_ep->ep.caps.type_control = true; 48172954522fSRobert Baldyga } else { 481838e9002bSVardan Mikayelyan if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) { 48192954522fSRobert Baldyga hs_ep->ep.caps.type_iso = true; 48202954522fSRobert Baldyga hs_ep->ep.caps.type_bulk = true; 482138e9002bSVardan Mikayelyan } 48222954522fSRobert Baldyga hs_ep->ep.caps.type_int = true; 48232954522fSRobert Baldyga } 48242954522fSRobert Baldyga 48252954522fSRobert Baldyga if (dir_in) 48262954522fSRobert Baldyga hs_ep->ep.caps.dir_in = true; 48272954522fSRobert Baldyga else 48282954522fSRobert Baldyga hs_ep->ep.caps.dir_out = true; 48292954522fSRobert Baldyga 483047a1685fSDinh Nguyen /* 483147a1685fSDinh Nguyen * if we're using dma, we need to set the next-endpoint pointer 483247a1685fSDinh Nguyen * to be something valid. 483347a1685fSDinh Nguyen */ 483447a1685fSDinh Nguyen 483547a1685fSDinh Nguyen if (using_dma(hsotg)) { 483647a1685fSDinh Nguyen u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15); 48379da51974SJohn Youn 4838c6f5c050SMian Yousaf Kaukab if (dir_in) 4839f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, next, DIEPCTL(epnum)); 4840c6f5c050SMian Yousaf Kaukab else 4841f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, next, DOEPCTL(epnum)); 484247a1685fSDinh Nguyen } 484347a1685fSDinh Nguyen } 484447a1685fSDinh Nguyen 484547a1685fSDinh Nguyen /** 48461f91b4ccSFelipe Balbi * dwc2_hsotg_hw_cfg - read HW configuration registers 48476fb914d7SGrigor Tovmasyan * @hsotg: Programming view of the DWC_otg controller 484847a1685fSDinh Nguyen * 484947a1685fSDinh Nguyen * Read the USB core HW configuration registers 485047a1685fSDinh Nguyen */ 48511f91b4ccSFelipe Balbi static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg) 485247a1685fSDinh Nguyen { 4853c6f5c050SMian Yousaf Kaukab u32 cfg; 4854c6f5c050SMian Yousaf Kaukab u32 ep_type; 4855c6f5c050SMian Yousaf Kaukab u32 i; 4856c6f5c050SMian Yousaf Kaukab 485747a1685fSDinh Nguyen /* check hardware configuration */ 485847a1685fSDinh Nguyen 485943e90349SJohn Youn hsotg->num_of_eps = hsotg->hw_params.num_dev_ep; 486043e90349SJohn Youn 4861c6f5c050SMian Yousaf Kaukab /* Add ep0 */ 4862c6f5c050SMian Yousaf Kaukab hsotg->num_of_eps++; 486347a1685fSDinh Nguyen 4864b98866c2SJohn Youn hsotg->eps_in[0] = devm_kzalloc(hsotg->dev, 4865b98866c2SJohn Youn sizeof(struct dwc2_hsotg_ep), 4866c6f5c050SMian Yousaf Kaukab GFP_KERNEL); 4867c6f5c050SMian Yousaf Kaukab if (!hsotg->eps_in[0]) 4868c6f5c050SMian Yousaf Kaukab return -ENOMEM; 48691f91b4ccSFelipe Balbi /* Same dwc2_hsotg_ep is used in both directions for ep0 */ 4870c6f5c050SMian Yousaf Kaukab hsotg->eps_out[0] = hsotg->eps_in[0]; 487147a1685fSDinh Nguyen 487243e90349SJohn Youn cfg = hsotg->hw_params.dev_ep_dirs; 4873251a17f5SRoshan Pius for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) { 4874c6f5c050SMian Yousaf Kaukab ep_type = cfg & 3; 4875c6f5c050SMian Yousaf Kaukab /* Direction in or both */ 4876c6f5c050SMian Yousaf Kaukab if (!(ep_type & 2)) { 4877c6f5c050SMian Yousaf Kaukab hsotg->eps_in[i] = devm_kzalloc(hsotg->dev, 48781f91b4ccSFelipe Balbi sizeof(struct dwc2_hsotg_ep), GFP_KERNEL); 4879c6f5c050SMian Yousaf Kaukab if (!hsotg->eps_in[i]) 4880c6f5c050SMian Yousaf Kaukab return -ENOMEM; 4881c6f5c050SMian Yousaf Kaukab } 4882c6f5c050SMian Yousaf Kaukab /* Direction out or both */ 4883c6f5c050SMian Yousaf Kaukab if (!(ep_type & 1)) { 4884c6f5c050SMian Yousaf Kaukab hsotg->eps_out[i] = devm_kzalloc(hsotg->dev, 48851f91b4ccSFelipe Balbi sizeof(struct dwc2_hsotg_ep), GFP_KERNEL); 4886c6f5c050SMian Yousaf Kaukab if (!hsotg->eps_out[i]) 4887c6f5c050SMian Yousaf Kaukab return -ENOMEM; 4888c6f5c050SMian Yousaf Kaukab } 4889c6f5c050SMian Yousaf Kaukab } 4890c6f5c050SMian Yousaf Kaukab 489143e90349SJohn Youn hsotg->fifo_mem = hsotg->hw_params.total_fifo_size; 489243e90349SJohn Youn hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo; 489347a1685fSDinh Nguyen 4894cff9eb75SMarek Szyprowski dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n", 4895cff9eb75SMarek Szyprowski hsotg->num_of_eps, 4896cff9eb75SMarek Szyprowski hsotg->dedicated_fifos ? "dedicated" : "shared", 4897cff9eb75SMarek Szyprowski hsotg->fifo_mem); 4898c6f5c050SMian Yousaf Kaukab return 0; 489947a1685fSDinh Nguyen } 490047a1685fSDinh Nguyen 490147a1685fSDinh Nguyen /** 49021f91b4ccSFelipe Balbi * dwc2_hsotg_dump - dump state of the udc 49036fb914d7SGrigor Tovmasyan * @hsotg: Programming view of the DWC_otg controller 49046fb914d7SGrigor Tovmasyan * 490547a1685fSDinh Nguyen */ 49061f91b4ccSFelipe Balbi static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg) 490747a1685fSDinh Nguyen { 490847a1685fSDinh Nguyen #ifdef DEBUG 490947a1685fSDinh Nguyen struct device *dev = hsotg->dev; 491047a1685fSDinh Nguyen u32 val; 491147a1685fSDinh Nguyen int idx; 491247a1685fSDinh Nguyen 491347a1685fSDinh Nguyen dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n", 4914f25c42b8SGevorg Sahakyan dwc2_readl(hsotg, DCFG), dwc2_readl(hsotg, DCTL), 4915f25c42b8SGevorg Sahakyan dwc2_readl(hsotg, DIEPMSK)); 491647a1685fSDinh Nguyen 4917f889f23dSMian Yousaf Kaukab dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n", 4918f25c42b8SGevorg Sahakyan dwc2_readl(hsotg, GAHBCFG), dwc2_readl(hsotg, GHWCFG1)); 491947a1685fSDinh Nguyen 492047a1685fSDinh Nguyen dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", 4921f25c42b8SGevorg Sahakyan dwc2_readl(hsotg, GRXFSIZ), dwc2_readl(hsotg, GNPTXFSIZ)); 492247a1685fSDinh Nguyen 492347a1685fSDinh Nguyen /* show periodic fifo settings */ 492447a1685fSDinh Nguyen 4925364f8e93SMian Yousaf Kaukab for (idx = 1; idx < hsotg->num_of_eps; idx++) { 4926f25c42b8SGevorg Sahakyan val = dwc2_readl(hsotg, DPTXFSIZN(idx)); 492747a1685fSDinh Nguyen dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx, 492847a1685fSDinh Nguyen val >> FIFOSIZE_DEPTH_SHIFT, 492947a1685fSDinh Nguyen val & FIFOSIZE_STARTADDR_MASK); 493047a1685fSDinh Nguyen } 493147a1685fSDinh Nguyen 4932364f8e93SMian Yousaf Kaukab for (idx = 0; idx < hsotg->num_of_eps; idx++) { 493347a1685fSDinh Nguyen dev_info(dev, 493447a1685fSDinh Nguyen "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx, 4935f25c42b8SGevorg Sahakyan dwc2_readl(hsotg, DIEPCTL(idx)), 4936f25c42b8SGevorg Sahakyan dwc2_readl(hsotg, DIEPTSIZ(idx)), 4937f25c42b8SGevorg Sahakyan dwc2_readl(hsotg, DIEPDMA(idx))); 493847a1685fSDinh Nguyen 4939f25c42b8SGevorg Sahakyan val = dwc2_readl(hsotg, DOEPCTL(idx)); 494047a1685fSDinh Nguyen dev_info(dev, 494147a1685fSDinh Nguyen "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", 4942f25c42b8SGevorg Sahakyan idx, dwc2_readl(hsotg, DOEPCTL(idx)), 4943f25c42b8SGevorg Sahakyan dwc2_readl(hsotg, DOEPTSIZ(idx)), 4944f25c42b8SGevorg Sahakyan dwc2_readl(hsotg, DOEPDMA(idx))); 494547a1685fSDinh Nguyen } 494647a1685fSDinh Nguyen 494747a1685fSDinh Nguyen dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n", 4948f25c42b8SGevorg Sahakyan dwc2_readl(hsotg, DVBUSDIS), dwc2_readl(hsotg, DVBUSPULSE)); 494947a1685fSDinh Nguyen #endif 495047a1685fSDinh Nguyen } 495147a1685fSDinh Nguyen 495247a1685fSDinh Nguyen /** 4953117777b2SDinh Nguyen * dwc2_gadget_init - init function for gadget 49546fb914d7SGrigor Tovmasyan * @hsotg: Programming view of the DWC_otg controller 49556fb914d7SGrigor Tovmasyan * 495647a1685fSDinh Nguyen */ 4957f3768997SVardan Mikayelyan int dwc2_gadget_init(struct dwc2_hsotg *hsotg) 495847a1685fSDinh Nguyen { 4959117777b2SDinh Nguyen struct device *dev = hsotg->dev; 496047a1685fSDinh Nguyen int epnum; 496147a1685fSDinh Nguyen int ret; 496243e90349SJohn Youn 49630a176279SGregory Herrero /* Dump fifo information */ 49640a176279SGregory Herrero dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n", 496505ee799fSJohn Youn hsotg->params.g_np_tx_fifo_size); 496605ee799fSJohn Youn dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size); 496747a1685fSDinh Nguyen 496847a1685fSDinh Nguyen hsotg->gadget.max_speed = USB_SPEED_HIGH; 49691f91b4ccSFelipe Balbi hsotg->gadget.ops = &dwc2_hsotg_gadget_ops; 497047a1685fSDinh Nguyen hsotg->gadget.name = dev_name(dev); 4971fa389a6dSVardan Mikayelyan hsotg->remote_wakeup_allowed = 0; 49727455f8b7SJohn Youn 49737455f8b7SJohn Youn if (hsotg->params.lpm) 49747455f8b7SJohn Youn hsotg->gadget.lpm_capable = true; 49757455f8b7SJohn Youn 4976097ee662SGregory Herrero if (hsotg->dr_mode == USB_DR_MODE_OTG) 4977097ee662SGregory Herrero hsotg->gadget.is_otg = 1; 4978ec4cc657SMian Yousaf Kaukab else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) 4979ec4cc657SMian Yousaf Kaukab hsotg->op_state = OTG_STATE_B_PERIPHERAL; 498047a1685fSDinh Nguyen 49811f91b4ccSFelipe Balbi ret = dwc2_hsotg_hw_cfg(hsotg); 4982c6f5c050SMian Yousaf Kaukab if (ret) { 4983c6f5c050SMian Yousaf Kaukab dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret); 498409a75e85SMarek Szyprowski return ret; 4985c6f5c050SMian Yousaf Kaukab } 4986c6f5c050SMian Yousaf Kaukab 49873f95001dSMian Yousaf Kaukab hsotg->ctrl_buff = devm_kzalloc(hsotg->dev, 49883f95001dSMian Yousaf Kaukab DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); 49898bae0f8cSWolfram Sang if (!hsotg->ctrl_buff) 499009a75e85SMarek Szyprowski return -ENOMEM; 49913f95001dSMian Yousaf Kaukab 49923f95001dSMian Yousaf Kaukab hsotg->ep0_buff = devm_kzalloc(hsotg->dev, 49933f95001dSMian Yousaf Kaukab DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); 49948bae0f8cSWolfram Sang if (!hsotg->ep0_buff) 499509a75e85SMarek Szyprowski return -ENOMEM; 49963f95001dSMian Yousaf Kaukab 49970f6b80c0SVahram Aharonyan if (using_desc_dma(hsotg)) { 49980f6b80c0SVahram Aharonyan ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg); 49990f6b80c0SVahram Aharonyan if (ret < 0) 50000f6b80c0SVahram Aharonyan return ret; 50010f6b80c0SVahram Aharonyan } 50020f6b80c0SVahram Aharonyan 5003f3768997SVardan Mikayelyan ret = devm_request_irq(hsotg->dev, hsotg->irq, dwc2_hsotg_irq, 5004f3768997SVardan Mikayelyan IRQF_SHARED, dev_name(hsotg->dev), hsotg); 5005eb3c56c5SMarek Szyprowski if (ret < 0) { 5006db8178c3SDinh Nguyen dev_err(dev, "cannot claim IRQ for gadget\n"); 500709a75e85SMarek Szyprowski return ret; 5008eb3c56c5SMarek Szyprowski } 5009eb3c56c5SMarek Szyprowski 501047a1685fSDinh Nguyen /* hsotg->num_of_eps holds number of EPs other than ep0 */ 501147a1685fSDinh Nguyen 501247a1685fSDinh Nguyen if (hsotg->num_of_eps == 0) { 501347a1685fSDinh Nguyen dev_err(dev, "wrong number of EPs (zero)\n"); 501409a75e85SMarek Szyprowski return -EINVAL; 501547a1685fSDinh Nguyen } 501647a1685fSDinh Nguyen 501747a1685fSDinh Nguyen /* setup endpoint information */ 501847a1685fSDinh Nguyen 501947a1685fSDinh Nguyen INIT_LIST_HEAD(&hsotg->gadget.ep_list); 5020c6f5c050SMian Yousaf Kaukab hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep; 502147a1685fSDinh Nguyen 502247a1685fSDinh Nguyen /* allocate EP0 request */ 502347a1685fSDinh Nguyen 50241f91b4ccSFelipe Balbi hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep, 502547a1685fSDinh Nguyen GFP_KERNEL); 502647a1685fSDinh Nguyen if (!hsotg->ctrl_req) { 502747a1685fSDinh Nguyen dev_err(dev, "failed to allocate ctrl req\n"); 502809a75e85SMarek Szyprowski return -ENOMEM; 502947a1685fSDinh Nguyen } 503047a1685fSDinh Nguyen 503147a1685fSDinh Nguyen /* initialise the endpoints now the core has been initialised */ 5032c6f5c050SMian Yousaf Kaukab for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) { 5033c6f5c050SMian Yousaf Kaukab if (hsotg->eps_in[epnum]) 50341f91b4ccSFelipe Balbi dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum], 5035c6f5c050SMian Yousaf Kaukab epnum, 1); 5036c6f5c050SMian Yousaf Kaukab if (hsotg->eps_out[epnum]) 50371f91b4ccSFelipe Balbi dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum], 5038c6f5c050SMian Yousaf Kaukab epnum, 0); 5039c6f5c050SMian Yousaf Kaukab } 504047a1685fSDinh Nguyen 50411f91b4ccSFelipe Balbi dwc2_hsotg_dump(hsotg); 504247a1685fSDinh Nguyen 504347a1685fSDinh Nguyen return 0; 504447a1685fSDinh Nguyen } 504547a1685fSDinh Nguyen 504647a1685fSDinh Nguyen /** 50471f91b4ccSFelipe Balbi * dwc2_hsotg_remove - remove function for hsotg driver 50486fb914d7SGrigor Tovmasyan * @hsotg: Programming view of the DWC_otg controller 50496fb914d7SGrigor Tovmasyan * 505047a1685fSDinh Nguyen */ 50511f91b4ccSFelipe Balbi int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg) 505247a1685fSDinh Nguyen { 505347a1685fSDinh Nguyen usb_del_gadget_udc(&hsotg->gadget); 50549bb073a0SGrigor Tovmasyan dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep, hsotg->ctrl_req); 505547a1685fSDinh Nguyen 505647a1685fSDinh Nguyen return 0; 505747a1685fSDinh Nguyen } 505847a1685fSDinh Nguyen 50591f91b4ccSFelipe Balbi int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg) 506047a1685fSDinh Nguyen { 506147a1685fSDinh Nguyen unsigned long flags; 506247a1685fSDinh Nguyen 50639e779778SGregory Herrero if (hsotg->lx_state != DWC2_L0) 506409a75e85SMarek Szyprowski return 0; 50659e779778SGregory Herrero 5066dc6e69e6SMarek Szyprowski if (hsotg->driver) { 5067dc6e69e6SMarek Szyprowski int ep; 5068dc6e69e6SMarek Szyprowski 506947a1685fSDinh Nguyen dev_info(hsotg->dev, "suspending usb gadget %s\n", 507047a1685fSDinh Nguyen hsotg->driver->driver.name); 507147a1685fSDinh Nguyen 507247a1685fSDinh Nguyen spin_lock_irqsave(&hsotg->lock, flags); 5073dc6e69e6SMarek Szyprowski if (hsotg->enabled) 50741f91b4ccSFelipe Balbi dwc2_hsotg_core_disconnect(hsotg); 50751f91b4ccSFelipe Balbi dwc2_hsotg_disconnect(hsotg); 507647a1685fSDinh Nguyen hsotg->gadget.speed = USB_SPEED_UNKNOWN; 507747a1685fSDinh Nguyen spin_unlock_irqrestore(&hsotg->lock, flags); 507847a1685fSDinh Nguyen 5079c6f5c050SMian Yousaf Kaukab for (ep = 0; ep < hsotg->num_of_eps; ep++) { 5080c6f5c050SMian Yousaf Kaukab if (hsotg->eps_in[ep]) 50814fe4f9feSMinas Harutyunyan dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep); 5082c6f5c050SMian Yousaf Kaukab if (hsotg->eps_out[ep]) 50834fe4f9feSMinas Harutyunyan dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep); 5084c6f5c050SMian Yousaf Kaukab } 508547a1685fSDinh Nguyen } 508647a1685fSDinh Nguyen 508709a75e85SMarek Szyprowski return 0; 508847a1685fSDinh Nguyen } 508947a1685fSDinh Nguyen 50901f91b4ccSFelipe Balbi int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg) 509147a1685fSDinh Nguyen { 509247a1685fSDinh Nguyen unsigned long flags; 509347a1685fSDinh Nguyen 50949e779778SGregory Herrero if (hsotg->lx_state == DWC2_L2) 509509a75e85SMarek Szyprowski return 0; 50969e779778SGregory Herrero 509747a1685fSDinh Nguyen if (hsotg->driver) { 509847a1685fSDinh Nguyen dev_info(hsotg->dev, "resuming usb gadget %s\n", 509947a1685fSDinh Nguyen hsotg->driver->driver.name); 5100d00b4142SRobert Baldyga 510147a1685fSDinh Nguyen spin_lock_irqsave(&hsotg->lock, flags); 51021f91b4ccSFelipe Balbi dwc2_hsotg_core_init_disconnected(hsotg, false); 510366e77a24SRazmik Karapetyan if (hsotg->enabled) { 510466e77a24SRazmik Karapetyan /* Enable ACG feature in device mode,if supported */ 510566e77a24SRazmik Karapetyan dwc2_enable_acg(hsotg); 51061f91b4ccSFelipe Balbi dwc2_hsotg_core_connect(hsotg); 510766e77a24SRazmik Karapetyan } 510847a1685fSDinh Nguyen spin_unlock_irqrestore(&hsotg->lock, flags); 5109dc6e69e6SMarek Szyprowski } 511047a1685fSDinh Nguyen 511109a75e85SMarek Szyprowski return 0; 511247a1685fSDinh Nguyen } 511358e52ff6SJohn Youn 511458e52ff6SJohn Youn /** 511558e52ff6SJohn Youn * dwc2_backup_device_registers() - Backup controller device registers. 511658e52ff6SJohn Youn * When suspending usb bus, registers needs to be backuped 511758e52ff6SJohn Youn * if controller power is disabled once suspended. 511858e52ff6SJohn Youn * 511958e52ff6SJohn Youn * @hsotg: Programming view of the DWC_otg controller 512058e52ff6SJohn Youn */ 512158e52ff6SJohn Youn int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) 512258e52ff6SJohn Youn { 512358e52ff6SJohn Youn struct dwc2_dregs_backup *dr; 512458e52ff6SJohn Youn int i; 512558e52ff6SJohn Youn 512658e52ff6SJohn Youn dev_dbg(hsotg->dev, "%s\n", __func__); 512758e52ff6SJohn Youn 512858e52ff6SJohn Youn /* Backup dev regs */ 512958e52ff6SJohn Youn dr = &hsotg->dr_backup; 513058e52ff6SJohn Youn 5131f25c42b8SGevorg Sahakyan dr->dcfg = dwc2_readl(hsotg, DCFG); 5132f25c42b8SGevorg Sahakyan dr->dctl = dwc2_readl(hsotg, DCTL); 5133f25c42b8SGevorg Sahakyan dr->daintmsk = dwc2_readl(hsotg, DAINTMSK); 5134f25c42b8SGevorg Sahakyan dr->diepmsk = dwc2_readl(hsotg, DIEPMSK); 5135f25c42b8SGevorg Sahakyan dr->doepmsk = dwc2_readl(hsotg, DOEPMSK); 513658e52ff6SJohn Youn 513758e52ff6SJohn Youn for (i = 0; i < hsotg->num_of_eps; i++) { 513858e52ff6SJohn Youn /* Backup IN EPs */ 5139f25c42b8SGevorg Sahakyan dr->diepctl[i] = dwc2_readl(hsotg, DIEPCTL(i)); 514058e52ff6SJohn Youn 514158e52ff6SJohn Youn /* Ensure DATA PID is correctly configured */ 514258e52ff6SJohn Youn if (dr->diepctl[i] & DXEPCTL_DPID) 514358e52ff6SJohn Youn dr->diepctl[i] |= DXEPCTL_SETD1PID; 514458e52ff6SJohn Youn else 514558e52ff6SJohn Youn dr->diepctl[i] |= DXEPCTL_SETD0PID; 514658e52ff6SJohn Youn 5147f25c42b8SGevorg Sahakyan dr->dieptsiz[i] = dwc2_readl(hsotg, DIEPTSIZ(i)); 5148f25c42b8SGevorg Sahakyan dr->diepdma[i] = dwc2_readl(hsotg, DIEPDMA(i)); 514958e52ff6SJohn Youn 515058e52ff6SJohn Youn /* Backup OUT EPs */ 5151f25c42b8SGevorg Sahakyan dr->doepctl[i] = dwc2_readl(hsotg, DOEPCTL(i)); 515258e52ff6SJohn Youn 515358e52ff6SJohn Youn /* Ensure DATA PID is correctly configured */ 515458e52ff6SJohn Youn if (dr->doepctl[i] & DXEPCTL_DPID) 515558e52ff6SJohn Youn dr->doepctl[i] |= DXEPCTL_SETD1PID; 515658e52ff6SJohn Youn else 515758e52ff6SJohn Youn dr->doepctl[i] |= DXEPCTL_SETD0PID; 515858e52ff6SJohn Youn 5159f25c42b8SGevorg Sahakyan dr->doeptsiz[i] = dwc2_readl(hsotg, DOEPTSIZ(i)); 5160f25c42b8SGevorg Sahakyan dr->doepdma[i] = dwc2_readl(hsotg, DOEPDMA(i)); 5161f25c42b8SGevorg Sahakyan dr->dtxfsiz[i] = dwc2_readl(hsotg, DPTXFSIZN(i)); 516258e52ff6SJohn Youn } 516358e52ff6SJohn Youn dr->valid = true; 516458e52ff6SJohn Youn return 0; 516558e52ff6SJohn Youn } 516658e52ff6SJohn Youn 516758e52ff6SJohn Youn /** 516858e52ff6SJohn Youn * dwc2_restore_device_registers() - Restore controller device registers. 516958e52ff6SJohn Youn * When resuming usb bus, device registers needs to be restored 517058e52ff6SJohn Youn * if controller power were disabled. 517158e52ff6SJohn Youn * 517258e52ff6SJohn Youn * @hsotg: Programming view of the DWC_otg controller 51739a5d2816SVardan Mikayelyan * @remote_wakeup: Indicates whether resume is initiated by Device or Host. 51749a5d2816SVardan Mikayelyan * 51759a5d2816SVardan Mikayelyan * Return: 0 if successful, negative error code otherwise 517658e52ff6SJohn Youn */ 51779a5d2816SVardan Mikayelyan int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup) 517858e52ff6SJohn Youn { 517958e52ff6SJohn Youn struct dwc2_dregs_backup *dr; 518058e52ff6SJohn Youn int i; 518158e52ff6SJohn Youn 518258e52ff6SJohn Youn dev_dbg(hsotg->dev, "%s\n", __func__); 518358e52ff6SJohn Youn 518458e52ff6SJohn Youn /* Restore dev regs */ 518558e52ff6SJohn Youn dr = &hsotg->dr_backup; 518658e52ff6SJohn Youn if (!dr->valid) { 518758e52ff6SJohn Youn dev_err(hsotg->dev, "%s: no device registers to restore\n", 518858e52ff6SJohn Youn __func__); 518958e52ff6SJohn Youn return -EINVAL; 519058e52ff6SJohn Youn } 519158e52ff6SJohn Youn dr->valid = false; 519258e52ff6SJohn Youn 51939a5d2816SVardan Mikayelyan if (!remote_wakeup) 5194f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, dr->dctl, DCTL); 51959a5d2816SVardan Mikayelyan 5196f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, dr->daintmsk, DAINTMSK); 5197f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, dr->diepmsk, DIEPMSK); 5198f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, dr->doepmsk, DOEPMSK); 519958e52ff6SJohn Youn 520058e52ff6SJohn Youn for (i = 0; i < hsotg->num_of_eps; i++) { 520158e52ff6SJohn Youn /* Restore IN EPs */ 5202f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, dr->dieptsiz[i], DIEPTSIZ(i)); 5203f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, dr->diepdma[i], DIEPDMA(i)); 5204f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i)); 52059a5d2816SVardan Mikayelyan /** WA for enabled EPx's IN in DDMA mode. On entering to 52069a5d2816SVardan Mikayelyan * hibernation wrong value read and saved from DIEPDMAx, 52079a5d2816SVardan Mikayelyan * as result BNA interrupt asserted on hibernation exit 52089a5d2816SVardan Mikayelyan * by restoring from saved area. 52099a5d2816SVardan Mikayelyan */ 52109a5d2816SVardan Mikayelyan if (hsotg->params.g_dma_desc && 52119a5d2816SVardan Mikayelyan (dr->diepctl[i] & DXEPCTL_EPENA)) 52129a5d2816SVardan Mikayelyan dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma; 5213f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, dr->dtxfsiz[i], DPTXFSIZN(i)); 5214f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, dr->diepctl[i], DIEPCTL(i)); 52159a5d2816SVardan Mikayelyan /* Restore OUT EPs */ 5216f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i)); 52179a5d2816SVardan Mikayelyan /* WA for enabled EPx's OUT in DDMA mode. On entering to 52189a5d2816SVardan Mikayelyan * hibernation wrong value read and saved from DOEPDMAx, 52199a5d2816SVardan Mikayelyan * as result BNA interrupt asserted on hibernation exit 52209a5d2816SVardan Mikayelyan * by restoring from saved area. 52219a5d2816SVardan Mikayelyan */ 52229a5d2816SVardan Mikayelyan if (hsotg->params.g_dma_desc && 52239a5d2816SVardan Mikayelyan (dr->doepctl[i] & DXEPCTL_EPENA)) 52249a5d2816SVardan Mikayelyan dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma; 5225f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, dr->doepdma[i], DOEPDMA(i)); 5226f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, dr->doepctl[i], DOEPCTL(i)); 522758e52ff6SJohn Youn } 522858e52ff6SJohn Youn 522958e52ff6SJohn Youn return 0; 523058e52ff6SJohn Youn } 523121b03405SSevak Arakelyan 523221b03405SSevak Arakelyan /** 523321b03405SSevak Arakelyan * dwc2_gadget_init_lpm - Configure the core to support LPM in device mode 523421b03405SSevak Arakelyan * 523521b03405SSevak Arakelyan * @hsotg: Programming view of DWC_otg controller 523621b03405SSevak Arakelyan * 523721b03405SSevak Arakelyan */ 523821b03405SSevak Arakelyan void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) 523921b03405SSevak Arakelyan { 524021b03405SSevak Arakelyan u32 val; 524121b03405SSevak Arakelyan 524221b03405SSevak Arakelyan if (!hsotg->params.lpm) 524321b03405SSevak Arakelyan return; 524421b03405SSevak Arakelyan 524521b03405SSevak Arakelyan val = GLPMCFG_LPMCAP | GLPMCFG_APPL1RES; 524621b03405SSevak Arakelyan val |= hsotg->params.hird_threshold_en ? GLPMCFG_HIRD_THRES_EN : 0; 524721b03405SSevak Arakelyan val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0; 524821b03405SSevak Arakelyan val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT; 524921b03405SSevak Arakelyan val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0; 525046637565SMinas Harutyunyan val |= GLPMCFG_LPM_REJECT_CTRL_CONTROL; 52519aed8c08SArtur Petrosyan val |= GLPMCFG_LPM_ACCEPT_CTRL_ISOC; 5252f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, val, GLPMCFG); 5253f25c42b8SGevorg Sahakyan dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg, GLPMCFG)); 52544abe4537SGrigor Tovmasyan 52554abe4537SGrigor Tovmasyan /* Unmask WKUP_ALERT Interrupt */ 52564abe4537SGrigor Tovmasyan if (hsotg->params.service_interval) 52574abe4537SGrigor Tovmasyan dwc2_set_bit(hsotg, GINTMSK2, GINTMSK2_WKUP_ALERT_INT_MSK); 525821b03405SSevak Arakelyan } 5259c5c403dcSVardan Mikayelyan 5260c5c403dcSVardan Mikayelyan /** 526115d9dbf8SGrigor Tovmasyan * dwc2_gadget_program_ref_clk - Program GREFCLK register in device mode 526215d9dbf8SGrigor Tovmasyan * 526315d9dbf8SGrigor Tovmasyan * @hsotg: Programming view of DWC_otg controller 526415d9dbf8SGrigor Tovmasyan * 526515d9dbf8SGrigor Tovmasyan */ 526615d9dbf8SGrigor Tovmasyan void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg) 526715d9dbf8SGrigor Tovmasyan { 526815d9dbf8SGrigor Tovmasyan u32 val = 0; 526915d9dbf8SGrigor Tovmasyan 527015d9dbf8SGrigor Tovmasyan val |= GREFCLK_REF_CLK_MODE; 527115d9dbf8SGrigor Tovmasyan val |= hsotg->params.ref_clk_per << GREFCLK_REFCLKPER_SHIFT; 527215d9dbf8SGrigor Tovmasyan val |= hsotg->params.sof_cnt_wkup_alert << 527315d9dbf8SGrigor Tovmasyan GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT; 527415d9dbf8SGrigor Tovmasyan 527515d9dbf8SGrigor Tovmasyan dwc2_writel(hsotg, val, GREFCLK); 527615d9dbf8SGrigor Tovmasyan dev_dbg(hsotg->dev, "GREFCLK=0x%08x\n", dwc2_readl(hsotg, GREFCLK)); 527715d9dbf8SGrigor Tovmasyan } 527815d9dbf8SGrigor Tovmasyan 527915d9dbf8SGrigor Tovmasyan /** 5280c5c403dcSVardan Mikayelyan * dwc2_gadget_enter_hibernation() - Put controller in Hibernation. 5281c5c403dcSVardan Mikayelyan * 5282c5c403dcSVardan Mikayelyan * @hsotg: Programming view of the DWC_otg controller 5283c5c403dcSVardan Mikayelyan * 5284c5c403dcSVardan Mikayelyan * Return non-zero if failed to enter to hibernation. 5285c5c403dcSVardan Mikayelyan */ 5286c5c403dcSVardan Mikayelyan int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg) 5287c5c403dcSVardan Mikayelyan { 5288c5c403dcSVardan Mikayelyan u32 gpwrdn; 5289c5c403dcSVardan Mikayelyan int ret = 0; 5290c5c403dcSVardan Mikayelyan 5291c5c403dcSVardan Mikayelyan /* Change to L2(suspend) state */ 5292c5c403dcSVardan Mikayelyan hsotg->lx_state = DWC2_L2; 5293c5c403dcSVardan Mikayelyan dev_dbg(hsotg->dev, "Start of hibernation completed\n"); 5294c5c403dcSVardan Mikayelyan ret = dwc2_backup_global_registers(hsotg); 5295c5c403dcSVardan Mikayelyan if (ret) { 5296c5c403dcSVardan Mikayelyan dev_err(hsotg->dev, "%s: failed to backup global registers\n", 5297c5c403dcSVardan Mikayelyan __func__); 5298c5c403dcSVardan Mikayelyan return ret; 5299c5c403dcSVardan Mikayelyan } 5300c5c403dcSVardan Mikayelyan ret = dwc2_backup_device_registers(hsotg); 5301c5c403dcSVardan Mikayelyan if (ret) { 5302c5c403dcSVardan Mikayelyan dev_err(hsotg->dev, "%s: failed to backup device registers\n", 5303c5c403dcSVardan Mikayelyan __func__); 5304c5c403dcSVardan Mikayelyan return ret; 5305c5c403dcSVardan Mikayelyan } 5306c5c403dcSVardan Mikayelyan 5307c5c403dcSVardan Mikayelyan gpwrdn = GPWRDN_PWRDNRSTN; 5308c5c403dcSVardan Mikayelyan gpwrdn |= GPWRDN_PMUACTV; 5309f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, gpwrdn, GPWRDN); 5310c5c403dcSVardan Mikayelyan udelay(10); 5311c5c403dcSVardan Mikayelyan 5312c5c403dcSVardan Mikayelyan /* Set flag to indicate that we are in hibernation */ 5313c5c403dcSVardan Mikayelyan hsotg->hibernated = 1; 5314c5c403dcSVardan Mikayelyan 5315c5c403dcSVardan Mikayelyan /* Enable interrupts from wake up logic */ 5316f25c42b8SGevorg Sahakyan gpwrdn = dwc2_readl(hsotg, GPWRDN); 5317c5c403dcSVardan Mikayelyan gpwrdn |= GPWRDN_PMUINTSEL; 5318f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, gpwrdn, GPWRDN); 5319c5c403dcSVardan Mikayelyan udelay(10); 5320c5c403dcSVardan Mikayelyan 5321c5c403dcSVardan Mikayelyan /* Unmask device mode interrupts in GPWRDN */ 5322f25c42b8SGevorg Sahakyan gpwrdn = dwc2_readl(hsotg, GPWRDN); 5323c5c403dcSVardan Mikayelyan gpwrdn |= GPWRDN_RST_DET_MSK; 5324c5c403dcSVardan Mikayelyan gpwrdn |= GPWRDN_LNSTSCHG_MSK; 5325c5c403dcSVardan Mikayelyan gpwrdn |= GPWRDN_STS_CHGINT_MSK; 5326f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, gpwrdn, GPWRDN); 5327c5c403dcSVardan Mikayelyan udelay(10); 5328c5c403dcSVardan Mikayelyan 5329c5c403dcSVardan Mikayelyan /* Enable Power Down Clamp */ 5330f25c42b8SGevorg Sahakyan gpwrdn = dwc2_readl(hsotg, GPWRDN); 5331c5c403dcSVardan Mikayelyan gpwrdn |= GPWRDN_PWRDNCLMP; 5332f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, gpwrdn, GPWRDN); 5333c5c403dcSVardan Mikayelyan udelay(10); 5334c5c403dcSVardan Mikayelyan 5335c5c403dcSVardan Mikayelyan /* Switch off VDD */ 5336f25c42b8SGevorg Sahakyan gpwrdn = dwc2_readl(hsotg, GPWRDN); 5337c5c403dcSVardan Mikayelyan gpwrdn |= GPWRDN_PWRDNSWTCH; 5338f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, gpwrdn, GPWRDN); 5339c5c403dcSVardan Mikayelyan udelay(10); 5340c5c403dcSVardan Mikayelyan 5341c5c403dcSVardan Mikayelyan /* Save gpwrdn register for further usage if stschng interrupt */ 5342f25c42b8SGevorg Sahakyan hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg, GPWRDN); 5343c5c403dcSVardan Mikayelyan dev_dbg(hsotg->dev, "Hibernation completed\n"); 5344c5c403dcSVardan Mikayelyan 5345c5c403dcSVardan Mikayelyan return ret; 5346c5c403dcSVardan Mikayelyan } 5347c5c403dcSVardan Mikayelyan 5348c5c403dcSVardan Mikayelyan /** 5349c5c403dcSVardan Mikayelyan * dwc2_gadget_exit_hibernation() 5350c5c403dcSVardan Mikayelyan * This function is for exiting from Device mode hibernation by host initiated 5351c5c403dcSVardan Mikayelyan * resume/reset and device initiated remote-wakeup. 5352c5c403dcSVardan Mikayelyan * 5353c5c403dcSVardan Mikayelyan * @hsotg: Programming view of the DWC_otg controller 5354c5c403dcSVardan Mikayelyan * @rem_wakeup: indicates whether resume is initiated by Device or Host. 53556fb914d7SGrigor Tovmasyan * @reset: indicates whether resume is initiated by Reset. 5356c5c403dcSVardan Mikayelyan * 5357c5c403dcSVardan Mikayelyan * Return non-zero if failed to exit from hibernation. 5358c5c403dcSVardan Mikayelyan */ 5359c5c403dcSVardan Mikayelyan int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg, 5360c5c403dcSVardan Mikayelyan int rem_wakeup, int reset) 5361c5c403dcSVardan Mikayelyan { 5362c5c403dcSVardan Mikayelyan u32 pcgcctl; 5363c5c403dcSVardan Mikayelyan u32 gpwrdn; 5364c5c403dcSVardan Mikayelyan u32 dctl; 5365c5c403dcSVardan Mikayelyan int ret = 0; 5366c5c403dcSVardan Mikayelyan struct dwc2_gregs_backup *gr; 5367c5c403dcSVardan Mikayelyan struct dwc2_dregs_backup *dr; 5368c5c403dcSVardan Mikayelyan 5369c5c403dcSVardan Mikayelyan gr = &hsotg->gr_backup; 5370c5c403dcSVardan Mikayelyan dr = &hsotg->dr_backup; 5371c5c403dcSVardan Mikayelyan 5372c5c403dcSVardan Mikayelyan if (!hsotg->hibernated) { 5373c5c403dcSVardan Mikayelyan dev_dbg(hsotg->dev, "Already exited from Hibernation\n"); 5374c5c403dcSVardan Mikayelyan return 1; 5375c5c403dcSVardan Mikayelyan } 5376c5c403dcSVardan Mikayelyan dev_dbg(hsotg->dev, 5377c5c403dcSVardan Mikayelyan "%s: called with rem_wakeup = %d reset = %d\n", 5378c5c403dcSVardan Mikayelyan __func__, rem_wakeup, reset); 5379c5c403dcSVardan Mikayelyan 5380c5c403dcSVardan Mikayelyan dwc2_hib_restore_common(hsotg, rem_wakeup, 0); 5381c5c403dcSVardan Mikayelyan 5382c5c403dcSVardan Mikayelyan if (!reset) { 5383c5c403dcSVardan Mikayelyan /* Clear all pending interupts */ 5384f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, 0xffffffff, GINTSTS); 5385c5c403dcSVardan Mikayelyan } 5386c5c403dcSVardan Mikayelyan 5387c5c403dcSVardan Mikayelyan /* De-assert Restore */ 5388f25c42b8SGevorg Sahakyan gpwrdn = dwc2_readl(hsotg, GPWRDN); 5389c5c403dcSVardan Mikayelyan gpwrdn &= ~GPWRDN_RESTORE; 5390f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, gpwrdn, GPWRDN); 5391c5c403dcSVardan Mikayelyan udelay(10); 5392c5c403dcSVardan Mikayelyan 5393c5c403dcSVardan Mikayelyan if (!rem_wakeup) { 5394f25c42b8SGevorg Sahakyan pcgcctl = dwc2_readl(hsotg, PCGCTL); 5395c5c403dcSVardan Mikayelyan pcgcctl &= ~PCGCTL_RSTPDWNMODULE; 5396f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, pcgcctl, PCGCTL); 5397c5c403dcSVardan Mikayelyan } 5398c5c403dcSVardan Mikayelyan 5399c5c403dcSVardan Mikayelyan /* Restore GUSBCFG, DCFG and DCTL */ 5400f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG); 5401f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, dr->dcfg, DCFG); 5402f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, dr->dctl, DCTL); 5403c5c403dcSVardan Mikayelyan 5404b29b494bSArtur Petrosyan /* On USB Reset, reset device address to zero */ 5405b29b494bSArtur Petrosyan if (reset) 5406b29b494bSArtur Petrosyan dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK); 5407b29b494bSArtur Petrosyan 5408c5c403dcSVardan Mikayelyan /* De-assert Wakeup Logic */ 5409f25c42b8SGevorg Sahakyan gpwrdn = dwc2_readl(hsotg, GPWRDN); 5410c5c403dcSVardan Mikayelyan gpwrdn &= ~GPWRDN_PMUACTV; 5411f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, gpwrdn, GPWRDN); 5412c5c403dcSVardan Mikayelyan 5413c5c403dcSVardan Mikayelyan if (rem_wakeup) { 5414c5c403dcSVardan Mikayelyan udelay(10); 5415c5c403dcSVardan Mikayelyan /* Start Remote Wakeup Signaling */ 5416f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, dr->dctl | DCTL_RMTWKUPSIG, DCTL); 5417c5c403dcSVardan Mikayelyan } else { 5418c5c403dcSVardan Mikayelyan udelay(50); 5419c5c403dcSVardan Mikayelyan /* Set Device programming done bit */ 5420f25c42b8SGevorg Sahakyan dctl = dwc2_readl(hsotg, DCTL); 5421c5c403dcSVardan Mikayelyan dctl |= DCTL_PWRONPRGDONE; 5422f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, dctl, DCTL); 5423c5c403dcSVardan Mikayelyan } 5424c5c403dcSVardan Mikayelyan /* Wait for interrupts which must be cleared */ 5425c5c403dcSVardan Mikayelyan mdelay(2); 5426c5c403dcSVardan Mikayelyan /* Clear all pending interupts */ 5427f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, 0xffffffff, GINTSTS); 5428c5c403dcSVardan Mikayelyan 5429c5c403dcSVardan Mikayelyan /* Restore global registers */ 5430c5c403dcSVardan Mikayelyan ret = dwc2_restore_global_registers(hsotg); 5431c5c403dcSVardan Mikayelyan if (ret) { 5432c5c403dcSVardan Mikayelyan dev_err(hsotg->dev, "%s: failed to restore registers\n", 5433c5c403dcSVardan Mikayelyan __func__); 5434c5c403dcSVardan Mikayelyan return ret; 5435c5c403dcSVardan Mikayelyan } 5436c5c403dcSVardan Mikayelyan 5437c5c403dcSVardan Mikayelyan /* Restore device registers */ 5438c5c403dcSVardan Mikayelyan ret = dwc2_restore_device_registers(hsotg, rem_wakeup); 5439c5c403dcSVardan Mikayelyan if (ret) { 5440c5c403dcSVardan Mikayelyan dev_err(hsotg->dev, "%s: failed to restore device registers\n", 5441c5c403dcSVardan Mikayelyan __func__); 5442c5c403dcSVardan Mikayelyan return ret; 5443c5c403dcSVardan Mikayelyan } 5444c5c403dcSVardan Mikayelyan 5445c5c403dcSVardan Mikayelyan if (rem_wakeup) { 5446c5c403dcSVardan Mikayelyan mdelay(10); 5447f25c42b8SGevorg Sahakyan dctl = dwc2_readl(hsotg, DCTL); 5448c5c403dcSVardan Mikayelyan dctl &= ~DCTL_RMTWKUPSIG; 5449f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, dctl, DCTL); 5450c5c403dcSVardan Mikayelyan } 5451c5c403dcSVardan Mikayelyan 5452c5c403dcSVardan Mikayelyan hsotg->hibernated = 0; 5453c5c403dcSVardan Mikayelyan hsotg->lx_state = DWC2_L0; 5454c5c403dcSVardan Mikayelyan dev_dbg(hsotg->dev, "Hibernation recovery completes here\n"); 5455c5c403dcSVardan Mikayelyan 5456c5c403dcSVardan Mikayelyan return ret; 5457c5c403dcSVardan Mikayelyan } 5458be2b960eSArtur Petrosyan 5459be2b960eSArtur Petrosyan /** 5460be2b960eSArtur Petrosyan * dwc2_gadget_enter_partial_power_down() - Put controller in partial 5461be2b960eSArtur Petrosyan * power down. 5462be2b960eSArtur Petrosyan * 5463be2b960eSArtur Petrosyan * @hsotg: Programming view of the DWC_otg controller 5464be2b960eSArtur Petrosyan * 5465be2b960eSArtur Petrosyan * Return: non-zero if failed to enter device partial power down. 5466be2b960eSArtur Petrosyan * 5467be2b960eSArtur Petrosyan * This function is for entering device mode partial power down. 5468be2b960eSArtur Petrosyan */ 5469be2b960eSArtur Petrosyan int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg) 5470be2b960eSArtur Petrosyan { 5471be2b960eSArtur Petrosyan u32 pcgcctl; 5472be2b960eSArtur Petrosyan int ret = 0; 5473be2b960eSArtur Petrosyan 5474be2b960eSArtur Petrosyan dev_dbg(hsotg->dev, "Entering device partial power down started.\n"); 5475be2b960eSArtur Petrosyan 5476be2b960eSArtur Petrosyan /* Backup all registers */ 5477be2b960eSArtur Petrosyan ret = dwc2_backup_global_registers(hsotg); 5478be2b960eSArtur Petrosyan if (ret) { 5479be2b960eSArtur Petrosyan dev_err(hsotg->dev, "%s: failed to backup global registers\n", 5480be2b960eSArtur Petrosyan __func__); 5481be2b960eSArtur Petrosyan return ret; 5482be2b960eSArtur Petrosyan } 5483be2b960eSArtur Petrosyan 5484be2b960eSArtur Petrosyan ret = dwc2_backup_device_registers(hsotg); 5485be2b960eSArtur Petrosyan if (ret) { 5486be2b960eSArtur Petrosyan dev_err(hsotg->dev, "%s: failed to backup device registers\n", 5487be2b960eSArtur Petrosyan __func__); 5488be2b960eSArtur Petrosyan return ret; 5489be2b960eSArtur Petrosyan } 5490be2b960eSArtur Petrosyan 5491be2b960eSArtur Petrosyan /* 5492be2b960eSArtur Petrosyan * Clear any pending interrupts since dwc2 will not be able to 5493be2b960eSArtur Petrosyan * clear them after entering partial_power_down. 5494be2b960eSArtur Petrosyan */ 5495be2b960eSArtur Petrosyan dwc2_writel(hsotg, 0xffffffff, GINTSTS); 5496be2b960eSArtur Petrosyan 5497be2b960eSArtur Petrosyan /* Put the controller in low power state */ 5498be2b960eSArtur Petrosyan pcgcctl = dwc2_readl(hsotg, PCGCTL); 5499be2b960eSArtur Petrosyan 5500be2b960eSArtur Petrosyan pcgcctl |= PCGCTL_PWRCLMP; 5501be2b960eSArtur Petrosyan dwc2_writel(hsotg, pcgcctl, PCGCTL); 5502be2b960eSArtur Petrosyan udelay(5); 5503be2b960eSArtur Petrosyan 5504be2b960eSArtur Petrosyan pcgcctl |= PCGCTL_RSTPDWNMODULE; 5505be2b960eSArtur Petrosyan dwc2_writel(hsotg, pcgcctl, PCGCTL); 5506be2b960eSArtur Petrosyan udelay(5); 5507be2b960eSArtur Petrosyan 5508be2b960eSArtur Petrosyan pcgcctl |= PCGCTL_STOPPCLK; 5509be2b960eSArtur Petrosyan dwc2_writel(hsotg, pcgcctl, PCGCTL); 5510be2b960eSArtur Petrosyan 5511be2b960eSArtur Petrosyan /* Set in_ppd flag to 1 as here core enters suspend. */ 5512be2b960eSArtur Petrosyan hsotg->in_ppd = 1; 5513be2b960eSArtur Petrosyan hsotg->lx_state = DWC2_L2; 5514be2b960eSArtur Petrosyan 5515be2b960eSArtur Petrosyan dev_dbg(hsotg->dev, "Entering device partial power down completed.\n"); 5516be2b960eSArtur Petrosyan 5517be2b960eSArtur Petrosyan return ret; 5518be2b960eSArtur Petrosyan } 5519be2b960eSArtur Petrosyan 5520be2b960eSArtur Petrosyan /* 5521be2b960eSArtur Petrosyan * dwc2_gadget_exit_partial_power_down() - Exit controller from device partial 5522be2b960eSArtur Petrosyan * power down. 5523be2b960eSArtur Petrosyan * 5524be2b960eSArtur Petrosyan * @hsotg: Programming view of the DWC_otg controller 5525be2b960eSArtur Petrosyan * @restore: indicates whether need to restore the registers or not. 5526be2b960eSArtur Petrosyan * 5527be2b960eSArtur Petrosyan * Return: non-zero if failed to exit device partial power down. 5528be2b960eSArtur Petrosyan * 5529be2b960eSArtur Petrosyan * This function is for exiting from device mode partial power down. 5530be2b960eSArtur Petrosyan */ 5531be2b960eSArtur Petrosyan int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg, 5532be2b960eSArtur Petrosyan bool restore) 5533be2b960eSArtur Petrosyan { 5534be2b960eSArtur Petrosyan u32 pcgcctl; 5535be2b960eSArtur Petrosyan u32 dctl; 5536be2b960eSArtur Petrosyan struct dwc2_dregs_backup *dr; 5537be2b960eSArtur Petrosyan int ret = 0; 5538be2b960eSArtur Petrosyan 5539be2b960eSArtur Petrosyan dr = &hsotg->dr_backup; 5540be2b960eSArtur Petrosyan 5541be2b960eSArtur Petrosyan dev_dbg(hsotg->dev, "Exiting device partial Power Down started.\n"); 5542be2b960eSArtur Petrosyan 5543be2b960eSArtur Petrosyan pcgcctl = dwc2_readl(hsotg, PCGCTL); 5544be2b960eSArtur Petrosyan pcgcctl &= ~PCGCTL_STOPPCLK; 5545be2b960eSArtur Petrosyan dwc2_writel(hsotg, pcgcctl, PCGCTL); 5546be2b960eSArtur Petrosyan 5547be2b960eSArtur Petrosyan pcgcctl = dwc2_readl(hsotg, PCGCTL); 5548be2b960eSArtur Petrosyan pcgcctl &= ~PCGCTL_PWRCLMP; 5549be2b960eSArtur Petrosyan dwc2_writel(hsotg, pcgcctl, PCGCTL); 5550be2b960eSArtur Petrosyan 5551be2b960eSArtur Petrosyan pcgcctl = dwc2_readl(hsotg, PCGCTL); 5552be2b960eSArtur Petrosyan pcgcctl &= ~PCGCTL_RSTPDWNMODULE; 5553be2b960eSArtur Petrosyan dwc2_writel(hsotg, pcgcctl, PCGCTL); 5554be2b960eSArtur Petrosyan 5555be2b960eSArtur Petrosyan udelay(100); 5556be2b960eSArtur Petrosyan if (restore) { 5557be2b960eSArtur Petrosyan ret = dwc2_restore_global_registers(hsotg); 5558be2b960eSArtur Petrosyan if (ret) { 5559be2b960eSArtur Petrosyan dev_err(hsotg->dev, "%s: failed to restore registers\n", 5560be2b960eSArtur Petrosyan __func__); 5561be2b960eSArtur Petrosyan return ret; 5562be2b960eSArtur Petrosyan } 5563be2b960eSArtur Petrosyan /* Restore DCFG */ 5564be2b960eSArtur Petrosyan dwc2_writel(hsotg, dr->dcfg, DCFG); 5565be2b960eSArtur Petrosyan 5566be2b960eSArtur Petrosyan ret = dwc2_restore_device_registers(hsotg, 0); 5567be2b960eSArtur Petrosyan if (ret) { 5568be2b960eSArtur Petrosyan dev_err(hsotg->dev, "%s: failed to restore device registers\n", 5569be2b960eSArtur Petrosyan __func__); 5570be2b960eSArtur Petrosyan return ret; 5571be2b960eSArtur Petrosyan } 5572be2b960eSArtur Petrosyan } 5573be2b960eSArtur Petrosyan 5574be2b960eSArtur Petrosyan /* Set the Power-On Programming done bit */ 5575be2b960eSArtur Petrosyan dctl = dwc2_readl(hsotg, DCTL); 5576be2b960eSArtur Petrosyan dctl |= DCTL_PWRONPRGDONE; 5577be2b960eSArtur Petrosyan dwc2_writel(hsotg, dctl, DCTL); 5578be2b960eSArtur Petrosyan 5579be2b960eSArtur Petrosyan /* Set in_ppd flag to 0 as here core exits from suspend. */ 5580be2b960eSArtur Petrosyan hsotg->in_ppd = 0; 5581be2b960eSArtur Petrosyan hsotg->lx_state = DWC2_L0; 5582be2b960eSArtur Petrosyan 5583be2b960eSArtur Petrosyan dev_dbg(hsotg->dev, "Exiting device partial Power Down completed.\n"); 5584be2b960eSArtur Petrosyan return ret; 5585be2b960eSArtur Petrosyan } 5586012466fcSArtur Petrosyan 5587012466fcSArtur Petrosyan /** 5588012466fcSArtur Petrosyan * dwc2_gadget_enter_clock_gating() - Put controller in clock gating. 5589012466fcSArtur Petrosyan * 5590012466fcSArtur Petrosyan * @hsotg: Programming view of the DWC_otg controller 5591012466fcSArtur Petrosyan * 5592012466fcSArtur Petrosyan * Return: non-zero if failed to enter device partial power down. 5593012466fcSArtur Petrosyan * 5594012466fcSArtur Petrosyan * This function is for entering device mode clock gating. 5595012466fcSArtur Petrosyan */ 5596012466fcSArtur Petrosyan void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg) 5597012466fcSArtur Petrosyan { 5598012466fcSArtur Petrosyan u32 pcgctl; 5599012466fcSArtur Petrosyan 5600012466fcSArtur Petrosyan dev_dbg(hsotg->dev, "Entering device clock gating.\n"); 5601012466fcSArtur Petrosyan 5602012466fcSArtur Petrosyan /* Set the Phy Clock bit as suspend is received. */ 5603012466fcSArtur Petrosyan pcgctl = dwc2_readl(hsotg, PCGCTL); 5604012466fcSArtur Petrosyan pcgctl |= PCGCTL_STOPPCLK; 5605012466fcSArtur Petrosyan dwc2_writel(hsotg, pcgctl, PCGCTL); 5606012466fcSArtur Petrosyan udelay(5); 5607012466fcSArtur Petrosyan 5608012466fcSArtur Petrosyan /* Set the Gate hclk as suspend is received. */ 5609012466fcSArtur Petrosyan pcgctl = dwc2_readl(hsotg, PCGCTL); 5610012466fcSArtur Petrosyan pcgctl |= PCGCTL_GATEHCLK; 5611012466fcSArtur Petrosyan dwc2_writel(hsotg, pcgctl, PCGCTL); 5612012466fcSArtur Petrosyan udelay(5); 5613012466fcSArtur Petrosyan 5614012466fcSArtur Petrosyan hsotg->lx_state = DWC2_L2; 5615012466fcSArtur Petrosyan hsotg->bus_suspended = true; 5616012466fcSArtur Petrosyan } 5617012466fcSArtur Petrosyan 5618012466fcSArtur Petrosyan /* 5619012466fcSArtur Petrosyan * dwc2_gadget_exit_clock_gating() - Exit controller from device clock gating. 5620012466fcSArtur Petrosyan * 5621012466fcSArtur Petrosyan * @hsotg: Programming view of the DWC_otg controller 5622012466fcSArtur Petrosyan * @rem_wakeup: indicates whether remote wake up is enabled. 5623012466fcSArtur Petrosyan * 5624012466fcSArtur Petrosyan * This function is for exiting from device mode clock gating. 5625012466fcSArtur Petrosyan */ 5626012466fcSArtur Petrosyan void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg, int rem_wakeup) 5627012466fcSArtur Petrosyan { 5628012466fcSArtur Petrosyan u32 pcgctl; 5629012466fcSArtur Petrosyan u32 dctl; 5630012466fcSArtur Petrosyan 5631012466fcSArtur Petrosyan dev_dbg(hsotg->dev, "Exiting device clock gating.\n"); 5632012466fcSArtur Petrosyan 5633012466fcSArtur Petrosyan /* Clear the Gate hclk. */ 5634012466fcSArtur Petrosyan pcgctl = dwc2_readl(hsotg, PCGCTL); 5635012466fcSArtur Petrosyan pcgctl &= ~PCGCTL_GATEHCLK; 5636012466fcSArtur Petrosyan dwc2_writel(hsotg, pcgctl, PCGCTL); 5637012466fcSArtur Petrosyan udelay(5); 5638012466fcSArtur Petrosyan 5639012466fcSArtur Petrosyan /* Phy Clock bit. */ 5640012466fcSArtur Petrosyan pcgctl = dwc2_readl(hsotg, PCGCTL); 5641012466fcSArtur Petrosyan pcgctl &= ~PCGCTL_STOPPCLK; 5642012466fcSArtur Petrosyan dwc2_writel(hsotg, pcgctl, PCGCTL); 5643012466fcSArtur Petrosyan udelay(5); 5644012466fcSArtur Petrosyan 5645012466fcSArtur Petrosyan if (rem_wakeup) { 5646012466fcSArtur Petrosyan /* Set Remote Wakeup Signaling */ 5647012466fcSArtur Petrosyan dctl = dwc2_readl(hsotg, DCTL); 5648012466fcSArtur Petrosyan dctl |= DCTL_RMTWKUPSIG; 5649012466fcSArtur Petrosyan dwc2_writel(hsotg, dctl, DCTL); 5650012466fcSArtur Petrosyan } 5651012466fcSArtur Petrosyan 5652012466fcSArtur Petrosyan /* Change to L0 state */ 5653012466fcSArtur Petrosyan call_gadget(hsotg, resume); 5654012466fcSArtur Petrosyan hsotg->lx_state = DWC2_L0; 5655012466fcSArtur Petrosyan hsotg->bus_suspended = false; 5656012466fcSArtur Petrosyan } 5657