1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* 3 * core_intr.c - DesignWare HS OTG Controller common interrupt handling 4 * 5 * Copyright (C) 2004-2013 Synopsys, Inc. 6 */ 7 8 /* 9 * This file contains the common interrupt handlers 10 */ 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/spinlock.h> 15 #include <linux/interrupt.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/io.h> 18 #include <linux/slab.h> 19 #include <linux/usb.h> 20 21 #include <linux/usb/hcd.h> 22 #include <linux/usb/ch11.h> 23 24 #include "core.h" 25 #include "hcd.h" 26 27 static const char *dwc2_op_state_str(struct dwc2_hsotg *hsotg) 28 { 29 switch (hsotg->op_state) { 30 case OTG_STATE_A_HOST: 31 return "a_host"; 32 case OTG_STATE_A_SUSPEND: 33 return "a_suspend"; 34 case OTG_STATE_A_PERIPHERAL: 35 return "a_peripheral"; 36 case OTG_STATE_B_PERIPHERAL: 37 return "b_peripheral"; 38 case OTG_STATE_B_HOST: 39 return "b_host"; 40 default: 41 return "unknown"; 42 } 43 } 44 45 /** 46 * dwc2_handle_usb_port_intr - handles OTG PRTINT interrupts. 47 * When the PRTINT interrupt fires, there are certain status bits in the Host 48 * Port that needs to get cleared. 49 * 50 * @hsotg: Programming view of DWC_otg controller 51 */ 52 static void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg) 53 { 54 u32 hprt0 = dwc2_readl(hsotg, HPRT0); 55 56 if (hprt0 & HPRT0_ENACHG) { 57 hprt0 &= ~HPRT0_ENA; 58 dwc2_writel(hsotg, hprt0, HPRT0); 59 } 60 } 61 62 /** 63 * dwc2_handle_mode_mismatch_intr() - Logs a mode mismatch warning message 64 * 65 * @hsotg: Programming view of DWC_otg controller 66 */ 67 static void dwc2_handle_mode_mismatch_intr(struct dwc2_hsotg *hsotg) 68 { 69 /* Clear interrupt */ 70 dwc2_writel(hsotg, GINTSTS_MODEMIS, GINTSTS); 71 72 dev_warn(hsotg->dev, "Mode Mismatch Interrupt: currently in %s mode\n", 73 dwc2_is_host_mode(hsotg) ? "Host" : "Device"); 74 } 75 76 /** 77 * dwc2_handle_otg_intr() - Handles the OTG Interrupts. It reads the OTG 78 * Interrupt Register (GOTGINT) to determine what interrupt has occurred. 79 * 80 * @hsotg: Programming view of DWC_otg controller 81 */ 82 static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg) 83 { 84 u32 gotgint; 85 u32 gotgctl; 86 u32 gintmsk; 87 u32 pcgctl; 88 89 gotgint = dwc2_readl(hsotg, GOTGINT); 90 gotgctl = dwc2_readl(hsotg, GOTGCTL); 91 dev_dbg(hsotg->dev, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint, 92 dwc2_op_state_str(hsotg)); 93 94 if (gotgint & GOTGINT_SES_END_DET) { 95 dev_dbg(hsotg->dev, 96 " ++OTG Interrupt: Session End Detected++ (%s)\n", 97 dwc2_op_state_str(hsotg)); 98 gotgctl = dwc2_readl(hsotg, GOTGCTL); 99 100 if (dwc2_is_device_mode(hsotg)) { 101 if (hsotg->params.eusb2_disc) { 102 /* Clear the Gate hclk. */ 103 pcgctl = dwc2_readl(hsotg, PCGCTL); 104 pcgctl &= ~PCGCTL_GATEHCLK; 105 dwc2_writel(hsotg, pcgctl, PCGCTL); 106 udelay(5); 107 108 /* Clear Phy Clock bit. */ 109 pcgctl = dwc2_readl(hsotg, PCGCTL); 110 pcgctl &= ~PCGCTL_STOPPCLK; 111 dwc2_writel(hsotg, pcgctl, PCGCTL); 112 udelay(5); 113 } 114 dwc2_hsotg_disconnect(hsotg); 115 } 116 117 if (hsotg->op_state == OTG_STATE_B_HOST) { 118 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 119 } else { 120 /* 121 * If not B_HOST and Device HNP still set, HNP did 122 * not succeed! 123 */ 124 if (gotgctl & GOTGCTL_DEVHNPEN) { 125 dev_dbg(hsotg->dev, "Session End Detected\n"); 126 dev_err(hsotg->dev, 127 "Device Not Connected/Responding!\n"); 128 } 129 130 /* 131 * If Session End Detected the B-Cable has been 132 * disconnected 133 */ 134 /* Reset to a clean state */ 135 hsotg->lx_state = DWC2_L3; 136 } 137 138 gotgctl = dwc2_readl(hsotg, GOTGCTL); 139 gotgctl &= ~GOTGCTL_DEVHNPEN; 140 dwc2_writel(hsotg, gotgctl, GOTGCTL); 141 } 142 143 if (gotgint & GOTGINT_SES_REQ_SUC_STS_CHNG) { 144 dev_dbg(hsotg->dev, 145 " ++OTG Interrupt: Session Request Success Status Change++\n"); 146 gotgctl = dwc2_readl(hsotg, GOTGCTL); 147 if (gotgctl & GOTGCTL_SESREQSCS) { 148 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS && 149 hsotg->params.i2c_enable) { 150 hsotg->srp_success = 1; 151 } else { 152 /* Clear Session Request */ 153 gotgctl = dwc2_readl(hsotg, GOTGCTL); 154 gotgctl &= ~GOTGCTL_SESREQ; 155 dwc2_writel(hsotg, gotgctl, GOTGCTL); 156 } 157 } 158 } 159 160 if (gotgint & GOTGINT_HST_NEG_SUC_STS_CHNG) { 161 /* 162 * Print statements during the HNP interrupt handling 163 * can cause it to fail 164 */ 165 gotgctl = dwc2_readl(hsotg, GOTGCTL); 166 /* 167 * WA for 3.00a- HW is not setting cur_mode, even sometimes 168 * this does not help 169 */ 170 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) 171 udelay(100); 172 if (gotgctl & GOTGCTL_HSTNEGSCS) { 173 if (dwc2_is_host_mode(hsotg)) { 174 hsotg->op_state = OTG_STATE_B_HOST; 175 /* 176 * Need to disable SOF interrupt immediately. 177 * When switching from device to host, the PCD 178 * interrupt handler won't handle the interrupt 179 * if host mode is already set. The HCD 180 * interrupt handler won't get called if the 181 * HCD state is HALT. This means that the 182 * interrupt does not get handled and Linux 183 * complains loudly. 184 */ 185 gintmsk = dwc2_readl(hsotg, GINTMSK); 186 gintmsk &= ~GINTSTS_SOF; 187 dwc2_writel(hsotg, gintmsk, GINTMSK); 188 189 /* 190 * Call callback function with spin lock 191 * released 192 */ 193 spin_unlock(&hsotg->lock); 194 195 /* Initialize the Core for Host mode */ 196 dwc2_hcd_start(hsotg); 197 spin_lock(&hsotg->lock); 198 hsotg->op_state = OTG_STATE_B_HOST; 199 } 200 } else { 201 gotgctl = dwc2_readl(hsotg, GOTGCTL); 202 gotgctl &= ~(GOTGCTL_HNPREQ | GOTGCTL_DEVHNPEN); 203 dwc2_writel(hsotg, gotgctl, GOTGCTL); 204 dev_dbg(hsotg->dev, "HNP Failed\n"); 205 dev_err(hsotg->dev, 206 "Device Not Connected/Responding\n"); 207 } 208 } 209 210 if (gotgint & GOTGINT_HST_NEG_DET) { 211 /* 212 * The disconnect interrupt is set at the same time as 213 * Host Negotiation Detected. During the mode switch all 214 * interrupts are cleared so the disconnect interrupt 215 * handler will not get executed. 216 */ 217 dev_dbg(hsotg->dev, 218 " ++OTG Interrupt: Host Negotiation Detected++ (%s)\n", 219 (dwc2_is_host_mode(hsotg) ? "Host" : "Device")); 220 if (dwc2_is_device_mode(hsotg)) { 221 dev_dbg(hsotg->dev, "a_suspend->a_peripheral (%d)\n", 222 hsotg->op_state); 223 spin_unlock(&hsotg->lock); 224 dwc2_hcd_disconnect(hsotg, false); 225 spin_lock(&hsotg->lock); 226 hsotg->op_state = OTG_STATE_A_PERIPHERAL; 227 } else { 228 /* Need to disable SOF interrupt immediately */ 229 gintmsk = dwc2_readl(hsotg, GINTMSK); 230 gintmsk &= ~GINTSTS_SOF; 231 dwc2_writel(hsotg, gintmsk, GINTMSK); 232 spin_unlock(&hsotg->lock); 233 dwc2_hcd_start(hsotg); 234 spin_lock(&hsotg->lock); 235 hsotg->op_state = OTG_STATE_A_HOST; 236 } 237 } 238 239 if (gotgint & GOTGINT_A_DEV_TOUT_CHG) 240 dev_dbg(hsotg->dev, 241 " ++OTG Interrupt: A-Device Timeout Change++\n"); 242 if (gotgint & GOTGINT_DBNCE_DONE) 243 dev_dbg(hsotg->dev, " ++OTG Interrupt: Debounce Done++\n"); 244 245 /* Clear GOTGINT */ 246 dwc2_writel(hsotg, gotgint, GOTGINT); 247 } 248 249 /** 250 * dwc2_handle_conn_id_status_change_intr() - Handles the Connector ID Status 251 * Change Interrupt 252 * 253 * @hsotg: Programming view of DWC_otg controller 254 * 255 * Reads the OTG Interrupt Register (GOTCTL) to determine whether this is a 256 * Device to Host Mode transition or a Host to Device Mode transition. This only 257 * occurs when the cable is connected/removed from the PHY connector. 258 */ 259 static void dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg *hsotg) 260 { 261 u32 gintmsk; 262 263 /* Clear interrupt */ 264 dwc2_writel(hsotg, GINTSTS_CONIDSTSCHNG, GINTSTS); 265 266 /* Need to disable SOF interrupt immediately */ 267 gintmsk = dwc2_readl(hsotg, GINTMSK); 268 gintmsk &= ~GINTSTS_SOF; 269 dwc2_writel(hsotg, gintmsk, GINTMSK); 270 271 dev_dbg(hsotg->dev, " ++Connector ID Status Change Interrupt++ (%s)\n", 272 dwc2_is_host_mode(hsotg) ? "Host" : "Device"); 273 274 /* 275 * Need to schedule a work, as there are possible DELAY function calls. 276 */ 277 if (hsotg->wq_otg) 278 queue_work(hsotg->wq_otg, &hsotg->wf_otg); 279 } 280 281 /** 282 * dwc2_handle_session_req_intr() - This interrupt indicates that a device is 283 * initiating the Session Request Protocol to request the host to turn on bus 284 * power so a new session can begin 285 * 286 * @hsotg: Programming view of DWC_otg controller 287 * 288 * This handler responds by turning on bus power. If the DWC_otg controller is 289 * in low power mode, this handler brings the controller out of low power mode 290 * before turning on bus power. 291 */ 292 static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg) 293 { 294 int ret; 295 u32 hprt0; 296 297 /* Clear interrupt */ 298 dwc2_writel(hsotg, GINTSTS_SESSREQINT, GINTSTS); 299 300 dev_dbg(hsotg->dev, "Session request interrupt - lx_state=%d\n", 301 hsotg->lx_state); 302 303 if (dwc2_is_device_mode(hsotg)) { 304 if (hsotg->lx_state != DWC2_L0) { 305 if (hsotg->in_ppd) { 306 ret = dwc2_exit_partial_power_down(hsotg, 0, 307 true); 308 if (ret) 309 dev_err(hsotg->dev, 310 "exit power_down failed\n"); 311 } 312 313 /* Exit gadget mode clock gating. */ 314 if (hsotg->params.power_down == 315 DWC2_POWER_DOWN_PARAM_NONE && hsotg->bus_suspended && 316 !hsotg->params.no_clock_gating) 317 dwc2_gadget_exit_clock_gating(hsotg, 0); 318 } 319 320 /* 321 * Report disconnect if there is any previous session 322 * established 323 */ 324 dwc2_hsotg_disconnect(hsotg); 325 } else { 326 /* Turn on the port power bit. */ 327 hprt0 = dwc2_read_hprt0(hsotg); 328 hprt0 |= HPRT0_PWR; 329 dwc2_writel(hsotg, hprt0, HPRT0); 330 /* Connect hcd after port power is set. */ 331 dwc2_hcd_connect(hsotg); 332 } 333 } 334 335 /** 336 * dwc2_wakeup_from_lpm_l1 - Exit the device from LPM L1 state 337 * @hsotg: Programming view of DWC_otg controller 338 * @remotewakeup: Whether this is a remote wakeup 339 */ 340 void dwc2_wakeup_from_lpm_l1(struct dwc2_hsotg *hsotg, bool remotewakeup) 341 { 342 u32 glpmcfg; 343 u32 pcgctl; 344 u32 dctl; 345 346 if (hsotg->lx_state != DWC2_L1) { 347 dev_err(hsotg->dev, "Core isn't in DWC2_L1 state\n"); 348 return; 349 } 350 351 glpmcfg = dwc2_readl(hsotg, GLPMCFG); 352 if (dwc2_is_device_mode(hsotg)) { 353 dev_dbg(hsotg->dev, "Exit from L1 state, remotewakeup=%d\n", remotewakeup); 354 glpmcfg &= ~GLPMCFG_ENBLSLPM; 355 glpmcfg &= ~GLPMCFG_HIRD_THRES_MASK; 356 dwc2_writel(hsotg, glpmcfg, GLPMCFG); 357 358 pcgctl = dwc2_readl(hsotg, PCGCTL); 359 pcgctl &= ~PCGCTL_ENBL_SLEEP_GATING; 360 dwc2_writel(hsotg, pcgctl, PCGCTL); 361 362 glpmcfg = dwc2_readl(hsotg, GLPMCFG); 363 if (glpmcfg & GLPMCFG_ENBESL) { 364 glpmcfg |= GLPMCFG_RSTRSLPSTS; 365 dwc2_writel(hsotg, glpmcfg, GLPMCFG); 366 } 367 368 if (remotewakeup) { 369 if (dwc2_hsotg_wait_bit_set(hsotg, GLPMCFG, GLPMCFG_L1RESUMEOK, 1000)) { 370 dev_warn(hsotg->dev, "%s: timeout GLPMCFG_L1RESUMEOK\n", __func__); 371 goto fail; 372 return; 373 } 374 375 dctl = dwc2_readl(hsotg, DCTL); 376 dctl |= DCTL_RMTWKUPSIG; 377 dwc2_writel(hsotg, dctl, DCTL); 378 379 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, GINTSTS_WKUPINT, 1000)) { 380 dev_warn(hsotg->dev, "%s: timeout GINTSTS_WKUPINT\n", __func__); 381 goto fail; 382 return; 383 } 384 } 385 386 glpmcfg = dwc2_readl(hsotg, GLPMCFG); 387 if (glpmcfg & GLPMCFG_COREL1RES_MASK || glpmcfg & GLPMCFG_SLPSTS || 388 glpmcfg & GLPMCFG_L1RESUMEOK) { 389 goto fail; 390 return; 391 } 392 393 /* Inform gadget to exit from L1 */ 394 call_gadget(hsotg, resume); 395 /* Change to L0 state */ 396 hsotg->lx_state = DWC2_L0; 397 hsotg->bus_suspended = false; 398 fail: dwc2_gadget_init_lpm(hsotg); 399 } else { 400 /* TODO */ 401 dev_err(hsotg->dev, "Host side LPM is not supported.\n"); 402 return; 403 } 404 } 405 406 /* 407 * This interrupt indicates that the DWC_otg controller has detected a 408 * resume or remote wakeup sequence. If the DWC_otg controller is in 409 * low power mode, the handler must brings the controller out of low 410 * power mode. The controller automatically begins resume signaling. 411 * The handler schedules a time to stop resume signaling. 412 */ 413 static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg) 414 { 415 int ret; 416 417 /* Clear interrupt */ 418 dwc2_writel(hsotg, GINTSTS_WKUPINT, GINTSTS); 419 420 dev_dbg(hsotg->dev, "++Resume or Remote Wakeup Detected Interrupt++\n"); 421 dev_dbg(hsotg->dev, "%s lxstate = %d\n", __func__, hsotg->lx_state); 422 423 if (hsotg->lx_state == DWC2_L1) { 424 dwc2_wakeup_from_lpm_l1(hsotg, false); 425 return; 426 } 427 428 if (dwc2_is_device_mode(hsotg)) { 429 dev_dbg(hsotg->dev, "DSTS=0x%0x\n", 430 dwc2_readl(hsotg, DSTS)); 431 if (hsotg->lx_state == DWC2_L2) { 432 if (hsotg->in_ppd) { 433 u32 dctl = dwc2_readl(hsotg, DCTL); 434 /* Clear Remote Wakeup Signaling */ 435 dctl &= ~DCTL_RMTWKUPSIG; 436 dwc2_writel(hsotg, dctl, DCTL); 437 ret = dwc2_exit_partial_power_down(hsotg, 1, 438 true); 439 if (ret) 440 dev_err(hsotg->dev, 441 "exit partial_power_down failed\n"); 442 call_gadget(hsotg, resume); 443 } 444 445 /* Exit gadget mode clock gating. */ 446 if (hsotg->params.power_down == 447 DWC2_POWER_DOWN_PARAM_NONE && hsotg->bus_suspended && 448 !hsotg->params.no_clock_gating) 449 dwc2_gadget_exit_clock_gating(hsotg, 0); 450 } else { 451 /* Change to L0 state */ 452 hsotg->lx_state = DWC2_L0; 453 } 454 } else { 455 if (hsotg->lx_state == DWC2_L2) { 456 if (hsotg->in_ppd) { 457 ret = dwc2_exit_partial_power_down(hsotg, 1, 458 true); 459 if (ret) 460 dev_err(hsotg->dev, 461 "exit partial_power_down failed\n"); 462 } 463 464 if (hsotg->params.power_down == 465 DWC2_POWER_DOWN_PARAM_NONE && hsotg->bus_suspended && 466 !hsotg->params.no_clock_gating) 467 dwc2_host_exit_clock_gating(hsotg, 1); 468 469 /* 470 * If we've got this quirk then the PHY is stuck upon 471 * wakeup. Assert reset. This will propagate out and 472 * eventually we'll re-enumerate the device. Not great 473 * but the best we can do. We can't call phy_reset() 474 * at interrupt time but there's no hurry, so we'll 475 * schedule it for later. 476 */ 477 if (hsotg->reset_phy_on_wake) 478 dwc2_host_schedule_phy_reset(hsotg); 479 480 mod_timer(&hsotg->wkp_timer, 481 jiffies + msecs_to_jiffies(71)); 482 } else { 483 /* Change to L0 state */ 484 hsotg->lx_state = DWC2_L0; 485 } 486 } 487 } 488 489 /* 490 * This interrupt indicates that a device has been disconnected from the 491 * root port 492 */ 493 static void dwc2_handle_disconnect_intr(struct dwc2_hsotg *hsotg) 494 { 495 dwc2_writel(hsotg, GINTSTS_DISCONNINT, GINTSTS); 496 497 dev_dbg(hsotg->dev, "++Disconnect Detected Interrupt++ (%s) %s\n", 498 dwc2_is_host_mode(hsotg) ? "Host" : "Device", 499 dwc2_op_state_str(hsotg)); 500 501 if (hsotg->op_state == OTG_STATE_A_HOST) 502 dwc2_hcd_disconnect(hsotg, false); 503 } 504 505 /* 506 * This interrupt indicates that SUSPEND state has been detected on the USB. 507 * 508 * For HNP the USB Suspend interrupt signals the change from "a_peripheral" 509 * to "a_host". 510 * 511 * When power management is enabled the core will be put in low power mode. 512 */ 513 static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg) 514 { 515 u32 dsts; 516 int ret; 517 518 /* Clear interrupt */ 519 dwc2_writel(hsotg, GINTSTS_USBSUSP, GINTSTS); 520 521 dev_dbg(hsotg->dev, "USB SUSPEND\n"); 522 523 if (dwc2_is_device_mode(hsotg)) { 524 /* 525 * Check the Device status register to determine if the Suspend 526 * state is active 527 */ 528 dsts = dwc2_readl(hsotg, DSTS); 529 dev_dbg(hsotg->dev, "%s: DSTS=0x%0x\n", __func__, dsts); 530 dev_dbg(hsotg->dev, 531 "DSTS.Suspend Status=%d HWCFG4.Power Optimize=%d HWCFG4.Hibernation=%d\n", 532 !!(dsts & DSTS_SUSPSTS), 533 hsotg->hw_params.power_optimized, 534 hsotg->hw_params.hibernation); 535 536 /* Ignore suspend request before enumeration */ 537 if (!dwc2_is_device_connected(hsotg)) { 538 dev_dbg(hsotg->dev, 539 "ignore suspend request before enumeration\n"); 540 return; 541 } 542 if (dsts & DSTS_SUSPSTS) { 543 switch (hsotg->params.power_down) { 544 case DWC2_POWER_DOWN_PARAM_PARTIAL: 545 ret = dwc2_enter_partial_power_down(hsotg); 546 if (ret) 547 dev_err(hsotg->dev, 548 "enter partial_power_down failed\n"); 549 550 udelay(100); 551 552 /* Ask phy to be suspended */ 553 if (!IS_ERR_OR_NULL(hsotg->uphy)) 554 usb_phy_set_suspend(hsotg->uphy, true); 555 break; 556 case DWC2_POWER_DOWN_PARAM_HIBERNATION: 557 ret = dwc2_enter_hibernation(hsotg, 0); 558 if (ret) 559 dev_err(hsotg->dev, 560 "enter hibernation failed\n"); 561 break; 562 case DWC2_POWER_DOWN_PARAM_NONE: 563 /* 564 * If neither hibernation nor partial power down are supported, 565 * clock gating is used to save power. 566 */ 567 if (!hsotg->params.no_clock_gating) 568 dwc2_gadget_enter_clock_gating(hsotg); 569 } 570 571 /* 572 * Change to L2 (suspend) state before releasing 573 * spinlock 574 */ 575 hsotg->lx_state = DWC2_L2; 576 577 /* Call gadget suspend callback */ 578 call_gadget(hsotg, suspend); 579 } 580 } else { 581 if (hsotg->op_state == OTG_STATE_A_PERIPHERAL) { 582 dev_dbg(hsotg->dev, "a_peripheral->a_host\n"); 583 584 /* Change to L2 (suspend) state */ 585 hsotg->lx_state = DWC2_L2; 586 /* Clear the a_peripheral flag, back to a_host */ 587 spin_unlock(&hsotg->lock); 588 dwc2_hcd_start(hsotg); 589 spin_lock(&hsotg->lock); 590 hsotg->op_state = OTG_STATE_A_HOST; 591 } 592 } 593 } 594 595 /** 596 * dwc2_handle_lpm_intr - GINTSTS_LPMTRANRCVD Interrupt handler 597 * 598 * @hsotg: Programming view of DWC_otg controller 599 * 600 */ 601 static void dwc2_handle_lpm_intr(struct dwc2_hsotg *hsotg) 602 { 603 u32 glpmcfg; 604 u32 pcgcctl; 605 u32 hird; 606 u32 hird_thres; 607 u32 hird_thres_en; 608 u32 enslpm; 609 610 /* Clear interrupt */ 611 dwc2_writel(hsotg, GINTSTS_LPMTRANRCVD, GINTSTS); 612 613 glpmcfg = dwc2_readl(hsotg, GLPMCFG); 614 615 if (!(glpmcfg & GLPMCFG_LPMCAP)) { 616 dev_err(hsotg->dev, "Unexpected LPM interrupt\n"); 617 return; 618 } 619 620 hird = (glpmcfg & GLPMCFG_HIRD_MASK) >> GLPMCFG_HIRD_SHIFT; 621 hird_thres = (glpmcfg & GLPMCFG_HIRD_THRES_MASK & 622 ~GLPMCFG_HIRD_THRES_EN) >> GLPMCFG_HIRD_THRES_SHIFT; 623 hird_thres_en = glpmcfg & GLPMCFG_HIRD_THRES_EN; 624 enslpm = glpmcfg & GLPMCFG_ENBLSLPM; 625 626 if (dwc2_is_device_mode(hsotg)) { 627 dev_dbg(hsotg->dev, "HIRD_THRES_EN = %d\n", hird_thres_en); 628 629 if (hird_thres_en && hird >= hird_thres) { 630 dev_dbg(hsotg->dev, "L1 with utmi_l1_suspend_n\n"); 631 } else if (enslpm) { 632 dev_dbg(hsotg->dev, "L1 with utmi_sleep_n\n"); 633 } else { 634 dev_dbg(hsotg->dev, "Entering Sleep with L1 Gating\n"); 635 636 pcgcctl = dwc2_readl(hsotg, PCGCTL); 637 pcgcctl |= PCGCTL_ENBL_SLEEP_GATING; 638 dwc2_writel(hsotg, pcgcctl, PCGCTL); 639 } 640 /** 641 * Examine prt_sleep_sts after TL1TokenTetry period max (10 us) 642 */ 643 udelay(10); 644 645 glpmcfg = dwc2_readl(hsotg, GLPMCFG); 646 647 if (glpmcfg & GLPMCFG_SLPSTS) { 648 /* Save the current state */ 649 hsotg->lx_state = DWC2_L1; 650 dev_dbg(hsotg->dev, 651 "Core is in L1 sleep glpmcfg=%08x\n", glpmcfg); 652 653 /* Inform gadget that we are in L1 state */ 654 call_gadget(hsotg, suspend); 655 } 656 } 657 } 658 659 #define GINTMSK_COMMON (GINTSTS_WKUPINT | GINTSTS_SESSREQINT | \ 660 GINTSTS_CONIDSTSCHNG | GINTSTS_OTGINT | \ 661 GINTSTS_MODEMIS | GINTSTS_DISCONNINT | \ 662 GINTSTS_USBSUSP | GINTSTS_PRTINT | \ 663 GINTSTS_LPMTRANRCVD) 664 665 /* 666 * This function returns the Core Interrupt register 667 */ 668 static u32 dwc2_read_common_intr(struct dwc2_hsotg *hsotg) 669 { 670 u32 gintsts; 671 u32 gintmsk; 672 u32 gahbcfg; 673 u32 gintmsk_common = GINTMSK_COMMON; 674 675 gintsts = dwc2_readl(hsotg, GINTSTS); 676 gintmsk = dwc2_readl(hsotg, GINTMSK); 677 gahbcfg = dwc2_readl(hsotg, GAHBCFG); 678 679 /* If any common interrupts set */ 680 if (gintsts & gintmsk_common) 681 dev_dbg(hsotg->dev, "gintsts=%08x gintmsk=%08x\n", 682 gintsts, gintmsk); 683 684 if (gahbcfg & GAHBCFG_GLBL_INTR_EN) 685 return gintsts & gintmsk & gintmsk_common; 686 else 687 return 0; 688 } 689 690 /** 691 * dwc_handle_gpwrdn_disc_det() - Handles the gpwrdn disconnect detect. 692 * Exits hibernation without restoring registers. 693 * 694 * @hsotg: Programming view of DWC_otg controller 695 * @gpwrdn: GPWRDN register 696 */ 697 static inline void dwc_handle_gpwrdn_disc_det(struct dwc2_hsotg *hsotg, 698 u32 gpwrdn) 699 { 700 u32 gpwrdn_tmp; 701 702 /* Switch-on voltage to the core */ 703 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN); 704 gpwrdn_tmp &= ~GPWRDN_PWRDNSWTCH; 705 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN); 706 udelay(5); 707 708 /* Reset core */ 709 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN); 710 gpwrdn_tmp &= ~GPWRDN_PWRDNRSTN; 711 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN); 712 udelay(5); 713 714 /* Disable Power Down Clamp */ 715 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN); 716 gpwrdn_tmp &= ~GPWRDN_PWRDNCLMP; 717 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN); 718 udelay(5); 719 720 /* Deassert reset core */ 721 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN); 722 gpwrdn_tmp |= GPWRDN_PWRDNRSTN; 723 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN); 724 udelay(5); 725 726 /* Disable PMU interrupt */ 727 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN); 728 gpwrdn_tmp &= ~GPWRDN_PMUINTSEL; 729 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN); 730 731 /* Reset ULPI latch */ 732 gpwrdn = dwc2_readl(hsotg, GPWRDN); 733 gpwrdn &= ~GPWRDN_ULPI_LATCH_EN_DURING_HIB_ENTRY; 734 dwc2_writel(hsotg, gpwrdn, GPWRDN); 735 736 /* De-assert Wakeup Logic */ 737 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN); 738 gpwrdn_tmp &= ~GPWRDN_PMUACTV; 739 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN); 740 741 hsotg->hibernated = 0; 742 hsotg->bus_suspended = 0; 743 744 if (gpwrdn & GPWRDN_IDSTS) { 745 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 746 dwc2_core_init(hsotg, false); 747 dwc2_enable_global_interrupts(hsotg); 748 dwc2_hsotg_core_init_disconnected(hsotg, false); 749 dwc2_hsotg_core_connect(hsotg); 750 } else { 751 hsotg->op_state = OTG_STATE_A_HOST; 752 753 /* Initialize the Core for Host mode */ 754 dwc2_core_init(hsotg, false); 755 dwc2_enable_global_interrupts(hsotg); 756 dwc2_hcd_start(hsotg); 757 } 758 } 759 760 /* 761 * GPWRDN interrupt handler. 762 * 763 * The GPWRDN interrupts are those that occur in both Host and 764 * Device mode while core is in hibernated state. 765 */ 766 static int dwc2_handle_gpwrdn_intr(struct dwc2_hsotg *hsotg) 767 { 768 u32 gpwrdn; 769 int linestate; 770 int ret = 0; 771 772 gpwrdn = dwc2_readl(hsotg, GPWRDN); 773 /* clear all interrupt */ 774 dwc2_writel(hsotg, gpwrdn, GPWRDN); 775 linestate = (gpwrdn & GPWRDN_LINESTATE_MASK) >> GPWRDN_LINESTATE_SHIFT; 776 dev_dbg(hsotg->dev, 777 "%s: dwc2_handle_gpwrdwn_intr called gpwrdn= %08x\n", __func__, 778 gpwrdn); 779 780 if ((gpwrdn & GPWRDN_DISCONN_DET) && 781 (gpwrdn & GPWRDN_DISCONN_DET_MSK) && !linestate) { 782 dev_dbg(hsotg->dev, "%s: GPWRDN_DISCONN_DET\n", __func__); 783 /* 784 * Call disconnect detect function to exit from 785 * hibernation 786 */ 787 dwc_handle_gpwrdn_disc_det(hsotg, gpwrdn); 788 } else if ((gpwrdn & GPWRDN_LNSTSCHG) && 789 (gpwrdn & GPWRDN_LNSTSCHG_MSK) && linestate) { 790 dev_dbg(hsotg->dev, "%s: GPWRDN_LNSTSCHG\n", __func__); 791 if (hsotg->hw_params.hibernation && 792 hsotg->hibernated) { 793 if (gpwrdn & GPWRDN_IDSTS) { 794 ret = dwc2_exit_hibernation(hsotg, 0, 0, 0); 795 if (ret) 796 dev_err(hsotg->dev, 797 "exit hibernation failed.\n"); 798 call_gadget(hsotg, resume); 799 } else { 800 ret = dwc2_exit_hibernation(hsotg, 1, 0, 1); 801 if (ret) 802 dev_err(hsotg->dev, 803 "exit hibernation failed.\n"); 804 } 805 } 806 } else if ((gpwrdn & GPWRDN_RST_DET) && 807 (gpwrdn & GPWRDN_RST_DET_MSK)) { 808 dev_dbg(hsotg->dev, "%s: GPWRDN_RST_DET\n", __func__); 809 if (!linestate) { 810 ret = dwc2_exit_hibernation(hsotg, 0, 1, 0); 811 if (ret) 812 dev_err(hsotg->dev, 813 "exit hibernation failed.\n"); 814 } 815 } else if ((gpwrdn & GPWRDN_STS_CHGINT) && 816 (gpwrdn & GPWRDN_STS_CHGINT_MSK)) { 817 dev_dbg(hsotg->dev, "%s: GPWRDN_STS_CHGINT\n", __func__); 818 /* 819 * As GPWRDN_STS_CHGINT exit from hibernation flow is 820 * the same as in GPWRDN_DISCONN_DET flow. Call 821 * disconnect detect helper function to exit from 822 * hibernation. 823 */ 824 dwc_handle_gpwrdn_disc_det(hsotg, gpwrdn); 825 } 826 827 return ret; 828 } 829 830 /* 831 * Common interrupt handler 832 * 833 * The common interrupts are those that occur in both Host and Device mode. 834 * This handler handles the following interrupts: 835 * - Mode Mismatch Interrupt 836 * - OTG Interrupt 837 * - Connector ID Status Change Interrupt 838 * - Disconnect Interrupt 839 * - Session Request Interrupt 840 * - Resume / Remote Wakeup Detected Interrupt 841 * - Suspend Interrupt 842 */ 843 irqreturn_t dwc2_handle_common_intr(int irq, void *dev) 844 { 845 struct dwc2_hsotg *hsotg = dev; 846 u32 gintsts; 847 irqreturn_t retval = IRQ_NONE; 848 849 spin_lock(&hsotg->lock); 850 851 if (!dwc2_is_controller_alive(hsotg)) { 852 dev_warn(hsotg->dev, "Controller is dead\n"); 853 goto out; 854 } 855 856 /* Reading current frame number value in device or host modes. */ 857 if (dwc2_is_device_mode(hsotg)) 858 hsotg->frame_number = (dwc2_readl(hsotg, DSTS) 859 & DSTS_SOFFN_MASK) >> DSTS_SOFFN_SHIFT; 860 else 861 hsotg->frame_number = (dwc2_readl(hsotg, HFNUM) 862 & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 863 864 gintsts = dwc2_read_common_intr(hsotg); 865 if (gintsts & ~GINTSTS_PRTINT) 866 retval = IRQ_HANDLED; 867 868 /* In case of hibernated state gintsts must not work */ 869 if (hsotg->hibernated) { 870 dwc2_handle_gpwrdn_intr(hsotg); 871 retval = IRQ_HANDLED; 872 goto out; 873 } 874 875 if (gintsts & GINTSTS_MODEMIS) 876 dwc2_handle_mode_mismatch_intr(hsotg); 877 if (gintsts & GINTSTS_OTGINT) 878 dwc2_handle_otg_intr(hsotg); 879 if (gintsts & GINTSTS_CONIDSTSCHNG) 880 dwc2_handle_conn_id_status_change_intr(hsotg); 881 if (gintsts & GINTSTS_DISCONNINT) 882 dwc2_handle_disconnect_intr(hsotg); 883 if (gintsts & GINTSTS_SESSREQINT) 884 dwc2_handle_session_req_intr(hsotg); 885 if (gintsts & GINTSTS_WKUPINT) 886 dwc2_handle_wakeup_detected_intr(hsotg); 887 if (gintsts & GINTSTS_USBSUSP) 888 dwc2_handle_usb_suspend_intr(hsotg); 889 if (gintsts & GINTSTS_LPMTRANRCVD) 890 dwc2_handle_lpm_intr(hsotg); 891 892 if (gintsts & GINTSTS_PRTINT) { 893 /* 894 * The port interrupt occurs while in device mode with HPRT0 895 * Port Enable/Disable 896 */ 897 if (dwc2_is_device_mode(hsotg)) { 898 dev_dbg(hsotg->dev, 899 " --Port interrupt received in Device mode--\n"); 900 dwc2_handle_usb_port_intr(hsotg); 901 retval = IRQ_HANDLED; 902 } 903 } 904 905 out: 906 spin_unlock(&hsotg->lock); 907 return retval; 908 } 909