1 /* 2 * core.c - ChipIdea USB IP core family device controller 3 * 4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved. 5 * 6 * Author: David Lopo 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 /* 14 * Description: ChipIdea USB IP core family device controller 15 * 16 * This driver is composed of several blocks: 17 * - HW: hardware interface 18 * - DBG: debug facilities (optional) 19 * - UTIL: utilities 20 * - ISR: interrupts handling 21 * - ENDPT: endpoint operations (Gadget API) 22 * - GADGET: gadget operations (Gadget API) 23 * - BUS: bus glue code, bus abstraction layer 24 * 25 * Compile Options 26 * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities 27 * - STALL_IN: non-empty bulk-in pipes cannot be halted 28 * if defined mass storage compliance succeeds but with warnings 29 * => case 4: Hi > Dn 30 * => case 5: Hi > Di 31 * => case 8: Hi <> Do 32 * if undefined usbtest 13 fails 33 * - TRACE: enable function tracing (depends on DEBUG) 34 * 35 * Main Features 36 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage 37 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined) 38 * - Normal & LPM support 39 * 40 * USBTEST Report 41 * - OK: 0-12, 13 (STALL_IN defined) & 14 42 * - Not Supported: 15 & 16 (ISO) 43 * 44 * TODO List 45 * - OTG 46 * - Interrupt Traffic 47 * - GET_STATUS(device) - always reports 0 48 * - Gadget API (majority of optional features) 49 * - Suspend & Remote Wakeup 50 */ 51 #include <linux/delay.h> 52 #include <linux/device.h> 53 #include <linux/dma-mapping.h> 54 #include <linux/platform_device.h> 55 #include <linux/module.h> 56 #include <linux/idr.h> 57 #include <linux/interrupt.h> 58 #include <linux/io.h> 59 #include <linux/kernel.h> 60 #include <linux/slab.h> 61 #include <linux/pm_runtime.h> 62 #include <linux/usb/ch9.h> 63 #include <linux/usb/gadget.h> 64 #include <linux/usb/otg.h> 65 #include <linux/usb/chipidea.h> 66 #include <linux/usb/of.h> 67 #include <linux/phy.h> 68 #include <linux/regulator/consumer.h> 69 70 #include "ci.h" 71 #include "udc.h" 72 #include "bits.h" 73 #include "host.h" 74 #include "debug.h" 75 #include "otg.h" 76 77 /* Controller register map */ 78 static const u8 ci_regs_nolpm[] = { 79 [CAP_CAPLENGTH] = 0x00U, 80 [CAP_HCCPARAMS] = 0x08U, 81 [CAP_DCCPARAMS] = 0x24U, 82 [CAP_TESTMODE] = 0x38U, 83 [OP_USBCMD] = 0x00U, 84 [OP_USBSTS] = 0x04U, 85 [OP_USBINTR] = 0x08U, 86 [OP_DEVICEADDR] = 0x14U, 87 [OP_ENDPTLISTADDR] = 0x18U, 88 [OP_PORTSC] = 0x44U, 89 [OP_DEVLC] = 0x84U, 90 [OP_OTGSC] = 0x64U, 91 [OP_USBMODE] = 0x68U, 92 [OP_ENDPTSETUPSTAT] = 0x6CU, 93 [OP_ENDPTPRIME] = 0x70U, 94 [OP_ENDPTFLUSH] = 0x74U, 95 [OP_ENDPTSTAT] = 0x78U, 96 [OP_ENDPTCOMPLETE] = 0x7CU, 97 [OP_ENDPTCTRL] = 0x80U, 98 }; 99 100 static const u8 ci_regs_lpm[] = { 101 [CAP_CAPLENGTH] = 0x00U, 102 [CAP_HCCPARAMS] = 0x08U, 103 [CAP_DCCPARAMS] = 0x24U, 104 [CAP_TESTMODE] = 0xFCU, 105 [OP_USBCMD] = 0x00U, 106 [OP_USBSTS] = 0x04U, 107 [OP_USBINTR] = 0x08U, 108 [OP_DEVICEADDR] = 0x14U, 109 [OP_ENDPTLISTADDR] = 0x18U, 110 [OP_PORTSC] = 0x44U, 111 [OP_DEVLC] = 0x84U, 112 [OP_OTGSC] = 0xC4U, 113 [OP_USBMODE] = 0xC8U, 114 [OP_ENDPTSETUPSTAT] = 0xD8U, 115 [OP_ENDPTPRIME] = 0xDCU, 116 [OP_ENDPTFLUSH] = 0xE0U, 117 [OP_ENDPTSTAT] = 0xE4U, 118 [OP_ENDPTCOMPLETE] = 0xE8U, 119 [OP_ENDPTCTRL] = 0xECU, 120 }; 121 122 static int hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm) 123 { 124 int i; 125 126 for (i = 0; i < OP_ENDPTCTRL; i++) 127 ci->hw_bank.regmap[i] = 128 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) + 129 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]); 130 131 for (; i <= OP_LAST; i++) 132 ci->hw_bank.regmap[i] = ci->hw_bank.op + 133 4 * (i - OP_ENDPTCTRL) + 134 (is_lpm 135 ? ci_regs_lpm[OP_ENDPTCTRL] 136 : ci_regs_nolpm[OP_ENDPTCTRL]); 137 138 return 0; 139 } 140 141 /** 142 * hw_port_test_set: writes port test mode (execute without interruption) 143 * @mode: new value 144 * 145 * This function returns an error code 146 */ 147 int hw_port_test_set(struct ci_hdrc *ci, u8 mode) 148 { 149 const u8 TEST_MODE_MAX = 7; 150 151 if (mode > TEST_MODE_MAX) 152 return -EINVAL; 153 154 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC)); 155 return 0; 156 } 157 158 /** 159 * hw_port_test_get: reads port test mode value 160 * 161 * This function returns port test mode value 162 */ 163 u8 hw_port_test_get(struct ci_hdrc *ci) 164 { 165 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC); 166 } 167 168 /* The PHY enters/leaves low power mode */ 169 static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable) 170 { 171 enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC; 172 bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm))); 173 174 if (enable && !lpm) { 175 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), 176 PORTSC_PHCD(ci->hw_bank.lpm)); 177 } else if (!enable && lpm) { 178 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), 179 0); 180 /* 181 * The controller needs at least 1ms to reflect 182 * PHY's status, the PHY also needs some time (less 183 * than 1ms) to leave low power mode. 184 */ 185 usleep_range(1500, 2000); 186 } 187 } 188 189 static int hw_device_init(struct ci_hdrc *ci, void __iomem *base) 190 { 191 u32 reg; 192 193 /* bank is a module variable */ 194 ci->hw_bank.abs = base; 195 196 ci->hw_bank.cap = ci->hw_bank.abs; 197 ci->hw_bank.cap += ci->platdata->capoffset; 198 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff); 199 200 hw_alloc_regmap(ci, false); 201 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >> 202 __ffs(HCCPARAMS_LEN); 203 ci->hw_bank.lpm = reg; 204 if (reg) 205 hw_alloc_regmap(ci, !!reg); 206 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs; 207 ci->hw_bank.size += OP_LAST; 208 ci->hw_bank.size /= sizeof(u32); 209 210 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >> 211 __ffs(DCCPARAMS_DEN); 212 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */ 213 214 if (ci->hw_ep_max > ENDPT_MAX) 215 return -ENODEV; 216 217 ci_hdrc_enter_lpm(ci, false); 218 219 /* Disable all interrupts bits */ 220 hw_write(ci, OP_USBINTR, 0xffffffff, 0); 221 222 /* Clear all interrupts status bits*/ 223 hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff); 224 225 dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n", 226 ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op); 227 228 /* setup lock mode ? */ 229 230 /* ENDPTSETUPSTAT is '0' by default */ 231 232 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */ 233 234 return 0; 235 } 236 237 static void hw_phymode_configure(struct ci_hdrc *ci) 238 { 239 u32 portsc, lpm, sts; 240 241 switch (ci->platdata->phy_mode) { 242 case USBPHY_INTERFACE_MODE_UTMI: 243 portsc = PORTSC_PTS(PTS_UTMI); 244 lpm = DEVLC_PTS(PTS_UTMI); 245 break; 246 case USBPHY_INTERFACE_MODE_UTMIW: 247 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW; 248 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW; 249 break; 250 case USBPHY_INTERFACE_MODE_ULPI: 251 portsc = PORTSC_PTS(PTS_ULPI); 252 lpm = DEVLC_PTS(PTS_ULPI); 253 break; 254 case USBPHY_INTERFACE_MODE_SERIAL: 255 portsc = PORTSC_PTS(PTS_SERIAL); 256 lpm = DEVLC_PTS(PTS_SERIAL); 257 sts = 1; 258 break; 259 case USBPHY_INTERFACE_MODE_HSIC: 260 portsc = PORTSC_PTS(PTS_HSIC); 261 lpm = DEVLC_PTS(PTS_HSIC); 262 break; 263 default: 264 return; 265 } 266 267 if (ci->hw_bank.lpm) { 268 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm); 269 hw_write(ci, OP_DEVLC, DEVLC_STS, sts); 270 } else { 271 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc); 272 hw_write(ci, OP_PORTSC, PORTSC_STS, sts); 273 } 274 } 275 276 /** 277 * hw_device_reset: resets chip (execute without interruption) 278 * @ci: the controller 279 * 280 * This function returns an error code 281 */ 282 int hw_device_reset(struct ci_hdrc *ci, u32 mode) 283 { 284 /* should flush & stop before reset */ 285 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0); 286 hw_write(ci, OP_USBCMD, USBCMD_RS, 0); 287 288 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST); 289 while (hw_read(ci, OP_USBCMD, USBCMD_RST)) 290 udelay(10); /* not RTOS friendly */ 291 292 if (ci->platdata->notify_event) 293 ci->platdata->notify_event(ci, 294 CI_HDRC_CONTROLLER_RESET_EVENT); 295 296 if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING) 297 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS); 298 299 /* USBMODE should be configured step by step */ 300 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE); 301 hw_write(ci, OP_USBMODE, USBMODE_CM, mode); 302 /* HW >= 2.3 */ 303 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM); 304 305 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) { 306 pr_err("cannot enter in %s mode", ci_role(ci)->name); 307 pr_err("lpm = %i", ci->hw_bank.lpm); 308 return -ENODEV; 309 } 310 311 return 0; 312 } 313 314 /** 315 * hw_wait_reg: wait the register value 316 * 317 * Sometimes, it needs to wait register value before going on. 318 * Eg, when switch to device mode, the vbus value should be lower 319 * than OTGSC_BSV before connects to host. 320 * 321 * @ci: the controller 322 * @reg: register index 323 * @mask: mast bit 324 * @value: the bit value to wait 325 * @timeout_ms: timeout in millisecond 326 * 327 * This function returns an error code if timeout 328 */ 329 int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask, 330 u32 value, unsigned int timeout_ms) 331 { 332 unsigned long elapse = jiffies + msecs_to_jiffies(timeout_ms); 333 334 while (hw_read(ci, reg, mask) != value) { 335 if (time_after(jiffies, elapse)) { 336 dev_err(ci->dev, "timeout waiting for %08x in %d\n", 337 mask, reg); 338 return -ETIMEDOUT; 339 } 340 msleep(20); 341 } 342 343 return 0; 344 } 345 346 static irqreturn_t ci_irq(int irq, void *data) 347 { 348 struct ci_hdrc *ci = data; 349 irqreturn_t ret = IRQ_NONE; 350 u32 otgsc = 0; 351 352 if (ci->is_otg) 353 otgsc = hw_read(ci, OP_OTGSC, ~0); 354 355 /* 356 * Handle id change interrupt, it indicates device/host function 357 * switch. 358 */ 359 if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) { 360 ci->id_event = true; 361 ci_clear_otg_interrupt(ci, OTGSC_IDIS); 362 disable_irq_nosync(ci->irq); 363 queue_work(ci->wq, &ci->work); 364 return IRQ_HANDLED; 365 } 366 367 /* 368 * Handle vbus change interrupt, it indicates device connection 369 * and disconnection events. 370 */ 371 if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) { 372 ci->b_sess_valid_event = true; 373 ci_clear_otg_interrupt(ci, OTGSC_BSVIS); 374 disable_irq_nosync(ci->irq); 375 queue_work(ci->wq, &ci->work); 376 return IRQ_HANDLED; 377 } 378 379 /* Handle device/host interrupt */ 380 if (ci->role != CI_ROLE_END) 381 ret = ci_role(ci)->irq(ci); 382 383 return ret; 384 } 385 386 static int ci_get_platdata(struct device *dev, 387 struct ci_hdrc_platform_data *platdata) 388 { 389 if (!platdata->phy_mode) 390 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node); 391 392 if (!platdata->dr_mode) 393 platdata->dr_mode = of_usb_get_dr_mode(dev->of_node); 394 395 if (platdata->dr_mode == USB_DR_MODE_UNKNOWN) 396 platdata->dr_mode = USB_DR_MODE_OTG; 397 398 if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) { 399 /* Get the vbus regulator */ 400 platdata->reg_vbus = devm_regulator_get(dev, "vbus"); 401 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) { 402 return -EPROBE_DEFER; 403 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) { 404 /* no vbus regualator is needed */ 405 platdata->reg_vbus = NULL; 406 } else if (IS_ERR(platdata->reg_vbus)) { 407 dev_err(dev, "Getting regulator error: %ld\n", 408 PTR_ERR(platdata->reg_vbus)); 409 return PTR_ERR(platdata->reg_vbus); 410 } 411 } 412 413 return 0; 414 } 415 416 static DEFINE_IDA(ci_ida); 417 418 struct platform_device *ci_hdrc_add_device(struct device *dev, 419 struct resource *res, int nres, 420 struct ci_hdrc_platform_data *platdata) 421 { 422 struct platform_device *pdev; 423 int id, ret; 424 425 ret = ci_get_platdata(dev, platdata); 426 if (ret) 427 return ERR_PTR(ret); 428 429 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL); 430 if (id < 0) 431 return ERR_PTR(id); 432 433 pdev = platform_device_alloc("ci_hdrc", id); 434 if (!pdev) { 435 ret = -ENOMEM; 436 goto put_id; 437 } 438 439 pdev->dev.parent = dev; 440 pdev->dev.dma_mask = dev->dma_mask; 441 pdev->dev.dma_parms = dev->dma_parms; 442 dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask); 443 444 ret = platform_device_add_resources(pdev, res, nres); 445 if (ret) 446 goto err; 447 448 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata)); 449 if (ret) 450 goto err; 451 452 ret = platform_device_add(pdev); 453 if (ret) 454 goto err; 455 456 return pdev; 457 458 err: 459 platform_device_put(pdev); 460 put_id: 461 ida_simple_remove(&ci_ida, id); 462 return ERR_PTR(ret); 463 } 464 EXPORT_SYMBOL_GPL(ci_hdrc_add_device); 465 466 void ci_hdrc_remove_device(struct platform_device *pdev) 467 { 468 int id = pdev->id; 469 platform_device_unregister(pdev); 470 ida_simple_remove(&ci_ida, id); 471 } 472 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device); 473 474 static inline void ci_role_destroy(struct ci_hdrc *ci) 475 { 476 ci_hdrc_gadget_destroy(ci); 477 ci_hdrc_host_destroy(ci); 478 if (ci->is_otg) 479 ci_hdrc_otg_destroy(ci); 480 } 481 482 static void ci_get_otg_capable(struct ci_hdrc *ci) 483 { 484 if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG) 485 ci->is_otg = false; 486 else 487 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS, 488 DCCPARAMS_DC | DCCPARAMS_HC) 489 == (DCCPARAMS_DC | DCCPARAMS_HC)); 490 if (ci->is_otg) { 491 dev_dbg(ci->dev, "It is OTG capable controller\n"); 492 ci_disable_otg_interrupt(ci, OTGSC_INT_EN_BITS); 493 ci_clear_otg_interrupt(ci, OTGSC_INT_STATUS_BITS); 494 } 495 } 496 497 static int ci_usb_phy_init(struct ci_hdrc *ci) 498 { 499 if (ci->platdata->phy) { 500 ci->transceiver = ci->platdata->phy; 501 return usb_phy_init(ci->transceiver); 502 } else { 503 ci->global_phy = true; 504 ci->transceiver = usb_get_phy(USB_PHY_TYPE_USB2); 505 if (IS_ERR(ci->transceiver)) 506 ci->transceiver = NULL; 507 508 return 0; 509 } 510 } 511 512 static void ci_usb_phy_destroy(struct ci_hdrc *ci) 513 { 514 if (!ci->transceiver) 515 return; 516 517 otg_set_peripheral(ci->transceiver->otg, NULL); 518 if (ci->global_phy) 519 usb_put_phy(ci->transceiver); 520 else 521 usb_phy_shutdown(ci->transceiver); 522 } 523 524 static int ci_hdrc_probe(struct platform_device *pdev) 525 { 526 struct device *dev = &pdev->dev; 527 struct ci_hdrc *ci; 528 struct resource *res; 529 void __iomem *base; 530 int ret; 531 enum usb_dr_mode dr_mode; 532 533 if (!dev->platform_data) { 534 dev_err(dev, "platform data missing\n"); 535 return -ENODEV; 536 } 537 538 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 539 base = devm_ioremap_resource(dev, res); 540 if (IS_ERR(base)) 541 return PTR_ERR(base); 542 543 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL); 544 if (!ci) { 545 dev_err(dev, "can't allocate device\n"); 546 return -ENOMEM; 547 } 548 549 ci->dev = dev; 550 ci->platdata = dev->platform_data; 551 552 ret = hw_device_init(ci, base); 553 if (ret < 0) { 554 dev_err(dev, "can't initialize hardware\n"); 555 return -ENODEV; 556 } 557 558 ret = ci_usb_phy_init(ci); 559 if (ret) { 560 dev_err(dev, "unable to init phy: %d\n", ret); 561 return ret; 562 } 563 564 ci->hw_bank.phys = res->start; 565 566 ci->irq = platform_get_irq(pdev, 0); 567 if (ci->irq < 0) { 568 dev_err(dev, "missing IRQ\n"); 569 ret = -ENODEV; 570 goto destroy_phy; 571 } 572 573 ci_get_otg_capable(ci); 574 575 hw_phymode_configure(ci); 576 577 dr_mode = ci->platdata->dr_mode; 578 /* initialize role(s) before the interrupt is requested */ 579 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) { 580 ret = ci_hdrc_host_init(ci); 581 if (ret) 582 dev_info(dev, "doesn't support host\n"); 583 } 584 585 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) { 586 ret = ci_hdrc_gadget_init(ci); 587 if (ret) 588 dev_info(dev, "doesn't support gadget\n"); 589 if (!ret && ci->transceiver) { 590 ret = otg_set_peripheral(ci->transceiver->otg, 591 &ci->gadget); 592 /* 593 * If we implement all USB functions using chipidea drivers, 594 * it doesn't need to call above API, meanwhile, if we only 595 * use gadget function, calling above API is useless. 596 */ 597 if (ret && ret != -ENOTSUPP) 598 goto destroy_phy; 599 } 600 } 601 602 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) { 603 dev_err(dev, "no supported roles\n"); 604 ret = -ENODEV; 605 goto destroy_phy; 606 } 607 608 if (ci->is_otg) { 609 ret = ci_hdrc_otg_init(ci); 610 if (ret) { 611 dev_err(dev, "init otg fails, ret = %d\n", ret); 612 goto stop; 613 } 614 } 615 616 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) { 617 if (ci->is_otg) { 618 /* 619 * ID pin needs 1ms debouce time, 620 * we delay 2ms for safe. 621 */ 622 mdelay(2); 623 ci->role = ci_otg_role(ci); 624 ci_enable_otg_interrupt(ci, OTGSC_IDIE); 625 } else { 626 /* 627 * If the controller is not OTG capable, but support 628 * role switch, the defalt role is gadget, and the 629 * user can switch it through debugfs. 630 */ 631 ci->role = CI_ROLE_GADGET; 632 } 633 } else { 634 ci->role = ci->roles[CI_ROLE_HOST] 635 ? CI_ROLE_HOST 636 : CI_ROLE_GADGET; 637 } 638 639 /* only update vbus status for peripheral */ 640 if (ci->role == CI_ROLE_GADGET) 641 ci_handle_vbus_change(ci); 642 643 ret = ci_role_start(ci, ci->role); 644 if (ret) { 645 dev_err(dev, "can't start %s role\n", ci_role(ci)->name); 646 goto stop; 647 } 648 649 platform_set_drvdata(pdev, ci); 650 ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->platdata->name, 651 ci); 652 if (ret) 653 goto stop; 654 655 ret = dbg_create_files(ci); 656 if (!ret) 657 return 0; 658 659 free_irq(ci->irq, ci); 660 stop: 661 ci_role_destroy(ci); 662 destroy_phy: 663 ci_usb_phy_destroy(ci); 664 665 return ret; 666 } 667 668 static int ci_hdrc_remove(struct platform_device *pdev) 669 { 670 struct ci_hdrc *ci = platform_get_drvdata(pdev); 671 672 dbg_remove_files(ci); 673 free_irq(ci->irq, ci); 674 ci_role_destroy(ci); 675 ci_hdrc_enter_lpm(ci, true); 676 ci_usb_phy_destroy(ci); 677 678 return 0; 679 } 680 681 static struct platform_driver ci_hdrc_driver = { 682 .probe = ci_hdrc_probe, 683 .remove = ci_hdrc_remove, 684 .driver = { 685 .name = "ci_hdrc", 686 }, 687 }; 688 689 module_platform_driver(ci_hdrc_driver); 690 691 MODULE_ALIAS("platform:ci_hdrc"); 692 MODULE_LICENSE("GPL v2"); 693 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>"); 694 MODULE_DESCRIPTION("ChipIdea HDRC Driver"); 695