1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * core.c - ChipIdea USB IP core family device controller 4 * 5 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved. 6 * Copyright (C) 2020 NXP 7 * 8 * Author: David Lopo 9 * Peter Chen <peter.chen@nxp.com> 10 * 11 * Main Features: 12 * - Four transfers are supported, usbtest is passed 13 * - USB Certification for gadget: CH9 and Mass Storage are passed 14 * - Low power mode 15 * - USB wakeup 16 */ 17 #include <linux/delay.h> 18 #include <linux/device.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/extcon.h> 21 #include <linux/phy/phy.h> 22 #include <linux/platform_device.h> 23 #include <linux/module.h> 24 #include <linux/idr.h> 25 #include <linux/interrupt.h> 26 #include <linux/io.h> 27 #include <linux/kernel.h> 28 #include <linux/slab.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/pinctrl/consumer.h> 31 #include <linux/usb/ch9.h> 32 #include <linux/usb/gadget.h> 33 #include <linux/usb/otg.h> 34 #include <linux/usb/chipidea.h> 35 #include <linux/usb/of.h> 36 #include <linux/of.h> 37 #include <linux/regulator/consumer.h> 38 #include <linux/usb/ehci_def.h> 39 40 #include "ci.h" 41 #include "udc.h" 42 #include "bits.h" 43 #include "host.h" 44 #include "otg.h" 45 #include "otg_fsm.h" 46 47 /* Controller register map */ 48 static const u8 ci_regs_nolpm[] = { 49 [CAP_CAPLENGTH] = 0x00U, 50 [CAP_HCCPARAMS] = 0x08U, 51 [CAP_DCCPARAMS] = 0x24U, 52 [CAP_TESTMODE] = 0x38U, 53 [OP_USBCMD] = 0x00U, 54 [OP_USBSTS] = 0x04U, 55 [OP_USBINTR] = 0x08U, 56 [OP_DEVICEADDR] = 0x14U, 57 [OP_ENDPTLISTADDR] = 0x18U, 58 [OP_TTCTRL] = 0x1CU, 59 [OP_BURSTSIZE] = 0x20U, 60 [OP_ULPI_VIEWPORT] = 0x30U, 61 [OP_PORTSC] = 0x44U, 62 [OP_DEVLC] = 0x84U, 63 [OP_OTGSC] = 0x64U, 64 [OP_USBMODE] = 0x68U, 65 [OP_ENDPTSETUPSTAT] = 0x6CU, 66 [OP_ENDPTPRIME] = 0x70U, 67 [OP_ENDPTFLUSH] = 0x74U, 68 [OP_ENDPTSTAT] = 0x78U, 69 [OP_ENDPTCOMPLETE] = 0x7CU, 70 [OP_ENDPTCTRL] = 0x80U, 71 }; 72 73 static const u8 ci_regs_lpm[] = { 74 [CAP_CAPLENGTH] = 0x00U, 75 [CAP_HCCPARAMS] = 0x08U, 76 [CAP_DCCPARAMS] = 0x24U, 77 [CAP_TESTMODE] = 0xFCU, 78 [OP_USBCMD] = 0x00U, 79 [OP_USBSTS] = 0x04U, 80 [OP_USBINTR] = 0x08U, 81 [OP_DEVICEADDR] = 0x14U, 82 [OP_ENDPTLISTADDR] = 0x18U, 83 [OP_TTCTRL] = 0x1CU, 84 [OP_BURSTSIZE] = 0x20U, 85 [OP_ULPI_VIEWPORT] = 0x30U, 86 [OP_PORTSC] = 0x44U, 87 [OP_DEVLC] = 0x84U, 88 [OP_OTGSC] = 0xC4U, 89 [OP_USBMODE] = 0xC8U, 90 [OP_ENDPTSETUPSTAT] = 0xD8U, 91 [OP_ENDPTPRIME] = 0xDCU, 92 [OP_ENDPTFLUSH] = 0xE0U, 93 [OP_ENDPTSTAT] = 0xE4U, 94 [OP_ENDPTCOMPLETE] = 0xE8U, 95 [OP_ENDPTCTRL] = 0xECU, 96 }; 97 98 static void hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm) 99 { 100 int i; 101 102 for (i = 0; i < OP_ENDPTCTRL; i++) 103 ci->hw_bank.regmap[i] = 104 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) + 105 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]); 106 107 for (; i <= OP_LAST; i++) 108 ci->hw_bank.regmap[i] = ci->hw_bank.op + 109 4 * (i - OP_ENDPTCTRL) + 110 (is_lpm 111 ? ci_regs_lpm[OP_ENDPTCTRL] 112 : ci_regs_nolpm[OP_ENDPTCTRL]); 113 114 } 115 116 static enum ci_revision ci_get_revision(struct ci_hdrc *ci) 117 { 118 int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION); 119 enum ci_revision rev = CI_REVISION_UNKNOWN; 120 121 if (ver == 0x2) { 122 rev = hw_read_id_reg(ci, ID_ID, REVISION) 123 >> __ffs(REVISION); 124 rev += CI_REVISION_20; 125 } else if (ver == 0x0) { 126 rev = CI_REVISION_1X; 127 } 128 129 return rev; 130 } 131 132 /** 133 * hw_read_intr_enable: returns interrupt enable register 134 * 135 * @ci: the controller 136 * 137 * This function returns register data 138 */ 139 u32 hw_read_intr_enable(struct ci_hdrc *ci) 140 { 141 return hw_read(ci, OP_USBINTR, ~0); 142 } 143 144 /** 145 * hw_read_intr_status: returns interrupt status register 146 * 147 * @ci: the controller 148 * 149 * This function returns register data 150 */ 151 u32 hw_read_intr_status(struct ci_hdrc *ci) 152 { 153 return hw_read(ci, OP_USBSTS, ~0); 154 } 155 156 /** 157 * hw_port_test_set: writes port test mode (execute without interruption) 158 * @ci: the controller 159 * @mode: new value 160 * 161 * This function returns an error code 162 */ 163 int hw_port_test_set(struct ci_hdrc *ci, u8 mode) 164 { 165 const u8 TEST_MODE_MAX = 7; 166 167 if (mode > TEST_MODE_MAX) 168 return -EINVAL; 169 170 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC)); 171 return 0; 172 } 173 174 /** 175 * hw_port_test_get: reads port test mode value 176 * 177 * @ci: the controller 178 * 179 * This function returns port test mode value 180 */ 181 u8 hw_port_test_get(struct ci_hdrc *ci) 182 { 183 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC); 184 } 185 186 static void hw_wait_phy_stable(void) 187 { 188 /* 189 * The phy needs some delay to output the stable status from low 190 * power mode. And for OTGSC, the status inputs are debounced 191 * using a 1 ms time constant, so, delay 2ms for controller to get 192 * the stable status, like vbus and id when the phy leaves low power. 193 */ 194 usleep_range(2000, 2500); 195 } 196 197 /* The PHY enters/leaves low power mode */ 198 static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable) 199 { 200 enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC; 201 bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm))); 202 203 if (enable && !lpm) 204 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), 205 PORTSC_PHCD(ci->hw_bank.lpm)); 206 else if (!enable && lpm) 207 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), 208 0); 209 } 210 211 static int hw_device_init(struct ci_hdrc *ci, void __iomem *base) 212 { 213 u32 reg; 214 215 /* bank is a module variable */ 216 ci->hw_bank.abs = base; 217 218 ci->hw_bank.cap = ci->hw_bank.abs; 219 ci->hw_bank.cap += ci->platdata->capoffset; 220 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff); 221 222 hw_alloc_regmap(ci, false); 223 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >> 224 __ffs(HCCPARAMS_LEN); 225 ci->hw_bank.lpm = reg; 226 if (reg) 227 hw_alloc_regmap(ci, !!reg); 228 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs; 229 ci->hw_bank.size += OP_LAST; 230 ci->hw_bank.size /= sizeof(u32); 231 232 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >> 233 __ffs(DCCPARAMS_DEN); 234 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */ 235 236 if (ci->hw_ep_max > ENDPT_MAX) 237 return -ENODEV; 238 239 ci_hdrc_enter_lpm(ci, false); 240 241 /* Disable all interrupts bits */ 242 hw_write(ci, OP_USBINTR, 0xffffffff, 0); 243 244 /* Clear all interrupts status bits*/ 245 hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff); 246 247 ci->rev = ci_get_revision(ci); 248 249 dev_dbg(ci->dev, 250 "revision: %d, lpm: %d; cap: %px op: %px\n", 251 ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op); 252 253 /* setup lock mode ? */ 254 255 /* ENDPTSETUPSTAT is '0' by default */ 256 257 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */ 258 259 return 0; 260 } 261 262 void hw_phymode_configure(struct ci_hdrc *ci) 263 { 264 u32 portsc, lpm, sts = 0; 265 266 switch (ci->platdata->phy_mode) { 267 case USBPHY_INTERFACE_MODE_UTMI: 268 portsc = PORTSC_PTS(PTS_UTMI); 269 lpm = DEVLC_PTS(PTS_UTMI); 270 break; 271 case USBPHY_INTERFACE_MODE_UTMIW: 272 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW; 273 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW; 274 break; 275 case USBPHY_INTERFACE_MODE_ULPI: 276 portsc = PORTSC_PTS(PTS_ULPI); 277 lpm = DEVLC_PTS(PTS_ULPI); 278 break; 279 case USBPHY_INTERFACE_MODE_SERIAL: 280 portsc = PORTSC_PTS(PTS_SERIAL); 281 lpm = DEVLC_PTS(PTS_SERIAL); 282 sts = 1; 283 break; 284 case USBPHY_INTERFACE_MODE_HSIC: 285 portsc = PORTSC_PTS(PTS_HSIC); 286 lpm = DEVLC_PTS(PTS_HSIC); 287 break; 288 default: 289 return; 290 } 291 292 if (ci->hw_bank.lpm) { 293 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm); 294 if (sts) 295 hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS); 296 } else { 297 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc); 298 if (sts) 299 hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS); 300 } 301 } 302 EXPORT_SYMBOL_GPL(hw_phymode_configure); 303 304 /** 305 * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy 306 * interfaces 307 * @ci: the controller 308 * 309 * This function returns an error code if the phy failed to init 310 */ 311 static int _ci_usb_phy_init(struct ci_hdrc *ci) 312 { 313 int ret; 314 315 if (ci->phy) { 316 ret = phy_init(ci->phy); 317 if (ret) 318 return ret; 319 320 ret = phy_power_on(ci->phy); 321 if (ret) { 322 phy_exit(ci->phy); 323 return ret; 324 } 325 } else { 326 ret = usb_phy_init(ci->usb_phy); 327 } 328 329 return ret; 330 } 331 332 /** 333 * _ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy 334 * interfaces 335 * @ci: the controller 336 */ 337 static void ci_usb_phy_exit(struct ci_hdrc *ci) 338 { 339 if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL) 340 return; 341 342 if (ci->phy) { 343 phy_power_off(ci->phy); 344 phy_exit(ci->phy); 345 } else { 346 usb_phy_shutdown(ci->usb_phy); 347 } 348 } 349 350 /** 351 * ci_usb_phy_init: initialize phy according to different phy type 352 * @ci: the controller 353 * 354 * This function returns an error code if usb_phy_init has failed 355 */ 356 static int ci_usb_phy_init(struct ci_hdrc *ci) 357 { 358 int ret; 359 360 if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL) 361 return 0; 362 363 switch (ci->platdata->phy_mode) { 364 case USBPHY_INTERFACE_MODE_UTMI: 365 case USBPHY_INTERFACE_MODE_UTMIW: 366 case USBPHY_INTERFACE_MODE_HSIC: 367 ret = _ci_usb_phy_init(ci); 368 if (!ret) 369 hw_wait_phy_stable(); 370 else 371 return ret; 372 hw_phymode_configure(ci); 373 break; 374 case USBPHY_INTERFACE_MODE_ULPI: 375 case USBPHY_INTERFACE_MODE_SERIAL: 376 hw_phymode_configure(ci); 377 ret = _ci_usb_phy_init(ci); 378 if (ret) 379 return ret; 380 break; 381 default: 382 ret = _ci_usb_phy_init(ci); 383 if (!ret) 384 hw_wait_phy_stable(); 385 } 386 387 return ret; 388 } 389 390 391 /** 392 * ci_platform_configure: do controller configure 393 * @ci: the controller 394 * 395 */ 396 void ci_platform_configure(struct ci_hdrc *ci) 397 { 398 bool is_device_mode, is_host_mode; 399 400 is_device_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_DC; 401 is_host_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_HC; 402 403 if (is_device_mode) { 404 phy_set_mode(ci->phy, PHY_MODE_USB_DEVICE); 405 406 if (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING) 407 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, 408 USBMODE_CI_SDIS); 409 } 410 411 if (is_host_mode) { 412 phy_set_mode(ci->phy, PHY_MODE_USB_HOST); 413 414 if (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING) 415 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, 416 USBMODE_CI_SDIS); 417 } 418 419 if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) { 420 if (ci->hw_bank.lpm) 421 hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC); 422 else 423 hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC); 424 } 425 426 if (ci->platdata->flags & CI_HDRC_SET_NON_ZERO_TTHA) 427 hw_write(ci, OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA); 428 429 hw_write(ci, OP_USBCMD, 0xff0000, ci->platdata->itc_setting << 16); 430 431 if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST) 432 hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK, 433 ci->platdata->ahb_burst_config); 434 435 /* override burst size, take effect only when ahb_burst_config is 0 */ 436 if (!hw_read_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK)) { 437 if (ci->platdata->flags & CI_HDRC_OVERRIDE_TX_BURST) 438 hw_write(ci, OP_BURSTSIZE, TX_BURST_MASK, 439 ci->platdata->tx_burst_size << __ffs(TX_BURST_MASK)); 440 441 if (ci->platdata->flags & CI_HDRC_OVERRIDE_RX_BURST) 442 hw_write(ci, OP_BURSTSIZE, RX_BURST_MASK, 443 ci->platdata->rx_burst_size); 444 } 445 } 446 447 /** 448 * hw_controller_reset: do controller reset 449 * @ci: the controller 450 * 451 * This function returns an error code 452 */ 453 static int hw_controller_reset(struct ci_hdrc *ci) 454 { 455 int count = 0; 456 457 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST); 458 while (hw_read(ci, OP_USBCMD, USBCMD_RST)) { 459 udelay(10); 460 if (count++ > 1000) 461 return -ETIMEDOUT; 462 } 463 464 return 0; 465 } 466 467 /** 468 * hw_device_reset: resets chip (execute without interruption) 469 * @ci: the controller 470 * 471 * This function returns an error code 472 */ 473 int hw_device_reset(struct ci_hdrc *ci) 474 { 475 int ret; 476 477 /* should flush & stop before reset */ 478 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0); 479 hw_write(ci, OP_USBCMD, USBCMD_RS, 0); 480 481 ret = hw_controller_reset(ci); 482 if (ret) { 483 dev_err(ci->dev, "error resetting controller, ret=%d\n", ret); 484 return ret; 485 } 486 487 if (ci->platdata->notify_event) { 488 ret = ci->platdata->notify_event(ci, 489 CI_HDRC_CONTROLLER_RESET_EVENT); 490 if (ret) 491 return ret; 492 } 493 494 /* USBMODE should be configured step by step */ 495 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE); 496 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC); 497 /* HW >= 2.3 */ 498 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM); 499 500 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) { 501 dev_err(ci->dev, "cannot enter in %s device mode\n", 502 ci_role(ci)->name); 503 dev_err(ci->dev, "lpm = %i\n", ci->hw_bank.lpm); 504 return -ENODEV; 505 } 506 507 ci_platform_configure(ci); 508 509 return 0; 510 } 511 512 static irqreturn_t ci_irq(int irq, void *data) 513 { 514 struct ci_hdrc *ci = data; 515 irqreturn_t ret = IRQ_NONE; 516 u32 otgsc = 0; 517 518 if (ci->in_lpm) { 519 disable_irq_nosync(irq); 520 ci->wakeup_int = true; 521 pm_runtime_get(ci->dev); 522 return IRQ_HANDLED; 523 } 524 525 if (ci->is_otg) { 526 otgsc = hw_read_otgsc(ci, ~0); 527 if (ci_otg_is_fsm_mode(ci)) { 528 ret = ci_otg_fsm_irq(ci); 529 if (ret == IRQ_HANDLED) 530 return ret; 531 } 532 } 533 534 /* 535 * Handle id change interrupt, it indicates device/host function 536 * switch. 537 */ 538 if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) { 539 ci->id_event = true; 540 /* Clear ID change irq status */ 541 hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS); 542 ci_otg_queue_work(ci); 543 return IRQ_HANDLED; 544 } 545 546 /* 547 * Handle vbus change interrupt, it indicates device connection 548 * and disconnection events. 549 */ 550 if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) { 551 ci->b_sess_valid_event = true; 552 /* Clear BSV irq */ 553 hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS); 554 ci_otg_queue_work(ci); 555 return IRQ_HANDLED; 556 } 557 558 /* Handle device/host interrupt */ 559 if (ci->role != CI_ROLE_END) 560 ret = ci_role(ci)->irq(ci); 561 562 return ret; 563 } 564 565 static int ci_cable_notifier(struct notifier_block *nb, unsigned long event, 566 void *ptr) 567 { 568 struct ci_hdrc_cable *cbl = container_of(nb, struct ci_hdrc_cable, nb); 569 struct ci_hdrc *ci = cbl->ci; 570 571 cbl->connected = event; 572 cbl->changed = true; 573 574 ci_irq(ci->irq, ci); 575 return NOTIFY_DONE; 576 } 577 578 static enum usb_role ci_usb_role_switch_get(struct usb_role_switch *sw) 579 { 580 struct ci_hdrc *ci = usb_role_switch_get_drvdata(sw); 581 enum usb_role role; 582 unsigned long flags; 583 584 spin_lock_irqsave(&ci->lock, flags); 585 role = ci_role_to_usb_role(ci); 586 spin_unlock_irqrestore(&ci->lock, flags); 587 588 return role; 589 } 590 591 static int ci_usb_role_switch_set(struct usb_role_switch *sw, 592 enum usb_role role) 593 { 594 struct ci_hdrc *ci = usb_role_switch_get_drvdata(sw); 595 struct ci_hdrc_cable *cable = NULL; 596 enum usb_role current_role = ci_role_to_usb_role(ci); 597 enum ci_role ci_role = usb_role_to_ci_role(role); 598 unsigned long flags; 599 600 if ((ci_role != CI_ROLE_END && !ci->roles[ci_role]) || 601 (current_role == role)) 602 return 0; 603 604 pm_runtime_get_sync(ci->dev); 605 /* Stop current role */ 606 spin_lock_irqsave(&ci->lock, flags); 607 if (current_role == USB_ROLE_DEVICE) 608 cable = &ci->platdata->vbus_extcon; 609 else if (current_role == USB_ROLE_HOST) 610 cable = &ci->platdata->id_extcon; 611 612 if (cable) { 613 cable->changed = true; 614 cable->connected = false; 615 ci_irq(ci->irq, ci); 616 spin_unlock_irqrestore(&ci->lock, flags); 617 if (ci->wq && role != USB_ROLE_NONE) 618 flush_workqueue(ci->wq); 619 spin_lock_irqsave(&ci->lock, flags); 620 } 621 622 cable = NULL; 623 624 /* Start target role */ 625 if (role == USB_ROLE_DEVICE) 626 cable = &ci->platdata->vbus_extcon; 627 else if (role == USB_ROLE_HOST) 628 cable = &ci->platdata->id_extcon; 629 630 if (cable) { 631 cable->changed = true; 632 cable->connected = true; 633 ci_irq(ci->irq, ci); 634 } 635 spin_unlock_irqrestore(&ci->lock, flags); 636 pm_runtime_put_sync(ci->dev); 637 638 return 0; 639 } 640 641 static struct usb_role_switch_desc ci_role_switch = { 642 .set = ci_usb_role_switch_set, 643 .get = ci_usb_role_switch_get, 644 .allow_userspace_control = true, 645 }; 646 647 static int ci_get_platdata(struct device *dev, 648 struct ci_hdrc_platform_data *platdata) 649 { 650 struct extcon_dev *ext_vbus, *ext_id; 651 struct ci_hdrc_cable *cable; 652 int ret; 653 654 if (!platdata->phy_mode) 655 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node); 656 657 if (!platdata->dr_mode) 658 platdata->dr_mode = usb_get_dr_mode(dev); 659 660 if (platdata->dr_mode == USB_DR_MODE_UNKNOWN) 661 platdata->dr_mode = USB_DR_MODE_OTG; 662 663 if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) { 664 /* Get the vbus regulator */ 665 platdata->reg_vbus = devm_regulator_get_optional(dev, "vbus"); 666 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) { 667 return -EPROBE_DEFER; 668 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) { 669 /* no vbus regulator is needed */ 670 platdata->reg_vbus = NULL; 671 } else if (IS_ERR(platdata->reg_vbus)) { 672 dev_err(dev, "Getting regulator error: %ld\n", 673 PTR_ERR(platdata->reg_vbus)); 674 return PTR_ERR(platdata->reg_vbus); 675 } 676 /* Get TPL support */ 677 if (!platdata->tpl_support) 678 platdata->tpl_support = 679 of_usb_host_tpl_support(dev->of_node); 680 } 681 682 if (platdata->dr_mode == USB_DR_MODE_OTG) { 683 /* We can support HNP and SRP of OTG 2.0 */ 684 platdata->ci_otg_caps.otg_rev = 0x0200; 685 platdata->ci_otg_caps.hnp_support = true; 686 platdata->ci_otg_caps.srp_support = true; 687 688 /* Update otg capabilities by DT properties */ 689 ret = of_usb_update_otg_caps(dev->of_node, 690 &platdata->ci_otg_caps); 691 if (ret) 692 return ret; 693 } 694 695 if (usb_get_maximum_speed(dev) == USB_SPEED_FULL) 696 platdata->flags |= CI_HDRC_FORCE_FULLSPEED; 697 698 of_property_read_u32(dev->of_node, "phy-clkgate-delay-us", 699 &platdata->phy_clkgate_delay_us); 700 701 platdata->itc_setting = 1; 702 703 of_property_read_u32(dev->of_node, "itc-setting", 704 &platdata->itc_setting); 705 706 ret = of_property_read_u32(dev->of_node, "ahb-burst-config", 707 &platdata->ahb_burst_config); 708 if (!ret) { 709 platdata->flags |= CI_HDRC_OVERRIDE_AHB_BURST; 710 } else if (ret != -EINVAL) { 711 dev_err(dev, "failed to get ahb-burst-config\n"); 712 return ret; 713 } 714 715 ret = of_property_read_u32(dev->of_node, "tx-burst-size-dword", 716 &platdata->tx_burst_size); 717 if (!ret) { 718 platdata->flags |= CI_HDRC_OVERRIDE_TX_BURST; 719 } else if (ret != -EINVAL) { 720 dev_err(dev, "failed to get tx-burst-size-dword\n"); 721 return ret; 722 } 723 724 ret = of_property_read_u32(dev->of_node, "rx-burst-size-dword", 725 &platdata->rx_burst_size); 726 if (!ret) { 727 platdata->flags |= CI_HDRC_OVERRIDE_RX_BURST; 728 } else if (ret != -EINVAL) { 729 dev_err(dev, "failed to get rx-burst-size-dword\n"); 730 return ret; 731 } 732 733 if (of_find_property(dev->of_node, "non-zero-ttctrl-ttha", NULL)) 734 platdata->flags |= CI_HDRC_SET_NON_ZERO_TTHA; 735 736 ext_id = ERR_PTR(-ENODEV); 737 ext_vbus = ERR_PTR(-ENODEV); 738 if (of_property_read_bool(dev->of_node, "extcon")) { 739 /* Each one of them is not mandatory */ 740 ext_vbus = extcon_get_edev_by_phandle(dev, 0); 741 if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV) 742 return PTR_ERR(ext_vbus); 743 744 ext_id = extcon_get_edev_by_phandle(dev, 1); 745 if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV) 746 return PTR_ERR(ext_id); 747 } 748 749 cable = &platdata->vbus_extcon; 750 cable->nb.notifier_call = ci_cable_notifier; 751 cable->edev = ext_vbus; 752 753 if (!IS_ERR(ext_vbus)) { 754 ret = extcon_get_state(cable->edev, EXTCON_USB); 755 if (ret) 756 cable->connected = true; 757 else 758 cable->connected = false; 759 } 760 761 cable = &platdata->id_extcon; 762 cable->nb.notifier_call = ci_cable_notifier; 763 cable->edev = ext_id; 764 765 if (!IS_ERR(ext_id)) { 766 ret = extcon_get_state(cable->edev, EXTCON_USB_HOST); 767 if (ret) 768 cable->connected = true; 769 else 770 cable->connected = false; 771 } 772 773 if (device_property_read_bool(dev, "usb-role-switch")) 774 ci_role_switch.fwnode = dev->fwnode; 775 776 platdata->pctl = devm_pinctrl_get(dev); 777 if (!IS_ERR(platdata->pctl)) { 778 struct pinctrl_state *p; 779 780 p = pinctrl_lookup_state(platdata->pctl, "default"); 781 if (!IS_ERR(p)) 782 platdata->pins_default = p; 783 784 p = pinctrl_lookup_state(platdata->pctl, "host"); 785 if (!IS_ERR(p)) 786 platdata->pins_host = p; 787 788 p = pinctrl_lookup_state(platdata->pctl, "device"); 789 if (!IS_ERR(p)) 790 platdata->pins_device = p; 791 } 792 793 return 0; 794 } 795 796 static int ci_extcon_register(struct ci_hdrc *ci) 797 { 798 struct ci_hdrc_cable *id, *vbus; 799 int ret; 800 801 id = &ci->platdata->id_extcon; 802 id->ci = ci; 803 if (!IS_ERR_OR_NULL(id->edev)) { 804 ret = devm_extcon_register_notifier(ci->dev, id->edev, 805 EXTCON_USB_HOST, &id->nb); 806 if (ret < 0) { 807 dev_err(ci->dev, "register ID failed\n"); 808 return ret; 809 } 810 } 811 812 vbus = &ci->platdata->vbus_extcon; 813 vbus->ci = ci; 814 if (!IS_ERR_OR_NULL(vbus->edev)) { 815 ret = devm_extcon_register_notifier(ci->dev, vbus->edev, 816 EXTCON_USB, &vbus->nb); 817 if (ret < 0) { 818 dev_err(ci->dev, "register VBUS failed\n"); 819 return ret; 820 } 821 } 822 823 return 0; 824 } 825 826 static DEFINE_IDA(ci_ida); 827 828 struct platform_device *ci_hdrc_add_device(struct device *dev, 829 struct resource *res, int nres, 830 struct ci_hdrc_platform_data *platdata) 831 { 832 struct platform_device *pdev; 833 int id, ret; 834 835 ret = ci_get_platdata(dev, platdata); 836 if (ret) 837 return ERR_PTR(ret); 838 839 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL); 840 if (id < 0) 841 return ERR_PTR(id); 842 843 pdev = platform_device_alloc("ci_hdrc", id); 844 if (!pdev) { 845 ret = -ENOMEM; 846 goto put_id; 847 } 848 849 pdev->dev.parent = dev; 850 851 ret = platform_device_add_resources(pdev, res, nres); 852 if (ret) 853 goto err; 854 855 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata)); 856 if (ret) 857 goto err; 858 859 ret = platform_device_add(pdev); 860 if (ret) 861 goto err; 862 863 return pdev; 864 865 err: 866 platform_device_put(pdev); 867 put_id: 868 ida_simple_remove(&ci_ida, id); 869 return ERR_PTR(ret); 870 } 871 EXPORT_SYMBOL_GPL(ci_hdrc_add_device); 872 873 void ci_hdrc_remove_device(struct platform_device *pdev) 874 { 875 int id = pdev->id; 876 platform_device_unregister(pdev); 877 ida_simple_remove(&ci_ida, id); 878 } 879 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device); 880 881 static inline void ci_role_destroy(struct ci_hdrc *ci) 882 { 883 ci_hdrc_gadget_destroy(ci); 884 ci_hdrc_host_destroy(ci); 885 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) 886 ci_hdrc_otg_destroy(ci); 887 } 888 889 static void ci_get_otg_capable(struct ci_hdrc *ci) 890 { 891 if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG) 892 ci->is_otg = false; 893 else 894 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS, 895 DCCPARAMS_DC | DCCPARAMS_HC) 896 == (DCCPARAMS_DC | DCCPARAMS_HC)); 897 if (ci->is_otg) { 898 dev_dbg(ci->dev, "It is OTG capable controller\n"); 899 /* Disable and clear all OTG irq */ 900 hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS, 901 OTGSC_INT_STATUS_BITS); 902 } 903 } 904 905 static ssize_t role_show(struct device *dev, struct device_attribute *attr, 906 char *buf) 907 { 908 struct ci_hdrc *ci = dev_get_drvdata(dev); 909 910 if (ci->role != CI_ROLE_END) 911 return sprintf(buf, "%s\n", ci_role(ci)->name); 912 913 return 0; 914 } 915 916 static ssize_t role_store(struct device *dev, 917 struct device_attribute *attr, const char *buf, size_t n) 918 { 919 struct ci_hdrc *ci = dev_get_drvdata(dev); 920 enum ci_role role; 921 int ret; 922 923 if (!(ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET])) { 924 dev_warn(dev, "Current configuration is not dual-role, quit\n"); 925 return -EPERM; 926 } 927 928 for (role = CI_ROLE_HOST; role < CI_ROLE_END; role++) 929 if (!strncmp(buf, ci->roles[role]->name, 930 strlen(ci->roles[role]->name))) 931 break; 932 933 if (role == CI_ROLE_END || role == ci->role) 934 return -EINVAL; 935 936 pm_runtime_get_sync(dev); 937 disable_irq(ci->irq); 938 ci_role_stop(ci); 939 ret = ci_role_start(ci, role); 940 if (!ret && ci->role == CI_ROLE_GADGET) 941 ci_handle_vbus_change(ci); 942 enable_irq(ci->irq); 943 pm_runtime_put_sync(dev); 944 945 return (ret == 0) ? n : ret; 946 } 947 static DEVICE_ATTR_RW(role); 948 949 static struct attribute *ci_attrs[] = { 950 &dev_attr_role.attr, 951 NULL, 952 }; 953 ATTRIBUTE_GROUPS(ci); 954 955 static int ci_hdrc_probe(struct platform_device *pdev) 956 { 957 struct device *dev = &pdev->dev; 958 struct ci_hdrc *ci; 959 struct resource *res; 960 void __iomem *base; 961 int ret; 962 enum usb_dr_mode dr_mode; 963 964 if (!dev_get_platdata(dev)) { 965 dev_err(dev, "platform data missing\n"); 966 return -ENODEV; 967 } 968 969 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 970 base = devm_ioremap_resource(dev, res); 971 if (IS_ERR(base)) 972 return PTR_ERR(base); 973 974 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL); 975 if (!ci) 976 return -ENOMEM; 977 978 spin_lock_init(&ci->lock); 979 ci->dev = dev; 980 ci->platdata = dev_get_platdata(dev); 981 ci->imx28_write_fix = !!(ci->platdata->flags & 982 CI_HDRC_IMX28_WRITE_FIX); 983 ci->supports_runtime_pm = !!(ci->platdata->flags & 984 CI_HDRC_SUPPORTS_RUNTIME_PM); 985 platform_set_drvdata(pdev, ci); 986 987 ret = hw_device_init(ci, base); 988 if (ret < 0) { 989 dev_err(dev, "can't initialize hardware\n"); 990 return -ENODEV; 991 } 992 993 ret = ci_ulpi_init(ci); 994 if (ret) 995 return ret; 996 997 if (ci->platdata->phy) { 998 ci->phy = ci->platdata->phy; 999 } else if (ci->platdata->usb_phy) { 1000 ci->usb_phy = ci->platdata->usb_phy; 1001 } else { 1002 /* Look for a generic PHY first */ 1003 ci->phy = devm_phy_get(dev->parent, "usb-phy"); 1004 1005 if (PTR_ERR(ci->phy) == -EPROBE_DEFER) { 1006 ret = -EPROBE_DEFER; 1007 goto ulpi_exit; 1008 } else if (IS_ERR(ci->phy)) { 1009 ci->phy = NULL; 1010 } 1011 1012 /* Look for a legacy USB PHY from device-tree next */ 1013 if (!ci->phy) { 1014 ci->usb_phy = devm_usb_get_phy_by_phandle(dev->parent, 1015 "phys", 0); 1016 1017 if (PTR_ERR(ci->usb_phy) == -EPROBE_DEFER) { 1018 ret = -EPROBE_DEFER; 1019 goto ulpi_exit; 1020 } else if (IS_ERR(ci->usb_phy)) { 1021 ci->usb_phy = NULL; 1022 } 1023 } 1024 1025 /* Look for any registered legacy USB PHY as last resort */ 1026 if (!ci->phy && !ci->usb_phy) { 1027 ci->usb_phy = devm_usb_get_phy(dev->parent, 1028 USB_PHY_TYPE_USB2); 1029 1030 if (PTR_ERR(ci->usb_phy) == -EPROBE_DEFER) { 1031 ret = -EPROBE_DEFER; 1032 goto ulpi_exit; 1033 } else if (IS_ERR(ci->usb_phy)) { 1034 ci->usb_phy = NULL; 1035 } 1036 } 1037 1038 /* No USB PHY was found in the end */ 1039 if (!ci->phy && !ci->usb_phy) { 1040 ret = -ENXIO; 1041 goto ulpi_exit; 1042 } 1043 } 1044 1045 ret = ci_usb_phy_init(ci); 1046 if (ret) { 1047 dev_err(dev, "unable to init phy: %d\n", ret); 1048 return ret; 1049 } 1050 1051 ci->hw_bank.phys = res->start; 1052 1053 ci->irq = platform_get_irq(pdev, 0); 1054 if (ci->irq < 0) { 1055 ret = ci->irq; 1056 goto deinit_phy; 1057 } 1058 1059 ci_get_otg_capable(ci); 1060 1061 dr_mode = ci->platdata->dr_mode; 1062 /* initialize role(s) before the interrupt is requested */ 1063 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) { 1064 ret = ci_hdrc_host_init(ci); 1065 if (ret) { 1066 if (ret == -ENXIO) 1067 dev_info(dev, "doesn't support host\n"); 1068 else 1069 goto deinit_phy; 1070 } 1071 } 1072 1073 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) { 1074 ret = ci_hdrc_gadget_init(ci); 1075 if (ret) { 1076 if (ret == -ENXIO) 1077 dev_info(dev, "doesn't support gadget\n"); 1078 else 1079 goto deinit_host; 1080 } 1081 } 1082 1083 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) { 1084 dev_err(dev, "no supported roles\n"); 1085 ret = -ENODEV; 1086 goto deinit_gadget; 1087 } 1088 1089 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) { 1090 ret = ci_hdrc_otg_init(ci); 1091 if (ret) { 1092 dev_err(dev, "init otg fails, ret = %d\n", ret); 1093 goto deinit_gadget; 1094 } 1095 } 1096 1097 if (ci_role_switch.fwnode) { 1098 ci_role_switch.driver_data = ci; 1099 ci->role_switch = usb_role_switch_register(dev, 1100 &ci_role_switch); 1101 if (IS_ERR(ci->role_switch)) { 1102 ret = PTR_ERR(ci->role_switch); 1103 goto deinit_otg; 1104 } 1105 } 1106 1107 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) { 1108 if (ci->is_otg) { 1109 ci->role = ci_otg_role(ci); 1110 /* Enable ID change irq */ 1111 hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE); 1112 } else { 1113 /* 1114 * If the controller is not OTG capable, but support 1115 * role switch, the defalt role is gadget, and the 1116 * user can switch it through debugfs. 1117 */ 1118 ci->role = CI_ROLE_GADGET; 1119 } 1120 } else { 1121 ci->role = ci->roles[CI_ROLE_HOST] 1122 ? CI_ROLE_HOST 1123 : CI_ROLE_GADGET; 1124 } 1125 1126 if (!ci_otg_is_fsm_mode(ci)) { 1127 /* only update vbus status for peripheral */ 1128 if (ci->role == CI_ROLE_GADGET) { 1129 /* Pull down DP for possible charger detection */ 1130 hw_write(ci, OP_USBCMD, USBCMD_RS, 0); 1131 ci_handle_vbus_change(ci); 1132 } 1133 1134 ret = ci_role_start(ci, ci->role); 1135 if (ret) { 1136 dev_err(dev, "can't start %s role\n", 1137 ci_role(ci)->name); 1138 goto stop; 1139 } 1140 } 1141 1142 ret = devm_request_irq(dev, ci->irq, ci_irq, IRQF_SHARED, 1143 ci->platdata->name, ci); 1144 if (ret) 1145 goto stop; 1146 1147 ret = ci_extcon_register(ci); 1148 if (ret) 1149 goto stop; 1150 1151 if (ci->supports_runtime_pm) { 1152 pm_runtime_set_active(&pdev->dev); 1153 pm_runtime_enable(&pdev->dev); 1154 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000); 1155 pm_runtime_mark_last_busy(ci->dev); 1156 pm_runtime_use_autosuspend(&pdev->dev); 1157 } 1158 1159 if (ci_otg_is_fsm_mode(ci)) 1160 ci_hdrc_otg_fsm_start(ci); 1161 1162 device_set_wakeup_capable(&pdev->dev, true); 1163 dbg_create_files(ci); 1164 1165 return 0; 1166 1167 stop: 1168 if (ci->role_switch) 1169 usb_role_switch_unregister(ci->role_switch); 1170 deinit_otg: 1171 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) 1172 ci_hdrc_otg_destroy(ci); 1173 deinit_gadget: 1174 ci_hdrc_gadget_destroy(ci); 1175 deinit_host: 1176 ci_hdrc_host_destroy(ci); 1177 deinit_phy: 1178 ci_usb_phy_exit(ci); 1179 ulpi_exit: 1180 ci_ulpi_exit(ci); 1181 1182 return ret; 1183 } 1184 1185 static int ci_hdrc_remove(struct platform_device *pdev) 1186 { 1187 struct ci_hdrc *ci = platform_get_drvdata(pdev); 1188 1189 if (ci->role_switch) 1190 usb_role_switch_unregister(ci->role_switch); 1191 1192 if (ci->supports_runtime_pm) { 1193 pm_runtime_get_sync(&pdev->dev); 1194 pm_runtime_disable(&pdev->dev); 1195 pm_runtime_put_noidle(&pdev->dev); 1196 } 1197 1198 dbg_remove_files(ci); 1199 ci_role_destroy(ci); 1200 ci_hdrc_enter_lpm(ci, true); 1201 ci_usb_phy_exit(ci); 1202 ci_ulpi_exit(ci); 1203 1204 return 0; 1205 } 1206 1207 #ifdef CONFIG_PM 1208 /* Prepare wakeup by SRP before suspend */ 1209 static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci) 1210 { 1211 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) && 1212 !hw_read_otgsc(ci, OTGSC_ID)) { 1213 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP, 1214 PORTSC_PP); 1215 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN, 1216 PORTSC_WKCN); 1217 } 1218 } 1219 1220 /* Handle SRP when wakeup by data pulse */ 1221 static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci) 1222 { 1223 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) && 1224 (ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) { 1225 if (!hw_read_otgsc(ci, OTGSC_ID)) { 1226 ci->fsm.a_srp_det = 1; 1227 ci->fsm.a_bus_drop = 0; 1228 } else { 1229 ci->fsm.id = 1; 1230 } 1231 ci_otg_queue_work(ci); 1232 } 1233 } 1234 1235 static void ci_controller_suspend(struct ci_hdrc *ci) 1236 { 1237 disable_irq(ci->irq); 1238 ci_hdrc_enter_lpm(ci, true); 1239 if (ci->platdata->phy_clkgate_delay_us) 1240 usleep_range(ci->platdata->phy_clkgate_delay_us, 1241 ci->platdata->phy_clkgate_delay_us + 50); 1242 usb_phy_set_suspend(ci->usb_phy, 1); 1243 ci->in_lpm = true; 1244 enable_irq(ci->irq); 1245 } 1246 1247 /* 1248 * Handle the wakeup interrupt triggered by extcon connector 1249 * We need to call ci_irq again for extcon since the first 1250 * interrupt (wakeup int) only let the controller be out of 1251 * low power mode, but not handle any interrupts. 1252 */ 1253 static void ci_extcon_wakeup_int(struct ci_hdrc *ci) 1254 { 1255 struct ci_hdrc_cable *cable_id, *cable_vbus; 1256 u32 otgsc = hw_read_otgsc(ci, ~0); 1257 1258 cable_id = &ci->platdata->id_extcon; 1259 cable_vbus = &ci->platdata->vbus_extcon; 1260 1261 if (!IS_ERR(cable_id->edev) && ci->is_otg && 1262 (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) 1263 ci_irq(ci->irq, ci); 1264 1265 if (!IS_ERR(cable_vbus->edev) && ci->is_otg && 1266 (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) 1267 ci_irq(ci->irq, ci); 1268 } 1269 1270 static int ci_controller_resume(struct device *dev) 1271 { 1272 struct ci_hdrc *ci = dev_get_drvdata(dev); 1273 int ret; 1274 1275 dev_dbg(dev, "at %s\n", __func__); 1276 1277 if (!ci->in_lpm) { 1278 WARN_ON(1); 1279 return 0; 1280 } 1281 1282 ci_hdrc_enter_lpm(ci, false); 1283 1284 ret = ci_ulpi_resume(ci); 1285 if (ret) 1286 return ret; 1287 1288 if (ci->usb_phy) { 1289 usb_phy_set_suspend(ci->usb_phy, 0); 1290 usb_phy_set_wakeup(ci->usb_phy, false); 1291 hw_wait_phy_stable(); 1292 } 1293 1294 ci->in_lpm = false; 1295 if (ci->wakeup_int) { 1296 ci->wakeup_int = false; 1297 pm_runtime_mark_last_busy(ci->dev); 1298 pm_runtime_put_autosuspend(ci->dev); 1299 enable_irq(ci->irq); 1300 if (ci_otg_is_fsm_mode(ci)) 1301 ci_otg_fsm_wakeup_by_srp(ci); 1302 ci_extcon_wakeup_int(ci); 1303 } 1304 1305 return 0; 1306 } 1307 1308 #ifdef CONFIG_PM_SLEEP 1309 static int ci_suspend(struct device *dev) 1310 { 1311 struct ci_hdrc *ci = dev_get_drvdata(dev); 1312 1313 if (ci->wq) 1314 flush_workqueue(ci->wq); 1315 /* 1316 * Controller needs to be active during suspend, otherwise the core 1317 * may run resume when the parent is at suspend if other driver's 1318 * suspend fails, it occurs before parent's suspend has not started, 1319 * but the core suspend has finished. 1320 */ 1321 if (ci->in_lpm) 1322 pm_runtime_resume(dev); 1323 1324 if (ci->in_lpm) { 1325 WARN_ON(1); 1326 return 0; 1327 } 1328 1329 if (device_may_wakeup(dev)) { 1330 if (ci_otg_is_fsm_mode(ci)) 1331 ci_otg_fsm_suspend_for_srp(ci); 1332 1333 usb_phy_set_wakeup(ci->usb_phy, true); 1334 enable_irq_wake(ci->irq); 1335 } 1336 1337 ci_controller_suspend(ci); 1338 1339 return 0; 1340 } 1341 1342 static int ci_resume(struct device *dev) 1343 { 1344 struct ci_hdrc *ci = dev_get_drvdata(dev); 1345 int ret; 1346 1347 if (device_may_wakeup(dev)) 1348 disable_irq_wake(ci->irq); 1349 1350 ret = ci_controller_resume(dev); 1351 if (ret) 1352 return ret; 1353 1354 if (ci->supports_runtime_pm) { 1355 pm_runtime_disable(dev); 1356 pm_runtime_set_active(dev); 1357 pm_runtime_enable(dev); 1358 } 1359 1360 return ret; 1361 } 1362 #endif /* CONFIG_PM_SLEEP */ 1363 1364 static int ci_runtime_suspend(struct device *dev) 1365 { 1366 struct ci_hdrc *ci = dev_get_drvdata(dev); 1367 1368 dev_dbg(dev, "at %s\n", __func__); 1369 1370 if (ci->in_lpm) { 1371 WARN_ON(1); 1372 return 0; 1373 } 1374 1375 if (ci_otg_is_fsm_mode(ci)) 1376 ci_otg_fsm_suspend_for_srp(ci); 1377 1378 usb_phy_set_wakeup(ci->usb_phy, true); 1379 ci_controller_suspend(ci); 1380 1381 return 0; 1382 } 1383 1384 static int ci_runtime_resume(struct device *dev) 1385 { 1386 return ci_controller_resume(dev); 1387 } 1388 1389 #endif /* CONFIG_PM */ 1390 static const struct dev_pm_ops ci_pm_ops = { 1391 SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume) 1392 SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL) 1393 }; 1394 1395 static struct platform_driver ci_hdrc_driver = { 1396 .probe = ci_hdrc_probe, 1397 .remove = ci_hdrc_remove, 1398 .driver = { 1399 .name = "ci_hdrc", 1400 .pm = &ci_pm_ops, 1401 .dev_groups = ci_groups, 1402 }, 1403 }; 1404 1405 static int __init ci_hdrc_platform_register(void) 1406 { 1407 ci_hdrc_host_driver_init(); 1408 return platform_driver_register(&ci_hdrc_driver); 1409 } 1410 module_init(ci_hdrc_platform_register); 1411 1412 static void __exit ci_hdrc_platform_unregister(void) 1413 { 1414 platform_driver_unregister(&ci_hdrc_driver); 1415 } 1416 module_exit(ci_hdrc_platform_unregister); 1417 1418 MODULE_ALIAS("platform:ci_hdrc"); 1419 MODULE_LICENSE("GPL v2"); 1420 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>"); 1421 MODULE_DESCRIPTION("ChipIdea HDRC Driver"); 1422