1 /* 2 * core.c - ChipIdea USB IP core family device controller 3 * 4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved. 5 * 6 * Author: David Lopo 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 /* 14 * Description: ChipIdea USB IP core family device controller 15 * 16 * This driver is composed of several blocks: 17 * - HW: hardware interface 18 * - DBG: debug facilities (optional) 19 * - UTIL: utilities 20 * - ISR: interrupts handling 21 * - ENDPT: endpoint operations (Gadget API) 22 * - GADGET: gadget operations (Gadget API) 23 * - BUS: bus glue code, bus abstraction layer 24 * 25 * Compile Options 26 * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities 27 * - STALL_IN: non-empty bulk-in pipes cannot be halted 28 * if defined mass storage compliance succeeds but with warnings 29 * => case 4: Hi > Dn 30 * => case 5: Hi > Di 31 * => case 8: Hi <> Do 32 * if undefined usbtest 13 fails 33 * - TRACE: enable function tracing (depends on DEBUG) 34 * 35 * Main Features 36 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage 37 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined) 38 * - Normal & LPM support 39 * 40 * USBTEST Report 41 * - OK: 0-12, 13 (STALL_IN defined) & 14 42 * - Not Supported: 15 & 16 (ISO) 43 * 44 * TODO List 45 * - OTG 46 * - Interrupt Traffic 47 * - GET_STATUS(device) - always reports 0 48 * - Gadget API (majority of optional features) 49 * - Suspend & Remote Wakeup 50 */ 51 #include <linux/delay.h> 52 #include <linux/device.h> 53 #include <linux/dma-mapping.h> 54 #include <linux/platform_device.h> 55 #include <linux/module.h> 56 #include <linux/idr.h> 57 #include <linux/interrupt.h> 58 #include <linux/io.h> 59 #include <linux/kernel.h> 60 #include <linux/slab.h> 61 #include <linux/pm_runtime.h> 62 #include <linux/usb/ch9.h> 63 #include <linux/usb/gadget.h> 64 #include <linux/usb/otg.h> 65 #include <linux/usb/chipidea.h> 66 #include <linux/usb/of.h> 67 #include <linux/phy.h> 68 #include <linux/regulator/consumer.h> 69 70 #include "ci.h" 71 #include "udc.h" 72 #include "bits.h" 73 #include "host.h" 74 #include "debug.h" 75 #include "otg.h" 76 77 /* Controller register map */ 78 static uintptr_t ci_regs_nolpm[] = { 79 [CAP_CAPLENGTH] = 0x000UL, 80 [CAP_HCCPARAMS] = 0x008UL, 81 [CAP_DCCPARAMS] = 0x024UL, 82 [CAP_TESTMODE] = 0x038UL, 83 [OP_USBCMD] = 0x000UL, 84 [OP_USBSTS] = 0x004UL, 85 [OP_USBINTR] = 0x008UL, 86 [OP_DEVICEADDR] = 0x014UL, 87 [OP_ENDPTLISTADDR] = 0x018UL, 88 [OP_PORTSC] = 0x044UL, 89 [OP_DEVLC] = 0x084UL, 90 [OP_OTGSC] = 0x064UL, 91 [OP_USBMODE] = 0x068UL, 92 [OP_ENDPTSETUPSTAT] = 0x06CUL, 93 [OP_ENDPTPRIME] = 0x070UL, 94 [OP_ENDPTFLUSH] = 0x074UL, 95 [OP_ENDPTSTAT] = 0x078UL, 96 [OP_ENDPTCOMPLETE] = 0x07CUL, 97 [OP_ENDPTCTRL] = 0x080UL, 98 }; 99 100 static uintptr_t ci_regs_lpm[] = { 101 [CAP_CAPLENGTH] = 0x000UL, 102 [CAP_HCCPARAMS] = 0x008UL, 103 [CAP_DCCPARAMS] = 0x024UL, 104 [CAP_TESTMODE] = 0x0FCUL, 105 [OP_USBCMD] = 0x000UL, 106 [OP_USBSTS] = 0x004UL, 107 [OP_USBINTR] = 0x008UL, 108 [OP_DEVICEADDR] = 0x014UL, 109 [OP_ENDPTLISTADDR] = 0x018UL, 110 [OP_PORTSC] = 0x044UL, 111 [OP_DEVLC] = 0x084UL, 112 [OP_OTGSC] = 0x0C4UL, 113 [OP_USBMODE] = 0x0C8UL, 114 [OP_ENDPTSETUPSTAT] = 0x0D8UL, 115 [OP_ENDPTPRIME] = 0x0DCUL, 116 [OP_ENDPTFLUSH] = 0x0E0UL, 117 [OP_ENDPTSTAT] = 0x0E4UL, 118 [OP_ENDPTCOMPLETE] = 0x0E8UL, 119 [OP_ENDPTCTRL] = 0x0ECUL, 120 }; 121 122 static int hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm) 123 { 124 int i; 125 126 kfree(ci->hw_bank.regmap); 127 128 ci->hw_bank.regmap = kzalloc((OP_LAST + 1) * sizeof(void *), 129 GFP_KERNEL); 130 if (!ci->hw_bank.regmap) 131 return -ENOMEM; 132 133 for (i = 0; i < OP_ENDPTCTRL; i++) 134 ci->hw_bank.regmap[i] = 135 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) + 136 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]); 137 138 for (; i <= OP_LAST; i++) 139 ci->hw_bank.regmap[i] = ci->hw_bank.op + 140 4 * (i - OP_ENDPTCTRL) + 141 (is_lpm 142 ? ci_regs_lpm[OP_ENDPTCTRL] 143 : ci_regs_nolpm[OP_ENDPTCTRL]); 144 145 return 0; 146 } 147 148 /** 149 * hw_port_test_set: writes port test mode (execute without interruption) 150 * @mode: new value 151 * 152 * This function returns an error code 153 */ 154 int hw_port_test_set(struct ci_hdrc *ci, u8 mode) 155 { 156 const u8 TEST_MODE_MAX = 7; 157 158 if (mode > TEST_MODE_MAX) 159 return -EINVAL; 160 161 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC)); 162 return 0; 163 } 164 165 /** 166 * hw_port_test_get: reads port test mode value 167 * 168 * This function returns port test mode value 169 */ 170 u8 hw_port_test_get(struct ci_hdrc *ci) 171 { 172 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC); 173 } 174 175 /* The PHY enters/leaves low power mode */ 176 static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable) 177 { 178 enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC; 179 bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm))); 180 181 if (enable && !lpm) { 182 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), 183 PORTSC_PHCD(ci->hw_bank.lpm)); 184 } else if (!enable && lpm) { 185 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), 186 0); 187 /* 188 * The controller needs at least 1ms to reflect 189 * PHY's status, the PHY also needs some time (less 190 * than 1ms) to leave low power mode. 191 */ 192 usleep_range(1500, 2000); 193 } 194 } 195 196 static int hw_device_init(struct ci_hdrc *ci, void __iomem *base) 197 { 198 u32 reg; 199 200 /* bank is a module variable */ 201 ci->hw_bank.abs = base; 202 203 ci->hw_bank.cap = ci->hw_bank.abs; 204 ci->hw_bank.cap += ci->platdata->capoffset; 205 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff); 206 207 hw_alloc_regmap(ci, false); 208 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >> 209 __ffs(HCCPARAMS_LEN); 210 ci->hw_bank.lpm = reg; 211 if (reg) 212 hw_alloc_regmap(ci, !!reg); 213 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs; 214 ci->hw_bank.size += OP_LAST; 215 ci->hw_bank.size /= sizeof(u32); 216 217 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >> 218 __ffs(DCCPARAMS_DEN); 219 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */ 220 221 if (ci->hw_ep_max > ENDPT_MAX) 222 return -ENODEV; 223 224 ci_hdrc_enter_lpm(ci, false); 225 226 /* Disable all interrupts bits */ 227 hw_write(ci, OP_USBINTR, 0xffffffff, 0); 228 229 /* Clear all interrupts status bits*/ 230 hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff); 231 232 dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n", 233 ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op); 234 235 /* setup lock mode ? */ 236 237 /* ENDPTSETUPSTAT is '0' by default */ 238 239 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */ 240 241 return 0; 242 } 243 244 static void hw_phymode_configure(struct ci_hdrc *ci) 245 { 246 u32 portsc, lpm, sts; 247 248 switch (ci->platdata->phy_mode) { 249 case USBPHY_INTERFACE_MODE_UTMI: 250 portsc = PORTSC_PTS(PTS_UTMI); 251 lpm = DEVLC_PTS(PTS_UTMI); 252 break; 253 case USBPHY_INTERFACE_MODE_UTMIW: 254 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW; 255 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW; 256 break; 257 case USBPHY_INTERFACE_MODE_ULPI: 258 portsc = PORTSC_PTS(PTS_ULPI); 259 lpm = DEVLC_PTS(PTS_ULPI); 260 break; 261 case USBPHY_INTERFACE_MODE_SERIAL: 262 portsc = PORTSC_PTS(PTS_SERIAL); 263 lpm = DEVLC_PTS(PTS_SERIAL); 264 sts = 1; 265 break; 266 case USBPHY_INTERFACE_MODE_HSIC: 267 portsc = PORTSC_PTS(PTS_HSIC); 268 lpm = DEVLC_PTS(PTS_HSIC); 269 break; 270 default: 271 return; 272 } 273 274 if (ci->hw_bank.lpm) { 275 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm); 276 hw_write(ci, OP_DEVLC, DEVLC_STS, sts); 277 } else { 278 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc); 279 hw_write(ci, OP_PORTSC, PORTSC_STS, sts); 280 } 281 } 282 283 /** 284 * hw_device_reset: resets chip (execute without interruption) 285 * @ci: the controller 286 * 287 * This function returns an error code 288 */ 289 int hw_device_reset(struct ci_hdrc *ci, u32 mode) 290 { 291 /* should flush & stop before reset */ 292 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0); 293 hw_write(ci, OP_USBCMD, USBCMD_RS, 0); 294 295 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST); 296 while (hw_read(ci, OP_USBCMD, USBCMD_RST)) 297 udelay(10); /* not RTOS friendly */ 298 299 if (ci->platdata->notify_event) 300 ci->platdata->notify_event(ci, 301 CI_HDRC_CONTROLLER_RESET_EVENT); 302 303 if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING) 304 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS); 305 306 /* USBMODE should be configured step by step */ 307 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE); 308 hw_write(ci, OP_USBMODE, USBMODE_CM, mode); 309 /* HW >= 2.3 */ 310 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM); 311 312 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) { 313 pr_err("cannot enter in %s mode", ci_role(ci)->name); 314 pr_err("lpm = %i", ci->hw_bank.lpm); 315 return -ENODEV; 316 } 317 318 return 0; 319 } 320 321 /** 322 * hw_wait_reg: wait the register value 323 * 324 * Sometimes, it needs to wait register value before going on. 325 * Eg, when switch to device mode, the vbus value should be lower 326 * than OTGSC_BSV before connects to host. 327 * 328 * @ci: the controller 329 * @reg: register index 330 * @mask: mast bit 331 * @value: the bit value to wait 332 * @timeout_ms: timeout in millisecond 333 * 334 * This function returns an error code if timeout 335 */ 336 int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask, 337 u32 value, unsigned int timeout_ms) 338 { 339 unsigned long elapse = jiffies + msecs_to_jiffies(timeout_ms); 340 341 while (hw_read(ci, reg, mask) != value) { 342 if (time_after(jiffies, elapse)) { 343 dev_err(ci->dev, "timeout waiting for %08x in %d\n", 344 mask, reg); 345 return -ETIMEDOUT; 346 } 347 msleep(20); 348 } 349 350 return 0; 351 } 352 353 static irqreturn_t ci_irq(int irq, void *data) 354 { 355 struct ci_hdrc *ci = data; 356 irqreturn_t ret = IRQ_NONE; 357 u32 otgsc = 0; 358 359 if (ci->is_otg) 360 otgsc = hw_read(ci, OP_OTGSC, ~0); 361 362 /* 363 * Handle id change interrupt, it indicates device/host function 364 * switch. 365 */ 366 if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) { 367 ci->id_event = true; 368 ci_clear_otg_interrupt(ci, OTGSC_IDIS); 369 disable_irq_nosync(ci->irq); 370 queue_work(ci->wq, &ci->work); 371 return IRQ_HANDLED; 372 } 373 374 /* 375 * Handle vbus change interrupt, it indicates device connection 376 * and disconnection events. 377 */ 378 if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) { 379 ci->b_sess_valid_event = true; 380 ci_clear_otg_interrupt(ci, OTGSC_BSVIS); 381 disable_irq_nosync(ci->irq); 382 queue_work(ci->wq, &ci->work); 383 return IRQ_HANDLED; 384 } 385 386 /* Handle device/host interrupt */ 387 if (ci->role != CI_ROLE_END) 388 ret = ci_role(ci)->irq(ci); 389 390 return ret; 391 } 392 393 static int ci_get_platdata(struct device *dev, 394 struct ci_hdrc_platform_data *platdata) 395 { 396 if (!platdata->phy_mode) 397 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node); 398 399 if (!platdata->dr_mode) 400 platdata->dr_mode = of_usb_get_dr_mode(dev->of_node); 401 402 if (platdata->dr_mode == USB_DR_MODE_UNKNOWN) 403 platdata->dr_mode = USB_DR_MODE_OTG; 404 405 if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) { 406 /* Get the vbus regulator */ 407 platdata->reg_vbus = devm_regulator_get(dev, "vbus"); 408 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) { 409 return -EPROBE_DEFER; 410 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) { 411 /* no vbus regualator is needed */ 412 platdata->reg_vbus = NULL; 413 } else if (IS_ERR(platdata->reg_vbus)) { 414 dev_err(dev, "Getting regulator error: %ld\n", 415 PTR_ERR(platdata->reg_vbus)); 416 return PTR_ERR(platdata->reg_vbus); 417 } 418 } 419 420 return 0; 421 } 422 423 static DEFINE_IDA(ci_ida); 424 425 struct platform_device *ci_hdrc_add_device(struct device *dev, 426 struct resource *res, int nres, 427 struct ci_hdrc_platform_data *platdata) 428 { 429 struct platform_device *pdev; 430 int id, ret; 431 432 ret = ci_get_platdata(dev, platdata); 433 if (ret) 434 return ERR_PTR(ret); 435 436 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL); 437 if (id < 0) 438 return ERR_PTR(id); 439 440 pdev = platform_device_alloc("ci_hdrc", id); 441 if (!pdev) { 442 ret = -ENOMEM; 443 goto put_id; 444 } 445 446 pdev->dev.parent = dev; 447 pdev->dev.dma_mask = dev->dma_mask; 448 pdev->dev.dma_parms = dev->dma_parms; 449 dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask); 450 451 ret = platform_device_add_resources(pdev, res, nres); 452 if (ret) 453 goto err; 454 455 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata)); 456 if (ret) 457 goto err; 458 459 ret = platform_device_add(pdev); 460 if (ret) 461 goto err; 462 463 return pdev; 464 465 err: 466 platform_device_put(pdev); 467 put_id: 468 ida_simple_remove(&ci_ida, id); 469 return ERR_PTR(ret); 470 } 471 EXPORT_SYMBOL_GPL(ci_hdrc_add_device); 472 473 void ci_hdrc_remove_device(struct platform_device *pdev) 474 { 475 int id = pdev->id; 476 platform_device_unregister(pdev); 477 ida_simple_remove(&ci_ida, id); 478 } 479 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device); 480 481 static inline void ci_role_destroy(struct ci_hdrc *ci) 482 { 483 ci_hdrc_gadget_destroy(ci); 484 ci_hdrc_host_destroy(ci); 485 if (ci->is_otg) 486 ci_hdrc_otg_destroy(ci); 487 } 488 489 static void ci_get_otg_capable(struct ci_hdrc *ci) 490 { 491 if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG) 492 ci->is_otg = false; 493 else 494 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS, 495 DCCPARAMS_DC | DCCPARAMS_HC) 496 == (DCCPARAMS_DC | DCCPARAMS_HC)); 497 if (ci->is_otg) { 498 dev_dbg(ci->dev, "It is OTG capable controller\n"); 499 ci_disable_otg_interrupt(ci, OTGSC_INT_EN_BITS); 500 ci_clear_otg_interrupt(ci, OTGSC_INT_STATUS_BITS); 501 } 502 } 503 504 static int ci_usb_phy_init(struct ci_hdrc *ci) 505 { 506 if (ci->platdata->phy) { 507 ci->transceiver = ci->platdata->phy; 508 return usb_phy_init(ci->transceiver); 509 } else { 510 ci->global_phy = true; 511 ci->transceiver = usb_get_phy(USB_PHY_TYPE_USB2); 512 if (IS_ERR(ci->transceiver)) 513 ci->transceiver = NULL; 514 515 return 0; 516 } 517 } 518 519 static void ci_usb_phy_destroy(struct ci_hdrc *ci) 520 { 521 if (!ci->transceiver) 522 return; 523 524 otg_set_peripheral(ci->transceiver->otg, NULL); 525 if (ci->global_phy) 526 usb_put_phy(ci->transceiver); 527 else 528 usb_phy_shutdown(ci->transceiver); 529 } 530 531 static int ci_hdrc_probe(struct platform_device *pdev) 532 { 533 struct device *dev = &pdev->dev; 534 struct ci_hdrc *ci; 535 struct resource *res; 536 void __iomem *base; 537 int ret; 538 enum usb_dr_mode dr_mode; 539 540 if (!dev->platform_data) { 541 dev_err(dev, "platform data missing\n"); 542 return -ENODEV; 543 } 544 545 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 546 base = devm_ioremap_resource(dev, res); 547 if (IS_ERR(base)) 548 return PTR_ERR(base); 549 550 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL); 551 if (!ci) { 552 dev_err(dev, "can't allocate device\n"); 553 return -ENOMEM; 554 } 555 556 ci->dev = dev; 557 ci->platdata = dev->platform_data; 558 559 ret = hw_device_init(ci, base); 560 if (ret < 0) { 561 dev_err(dev, "can't initialize hardware\n"); 562 return -ENODEV; 563 } 564 565 ret = ci_usb_phy_init(ci); 566 if (ret) { 567 dev_err(dev, "unable to init phy: %d\n", ret); 568 return ret; 569 } 570 571 ci->hw_bank.phys = res->start; 572 573 ci->irq = platform_get_irq(pdev, 0); 574 if (ci->irq < 0) { 575 dev_err(dev, "missing IRQ\n"); 576 ret = -ENODEV; 577 goto destroy_phy; 578 } 579 580 ci_get_otg_capable(ci); 581 582 hw_phymode_configure(ci); 583 584 dr_mode = ci->platdata->dr_mode; 585 /* initialize role(s) before the interrupt is requested */ 586 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) { 587 ret = ci_hdrc_host_init(ci); 588 if (ret) 589 dev_info(dev, "doesn't support host\n"); 590 } 591 592 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) { 593 ret = ci_hdrc_gadget_init(ci); 594 if (ret) 595 dev_info(dev, "doesn't support gadget\n"); 596 if (!ret && ci->transceiver) { 597 ret = otg_set_peripheral(ci->transceiver->otg, 598 &ci->gadget); 599 /* 600 * If we implement all USB functions using chipidea drivers, 601 * it doesn't need to call above API, meanwhile, if we only 602 * use gadget function, calling above API is useless. 603 */ 604 if (ret && ret != -ENOTSUPP) 605 goto destroy_phy; 606 } 607 } 608 609 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) { 610 dev_err(dev, "no supported roles\n"); 611 ret = -ENODEV; 612 goto destroy_phy; 613 } 614 615 if (ci->is_otg) { 616 ret = ci_hdrc_otg_init(ci); 617 if (ret) { 618 dev_err(dev, "init otg fails, ret = %d\n", ret); 619 goto stop; 620 } 621 } 622 623 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) { 624 if (ci->is_otg) { 625 /* 626 * ID pin needs 1ms debouce time, 627 * we delay 2ms for safe. 628 */ 629 mdelay(2); 630 ci->role = ci_otg_role(ci); 631 ci_enable_otg_interrupt(ci, OTGSC_IDIE); 632 } else { 633 /* 634 * If the controller is not OTG capable, but support 635 * role switch, the defalt role is gadget, and the 636 * user can switch it through debugfs. 637 */ 638 ci->role = CI_ROLE_GADGET; 639 } 640 } else { 641 ci->role = ci->roles[CI_ROLE_HOST] 642 ? CI_ROLE_HOST 643 : CI_ROLE_GADGET; 644 } 645 646 /* only update vbus status for peripheral */ 647 if (ci->role == CI_ROLE_GADGET) 648 ci_handle_vbus_change(ci); 649 650 ret = ci_role_start(ci, ci->role); 651 if (ret) { 652 dev_err(dev, "can't start %s role\n", ci_role(ci)->name); 653 goto stop; 654 } 655 656 platform_set_drvdata(pdev, ci); 657 ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->platdata->name, 658 ci); 659 if (ret) 660 goto stop; 661 662 ret = dbg_create_files(ci); 663 if (!ret) 664 return 0; 665 666 free_irq(ci->irq, ci); 667 stop: 668 ci_role_destroy(ci); 669 destroy_phy: 670 ci_usb_phy_destroy(ci); 671 672 return ret; 673 } 674 675 static int ci_hdrc_remove(struct platform_device *pdev) 676 { 677 struct ci_hdrc *ci = platform_get_drvdata(pdev); 678 679 dbg_remove_files(ci); 680 free_irq(ci->irq, ci); 681 ci_role_destroy(ci); 682 ci_hdrc_enter_lpm(ci, true); 683 ci_usb_phy_destroy(ci); 684 kfree(ci->hw_bank.regmap); 685 686 return 0; 687 } 688 689 static struct platform_driver ci_hdrc_driver = { 690 .probe = ci_hdrc_probe, 691 .remove = ci_hdrc_remove, 692 .driver = { 693 .name = "ci_hdrc", 694 }, 695 }; 696 697 module_platform_driver(ci_hdrc_driver); 698 699 MODULE_ALIAS("platform:ci_hdrc"); 700 MODULE_LICENSE("GPL v2"); 701 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>"); 702 MODULE_DESCRIPTION("ChipIdea HDRC Driver"); 703