1 /* 2 * core.c - ChipIdea USB IP core family device controller 3 * 4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved. 5 * 6 * Author: David Lopo 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 /* 14 * Description: ChipIdea USB IP core family device controller 15 * 16 * This driver is composed of several blocks: 17 * - HW: hardware interface 18 * - DBG: debug facilities (optional) 19 * - UTIL: utilities 20 * - ISR: interrupts handling 21 * - ENDPT: endpoint operations (Gadget API) 22 * - GADGET: gadget operations (Gadget API) 23 * - BUS: bus glue code, bus abstraction layer 24 * 25 * Compile Options 26 * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities 27 * - STALL_IN: non-empty bulk-in pipes cannot be halted 28 * if defined mass storage compliance succeeds but with warnings 29 * => case 4: Hi > Dn 30 * => case 5: Hi > Di 31 * => case 8: Hi <> Do 32 * if undefined usbtest 13 fails 33 * - TRACE: enable function tracing (depends on DEBUG) 34 * 35 * Main Features 36 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage 37 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined) 38 * - Normal & LPM support 39 * 40 * USBTEST Report 41 * - OK: 0-12, 13 (STALL_IN defined) & 14 42 * - Not Supported: 15 & 16 (ISO) 43 * 44 * TODO List 45 * - OTG 46 * - Isochronous & Interrupt Traffic 47 * - Handle requests which spawns into several TDs 48 * - GET_STATUS(device) - always reports 0 49 * - Gadget API (majority of optional features) 50 * - Suspend & Remote Wakeup 51 */ 52 #include <linux/delay.h> 53 #include <linux/device.h> 54 #include <linux/dma-mapping.h> 55 #include <linux/platform_device.h> 56 #include <linux/module.h> 57 #include <linux/idr.h> 58 #include <linux/interrupt.h> 59 #include <linux/io.h> 60 #include <linux/kernel.h> 61 #include <linux/slab.h> 62 #include <linux/pm_runtime.h> 63 #include <linux/usb/ch9.h> 64 #include <linux/usb/gadget.h> 65 #include <linux/usb/otg.h> 66 #include <linux/usb/chipidea.h> 67 68 #include "ci.h" 69 #include "udc.h" 70 #include "bits.h" 71 #include "host.h" 72 #include "debug.h" 73 74 /* Controller register map */ 75 static uintptr_t ci_regs_nolpm[] = { 76 [CAP_CAPLENGTH] = 0x000UL, 77 [CAP_HCCPARAMS] = 0x008UL, 78 [CAP_DCCPARAMS] = 0x024UL, 79 [CAP_TESTMODE] = 0x038UL, 80 [OP_USBCMD] = 0x000UL, 81 [OP_USBSTS] = 0x004UL, 82 [OP_USBINTR] = 0x008UL, 83 [OP_DEVICEADDR] = 0x014UL, 84 [OP_ENDPTLISTADDR] = 0x018UL, 85 [OP_PORTSC] = 0x044UL, 86 [OP_DEVLC] = 0x084UL, 87 [OP_OTGSC] = 0x064UL, 88 [OP_USBMODE] = 0x068UL, 89 [OP_ENDPTSETUPSTAT] = 0x06CUL, 90 [OP_ENDPTPRIME] = 0x070UL, 91 [OP_ENDPTFLUSH] = 0x074UL, 92 [OP_ENDPTSTAT] = 0x078UL, 93 [OP_ENDPTCOMPLETE] = 0x07CUL, 94 [OP_ENDPTCTRL] = 0x080UL, 95 }; 96 97 static uintptr_t ci_regs_lpm[] = { 98 [CAP_CAPLENGTH] = 0x000UL, 99 [CAP_HCCPARAMS] = 0x008UL, 100 [CAP_DCCPARAMS] = 0x024UL, 101 [CAP_TESTMODE] = 0x0FCUL, 102 [OP_USBCMD] = 0x000UL, 103 [OP_USBSTS] = 0x004UL, 104 [OP_USBINTR] = 0x008UL, 105 [OP_DEVICEADDR] = 0x014UL, 106 [OP_ENDPTLISTADDR] = 0x018UL, 107 [OP_PORTSC] = 0x044UL, 108 [OP_DEVLC] = 0x084UL, 109 [OP_OTGSC] = 0x0C4UL, 110 [OP_USBMODE] = 0x0C8UL, 111 [OP_ENDPTSETUPSTAT] = 0x0D8UL, 112 [OP_ENDPTPRIME] = 0x0DCUL, 113 [OP_ENDPTFLUSH] = 0x0E0UL, 114 [OP_ENDPTSTAT] = 0x0E4UL, 115 [OP_ENDPTCOMPLETE] = 0x0E8UL, 116 [OP_ENDPTCTRL] = 0x0ECUL, 117 }; 118 119 static int hw_alloc_regmap(struct ci13xxx *ci, bool is_lpm) 120 { 121 int i; 122 123 kfree(ci->hw_bank.regmap); 124 125 ci->hw_bank.regmap = kzalloc((OP_LAST + 1) * sizeof(void *), 126 GFP_KERNEL); 127 if (!ci->hw_bank.regmap) 128 return -ENOMEM; 129 130 for (i = 0; i < OP_ENDPTCTRL; i++) 131 ci->hw_bank.regmap[i] = 132 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) + 133 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]); 134 135 for (; i <= OP_LAST; i++) 136 ci->hw_bank.regmap[i] = ci->hw_bank.op + 137 4 * (i - OP_ENDPTCTRL) + 138 (is_lpm 139 ? ci_regs_lpm[OP_ENDPTCTRL] 140 : ci_regs_nolpm[OP_ENDPTCTRL]); 141 142 return 0; 143 } 144 145 /** 146 * hw_port_test_set: writes port test mode (execute without interruption) 147 * @mode: new value 148 * 149 * This function returns an error code 150 */ 151 int hw_port_test_set(struct ci13xxx *ci, u8 mode) 152 { 153 const u8 TEST_MODE_MAX = 7; 154 155 if (mode > TEST_MODE_MAX) 156 return -EINVAL; 157 158 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC)); 159 return 0; 160 } 161 162 /** 163 * hw_port_test_get: reads port test mode value 164 * 165 * This function returns port test mode value 166 */ 167 u8 hw_port_test_get(struct ci13xxx *ci) 168 { 169 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC); 170 } 171 172 static int hw_device_init(struct ci13xxx *ci, void __iomem *base) 173 { 174 u32 reg; 175 176 /* bank is a module variable */ 177 ci->hw_bank.abs = base; 178 179 ci->hw_bank.cap = ci->hw_bank.abs; 180 ci->hw_bank.cap += ci->platdata->capoffset; 181 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff); 182 183 hw_alloc_regmap(ci, false); 184 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >> 185 __ffs(HCCPARAMS_LEN); 186 ci->hw_bank.lpm = reg; 187 hw_alloc_regmap(ci, !!reg); 188 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs; 189 ci->hw_bank.size += OP_LAST; 190 ci->hw_bank.size /= sizeof(u32); 191 192 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >> 193 __ffs(DCCPARAMS_DEN); 194 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */ 195 196 if (ci->hw_ep_max > ENDPT_MAX) 197 return -ENODEV; 198 199 dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n", 200 ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op); 201 202 /* setup lock mode ? */ 203 204 /* ENDPTSETUPSTAT is '0' by default */ 205 206 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */ 207 208 return 0; 209 } 210 211 /** 212 * hw_device_reset: resets chip (execute without interruption) 213 * @ci: the controller 214 * 215 * This function returns an error code 216 */ 217 int hw_device_reset(struct ci13xxx *ci, u32 mode) 218 { 219 /* should flush & stop before reset */ 220 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0); 221 hw_write(ci, OP_USBCMD, USBCMD_RS, 0); 222 223 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST); 224 while (hw_read(ci, OP_USBCMD, USBCMD_RST)) 225 udelay(10); /* not RTOS friendly */ 226 227 228 if (ci->platdata->notify_event) 229 ci->platdata->notify_event(ci, 230 CI13XXX_CONTROLLER_RESET_EVENT); 231 232 if (ci->platdata->flags & CI13XXX_DISABLE_STREAMING) 233 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS); 234 235 /* USBMODE should be configured step by step */ 236 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE); 237 hw_write(ci, OP_USBMODE, USBMODE_CM, mode); 238 /* HW >= 2.3 */ 239 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM); 240 241 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) { 242 pr_err("cannot enter in %s mode", ci_role(ci)->name); 243 pr_err("lpm = %i", ci->hw_bank.lpm); 244 return -ENODEV; 245 } 246 247 return 0; 248 } 249 250 /** 251 * ci_otg_role - pick role based on ID pin state 252 * @ci: the controller 253 */ 254 static enum ci_role ci_otg_role(struct ci13xxx *ci) 255 { 256 u32 sts = hw_read(ci, OP_OTGSC, ~0); 257 enum ci_role role = sts & OTGSC_ID 258 ? CI_ROLE_GADGET 259 : CI_ROLE_HOST; 260 261 return role; 262 } 263 264 /** 265 * ci_role_work - perform role changing based on ID pin 266 * @work: work struct 267 */ 268 static void ci_role_work(struct work_struct *work) 269 { 270 struct ci13xxx *ci = container_of(work, struct ci13xxx, work); 271 enum ci_role role = ci_otg_role(ci); 272 273 if (role != ci->role) { 274 dev_dbg(ci->dev, "switching from %s to %s\n", 275 ci_role(ci)->name, ci->roles[role]->name); 276 277 ci_role_stop(ci); 278 ci_role_start(ci, role); 279 } 280 281 enable_irq(ci->irq); 282 } 283 284 static irqreturn_t ci_irq(int irq, void *data) 285 { 286 struct ci13xxx *ci = data; 287 irqreturn_t ret = IRQ_NONE; 288 u32 otgsc = 0; 289 290 if (ci->is_otg) 291 otgsc = hw_read(ci, OP_OTGSC, ~0); 292 293 if (ci->role != CI_ROLE_END) 294 ret = ci_role(ci)->irq(ci); 295 296 if (ci->is_otg && (otgsc & OTGSC_IDIS)) { 297 hw_write(ci, OP_OTGSC, OTGSC_IDIS, OTGSC_IDIS); 298 disable_irq_nosync(ci->irq); 299 queue_work(ci->wq, &ci->work); 300 ret = IRQ_HANDLED; 301 } 302 303 return ret; 304 } 305 306 static DEFINE_IDA(ci_ida); 307 308 struct platform_device *ci13xxx_add_device(struct device *dev, 309 struct resource *res, int nres, 310 struct ci13xxx_platform_data *platdata) 311 { 312 struct platform_device *pdev; 313 int id, ret; 314 315 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL); 316 if (id < 0) 317 return ERR_PTR(id); 318 319 pdev = platform_device_alloc("ci_hdrc", id); 320 if (!pdev) { 321 ret = -ENOMEM; 322 goto put_id; 323 } 324 325 pdev->dev.parent = dev; 326 pdev->dev.dma_mask = dev->dma_mask; 327 pdev->dev.dma_parms = dev->dma_parms; 328 dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask); 329 330 ret = platform_device_add_resources(pdev, res, nres); 331 if (ret) 332 goto err; 333 334 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata)); 335 if (ret) 336 goto err; 337 338 ret = platform_device_add(pdev); 339 if (ret) 340 goto err; 341 342 return pdev; 343 344 err: 345 platform_device_put(pdev); 346 put_id: 347 ida_simple_remove(&ci_ida, id); 348 return ERR_PTR(ret); 349 } 350 EXPORT_SYMBOL_GPL(ci13xxx_add_device); 351 352 void ci13xxx_remove_device(struct platform_device *pdev) 353 { 354 int id = pdev->id; 355 platform_device_unregister(pdev); 356 ida_simple_remove(&ci_ida, id); 357 } 358 EXPORT_SYMBOL_GPL(ci13xxx_remove_device); 359 360 static int ci_hdrc_probe(struct platform_device *pdev) 361 { 362 struct device *dev = &pdev->dev; 363 struct ci13xxx *ci; 364 struct resource *res; 365 void __iomem *base; 366 int ret; 367 368 if (!dev->platform_data) { 369 dev_err(dev, "platform data missing\n"); 370 return -ENODEV; 371 } 372 373 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 374 base = devm_ioremap_resource(dev, res); 375 if (IS_ERR(base)) 376 return PTR_ERR(base); 377 378 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL); 379 if (!ci) { 380 dev_err(dev, "can't allocate device\n"); 381 return -ENOMEM; 382 } 383 384 ci->dev = dev; 385 ci->platdata = dev->platform_data; 386 if (ci->platdata->phy) 387 ci->transceiver = ci->platdata->phy; 388 else 389 ci->global_phy = true; 390 391 ret = hw_device_init(ci, base); 392 if (ret < 0) { 393 dev_err(dev, "can't initialize hardware\n"); 394 return -ENODEV; 395 } 396 397 ci->hw_bank.phys = res->start; 398 399 ci->irq = platform_get_irq(pdev, 0); 400 if (ci->irq < 0) { 401 dev_err(dev, "missing IRQ\n"); 402 return -ENODEV; 403 } 404 405 INIT_WORK(&ci->work, ci_role_work); 406 ci->wq = create_singlethread_workqueue("ci_otg"); 407 if (!ci->wq) { 408 dev_err(dev, "can't create workqueue\n"); 409 return -ENODEV; 410 } 411 412 /* initialize role(s) before the interrupt is requested */ 413 ret = ci_hdrc_host_init(ci); 414 if (ret) 415 dev_info(dev, "doesn't support host\n"); 416 417 ret = ci_hdrc_gadget_init(ci); 418 if (ret) 419 dev_info(dev, "doesn't support gadget\n"); 420 421 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) { 422 dev_err(dev, "no supported roles\n"); 423 ret = -ENODEV; 424 goto rm_wq; 425 } 426 427 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) { 428 ci->is_otg = true; 429 /* ID pin needs 1ms debouce time, we delay 2ms for safe */ 430 mdelay(2); 431 ci->role = ci_otg_role(ci); 432 } else { 433 ci->role = ci->roles[CI_ROLE_HOST] 434 ? CI_ROLE_HOST 435 : CI_ROLE_GADGET; 436 } 437 438 ret = ci_role_start(ci, ci->role); 439 if (ret) { 440 dev_err(dev, "can't start %s role\n", ci_role(ci)->name); 441 ret = -ENODEV; 442 goto rm_wq; 443 } 444 445 platform_set_drvdata(pdev, ci); 446 ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->platdata->name, 447 ci); 448 if (ret) 449 goto stop; 450 451 if (ci->is_otg) 452 hw_write(ci, OP_OTGSC, OTGSC_IDIE, OTGSC_IDIE); 453 454 ret = dbg_create_files(ci); 455 if (!ret) 456 return 0; 457 458 free_irq(ci->irq, ci); 459 stop: 460 ci_role_stop(ci); 461 rm_wq: 462 flush_workqueue(ci->wq); 463 destroy_workqueue(ci->wq); 464 465 return ret; 466 } 467 468 static int ci_hdrc_remove(struct platform_device *pdev) 469 { 470 struct ci13xxx *ci = platform_get_drvdata(pdev); 471 472 dbg_remove_files(ci); 473 flush_workqueue(ci->wq); 474 destroy_workqueue(ci->wq); 475 free_irq(ci->irq, ci); 476 ci_role_stop(ci); 477 478 return 0; 479 } 480 481 static struct platform_driver ci_hdrc_driver = { 482 .probe = ci_hdrc_probe, 483 .remove = ci_hdrc_remove, 484 .driver = { 485 .name = "ci_hdrc", 486 }, 487 }; 488 489 module_platform_driver(ci_hdrc_driver); 490 491 MODULE_ALIAS("platform:ci_hdrc"); 492 MODULE_ALIAS("platform:ci13xxx"); 493 MODULE_LICENSE("GPL v2"); 494 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>"); 495 MODULE_DESCRIPTION("ChipIdea HDRC Driver"); 496