1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * core.c - ChipIdea USB IP core family device controller 4 * 5 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved. 6 * 7 * Author: David Lopo 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 /* 15 * Description: ChipIdea USB IP core family device controller 16 * 17 * This driver is composed of several blocks: 18 * - HW: hardware interface 19 * - DBG: debug facilities (optional) 20 * - UTIL: utilities 21 * - ISR: interrupts handling 22 * - ENDPT: endpoint operations (Gadget API) 23 * - GADGET: gadget operations (Gadget API) 24 * - BUS: bus glue code, bus abstraction layer 25 * 26 * Compile Options 27 * - STALL_IN: non-empty bulk-in pipes cannot be halted 28 * if defined mass storage compliance succeeds but with warnings 29 * => case 4: Hi > Dn 30 * => case 5: Hi > Di 31 * => case 8: Hi <> Do 32 * if undefined usbtest 13 fails 33 * - TRACE: enable function tracing (depends on DEBUG) 34 * 35 * Main Features 36 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage 37 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined) 38 * - Normal & LPM support 39 * 40 * USBTEST Report 41 * - OK: 0-12, 13 (STALL_IN defined) & 14 42 * - Not Supported: 15 & 16 (ISO) 43 * 44 * TODO List 45 * - Suspend & Remote Wakeup 46 */ 47 #include <linux/delay.h> 48 #include <linux/device.h> 49 #include <linux/dma-mapping.h> 50 #include <linux/extcon.h> 51 #include <linux/phy/phy.h> 52 #include <linux/platform_device.h> 53 #include <linux/module.h> 54 #include <linux/idr.h> 55 #include <linux/interrupt.h> 56 #include <linux/io.h> 57 #include <linux/kernel.h> 58 #include <linux/slab.h> 59 #include <linux/pm_runtime.h> 60 #include <linux/usb/ch9.h> 61 #include <linux/usb/gadget.h> 62 #include <linux/usb/otg.h> 63 #include <linux/usb/chipidea.h> 64 #include <linux/usb/of.h> 65 #include <linux/of.h> 66 #include <linux/regulator/consumer.h> 67 #include <linux/usb/ehci_def.h> 68 69 #include "ci.h" 70 #include "udc.h" 71 #include "bits.h" 72 #include "host.h" 73 #include "otg.h" 74 #include "otg_fsm.h" 75 76 /* Controller register map */ 77 static const u8 ci_regs_nolpm[] = { 78 [CAP_CAPLENGTH] = 0x00U, 79 [CAP_HCCPARAMS] = 0x08U, 80 [CAP_DCCPARAMS] = 0x24U, 81 [CAP_TESTMODE] = 0x38U, 82 [OP_USBCMD] = 0x00U, 83 [OP_USBSTS] = 0x04U, 84 [OP_USBINTR] = 0x08U, 85 [OP_DEVICEADDR] = 0x14U, 86 [OP_ENDPTLISTADDR] = 0x18U, 87 [OP_TTCTRL] = 0x1CU, 88 [OP_BURSTSIZE] = 0x20U, 89 [OP_ULPI_VIEWPORT] = 0x30U, 90 [OP_PORTSC] = 0x44U, 91 [OP_DEVLC] = 0x84U, 92 [OP_OTGSC] = 0x64U, 93 [OP_USBMODE] = 0x68U, 94 [OP_ENDPTSETUPSTAT] = 0x6CU, 95 [OP_ENDPTPRIME] = 0x70U, 96 [OP_ENDPTFLUSH] = 0x74U, 97 [OP_ENDPTSTAT] = 0x78U, 98 [OP_ENDPTCOMPLETE] = 0x7CU, 99 [OP_ENDPTCTRL] = 0x80U, 100 }; 101 102 static const u8 ci_regs_lpm[] = { 103 [CAP_CAPLENGTH] = 0x00U, 104 [CAP_HCCPARAMS] = 0x08U, 105 [CAP_DCCPARAMS] = 0x24U, 106 [CAP_TESTMODE] = 0xFCU, 107 [OP_USBCMD] = 0x00U, 108 [OP_USBSTS] = 0x04U, 109 [OP_USBINTR] = 0x08U, 110 [OP_DEVICEADDR] = 0x14U, 111 [OP_ENDPTLISTADDR] = 0x18U, 112 [OP_TTCTRL] = 0x1CU, 113 [OP_BURSTSIZE] = 0x20U, 114 [OP_ULPI_VIEWPORT] = 0x30U, 115 [OP_PORTSC] = 0x44U, 116 [OP_DEVLC] = 0x84U, 117 [OP_OTGSC] = 0xC4U, 118 [OP_USBMODE] = 0xC8U, 119 [OP_ENDPTSETUPSTAT] = 0xD8U, 120 [OP_ENDPTPRIME] = 0xDCU, 121 [OP_ENDPTFLUSH] = 0xE0U, 122 [OP_ENDPTSTAT] = 0xE4U, 123 [OP_ENDPTCOMPLETE] = 0xE8U, 124 [OP_ENDPTCTRL] = 0xECU, 125 }; 126 127 static void hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm) 128 { 129 int i; 130 131 for (i = 0; i < OP_ENDPTCTRL; i++) 132 ci->hw_bank.regmap[i] = 133 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) + 134 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]); 135 136 for (; i <= OP_LAST; i++) 137 ci->hw_bank.regmap[i] = ci->hw_bank.op + 138 4 * (i - OP_ENDPTCTRL) + 139 (is_lpm 140 ? ci_regs_lpm[OP_ENDPTCTRL] 141 : ci_regs_nolpm[OP_ENDPTCTRL]); 142 143 } 144 145 static enum ci_revision ci_get_revision(struct ci_hdrc *ci) 146 { 147 int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION); 148 enum ci_revision rev = CI_REVISION_UNKNOWN; 149 150 if (ver == 0x2) { 151 rev = hw_read_id_reg(ci, ID_ID, REVISION) 152 >> __ffs(REVISION); 153 rev += CI_REVISION_20; 154 } else if (ver == 0x0) { 155 rev = CI_REVISION_1X; 156 } 157 158 return rev; 159 } 160 161 /** 162 * hw_read_intr_enable: returns interrupt enable register 163 * 164 * @ci: the controller 165 * 166 * This function returns register data 167 */ 168 u32 hw_read_intr_enable(struct ci_hdrc *ci) 169 { 170 return hw_read(ci, OP_USBINTR, ~0); 171 } 172 173 /** 174 * hw_read_intr_status: returns interrupt status register 175 * 176 * @ci: the controller 177 * 178 * This function returns register data 179 */ 180 u32 hw_read_intr_status(struct ci_hdrc *ci) 181 { 182 return hw_read(ci, OP_USBSTS, ~0); 183 } 184 185 /** 186 * hw_port_test_set: writes port test mode (execute without interruption) 187 * @mode: new value 188 * 189 * This function returns an error code 190 */ 191 int hw_port_test_set(struct ci_hdrc *ci, u8 mode) 192 { 193 const u8 TEST_MODE_MAX = 7; 194 195 if (mode > TEST_MODE_MAX) 196 return -EINVAL; 197 198 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC)); 199 return 0; 200 } 201 202 /** 203 * hw_port_test_get: reads port test mode value 204 * 205 * @ci: the controller 206 * 207 * This function returns port test mode value 208 */ 209 u8 hw_port_test_get(struct ci_hdrc *ci) 210 { 211 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC); 212 } 213 214 static void hw_wait_phy_stable(void) 215 { 216 /* 217 * The phy needs some delay to output the stable status from low 218 * power mode. And for OTGSC, the status inputs are debounced 219 * using a 1 ms time constant, so, delay 2ms for controller to get 220 * the stable status, like vbus and id when the phy leaves low power. 221 */ 222 usleep_range(2000, 2500); 223 } 224 225 /* The PHY enters/leaves low power mode */ 226 static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable) 227 { 228 enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC; 229 bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm))); 230 231 if (enable && !lpm) 232 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), 233 PORTSC_PHCD(ci->hw_bank.lpm)); 234 else if (!enable && lpm) 235 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), 236 0); 237 } 238 239 static int hw_device_init(struct ci_hdrc *ci, void __iomem *base) 240 { 241 u32 reg; 242 243 /* bank is a module variable */ 244 ci->hw_bank.abs = base; 245 246 ci->hw_bank.cap = ci->hw_bank.abs; 247 ci->hw_bank.cap += ci->platdata->capoffset; 248 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff); 249 250 hw_alloc_regmap(ci, false); 251 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >> 252 __ffs(HCCPARAMS_LEN); 253 ci->hw_bank.lpm = reg; 254 if (reg) 255 hw_alloc_regmap(ci, !!reg); 256 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs; 257 ci->hw_bank.size += OP_LAST; 258 ci->hw_bank.size /= sizeof(u32); 259 260 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >> 261 __ffs(DCCPARAMS_DEN); 262 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */ 263 264 if (ci->hw_ep_max > ENDPT_MAX) 265 return -ENODEV; 266 267 ci_hdrc_enter_lpm(ci, false); 268 269 /* Disable all interrupts bits */ 270 hw_write(ci, OP_USBINTR, 0xffffffff, 0); 271 272 /* Clear all interrupts status bits*/ 273 hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff); 274 275 ci->rev = ci_get_revision(ci); 276 277 dev_dbg(ci->dev, 278 "ChipIdea HDRC found, revision: %d, lpm: %d; cap: %p op: %p\n", 279 ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op); 280 281 /* setup lock mode ? */ 282 283 /* ENDPTSETUPSTAT is '0' by default */ 284 285 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */ 286 287 return 0; 288 } 289 290 void hw_phymode_configure(struct ci_hdrc *ci) 291 { 292 u32 portsc, lpm, sts = 0; 293 294 switch (ci->platdata->phy_mode) { 295 case USBPHY_INTERFACE_MODE_UTMI: 296 portsc = PORTSC_PTS(PTS_UTMI); 297 lpm = DEVLC_PTS(PTS_UTMI); 298 break; 299 case USBPHY_INTERFACE_MODE_UTMIW: 300 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW; 301 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW; 302 break; 303 case USBPHY_INTERFACE_MODE_ULPI: 304 portsc = PORTSC_PTS(PTS_ULPI); 305 lpm = DEVLC_PTS(PTS_ULPI); 306 break; 307 case USBPHY_INTERFACE_MODE_SERIAL: 308 portsc = PORTSC_PTS(PTS_SERIAL); 309 lpm = DEVLC_PTS(PTS_SERIAL); 310 sts = 1; 311 break; 312 case USBPHY_INTERFACE_MODE_HSIC: 313 portsc = PORTSC_PTS(PTS_HSIC); 314 lpm = DEVLC_PTS(PTS_HSIC); 315 break; 316 default: 317 return; 318 } 319 320 if (ci->hw_bank.lpm) { 321 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm); 322 if (sts) 323 hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS); 324 } else { 325 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc); 326 if (sts) 327 hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS); 328 } 329 } 330 EXPORT_SYMBOL_GPL(hw_phymode_configure); 331 332 /** 333 * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy 334 * interfaces 335 * @ci: the controller 336 * 337 * This function returns an error code if the phy failed to init 338 */ 339 static int _ci_usb_phy_init(struct ci_hdrc *ci) 340 { 341 int ret; 342 343 if (ci->phy) { 344 ret = phy_init(ci->phy); 345 if (ret) 346 return ret; 347 348 ret = phy_power_on(ci->phy); 349 if (ret) { 350 phy_exit(ci->phy); 351 return ret; 352 } 353 } else { 354 ret = usb_phy_init(ci->usb_phy); 355 } 356 357 return ret; 358 } 359 360 /** 361 * _ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy 362 * interfaces 363 * @ci: the controller 364 */ 365 static void ci_usb_phy_exit(struct ci_hdrc *ci) 366 { 367 if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL) 368 return; 369 370 if (ci->phy) { 371 phy_power_off(ci->phy); 372 phy_exit(ci->phy); 373 } else { 374 usb_phy_shutdown(ci->usb_phy); 375 } 376 } 377 378 /** 379 * ci_usb_phy_init: initialize phy according to different phy type 380 * @ci: the controller 381 * 382 * This function returns an error code if usb_phy_init has failed 383 */ 384 static int ci_usb_phy_init(struct ci_hdrc *ci) 385 { 386 int ret; 387 388 if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL) 389 return 0; 390 391 switch (ci->platdata->phy_mode) { 392 case USBPHY_INTERFACE_MODE_UTMI: 393 case USBPHY_INTERFACE_MODE_UTMIW: 394 case USBPHY_INTERFACE_MODE_HSIC: 395 ret = _ci_usb_phy_init(ci); 396 if (!ret) 397 hw_wait_phy_stable(); 398 else 399 return ret; 400 hw_phymode_configure(ci); 401 break; 402 case USBPHY_INTERFACE_MODE_ULPI: 403 case USBPHY_INTERFACE_MODE_SERIAL: 404 hw_phymode_configure(ci); 405 ret = _ci_usb_phy_init(ci); 406 if (ret) 407 return ret; 408 break; 409 default: 410 ret = _ci_usb_phy_init(ci); 411 if (!ret) 412 hw_wait_phy_stable(); 413 } 414 415 return ret; 416 } 417 418 419 /** 420 * ci_platform_configure: do controller configure 421 * @ci: the controller 422 * 423 */ 424 void ci_platform_configure(struct ci_hdrc *ci) 425 { 426 bool is_device_mode, is_host_mode; 427 428 is_device_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_DC; 429 is_host_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_HC; 430 431 if (is_device_mode) { 432 phy_set_mode(ci->phy, PHY_MODE_USB_DEVICE); 433 434 if (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING) 435 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, 436 USBMODE_CI_SDIS); 437 } 438 439 if (is_host_mode) { 440 phy_set_mode(ci->phy, PHY_MODE_USB_HOST); 441 442 if (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING) 443 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, 444 USBMODE_CI_SDIS); 445 } 446 447 if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) { 448 if (ci->hw_bank.lpm) 449 hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC); 450 else 451 hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC); 452 } 453 454 if (ci->platdata->flags & CI_HDRC_SET_NON_ZERO_TTHA) 455 hw_write(ci, OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA); 456 457 hw_write(ci, OP_USBCMD, 0xff0000, ci->platdata->itc_setting << 16); 458 459 if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST) 460 hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK, 461 ci->platdata->ahb_burst_config); 462 463 /* override burst size, take effect only when ahb_burst_config is 0 */ 464 if (!hw_read_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK)) { 465 if (ci->platdata->flags & CI_HDRC_OVERRIDE_TX_BURST) 466 hw_write(ci, OP_BURSTSIZE, TX_BURST_MASK, 467 ci->platdata->tx_burst_size << __ffs(TX_BURST_MASK)); 468 469 if (ci->platdata->flags & CI_HDRC_OVERRIDE_RX_BURST) 470 hw_write(ci, OP_BURSTSIZE, RX_BURST_MASK, 471 ci->platdata->rx_burst_size); 472 } 473 } 474 475 /** 476 * hw_controller_reset: do controller reset 477 * @ci: the controller 478 * 479 * This function returns an error code 480 */ 481 static int hw_controller_reset(struct ci_hdrc *ci) 482 { 483 int count = 0; 484 485 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST); 486 while (hw_read(ci, OP_USBCMD, USBCMD_RST)) { 487 udelay(10); 488 if (count++ > 1000) 489 return -ETIMEDOUT; 490 } 491 492 return 0; 493 } 494 495 /** 496 * hw_device_reset: resets chip (execute without interruption) 497 * @ci: the controller 498 * 499 * This function returns an error code 500 */ 501 int hw_device_reset(struct ci_hdrc *ci) 502 { 503 int ret; 504 505 /* should flush & stop before reset */ 506 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0); 507 hw_write(ci, OP_USBCMD, USBCMD_RS, 0); 508 509 ret = hw_controller_reset(ci); 510 if (ret) { 511 dev_err(ci->dev, "error resetting controller, ret=%d\n", ret); 512 return ret; 513 } 514 515 if (ci->platdata->notify_event) { 516 ret = ci->platdata->notify_event(ci, 517 CI_HDRC_CONTROLLER_RESET_EVENT); 518 if (ret) 519 return ret; 520 } 521 522 /* USBMODE should be configured step by step */ 523 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE); 524 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC); 525 /* HW >= 2.3 */ 526 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM); 527 528 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) { 529 pr_err("cannot enter in %s device mode", ci_role(ci)->name); 530 pr_err("lpm = %i", ci->hw_bank.lpm); 531 return -ENODEV; 532 } 533 534 ci_platform_configure(ci); 535 536 return 0; 537 } 538 539 static irqreturn_t ci_irq(int irq, void *data) 540 { 541 struct ci_hdrc *ci = data; 542 irqreturn_t ret = IRQ_NONE; 543 u32 otgsc = 0; 544 545 if (ci->in_lpm) { 546 disable_irq_nosync(irq); 547 ci->wakeup_int = true; 548 pm_runtime_get(ci->dev); 549 return IRQ_HANDLED; 550 } 551 552 if (ci->is_otg) { 553 otgsc = hw_read_otgsc(ci, ~0); 554 if (ci_otg_is_fsm_mode(ci)) { 555 ret = ci_otg_fsm_irq(ci); 556 if (ret == IRQ_HANDLED) 557 return ret; 558 } 559 } 560 561 /* 562 * Handle id change interrupt, it indicates device/host function 563 * switch. 564 */ 565 if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) { 566 ci->id_event = true; 567 /* Clear ID change irq status */ 568 hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS); 569 ci_otg_queue_work(ci); 570 return IRQ_HANDLED; 571 } 572 573 /* 574 * Handle vbus change interrupt, it indicates device connection 575 * and disconnection events. 576 */ 577 if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) { 578 ci->b_sess_valid_event = true; 579 /* Clear BSV irq */ 580 hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS); 581 ci_otg_queue_work(ci); 582 return IRQ_HANDLED; 583 } 584 585 /* Handle device/host interrupt */ 586 if (ci->role != CI_ROLE_END) 587 ret = ci_role(ci)->irq(ci); 588 589 return ret; 590 } 591 592 static int ci_cable_notifier(struct notifier_block *nb, unsigned long event, 593 void *ptr) 594 { 595 struct ci_hdrc_cable *cbl = container_of(nb, struct ci_hdrc_cable, nb); 596 struct ci_hdrc *ci = cbl->ci; 597 598 cbl->connected = event; 599 cbl->changed = true; 600 601 ci_irq(ci->irq, ci); 602 return NOTIFY_DONE; 603 } 604 605 static int ci_get_platdata(struct device *dev, 606 struct ci_hdrc_platform_data *platdata) 607 { 608 struct extcon_dev *ext_vbus, *ext_id; 609 struct ci_hdrc_cable *cable; 610 int ret; 611 612 if (!platdata->phy_mode) 613 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node); 614 615 if (!platdata->dr_mode) 616 platdata->dr_mode = usb_get_dr_mode(dev); 617 618 if (platdata->dr_mode == USB_DR_MODE_UNKNOWN) 619 platdata->dr_mode = USB_DR_MODE_OTG; 620 621 if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) { 622 /* Get the vbus regulator */ 623 platdata->reg_vbus = devm_regulator_get(dev, "vbus"); 624 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) { 625 return -EPROBE_DEFER; 626 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) { 627 /* no vbus regulator is needed */ 628 platdata->reg_vbus = NULL; 629 } else if (IS_ERR(platdata->reg_vbus)) { 630 dev_err(dev, "Getting regulator error: %ld\n", 631 PTR_ERR(platdata->reg_vbus)); 632 return PTR_ERR(platdata->reg_vbus); 633 } 634 /* Get TPL support */ 635 if (!platdata->tpl_support) 636 platdata->tpl_support = 637 of_usb_host_tpl_support(dev->of_node); 638 } 639 640 if (platdata->dr_mode == USB_DR_MODE_OTG) { 641 /* We can support HNP and SRP of OTG 2.0 */ 642 platdata->ci_otg_caps.otg_rev = 0x0200; 643 platdata->ci_otg_caps.hnp_support = true; 644 platdata->ci_otg_caps.srp_support = true; 645 646 /* Update otg capabilities by DT properties */ 647 ret = of_usb_update_otg_caps(dev->of_node, 648 &platdata->ci_otg_caps); 649 if (ret) 650 return ret; 651 } 652 653 if (usb_get_maximum_speed(dev) == USB_SPEED_FULL) 654 platdata->flags |= CI_HDRC_FORCE_FULLSPEED; 655 656 of_property_read_u32(dev->of_node, "phy-clkgate-delay-us", 657 &platdata->phy_clkgate_delay_us); 658 659 platdata->itc_setting = 1; 660 661 of_property_read_u32(dev->of_node, "itc-setting", 662 &platdata->itc_setting); 663 664 ret = of_property_read_u32(dev->of_node, "ahb-burst-config", 665 &platdata->ahb_burst_config); 666 if (!ret) { 667 platdata->flags |= CI_HDRC_OVERRIDE_AHB_BURST; 668 } else if (ret != -EINVAL) { 669 dev_err(dev, "failed to get ahb-burst-config\n"); 670 return ret; 671 } 672 673 ret = of_property_read_u32(dev->of_node, "tx-burst-size-dword", 674 &platdata->tx_burst_size); 675 if (!ret) { 676 platdata->flags |= CI_HDRC_OVERRIDE_TX_BURST; 677 } else if (ret != -EINVAL) { 678 dev_err(dev, "failed to get tx-burst-size-dword\n"); 679 return ret; 680 } 681 682 ret = of_property_read_u32(dev->of_node, "rx-burst-size-dword", 683 &platdata->rx_burst_size); 684 if (!ret) { 685 platdata->flags |= CI_HDRC_OVERRIDE_RX_BURST; 686 } else if (ret != -EINVAL) { 687 dev_err(dev, "failed to get rx-burst-size-dword\n"); 688 return ret; 689 } 690 691 if (of_find_property(dev->of_node, "non-zero-ttctrl-ttha", NULL)) 692 platdata->flags |= CI_HDRC_SET_NON_ZERO_TTHA; 693 694 ext_id = ERR_PTR(-ENODEV); 695 ext_vbus = ERR_PTR(-ENODEV); 696 if (of_property_read_bool(dev->of_node, "extcon")) { 697 /* Each one of them is not mandatory */ 698 ext_vbus = extcon_get_edev_by_phandle(dev, 0); 699 if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV) 700 return PTR_ERR(ext_vbus); 701 702 ext_id = extcon_get_edev_by_phandle(dev, 1); 703 if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV) 704 return PTR_ERR(ext_id); 705 } 706 707 cable = &platdata->vbus_extcon; 708 cable->nb.notifier_call = ci_cable_notifier; 709 cable->edev = ext_vbus; 710 711 if (!IS_ERR(ext_vbus)) { 712 ret = extcon_get_state(cable->edev, EXTCON_USB); 713 if (ret) 714 cable->connected = true; 715 else 716 cable->connected = false; 717 } 718 719 cable = &platdata->id_extcon; 720 cable->nb.notifier_call = ci_cable_notifier; 721 cable->edev = ext_id; 722 723 if (!IS_ERR(ext_id)) { 724 ret = extcon_get_state(cable->edev, EXTCON_USB_HOST); 725 if (ret) 726 cable->connected = true; 727 else 728 cable->connected = false; 729 } 730 return 0; 731 } 732 733 static int ci_extcon_register(struct ci_hdrc *ci) 734 { 735 struct ci_hdrc_cable *id, *vbus; 736 int ret; 737 738 id = &ci->platdata->id_extcon; 739 id->ci = ci; 740 if (!IS_ERR_OR_NULL(id->edev)) { 741 ret = devm_extcon_register_notifier(ci->dev, id->edev, 742 EXTCON_USB_HOST, &id->nb); 743 if (ret < 0) { 744 dev_err(ci->dev, "register ID failed\n"); 745 return ret; 746 } 747 } 748 749 vbus = &ci->platdata->vbus_extcon; 750 vbus->ci = ci; 751 if (!IS_ERR_OR_NULL(vbus->edev)) { 752 ret = devm_extcon_register_notifier(ci->dev, vbus->edev, 753 EXTCON_USB, &vbus->nb); 754 if (ret < 0) { 755 dev_err(ci->dev, "register VBUS failed\n"); 756 return ret; 757 } 758 } 759 760 return 0; 761 } 762 763 static DEFINE_IDA(ci_ida); 764 765 struct platform_device *ci_hdrc_add_device(struct device *dev, 766 struct resource *res, int nres, 767 struct ci_hdrc_platform_data *platdata) 768 { 769 struct platform_device *pdev; 770 int id, ret; 771 772 ret = ci_get_platdata(dev, platdata); 773 if (ret) 774 return ERR_PTR(ret); 775 776 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL); 777 if (id < 0) 778 return ERR_PTR(id); 779 780 pdev = platform_device_alloc("ci_hdrc", id); 781 if (!pdev) { 782 ret = -ENOMEM; 783 goto put_id; 784 } 785 786 pdev->dev.parent = dev; 787 788 ret = platform_device_add_resources(pdev, res, nres); 789 if (ret) 790 goto err; 791 792 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata)); 793 if (ret) 794 goto err; 795 796 ret = platform_device_add(pdev); 797 if (ret) 798 goto err; 799 800 return pdev; 801 802 err: 803 platform_device_put(pdev); 804 put_id: 805 ida_simple_remove(&ci_ida, id); 806 return ERR_PTR(ret); 807 } 808 EXPORT_SYMBOL_GPL(ci_hdrc_add_device); 809 810 void ci_hdrc_remove_device(struct platform_device *pdev) 811 { 812 int id = pdev->id; 813 platform_device_unregister(pdev); 814 ida_simple_remove(&ci_ida, id); 815 } 816 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device); 817 818 static inline void ci_role_destroy(struct ci_hdrc *ci) 819 { 820 ci_hdrc_gadget_destroy(ci); 821 ci_hdrc_host_destroy(ci); 822 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) 823 ci_hdrc_otg_destroy(ci); 824 } 825 826 static void ci_get_otg_capable(struct ci_hdrc *ci) 827 { 828 if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG) 829 ci->is_otg = false; 830 else 831 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS, 832 DCCPARAMS_DC | DCCPARAMS_HC) 833 == (DCCPARAMS_DC | DCCPARAMS_HC)); 834 if (ci->is_otg) { 835 dev_dbg(ci->dev, "It is OTG capable controller\n"); 836 /* Disable and clear all OTG irq */ 837 hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS, 838 OTGSC_INT_STATUS_BITS); 839 } 840 } 841 842 static ssize_t ci_role_show(struct device *dev, struct device_attribute *attr, 843 char *buf) 844 { 845 struct ci_hdrc *ci = dev_get_drvdata(dev); 846 847 if (ci->role != CI_ROLE_END) 848 return sprintf(buf, "%s\n", ci_role(ci)->name); 849 850 return 0; 851 } 852 853 static ssize_t ci_role_store(struct device *dev, 854 struct device_attribute *attr, const char *buf, size_t n) 855 { 856 struct ci_hdrc *ci = dev_get_drvdata(dev); 857 enum ci_role role; 858 int ret; 859 860 if (!(ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET])) { 861 dev_warn(dev, "Current configuration is not dual-role, quit\n"); 862 return -EPERM; 863 } 864 865 for (role = CI_ROLE_HOST; role < CI_ROLE_END; role++) 866 if (!strncmp(buf, ci->roles[role]->name, 867 strlen(ci->roles[role]->name))) 868 break; 869 870 if (role == CI_ROLE_END || role == ci->role) 871 return -EINVAL; 872 873 pm_runtime_get_sync(dev); 874 disable_irq(ci->irq); 875 ci_role_stop(ci); 876 ret = ci_role_start(ci, role); 877 if (!ret && ci->role == CI_ROLE_GADGET) 878 ci_handle_vbus_change(ci); 879 enable_irq(ci->irq); 880 pm_runtime_put_sync(dev); 881 882 return (ret == 0) ? n : ret; 883 } 884 static DEVICE_ATTR(role, 0644, ci_role_show, ci_role_store); 885 886 static struct attribute *ci_attrs[] = { 887 &dev_attr_role.attr, 888 NULL, 889 }; 890 891 static const struct attribute_group ci_attr_group = { 892 .attrs = ci_attrs, 893 }; 894 895 static int ci_hdrc_probe(struct platform_device *pdev) 896 { 897 struct device *dev = &pdev->dev; 898 struct ci_hdrc *ci; 899 struct resource *res; 900 void __iomem *base; 901 int ret; 902 enum usb_dr_mode dr_mode; 903 904 if (!dev_get_platdata(dev)) { 905 dev_err(dev, "platform data missing\n"); 906 return -ENODEV; 907 } 908 909 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 910 base = devm_ioremap_resource(dev, res); 911 if (IS_ERR(base)) 912 return PTR_ERR(base); 913 914 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL); 915 if (!ci) 916 return -ENOMEM; 917 918 spin_lock_init(&ci->lock); 919 ci->dev = dev; 920 ci->platdata = dev_get_platdata(dev); 921 ci->imx28_write_fix = !!(ci->platdata->flags & 922 CI_HDRC_IMX28_WRITE_FIX); 923 ci->supports_runtime_pm = !!(ci->platdata->flags & 924 CI_HDRC_SUPPORTS_RUNTIME_PM); 925 platform_set_drvdata(pdev, ci); 926 927 ret = hw_device_init(ci, base); 928 if (ret < 0) { 929 dev_err(dev, "can't initialize hardware\n"); 930 return -ENODEV; 931 } 932 933 ret = ci_ulpi_init(ci); 934 if (ret) 935 return ret; 936 937 if (ci->platdata->phy) { 938 ci->phy = ci->platdata->phy; 939 } else if (ci->platdata->usb_phy) { 940 ci->usb_phy = ci->platdata->usb_phy; 941 } else { 942 ci->phy = devm_phy_get(dev->parent, "usb-phy"); 943 ci->usb_phy = devm_usb_get_phy(dev->parent, USB_PHY_TYPE_USB2); 944 945 /* if both generic PHY and USB PHY layers aren't enabled */ 946 if (PTR_ERR(ci->phy) == -ENOSYS && 947 PTR_ERR(ci->usb_phy) == -ENXIO) { 948 ret = -ENXIO; 949 goto ulpi_exit; 950 } 951 952 if (IS_ERR(ci->phy) && IS_ERR(ci->usb_phy)) { 953 ret = -EPROBE_DEFER; 954 goto ulpi_exit; 955 } 956 957 if (IS_ERR(ci->phy)) 958 ci->phy = NULL; 959 else if (IS_ERR(ci->usb_phy)) 960 ci->usb_phy = NULL; 961 } 962 963 ret = ci_usb_phy_init(ci); 964 if (ret) { 965 dev_err(dev, "unable to init phy: %d\n", ret); 966 return ret; 967 } 968 969 ci->hw_bank.phys = res->start; 970 971 ci->irq = platform_get_irq(pdev, 0); 972 if (ci->irq < 0) { 973 dev_err(dev, "missing IRQ\n"); 974 ret = ci->irq; 975 goto deinit_phy; 976 } 977 978 ci_get_otg_capable(ci); 979 980 dr_mode = ci->platdata->dr_mode; 981 /* initialize role(s) before the interrupt is requested */ 982 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) { 983 ret = ci_hdrc_host_init(ci); 984 if (ret) { 985 if (ret == -ENXIO) 986 dev_info(dev, "doesn't support host\n"); 987 else 988 goto deinit_phy; 989 } 990 } 991 992 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) { 993 ret = ci_hdrc_gadget_init(ci); 994 if (ret) { 995 if (ret == -ENXIO) 996 dev_info(dev, "doesn't support gadget\n"); 997 else 998 goto deinit_host; 999 } 1000 } 1001 1002 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) { 1003 dev_err(dev, "no supported roles\n"); 1004 ret = -ENODEV; 1005 goto deinit_gadget; 1006 } 1007 1008 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) { 1009 ret = ci_hdrc_otg_init(ci); 1010 if (ret) { 1011 dev_err(dev, "init otg fails, ret = %d\n", ret); 1012 goto deinit_gadget; 1013 } 1014 } 1015 1016 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) { 1017 if (ci->is_otg) { 1018 ci->role = ci_otg_role(ci); 1019 /* Enable ID change irq */ 1020 hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE); 1021 } else { 1022 /* 1023 * If the controller is not OTG capable, but support 1024 * role switch, the defalt role is gadget, and the 1025 * user can switch it through debugfs. 1026 */ 1027 ci->role = CI_ROLE_GADGET; 1028 } 1029 } else { 1030 ci->role = ci->roles[CI_ROLE_HOST] 1031 ? CI_ROLE_HOST 1032 : CI_ROLE_GADGET; 1033 } 1034 1035 if (!ci_otg_is_fsm_mode(ci)) { 1036 /* only update vbus status for peripheral */ 1037 if (ci->role == CI_ROLE_GADGET) 1038 ci_handle_vbus_change(ci); 1039 1040 ret = ci_role_start(ci, ci->role); 1041 if (ret) { 1042 dev_err(dev, "can't start %s role\n", 1043 ci_role(ci)->name); 1044 goto stop; 1045 } 1046 } 1047 1048 ret = devm_request_irq(dev, ci->irq, ci_irq, IRQF_SHARED, 1049 ci->platdata->name, ci); 1050 if (ret) 1051 goto stop; 1052 1053 ret = ci_extcon_register(ci); 1054 if (ret) 1055 goto stop; 1056 1057 if (ci->supports_runtime_pm) { 1058 pm_runtime_set_active(&pdev->dev); 1059 pm_runtime_enable(&pdev->dev); 1060 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000); 1061 pm_runtime_mark_last_busy(ci->dev); 1062 pm_runtime_use_autosuspend(&pdev->dev); 1063 } 1064 1065 if (ci_otg_is_fsm_mode(ci)) 1066 ci_hdrc_otg_fsm_start(ci); 1067 1068 device_set_wakeup_capable(&pdev->dev, true); 1069 ret = dbg_create_files(ci); 1070 if (ret) 1071 goto stop; 1072 1073 ret = sysfs_create_group(&dev->kobj, &ci_attr_group); 1074 if (ret) 1075 goto remove_debug; 1076 1077 return 0; 1078 1079 remove_debug: 1080 dbg_remove_files(ci); 1081 stop: 1082 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) 1083 ci_hdrc_otg_destroy(ci); 1084 deinit_gadget: 1085 ci_hdrc_gadget_destroy(ci); 1086 deinit_host: 1087 ci_hdrc_host_destroy(ci); 1088 deinit_phy: 1089 ci_usb_phy_exit(ci); 1090 ulpi_exit: 1091 ci_ulpi_exit(ci); 1092 1093 return ret; 1094 } 1095 1096 static int ci_hdrc_remove(struct platform_device *pdev) 1097 { 1098 struct ci_hdrc *ci = platform_get_drvdata(pdev); 1099 1100 if (ci->supports_runtime_pm) { 1101 pm_runtime_get_sync(&pdev->dev); 1102 pm_runtime_disable(&pdev->dev); 1103 pm_runtime_put_noidle(&pdev->dev); 1104 } 1105 1106 dbg_remove_files(ci); 1107 sysfs_remove_group(&ci->dev->kobj, &ci_attr_group); 1108 ci_role_destroy(ci); 1109 ci_hdrc_enter_lpm(ci, true); 1110 ci_usb_phy_exit(ci); 1111 ci_ulpi_exit(ci); 1112 1113 return 0; 1114 } 1115 1116 #ifdef CONFIG_PM 1117 /* Prepare wakeup by SRP before suspend */ 1118 static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci) 1119 { 1120 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) && 1121 !hw_read_otgsc(ci, OTGSC_ID)) { 1122 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP, 1123 PORTSC_PP); 1124 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN, 1125 PORTSC_WKCN); 1126 } 1127 } 1128 1129 /* Handle SRP when wakeup by data pulse */ 1130 static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci) 1131 { 1132 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) && 1133 (ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) { 1134 if (!hw_read_otgsc(ci, OTGSC_ID)) { 1135 ci->fsm.a_srp_det = 1; 1136 ci->fsm.a_bus_drop = 0; 1137 } else { 1138 ci->fsm.id = 1; 1139 } 1140 ci_otg_queue_work(ci); 1141 } 1142 } 1143 1144 static void ci_controller_suspend(struct ci_hdrc *ci) 1145 { 1146 disable_irq(ci->irq); 1147 ci_hdrc_enter_lpm(ci, true); 1148 if (ci->platdata->phy_clkgate_delay_us) 1149 usleep_range(ci->platdata->phy_clkgate_delay_us, 1150 ci->platdata->phy_clkgate_delay_us + 50); 1151 usb_phy_set_suspend(ci->usb_phy, 1); 1152 ci->in_lpm = true; 1153 enable_irq(ci->irq); 1154 } 1155 1156 static int ci_controller_resume(struct device *dev) 1157 { 1158 struct ci_hdrc *ci = dev_get_drvdata(dev); 1159 int ret; 1160 1161 dev_dbg(dev, "at %s\n", __func__); 1162 1163 if (!ci->in_lpm) { 1164 WARN_ON(1); 1165 return 0; 1166 } 1167 1168 ci_hdrc_enter_lpm(ci, false); 1169 1170 ret = ci_ulpi_resume(ci); 1171 if (ret) 1172 return ret; 1173 1174 if (ci->usb_phy) { 1175 usb_phy_set_suspend(ci->usb_phy, 0); 1176 usb_phy_set_wakeup(ci->usb_phy, false); 1177 hw_wait_phy_stable(); 1178 } 1179 1180 ci->in_lpm = false; 1181 if (ci->wakeup_int) { 1182 ci->wakeup_int = false; 1183 pm_runtime_mark_last_busy(ci->dev); 1184 pm_runtime_put_autosuspend(ci->dev); 1185 enable_irq(ci->irq); 1186 if (ci_otg_is_fsm_mode(ci)) 1187 ci_otg_fsm_wakeup_by_srp(ci); 1188 } 1189 1190 return 0; 1191 } 1192 1193 #ifdef CONFIG_PM_SLEEP 1194 static int ci_suspend(struct device *dev) 1195 { 1196 struct ci_hdrc *ci = dev_get_drvdata(dev); 1197 1198 if (ci->wq) 1199 flush_workqueue(ci->wq); 1200 /* 1201 * Controller needs to be active during suspend, otherwise the core 1202 * may run resume when the parent is at suspend if other driver's 1203 * suspend fails, it occurs before parent's suspend has not started, 1204 * but the core suspend has finished. 1205 */ 1206 if (ci->in_lpm) 1207 pm_runtime_resume(dev); 1208 1209 if (ci->in_lpm) { 1210 WARN_ON(1); 1211 return 0; 1212 } 1213 1214 if (device_may_wakeup(dev)) { 1215 if (ci_otg_is_fsm_mode(ci)) 1216 ci_otg_fsm_suspend_for_srp(ci); 1217 1218 usb_phy_set_wakeup(ci->usb_phy, true); 1219 enable_irq_wake(ci->irq); 1220 } 1221 1222 ci_controller_suspend(ci); 1223 1224 return 0; 1225 } 1226 1227 static int ci_resume(struct device *dev) 1228 { 1229 struct ci_hdrc *ci = dev_get_drvdata(dev); 1230 int ret; 1231 1232 if (device_may_wakeup(dev)) 1233 disable_irq_wake(ci->irq); 1234 1235 ret = ci_controller_resume(dev); 1236 if (ret) 1237 return ret; 1238 1239 if (ci->supports_runtime_pm) { 1240 pm_runtime_disable(dev); 1241 pm_runtime_set_active(dev); 1242 pm_runtime_enable(dev); 1243 } 1244 1245 return ret; 1246 } 1247 #endif /* CONFIG_PM_SLEEP */ 1248 1249 static int ci_runtime_suspend(struct device *dev) 1250 { 1251 struct ci_hdrc *ci = dev_get_drvdata(dev); 1252 1253 dev_dbg(dev, "at %s\n", __func__); 1254 1255 if (ci->in_lpm) { 1256 WARN_ON(1); 1257 return 0; 1258 } 1259 1260 if (ci_otg_is_fsm_mode(ci)) 1261 ci_otg_fsm_suspend_for_srp(ci); 1262 1263 usb_phy_set_wakeup(ci->usb_phy, true); 1264 ci_controller_suspend(ci); 1265 1266 return 0; 1267 } 1268 1269 static int ci_runtime_resume(struct device *dev) 1270 { 1271 return ci_controller_resume(dev); 1272 } 1273 1274 #endif /* CONFIG_PM */ 1275 static const struct dev_pm_ops ci_pm_ops = { 1276 SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume) 1277 SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL) 1278 }; 1279 1280 static struct platform_driver ci_hdrc_driver = { 1281 .probe = ci_hdrc_probe, 1282 .remove = ci_hdrc_remove, 1283 .driver = { 1284 .name = "ci_hdrc", 1285 .pm = &ci_pm_ops, 1286 }, 1287 }; 1288 1289 static int __init ci_hdrc_platform_register(void) 1290 { 1291 ci_hdrc_host_driver_init(); 1292 return platform_driver_register(&ci_hdrc_driver); 1293 } 1294 module_init(ci_hdrc_platform_register); 1295 1296 static void __exit ci_hdrc_platform_unregister(void) 1297 { 1298 platform_driver_unregister(&ci_hdrc_driver); 1299 } 1300 module_exit(ci_hdrc_platform_unregister); 1301 1302 MODULE_ALIAS("platform:ci_hdrc"); 1303 MODULE_LICENSE("GPL v2"); 1304 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>"); 1305 MODULE_DESCRIPTION("ChipIdea HDRC Driver"); 1306