1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * core.c - ChipIdea USB IP core family device controller 4 * 5 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved. 6 * Copyright (C) 2020 NXP 7 * 8 * Author: David Lopo 9 * Peter Chen <peter.chen@nxp.com> 10 * 11 * Main Features: 12 * - Four transfers are supported, usbtest is passed 13 * - USB Certification for gadget: CH9 and Mass Storage are passed 14 * - Low power mode 15 * - USB wakeup 16 */ 17 #include <linux/delay.h> 18 #include <linux/device.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/extcon.h> 21 #include <linux/phy/phy.h> 22 #include <linux/platform_device.h> 23 #include <linux/module.h> 24 #include <linux/idr.h> 25 #include <linux/interrupt.h> 26 #include <linux/io.h> 27 #include <linux/kernel.h> 28 #include <linux/slab.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/pm_domain.h> 31 #include <linux/pinctrl/consumer.h> 32 #include <linux/usb/ch9.h> 33 #include <linux/usb/gadget.h> 34 #include <linux/usb/otg.h> 35 #include <linux/usb/chipidea.h> 36 #include <linux/usb/of.h> 37 #include <linux/of.h> 38 #include <linux/regulator/consumer.h> 39 #include <linux/usb/ehci_def.h> 40 41 #include "ci.h" 42 #include "udc.h" 43 #include "bits.h" 44 #include "host.h" 45 #include "otg.h" 46 #include "otg_fsm.h" 47 48 /* Controller register map */ 49 static const u8 ci_regs_nolpm[] = { 50 [CAP_CAPLENGTH] = 0x00U, 51 [CAP_HCCPARAMS] = 0x08U, 52 [CAP_DCCPARAMS] = 0x24U, 53 [CAP_TESTMODE] = 0x38U, 54 [OP_USBCMD] = 0x00U, 55 [OP_USBSTS] = 0x04U, 56 [OP_USBINTR] = 0x08U, 57 [OP_FRINDEX] = 0x0CU, 58 [OP_DEVICEADDR] = 0x14U, 59 [OP_ENDPTLISTADDR] = 0x18U, 60 [OP_TTCTRL] = 0x1CU, 61 [OP_BURSTSIZE] = 0x20U, 62 [OP_ULPI_VIEWPORT] = 0x30U, 63 [OP_PORTSC] = 0x44U, 64 [OP_DEVLC] = 0x84U, 65 [OP_OTGSC] = 0x64U, 66 [OP_USBMODE] = 0x68U, 67 [OP_ENDPTSETUPSTAT] = 0x6CU, 68 [OP_ENDPTPRIME] = 0x70U, 69 [OP_ENDPTFLUSH] = 0x74U, 70 [OP_ENDPTSTAT] = 0x78U, 71 [OP_ENDPTCOMPLETE] = 0x7CU, 72 [OP_ENDPTCTRL] = 0x80U, 73 }; 74 75 static const u8 ci_regs_lpm[] = { 76 [CAP_CAPLENGTH] = 0x00U, 77 [CAP_HCCPARAMS] = 0x08U, 78 [CAP_DCCPARAMS] = 0x24U, 79 [CAP_TESTMODE] = 0xFCU, 80 [OP_USBCMD] = 0x00U, 81 [OP_USBSTS] = 0x04U, 82 [OP_USBINTR] = 0x08U, 83 [OP_FRINDEX] = 0x0CU, 84 [OP_DEVICEADDR] = 0x14U, 85 [OP_ENDPTLISTADDR] = 0x18U, 86 [OP_TTCTRL] = 0x1CU, 87 [OP_BURSTSIZE] = 0x20U, 88 [OP_ULPI_VIEWPORT] = 0x30U, 89 [OP_PORTSC] = 0x44U, 90 [OP_DEVLC] = 0x84U, 91 [OP_OTGSC] = 0xC4U, 92 [OP_USBMODE] = 0xC8U, 93 [OP_ENDPTSETUPSTAT] = 0xD8U, 94 [OP_ENDPTPRIME] = 0xDCU, 95 [OP_ENDPTFLUSH] = 0xE0U, 96 [OP_ENDPTSTAT] = 0xE4U, 97 [OP_ENDPTCOMPLETE] = 0xE8U, 98 [OP_ENDPTCTRL] = 0xECU, 99 }; 100 101 static void hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm) 102 { 103 int i; 104 105 for (i = 0; i < OP_ENDPTCTRL; i++) 106 ci->hw_bank.regmap[i] = 107 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) + 108 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]); 109 110 for (; i <= OP_LAST; i++) 111 ci->hw_bank.regmap[i] = ci->hw_bank.op + 112 4 * (i - OP_ENDPTCTRL) + 113 (is_lpm 114 ? ci_regs_lpm[OP_ENDPTCTRL] 115 : ci_regs_nolpm[OP_ENDPTCTRL]); 116 117 } 118 119 static enum ci_revision ci_get_revision(struct ci_hdrc *ci) 120 { 121 int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION); 122 enum ci_revision rev = CI_REVISION_UNKNOWN; 123 124 if (ver == 0x2) { 125 rev = hw_read_id_reg(ci, ID_ID, REVISION) 126 >> __ffs(REVISION); 127 rev += CI_REVISION_20; 128 } else if (ver == 0x0) { 129 rev = CI_REVISION_1X; 130 } 131 132 return rev; 133 } 134 135 /** 136 * hw_read_intr_enable: returns interrupt enable register 137 * 138 * @ci: the controller 139 * 140 * This function returns register data 141 */ 142 u32 hw_read_intr_enable(struct ci_hdrc *ci) 143 { 144 return hw_read(ci, OP_USBINTR, ~0); 145 } 146 147 /** 148 * hw_read_intr_status: returns interrupt status register 149 * 150 * @ci: the controller 151 * 152 * This function returns register data 153 */ 154 u32 hw_read_intr_status(struct ci_hdrc *ci) 155 { 156 return hw_read(ci, OP_USBSTS, ~0); 157 } 158 159 /** 160 * hw_port_test_set: writes port test mode (execute without interruption) 161 * @ci: the controller 162 * @mode: new value 163 * 164 * This function returns an error code 165 */ 166 int hw_port_test_set(struct ci_hdrc *ci, u8 mode) 167 { 168 const u8 TEST_MODE_MAX = 7; 169 170 if (mode > TEST_MODE_MAX) 171 return -EINVAL; 172 173 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC)); 174 return 0; 175 } 176 177 /** 178 * hw_port_test_get: reads port test mode value 179 * 180 * @ci: the controller 181 * 182 * This function returns port test mode value 183 */ 184 u8 hw_port_test_get(struct ci_hdrc *ci) 185 { 186 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC); 187 } 188 189 static void hw_wait_phy_stable(void) 190 { 191 /* 192 * The phy needs some delay to output the stable status from low 193 * power mode. And for OTGSC, the status inputs are debounced 194 * using a 1 ms time constant, so, delay 2ms for controller to get 195 * the stable status, like vbus and id when the phy leaves low power. 196 */ 197 usleep_range(2000, 2500); 198 } 199 200 /* The PHY enters/leaves low power mode */ 201 static void ci_hdrc_enter_lpm_common(struct ci_hdrc *ci, bool enable) 202 { 203 enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC; 204 bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm))); 205 206 if (enable && !lpm) 207 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), 208 PORTSC_PHCD(ci->hw_bank.lpm)); 209 else if (!enable && lpm) 210 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), 211 0); 212 } 213 214 static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable) 215 { 216 return ci->platdata->enter_lpm(ci, enable); 217 } 218 219 static int hw_device_init(struct ci_hdrc *ci, void __iomem *base) 220 { 221 u32 reg; 222 223 /* bank is a module variable */ 224 ci->hw_bank.abs = base; 225 226 ci->hw_bank.cap = ci->hw_bank.abs; 227 ci->hw_bank.cap += ci->platdata->capoffset; 228 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff); 229 230 hw_alloc_regmap(ci, false); 231 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >> 232 __ffs(HCCPARAMS_LEN); 233 ci->hw_bank.lpm = reg; 234 if (reg) 235 hw_alloc_regmap(ci, !!reg); 236 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs; 237 ci->hw_bank.size += OP_LAST; 238 ci->hw_bank.size /= sizeof(u32); 239 240 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >> 241 __ffs(DCCPARAMS_DEN); 242 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */ 243 244 if (ci->hw_ep_max > ENDPT_MAX) 245 return -ENODEV; 246 247 ci_hdrc_enter_lpm(ci, false); 248 249 /* Disable all interrupts bits */ 250 hw_write(ci, OP_USBINTR, 0xffffffff, 0); 251 252 /* Clear all interrupts status bits*/ 253 hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff); 254 255 ci->rev = ci_get_revision(ci); 256 257 dev_dbg(ci->dev, 258 "revision: %d, lpm: %d; cap: %px op: %px\n", 259 ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op); 260 261 /* setup lock mode ? */ 262 263 /* ENDPTSETUPSTAT is '0' by default */ 264 265 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */ 266 267 return 0; 268 } 269 270 void hw_phymode_configure(struct ci_hdrc *ci) 271 { 272 u32 portsc, lpm, sts = 0; 273 274 switch (ci->platdata->phy_mode) { 275 case USBPHY_INTERFACE_MODE_UTMI: 276 portsc = PORTSC_PTS(PTS_UTMI); 277 lpm = DEVLC_PTS(PTS_UTMI); 278 break; 279 case USBPHY_INTERFACE_MODE_UTMIW: 280 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW; 281 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW; 282 break; 283 case USBPHY_INTERFACE_MODE_ULPI: 284 portsc = PORTSC_PTS(PTS_ULPI); 285 lpm = DEVLC_PTS(PTS_ULPI); 286 break; 287 case USBPHY_INTERFACE_MODE_SERIAL: 288 portsc = PORTSC_PTS(PTS_SERIAL); 289 lpm = DEVLC_PTS(PTS_SERIAL); 290 sts = 1; 291 break; 292 case USBPHY_INTERFACE_MODE_HSIC: 293 portsc = PORTSC_PTS(PTS_HSIC); 294 lpm = DEVLC_PTS(PTS_HSIC); 295 break; 296 default: 297 return; 298 } 299 300 if (ci->hw_bank.lpm) { 301 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm); 302 if (sts) 303 hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS); 304 } else { 305 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc); 306 if (sts) 307 hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS); 308 } 309 } 310 EXPORT_SYMBOL_GPL(hw_phymode_configure); 311 312 /** 313 * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy 314 * interfaces 315 * @ci: the controller 316 * 317 * This function returns an error code if the phy failed to init 318 */ 319 static int _ci_usb_phy_init(struct ci_hdrc *ci) 320 { 321 int ret; 322 323 if (ci->phy) { 324 ret = phy_init(ci->phy); 325 if (ret) 326 return ret; 327 328 ret = phy_power_on(ci->phy); 329 if (ret) { 330 phy_exit(ci->phy); 331 return ret; 332 } 333 } else { 334 ret = usb_phy_init(ci->usb_phy); 335 } 336 337 return ret; 338 } 339 340 /** 341 * ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy 342 * interfaces 343 * @ci: the controller 344 */ 345 static void ci_usb_phy_exit(struct ci_hdrc *ci) 346 { 347 if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL) 348 return; 349 350 if (ci->phy) { 351 phy_power_off(ci->phy); 352 phy_exit(ci->phy); 353 } else { 354 usb_phy_shutdown(ci->usb_phy); 355 } 356 } 357 358 /** 359 * ci_usb_phy_init: initialize phy according to different phy type 360 * @ci: the controller 361 * 362 * This function returns an error code if usb_phy_init has failed 363 */ 364 static int ci_usb_phy_init(struct ci_hdrc *ci) 365 { 366 int ret; 367 368 if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL) 369 return 0; 370 371 switch (ci->platdata->phy_mode) { 372 case USBPHY_INTERFACE_MODE_UTMI: 373 case USBPHY_INTERFACE_MODE_UTMIW: 374 case USBPHY_INTERFACE_MODE_HSIC: 375 ret = _ci_usb_phy_init(ci); 376 if (!ret) 377 hw_wait_phy_stable(); 378 else 379 return ret; 380 hw_phymode_configure(ci); 381 break; 382 case USBPHY_INTERFACE_MODE_ULPI: 383 case USBPHY_INTERFACE_MODE_SERIAL: 384 hw_phymode_configure(ci); 385 ret = _ci_usb_phy_init(ci); 386 if (ret) 387 return ret; 388 break; 389 default: 390 ret = _ci_usb_phy_init(ci); 391 if (!ret) 392 hw_wait_phy_stable(); 393 } 394 395 return ret; 396 } 397 398 399 /** 400 * ci_platform_configure: do controller configure 401 * @ci: the controller 402 * 403 */ 404 void ci_platform_configure(struct ci_hdrc *ci) 405 { 406 bool is_device_mode, is_host_mode; 407 408 is_device_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_DC; 409 is_host_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_HC; 410 411 if (is_device_mode) { 412 phy_set_mode(ci->phy, PHY_MODE_USB_DEVICE); 413 414 if (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING) 415 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, 416 USBMODE_CI_SDIS); 417 } 418 419 if (is_host_mode) { 420 phy_set_mode(ci->phy, PHY_MODE_USB_HOST); 421 422 if (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING) 423 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, 424 USBMODE_CI_SDIS); 425 } 426 427 if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) { 428 if (ci->hw_bank.lpm) 429 hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC); 430 else 431 hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC); 432 } 433 434 if (ci->platdata->flags & CI_HDRC_SET_NON_ZERO_TTHA) 435 hw_write(ci, OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA); 436 437 hw_write(ci, OP_USBCMD, 0xff0000, ci->platdata->itc_setting << 16); 438 439 if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST) 440 hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK, 441 ci->platdata->ahb_burst_config); 442 443 /* override burst size, take effect only when ahb_burst_config is 0 */ 444 if (!hw_read_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK)) { 445 if (ci->platdata->flags & CI_HDRC_OVERRIDE_TX_BURST) 446 hw_write(ci, OP_BURSTSIZE, TX_BURST_MASK, 447 ci->platdata->tx_burst_size << __ffs(TX_BURST_MASK)); 448 449 if (ci->platdata->flags & CI_HDRC_OVERRIDE_RX_BURST) 450 hw_write(ci, OP_BURSTSIZE, RX_BURST_MASK, 451 ci->platdata->rx_burst_size); 452 } 453 } 454 455 /** 456 * hw_controller_reset: do controller reset 457 * @ci: the controller 458 * 459 * This function returns an error code 460 */ 461 static int hw_controller_reset(struct ci_hdrc *ci) 462 { 463 int count = 0; 464 465 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST); 466 while (hw_read(ci, OP_USBCMD, USBCMD_RST)) { 467 udelay(10); 468 if (count++ > 1000) 469 return -ETIMEDOUT; 470 } 471 472 return 0; 473 } 474 475 /** 476 * hw_device_reset: resets chip (execute without interruption) 477 * @ci: the controller 478 * 479 * This function returns an error code 480 */ 481 int hw_device_reset(struct ci_hdrc *ci) 482 { 483 int ret; 484 485 /* should flush & stop before reset */ 486 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0); 487 hw_write(ci, OP_USBCMD, USBCMD_RS, 0); 488 489 ret = hw_controller_reset(ci); 490 if (ret) { 491 dev_err(ci->dev, "error resetting controller, ret=%d\n", ret); 492 return ret; 493 } 494 495 if (ci->platdata->notify_event) { 496 ret = ci->platdata->notify_event(ci, 497 CI_HDRC_CONTROLLER_RESET_EVENT); 498 if (ret) 499 return ret; 500 } 501 502 /* USBMODE should be configured step by step */ 503 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE); 504 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC); 505 /* HW >= 2.3 */ 506 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM); 507 508 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) { 509 dev_err(ci->dev, "cannot enter in %s device mode\n", 510 ci_role(ci)->name); 511 dev_err(ci->dev, "lpm = %i\n", ci->hw_bank.lpm); 512 return -ENODEV; 513 } 514 515 ci_platform_configure(ci); 516 517 return 0; 518 } 519 520 static irqreturn_t ci_irq_handler(int irq, void *data) 521 { 522 struct ci_hdrc *ci = data; 523 irqreturn_t ret = IRQ_NONE; 524 u32 otgsc = 0; 525 526 if (ci->in_lpm) { 527 /* 528 * If we already have a wakeup irq pending there, 529 * let's just return to wait resume finished firstly. 530 */ 531 if (ci->wakeup_int) 532 return IRQ_HANDLED; 533 534 disable_irq_nosync(irq); 535 ci->wakeup_int = true; 536 pm_runtime_get(ci->dev); 537 return IRQ_HANDLED; 538 } 539 540 if (ci->is_otg) { 541 otgsc = hw_read_otgsc(ci, ~0); 542 if (ci_otg_is_fsm_mode(ci)) { 543 ret = ci_otg_fsm_irq(ci); 544 if (ret == IRQ_HANDLED) 545 return ret; 546 } 547 } 548 549 /* 550 * Handle id change interrupt, it indicates device/host function 551 * switch. 552 */ 553 if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) { 554 ci->id_event = true; 555 /* Clear ID change irq status */ 556 hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS); 557 ci_otg_queue_work(ci); 558 return IRQ_HANDLED; 559 } 560 561 /* 562 * Handle vbus change interrupt, it indicates device connection 563 * and disconnection events. 564 */ 565 if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) { 566 ci->b_sess_valid_event = true; 567 /* Clear BSV irq */ 568 hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS); 569 ci_otg_queue_work(ci); 570 return IRQ_HANDLED; 571 } 572 573 /* Handle device/host interrupt */ 574 if (ci->role != CI_ROLE_END) 575 ret = ci_role(ci)->irq(ci); 576 577 return ret; 578 } 579 580 static void ci_irq(struct ci_hdrc *ci) 581 { 582 unsigned long flags; 583 584 local_irq_save(flags); 585 ci_irq_handler(ci->irq, ci); 586 local_irq_restore(flags); 587 } 588 589 static int ci_cable_notifier(struct notifier_block *nb, unsigned long event, 590 void *ptr) 591 { 592 struct ci_hdrc_cable *cbl = container_of(nb, struct ci_hdrc_cable, nb); 593 struct ci_hdrc *ci = cbl->ci; 594 595 cbl->connected = event; 596 cbl->changed = true; 597 598 ci_irq(ci); 599 return NOTIFY_DONE; 600 } 601 602 static enum usb_role ci_usb_role_switch_get(struct usb_role_switch *sw) 603 { 604 struct ci_hdrc *ci = usb_role_switch_get_drvdata(sw); 605 enum usb_role role; 606 unsigned long flags; 607 608 spin_lock_irqsave(&ci->lock, flags); 609 role = ci_role_to_usb_role(ci); 610 spin_unlock_irqrestore(&ci->lock, flags); 611 612 return role; 613 } 614 615 static int ci_usb_role_switch_set(struct usb_role_switch *sw, 616 enum usb_role role) 617 { 618 struct ci_hdrc *ci = usb_role_switch_get_drvdata(sw); 619 struct ci_hdrc_cable *cable; 620 621 if (role == USB_ROLE_HOST) { 622 cable = &ci->platdata->id_extcon; 623 cable->changed = true; 624 cable->connected = true; 625 cable = &ci->platdata->vbus_extcon; 626 cable->changed = true; 627 cable->connected = false; 628 } else if (role == USB_ROLE_DEVICE) { 629 cable = &ci->platdata->id_extcon; 630 cable->changed = true; 631 cable->connected = false; 632 cable = &ci->platdata->vbus_extcon; 633 cable->changed = true; 634 cable->connected = true; 635 } else { 636 cable = &ci->platdata->id_extcon; 637 cable->changed = true; 638 cable->connected = false; 639 cable = &ci->platdata->vbus_extcon; 640 cable->changed = true; 641 cable->connected = false; 642 } 643 644 ci_irq(ci); 645 return 0; 646 } 647 648 static enum ci_role ci_get_role(struct ci_hdrc *ci) 649 { 650 enum ci_role role; 651 652 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) { 653 if (ci->is_otg) { 654 role = ci_otg_role(ci); 655 hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE); 656 } else { 657 /* 658 * If the controller is not OTG capable, but support 659 * role switch, the defalt role is gadget, and the 660 * user can switch it through debugfs. 661 */ 662 role = CI_ROLE_GADGET; 663 } 664 } else { 665 role = ci->roles[CI_ROLE_HOST] ? CI_ROLE_HOST 666 : CI_ROLE_GADGET; 667 } 668 669 return role; 670 } 671 672 static struct usb_role_switch_desc ci_role_switch = { 673 .set = ci_usb_role_switch_set, 674 .get = ci_usb_role_switch_get, 675 .allow_userspace_control = true, 676 }; 677 678 static int ci_get_platdata(struct device *dev, 679 struct ci_hdrc_platform_data *platdata) 680 { 681 struct extcon_dev *ext_vbus, *ext_id; 682 struct ci_hdrc_cable *cable; 683 int ret; 684 685 if (!platdata->phy_mode) 686 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node); 687 688 if (!platdata->dr_mode) 689 platdata->dr_mode = usb_get_dr_mode(dev); 690 691 if (platdata->dr_mode == USB_DR_MODE_UNKNOWN) 692 platdata->dr_mode = USB_DR_MODE_OTG; 693 694 if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) { 695 /* Get the vbus regulator */ 696 platdata->reg_vbus = devm_regulator_get_optional(dev, "vbus"); 697 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) { 698 return -EPROBE_DEFER; 699 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) { 700 /* no vbus regulator is needed */ 701 platdata->reg_vbus = NULL; 702 } else if (IS_ERR(platdata->reg_vbus)) { 703 dev_err(dev, "Getting regulator error: %ld\n", 704 PTR_ERR(platdata->reg_vbus)); 705 return PTR_ERR(platdata->reg_vbus); 706 } 707 /* Get TPL support */ 708 if (!platdata->tpl_support) 709 platdata->tpl_support = 710 of_usb_host_tpl_support(dev->of_node); 711 } 712 713 if (platdata->dr_mode == USB_DR_MODE_OTG) { 714 /* We can support HNP and SRP of OTG 2.0 */ 715 platdata->ci_otg_caps.otg_rev = 0x0200; 716 platdata->ci_otg_caps.hnp_support = true; 717 platdata->ci_otg_caps.srp_support = true; 718 719 /* Update otg capabilities by DT properties */ 720 ret = of_usb_update_otg_caps(dev->of_node, 721 &platdata->ci_otg_caps); 722 if (ret) 723 return ret; 724 } 725 726 if (usb_get_maximum_speed(dev) == USB_SPEED_FULL) 727 platdata->flags |= CI_HDRC_FORCE_FULLSPEED; 728 729 of_property_read_u32(dev->of_node, "phy-clkgate-delay-us", 730 &platdata->phy_clkgate_delay_us); 731 732 platdata->itc_setting = 1; 733 734 of_property_read_u32(dev->of_node, "itc-setting", 735 &platdata->itc_setting); 736 737 ret = of_property_read_u32(dev->of_node, "ahb-burst-config", 738 &platdata->ahb_burst_config); 739 if (!ret) { 740 platdata->flags |= CI_HDRC_OVERRIDE_AHB_BURST; 741 } else if (ret != -EINVAL) { 742 dev_err(dev, "failed to get ahb-burst-config\n"); 743 return ret; 744 } 745 746 ret = of_property_read_u32(dev->of_node, "tx-burst-size-dword", 747 &platdata->tx_burst_size); 748 if (!ret) { 749 platdata->flags |= CI_HDRC_OVERRIDE_TX_BURST; 750 } else if (ret != -EINVAL) { 751 dev_err(dev, "failed to get tx-burst-size-dword\n"); 752 return ret; 753 } 754 755 ret = of_property_read_u32(dev->of_node, "rx-burst-size-dword", 756 &platdata->rx_burst_size); 757 if (!ret) { 758 platdata->flags |= CI_HDRC_OVERRIDE_RX_BURST; 759 } else if (ret != -EINVAL) { 760 dev_err(dev, "failed to get rx-burst-size-dword\n"); 761 return ret; 762 } 763 764 if (of_property_read_bool(dev->of_node, "non-zero-ttctrl-ttha")) 765 platdata->flags |= CI_HDRC_SET_NON_ZERO_TTHA; 766 767 ext_id = ERR_PTR(-ENODEV); 768 ext_vbus = ERR_PTR(-ENODEV); 769 if (of_property_present(dev->of_node, "extcon")) { 770 /* Each one of them is not mandatory */ 771 ext_vbus = extcon_get_edev_by_phandle(dev, 0); 772 if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV) 773 return PTR_ERR(ext_vbus); 774 775 ext_id = extcon_get_edev_by_phandle(dev, 1); 776 if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV) 777 return PTR_ERR(ext_id); 778 } 779 780 cable = &platdata->vbus_extcon; 781 cable->nb.notifier_call = ci_cable_notifier; 782 cable->edev = ext_vbus; 783 784 if (!IS_ERR(ext_vbus)) { 785 ret = extcon_get_state(cable->edev, EXTCON_USB); 786 if (ret) 787 cable->connected = true; 788 else 789 cable->connected = false; 790 } 791 792 cable = &platdata->id_extcon; 793 cable->nb.notifier_call = ci_cable_notifier; 794 cable->edev = ext_id; 795 796 if (!IS_ERR(ext_id)) { 797 ret = extcon_get_state(cable->edev, EXTCON_USB_HOST); 798 if (ret) 799 cable->connected = true; 800 else 801 cable->connected = false; 802 } 803 804 if (device_property_read_bool(dev, "usb-role-switch")) 805 ci_role_switch.fwnode = dev->fwnode; 806 807 platdata->pctl = devm_pinctrl_get(dev); 808 if (!IS_ERR(platdata->pctl)) { 809 struct pinctrl_state *p; 810 811 p = pinctrl_lookup_state(platdata->pctl, "default"); 812 if (!IS_ERR(p)) 813 platdata->pins_default = p; 814 815 p = pinctrl_lookup_state(platdata->pctl, "host"); 816 if (!IS_ERR(p)) 817 platdata->pins_host = p; 818 819 p = pinctrl_lookup_state(platdata->pctl, "device"); 820 if (!IS_ERR(p)) 821 platdata->pins_device = p; 822 } 823 824 if (!platdata->enter_lpm) 825 platdata->enter_lpm = ci_hdrc_enter_lpm_common; 826 827 return 0; 828 } 829 830 static int ci_extcon_register(struct ci_hdrc *ci) 831 { 832 struct ci_hdrc_cable *id, *vbus; 833 int ret; 834 835 id = &ci->platdata->id_extcon; 836 id->ci = ci; 837 if (!IS_ERR_OR_NULL(id->edev)) { 838 ret = devm_extcon_register_notifier(ci->dev, id->edev, 839 EXTCON_USB_HOST, &id->nb); 840 if (ret < 0) { 841 dev_err(ci->dev, "register ID failed\n"); 842 return ret; 843 } 844 } 845 846 vbus = &ci->platdata->vbus_extcon; 847 vbus->ci = ci; 848 if (!IS_ERR_OR_NULL(vbus->edev)) { 849 ret = devm_extcon_register_notifier(ci->dev, vbus->edev, 850 EXTCON_USB, &vbus->nb); 851 if (ret < 0) { 852 dev_err(ci->dev, "register VBUS failed\n"); 853 return ret; 854 } 855 } 856 857 return 0; 858 } 859 860 static void ci_power_lost_work(struct work_struct *work) 861 { 862 struct ci_hdrc *ci = container_of(work, struct ci_hdrc, power_lost_work); 863 enum ci_role role; 864 865 disable_irq_nosync(ci->irq); 866 pm_runtime_get_sync(ci->dev); 867 if (!ci_otg_is_fsm_mode(ci)) { 868 role = ci_get_role(ci); 869 870 if (ci->role != role) { 871 ci_handle_id_switch(ci); 872 } else if (role == CI_ROLE_GADGET) { 873 if (ci->is_otg && hw_read_otgsc(ci, OTGSC_BSV)) 874 usb_gadget_vbus_connect(&ci->gadget); 875 } 876 } 877 pm_runtime_put_sync(ci->dev); 878 enable_irq(ci->irq); 879 } 880 881 static DEFINE_IDA(ci_ida); 882 883 struct platform_device *ci_hdrc_add_device(struct device *dev, 884 struct resource *res, int nres, 885 struct ci_hdrc_platform_data *platdata) 886 { 887 struct platform_device *pdev; 888 int id, ret; 889 890 ret = ci_get_platdata(dev, platdata); 891 if (ret) 892 return ERR_PTR(ret); 893 894 id = ida_alloc(&ci_ida, GFP_KERNEL); 895 if (id < 0) 896 return ERR_PTR(id); 897 898 pdev = platform_device_alloc("ci_hdrc", id); 899 if (!pdev) { 900 ret = -ENOMEM; 901 goto put_id; 902 } 903 904 pdev->dev.parent = dev; 905 device_set_of_node_from_dev(&pdev->dev, dev); 906 907 ret = platform_device_add_resources(pdev, res, nres); 908 if (ret) 909 goto err; 910 911 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata)); 912 if (ret) 913 goto err; 914 915 ret = platform_device_add(pdev); 916 if (ret) 917 goto err; 918 919 dev_pm_domain_detach(&pdev->dev, false); 920 921 return pdev; 922 923 err: 924 platform_device_put(pdev); 925 put_id: 926 ida_free(&ci_ida, id); 927 return ERR_PTR(ret); 928 } 929 EXPORT_SYMBOL_GPL(ci_hdrc_add_device); 930 931 void ci_hdrc_remove_device(struct platform_device *pdev) 932 { 933 int id = pdev->id; 934 platform_device_unregister(pdev); 935 ida_free(&ci_ida, id); 936 } 937 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device); 938 939 /** 940 * ci_hdrc_query_available_role: get runtime available operation mode 941 * 942 * The glue layer can get current operation mode (host/peripheral/otg) 943 * This function should be called after ci core device has created. 944 * 945 * @pdev: the platform device of ci core. 946 * 947 * Return runtime usb_dr_mode. 948 */ 949 enum usb_dr_mode ci_hdrc_query_available_role(struct platform_device *pdev) 950 { 951 struct ci_hdrc *ci = platform_get_drvdata(pdev); 952 953 if (!ci) 954 return USB_DR_MODE_UNKNOWN; 955 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) 956 return USB_DR_MODE_OTG; 957 else if (ci->roles[CI_ROLE_HOST]) 958 return USB_DR_MODE_HOST; 959 else if (ci->roles[CI_ROLE_GADGET]) 960 return USB_DR_MODE_PERIPHERAL; 961 else 962 return USB_DR_MODE_UNKNOWN; 963 } 964 EXPORT_SYMBOL_GPL(ci_hdrc_query_available_role); 965 966 static inline void ci_role_destroy(struct ci_hdrc *ci) 967 { 968 ci_hdrc_gadget_destroy(ci); 969 ci_hdrc_host_destroy(ci); 970 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) 971 ci_hdrc_otg_destroy(ci); 972 } 973 974 static void ci_get_otg_capable(struct ci_hdrc *ci) 975 { 976 if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG) 977 ci->is_otg = false; 978 else 979 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS, 980 DCCPARAMS_DC | DCCPARAMS_HC) 981 == (DCCPARAMS_DC | DCCPARAMS_HC)); 982 if (ci->is_otg) { 983 dev_dbg(ci->dev, "It is OTG capable controller\n"); 984 /* Disable and clear all OTG irq */ 985 hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS, 986 OTGSC_INT_STATUS_BITS); 987 } 988 } 989 990 static ssize_t role_show(struct device *dev, struct device_attribute *attr, 991 char *buf) 992 { 993 struct ci_hdrc *ci = dev_get_drvdata(dev); 994 995 if (ci->role != CI_ROLE_END) 996 return sprintf(buf, "%s\n", ci_role(ci)->name); 997 998 return 0; 999 } 1000 1001 static ssize_t role_store(struct device *dev, 1002 struct device_attribute *attr, const char *buf, size_t n) 1003 { 1004 struct ci_hdrc *ci = dev_get_drvdata(dev); 1005 enum ci_role role; 1006 int ret; 1007 1008 if (!(ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET])) { 1009 dev_warn(dev, "Current configuration is not dual-role, quit\n"); 1010 return -EPERM; 1011 } 1012 1013 for (role = CI_ROLE_HOST; role < CI_ROLE_END; role++) 1014 if (!strncmp(buf, ci->roles[role]->name, 1015 strlen(ci->roles[role]->name))) 1016 break; 1017 1018 if (role == CI_ROLE_END) 1019 return -EINVAL; 1020 1021 mutex_lock(&ci->mutex); 1022 1023 if (role == ci->role) { 1024 mutex_unlock(&ci->mutex); 1025 return n; 1026 } 1027 1028 pm_runtime_get_sync(dev); 1029 disable_irq(ci->irq); 1030 ci_role_stop(ci); 1031 ret = ci_role_start(ci, role); 1032 if (!ret && ci->role == CI_ROLE_GADGET) 1033 ci_handle_vbus_change(ci); 1034 enable_irq(ci->irq); 1035 pm_runtime_put_sync(dev); 1036 mutex_unlock(&ci->mutex); 1037 1038 return (ret == 0) ? n : ret; 1039 } 1040 static DEVICE_ATTR_RW(role); 1041 1042 static struct attribute *ci_attrs[] = { 1043 &dev_attr_role.attr, 1044 NULL, 1045 }; 1046 ATTRIBUTE_GROUPS(ci); 1047 1048 static int ci_hdrc_probe(struct platform_device *pdev) 1049 { 1050 struct device *dev = &pdev->dev; 1051 struct ci_hdrc *ci; 1052 struct resource *res; 1053 void __iomem *base; 1054 int ret; 1055 enum usb_dr_mode dr_mode; 1056 1057 if (!dev_get_platdata(dev)) { 1058 dev_err(dev, "platform data missing\n"); 1059 return -ENODEV; 1060 } 1061 1062 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1063 if (IS_ERR(base)) 1064 return PTR_ERR(base); 1065 1066 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL); 1067 if (!ci) 1068 return -ENOMEM; 1069 1070 spin_lock_init(&ci->lock); 1071 mutex_init(&ci->mutex); 1072 INIT_WORK(&ci->power_lost_work, ci_power_lost_work); 1073 1074 ci->dev = dev; 1075 ci->platdata = dev_get_platdata(dev); 1076 ci->imx28_write_fix = !!(ci->platdata->flags & 1077 CI_HDRC_IMX28_WRITE_FIX); 1078 ci->supports_runtime_pm = !!(ci->platdata->flags & 1079 CI_HDRC_SUPPORTS_RUNTIME_PM); 1080 ci->has_portsc_pec_bug = !!(ci->platdata->flags & 1081 CI_HDRC_HAS_PORTSC_PEC_MISSED); 1082 ci->has_short_pkt_limit = !!(ci->platdata->flags & 1083 CI_HDRC_HAS_SHORT_PKT_LIMIT); 1084 platform_set_drvdata(pdev, ci); 1085 1086 ret = hw_device_init(ci, base); 1087 if (ret < 0) { 1088 dev_err(dev, "can't initialize hardware\n"); 1089 return -ENODEV; 1090 } 1091 1092 ret = ci_ulpi_init(ci); 1093 if (ret) 1094 return ret; 1095 1096 if (ci->platdata->phy) { 1097 ci->phy = ci->platdata->phy; 1098 } else if (ci->platdata->usb_phy) { 1099 ci->usb_phy = ci->platdata->usb_phy; 1100 } else { 1101 /* Look for a generic PHY first */ 1102 ci->phy = devm_phy_get(dev->parent, "usb-phy"); 1103 1104 if (PTR_ERR(ci->phy) == -EPROBE_DEFER) { 1105 ret = -EPROBE_DEFER; 1106 goto ulpi_exit; 1107 } else if (IS_ERR(ci->phy)) { 1108 ci->phy = NULL; 1109 } 1110 1111 /* Look for a legacy USB PHY from device-tree next */ 1112 if (!ci->phy) { 1113 ci->usb_phy = devm_usb_get_phy_by_phandle(dev->parent, 1114 "phys", 0); 1115 1116 if (PTR_ERR(ci->usb_phy) == -EPROBE_DEFER) { 1117 ret = -EPROBE_DEFER; 1118 goto ulpi_exit; 1119 } else if (IS_ERR(ci->usb_phy)) { 1120 ci->usb_phy = NULL; 1121 } 1122 } 1123 1124 /* Look for any registered legacy USB PHY as last resort */ 1125 if (!ci->phy && !ci->usb_phy) { 1126 ci->usb_phy = devm_usb_get_phy(dev->parent, 1127 USB_PHY_TYPE_USB2); 1128 1129 if (PTR_ERR(ci->usb_phy) == -EPROBE_DEFER) { 1130 ret = -EPROBE_DEFER; 1131 goto ulpi_exit; 1132 } else if (IS_ERR(ci->usb_phy)) { 1133 ci->usb_phy = NULL; 1134 } 1135 } 1136 1137 /* No USB PHY was found in the end */ 1138 if (!ci->phy && !ci->usb_phy) { 1139 ret = -ENXIO; 1140 goto ulpi_exit; 1141 } 1142 } 1143 1144 ret = ci_usb_phy_init(ci); 1145 if (ret) { 1146 dev_err(dev, "unable to init phy: %d\n", ret); 1147 goto ulpi_exit; 1148 } 1149 1150 ci->hw_bank.phys = res->start; 1151 1152 ci->irq = platform_get_irq(pdev, 0); 1153 if (ci->irq < 0) { 1154 ret = ci->irq; 1155 goto deinit_phy; 1156 } 1157 1158 ci_get_otg_capable(ci); 1159 1160 dr_mode = ci->platdata->dr_mode; 1161 /* initialize role(s) before the interrupt is requested */ 1162 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) { 1163 ret = ci_hdrc_host_init(ci); 1164 if (ret) { 1165 if (ret == -ENXIO) 1166 dev_info(dev, "doesn't support host\n"); 1167 else 1168 goto deinit_phy; 1169 } 1170 } 1171 1172 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) { 1173 ret = ci_hdrc_gadget_init(ci); 1174 if (ret) { 1175 if (ret == -ENXIO) 1176 dev_info(dev, "doesn't support gadget\n"); 1177 else 1178 goto deinit_host; 1179 } 1180 } 1181 1182 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) { 1183 dev_err(dev, "no supported roles\n"); 1184 ret = -ENODEV; 1185 goto deinit_gadget; 1186 } 1187 1188 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) { 1189 ret = ci_hdrc_otg_init(ci); 1190 if (ret) { 1191 dev_err(dev, "init otg fails, ret = %d\n", ret); 1192 goto deinit_gadget; 1193 } 1194 } 1195 1196 if (ci_role_switch.fwnode) { 1197 ci_role_switch.driver_data = ci; 1198 ci->role_switch = usb_role_switch_register(dev, 1199 &ci_role_switch); 1200 if (IS_ERR(ci->role_switch)) { 1201 ret = PTR_ERR(ci->role_switch); 1202 goto deinit_otg; 1203 } 1204 } 1205 1206 ci->role = ci_get_role(ci); 1207 if (!ci_otg_is_fsm_mode(ci)) { 1208 /* only update vbus status for peripheral */ 1209 if (ci->role == CI_ROLE_GADGET) { 1210 /* Pull down DP for possible charger detection */ 1211 hw_write(ci, OP_USBCMD, USBCMD_RS, 0); 1212 ci_handle_vbus_change(ci); 1213 } 1214 1215 ret = ci_role_start(ci, ci->role); 1216 if (ret) { 1217 dev_err(dev, "can't start %s role\n", 1218 ci_role(ci)->name); 1219 goto stop; 1220 } 1221 } 1222 1223 ret = devm_request_irq(dev, ci->irq, ci_irq_handler, IRQF_SHARED, 1224 ci->platdata->name, ci); 1225 if (ret) 1226 goto stop; 1227 1228 ret = ci_extcon_register(ci); 1229 if (ret) 1230 goto stop; 1231 1232 if (ci->supports_runtime_pm) { 1233 pm_runtime_set_active(&pdev->dev); 1234 pm_runtime_enable(&pdev->dev); 1235 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000); 1236 pm_runtime_mark_last_busy(ci->dev); 1237 pm_runtime_use_autosuspend(&pdev->dev); 1238 } 1239 1240 if (ci_otg_is_fsm_mode(ci)) 1241 ci_hdrc_otg_fsm_start(ci); 1242 1243 device_set_wakeup_capable(&pdev->dev, true); 1244 dbg_create_files(ci); 1245 1246 return 0; 1247 1248 stop: 1249 if (ci->role_switch) 1250 usb_role_switch_unregister(ci->role_switch); 1251 deinit_otg: 1252 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) 1253 ci_hdrc_otg_destroy(ci); 1254 deinit_gadget: 1255 ci_hdrc_gadget_destroy(ci); 1256 deinit_host: 1257 ci_hdrc_host_destroy(ci); 1258 deinit_phy: 1259 ci_usb_phy_exit(ci); 1260 ulpi_exit: 1261 ci_ulpi_exit(ci); 1262 1263 return ret; 1264 } 1265 1266 static void ci_hdrc_remove(struct platform_device *pdev) 1267 { 1268 struct ci_hdrc *ci = platform_get_drvdata(pdev); 1269 1270 if (ci->role_switch) 1271 usb_role_switch_unregister(ci->role_switch); 1272 1273 if (ci->supports_runtime_pm) { 1274 pm_runtime_get_sync(&pdev->dev); 1275 pm_runtime_disable(&pdev->dev); 1276 pm_runtime_put_noidle(&pdev->dev); 1277 } 1278 1279 dbg_remove_files(ci); 1280 ci_role_destroy(ci); 1281 ci_hdrc_enter_lpm(ci, true); 1282 ci_usb_phy_exit(ci); 1283 ci_ulpi_exit(ci); 1284 } 1285 1286 #ifdef CONFIG_PM 1287 /* Prepare wakeup by SRP before suspend */ 1288 static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci) 1289 { 1290 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) && 1291 !hw_read_otgsc(ci, OTGSC_ID)) { 1292 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP, 1293 PORTSC_PP); 1294 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN, 1295 PORTSC_WKCN); 1296 } 1297 } 1298 1299 /* Handle SRP when wakeup by data pulse */ 1300 static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci) 1301 { 1302 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) && 1303 (ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) { 1304 if (!hw_read_otgsc(ci, OTGSC_ID)) { 1305 ci->fsm.a_srp_det = 1; 1306 ci->fsm.a_bus_drop = 0; 1307 } else { 1308 ci->fsm.id = 1; 1309 } 1310 ci_otg_queue_work(ci); 1311 } 1312 } 1313 1314 static void ci_controller_suspend(struct ci_hdrc *ci) 1315 { 1316 disable_irq(ci->irq); 1317 ci_hdrc_enter_lpm(ci, true); 1318 if (ci->platdata->phy_clkgate_delay_us) 1319 usleep_range(ci->platdata->phy_clkgate_delay_us, 1320 ci->platdata->phy_clkgate_delay_us + 50); 1321 usb_phy_set_suspend(ci->usb_phy, 1); 1322 ci->in_lpm = true; 1323 enable_irq(ci->irq); 1324 } 1325 1326 /* 1327 * Handle the wakeup interrupt triggered by extcon connector 1328 * We need to call ci_irq again for extcon since the first 1329 * interrupt (wakeup int) only let the controller be out of 1330 * low power mode, but not handle any interrupts. 1331 */ 1332 static void ci_extcon_wakeup_int(struct ci_hdrc *ci) 1333 { 1334 struct ci_hdrc_cable *cable_id, *cable_vbus; 1335 u32 otgsc = hw_read_otgsc(ci, ~0); 1336 1337 cable_id = &ci->platdata->id_extcon; 1338 cable_vbus = &ci->platdata->vbus_extcon; 1339 1340 if ((!IS_ERR(cable_id->edev) || ci->role_switch) 1341 && ci->is_otg && 1342 (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) 1343 ci_irq(ci); 1344 1345 if ((!IS_ERR(cable_vbus->edev) || ci->role_switch) 1346 && ci->is_otg && 1347 (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) 1348 ci_irq(ci); 1349 } 1350 1351 static int ci_controller_resume(struct device *dev) 1352 { 1353 struct ci_hdrc *ci = dev_get_drvdata(dev); 1354 int ret; 1355 1356 dev_dbg(dev, "at %s\n", __func__); 1357 1358 if (!ci->in_lpm) { 1359 WARN_ON(1); 1360 return 0; 1361 } 1362 1363 ci_hdrc_enter_lpm(ci, false); 1364 1365 ret = ci_ulpi_resume(ci); 1366 if (ret) 1367 return ret; 1368 1369 if (ci->usb_phy) { 1370 usb_phy_set_suspend(ci->usb_phy, 0); 1371 usb_phy_set_wakeup(ci->usb_phy, false); 1372 hw_wait_phy_stable(); 1373 } 1374 1375 ci->in_lpm = false; 1376 if (ci->wakeup_int) { 1377 ci->wakeup_int = false; 1378 pm_runtime_mark_last_busy(ci->dev); 1379 pm_runtime_put_autosuspend(ci->dev); 1380 enable_irq(ci->irq); 1381 if (ci_otg_is_fsm_mode(ci)) 1382 ci_otg_fsm_wakeup_by_srp(ci); 1383 ci_extcon_wakeup_int(ci); 1384 } 1385 1386 return 0; 1387 } 1388 1389 #ifdef CONFIG_PM_SLEEP 1390 static int ci_suspend(struct device *dev) 1391 { 1392 struct ci_hdrc *ci = dev_get_drvdata(dev); 1393 1394 if (ci->wq) 1395 flush_workqueue(ci->wq); 1396 /* 1397 * Controller needs to be active during suspend, otherwise the core 1398 * may run resume when the parent is at suspend if other driver's 1399 * suspend fails, it occurs before parent's suspend has not started, 1400 * but the core suspend has finished. 1401 */ 1402 if (ci->in_lpm) 1403 pm_runtime_resume(dev); 1404 1405 if (ci->in_lpm) { 1406 WARN_ON(1); 1407 return 0; 1408 } 1409 1410 /* Extra routine per role before system suspend */ 1411 if (ci->role != CI_ROLE_END && ci_role(ci)->suspend) 1412 ci_role(ci)->suspend(ci); 1413 1414 if (device_may_wakeup(dev)) { 1415 if (ci_otg_is_fsm_mode(ci)) 1416 ci_otg_fsm_suspend_for_srp(ci); 1417 1418 usb_phy_set_wakeup(ci->usb_phy, true); 1419 enable_irq_wake(ci->irq); 1420 } 1421 1422 ci_controller_suspend(ci); 1423 1424 return 0; 1425 } 1426 1427 static int ci_resume(struct device *dev) 1428 { 1429 struct ci_hdrc *ci = dev_get_drvdata(dev); 1430 bool power_lost; 1431 int ret; 1432 1433 /* Since ASYNCLISTADDR (host mode) and ENDPTLISTADDR (device 1434 * mode) share the same register address. We can check if 1435 * controller resume from power lost based on this address 1436 * due to this register will be reset after power lost. 1437 */ 1438 power_lost = !hw_read(ci, OP_ENDPTLISTADDR, ~0); 1439 1440 if (device_may_wakeup(dev)) 1441 disable_irq_wake(ci->irq); 1442 1443 ret = ci_controller_resume(dev); 1444 if (ret) 1445 return ret; 1446 1447 if (power_lost) { 1448 /* shutdown and re-init for phy */ 1449 ci_usb_phy_exit(ci); 1450 ci_usb_phy_init(ci); 1451 } 1452 1453 /* Extra routine per role after system resume */ 1454 if (ci->role != CI_ROLE_END && ci_role(ci)->resume) 1455 ci_role(ci)->resume(ci, power_lost); 1456 1457 if (power_lost) 1458 queue_work(system_freezable_wq, &ci->power_lost_work); 1459 1460 if (ci->supports_runtime_pm) { 1461 pm_runtime_disable(dev); 1462 pm_runtime_set_active(dev); 1463 pm_runtime_enable(dev); 1464 } 1465 1466 return ret; 1467 } 1468 #endif /* CONFIG_PM_SLEEP */ 1469 1470 static int ci_runtime_suspend(struct device *dev) 1471 { 1472 struct ci_hdrc *ci = dev_get_drvdata(dev); 1473 1474 dev_dbg(dev, "at %s\n", __func__); 1475 1476 if (ci->in_lpm) { 1477 WARN_ON(1); 1478 return 0; 1479 } 1480 1481 if (ci_otg_is_fsm_mode(ci)) 1482 ci_otg_fsm_suspend_for_srp(ci); 1483 1484 usb_phy_set_wakeup(ci->usb_phy, true); 1485 ci_controller_suspend(ci); 1486 1487 return 0; 1488 } 1489 1490 static int ci_runtime_resume(struct device *dev) 1491 { 1492 return ci_controller_resume(dev); 1493 } 1494 1495 #endif /* CONFIG_PM */ 1496 static const struct dev_pm_ops ci_pm_ops = { 1497 SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume) 1498 SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL) 1499 }; 1500 1501 static struct platform_driver ci_hdrc_driver = { 1502 .probe = ci_hdrc_probe, 1503 .remove = ci_hdrc_remove, 1504 .driver = { 1505 .name = "ci_hdrc", 1506 .pm = &ci_pm_ops, 1507 .dev_groups = ci_groups, 1508 }, 1509 }; 1510 1511 static int __init ci_hdrc_platform_register(void) 1512 { 1513 ci_hdrc_host_driver_init(); 1514 return platform_driver_register(&ci_hdrc_driver); 1515 } 1516 module_init(ci_hdrc_platform_register); 1517 1518 static void __exit ci_hdrc_platform_unregister(void) 1519 { 1520 platform_driver_unregister(&ci_hdrc_driver); 1521 } 1522 module_exit(ci_hdrc_platform_unregister); 1523 1524 MODULE_ALIAS("platform:ci_hdrc"); 1525 MODULE_LICENSE("GPL v2"); 1526 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>"); 1527 MODULE_DESCRIPTION("ChipIdea HDRC Driver"); 1528