1 /* Copyright (c) 2010, Code Aurora Forum. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 */ 7 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/pm_runtime.h> 11 #include <linux/usb/chipidea.h> 12 #include <linux/clk.h> 13 #include <linux/reset.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/regmap.h> 16 #include <linux/io.h> 17 #include <linux/reset-controller.h> 18 #include <linux/extcon.h> 19 #include <linux/of.h> 20 21 #include "ci.h" 22 23 #define HS_PHY_AHB_MODE 0x0098 24 25 #define HS_PHY_GENCONFIG 0x009c 26 #define HS_PHY_TXFIFO_IDLE_FORCE_DIS BIT(4) 27 28 #define HS_PHY_GENCONFIG_2 0x00a0 29 #define HS_PHY_SESS_VLD_CTRL_EN BIT(7) 30 #define HS_PHY_ULPI_TX_PKT_EN_CLR_FIX BIT(19) 31 32 #define HSPHY_SESS_VLD_CTRL BIT(25) 33 34 /* Vendor base starts at 0x200 beyond CI base */ 35 #define HS_PHY_CTRL 0x0040 36 #define HS_PHY_SEC_CTRL 0x0078 37 #define HS_PHY_DIG_CLAMP_N BIT(16) 38 #define HS_PHY_POR_ASSERT BIT(0) 39 40 struct ci_hdrc_msm { 41 struct platform_device *ci; 42 struct clk *core_clk; 43 struct clk *iface_clk; 44 struct clk *fs_clk; 45 struct ci_hdrc_platform_data pdata; 46 struct reset_controller_dev rcdev; 47 bool secondary_phy; 48 bool hsic; 49 void __iomem *base; 50 }; 51 52 static int 53 ci_hdrc_msm_por_reset(struct reset_controller_dev *r, unsigned long id) 54 { 55 struct ci_hdrc_msm *ci_msm = container_of(r, struct ci_hdrc_msm, rcdev); 56 void __iomem *addr = ci_msm->base; 57 u32 val; 58 59 if (id) 60 addr += HS_PHY_SEC_CTRL; 61 else 62 addr += HS_PHY_CTRL; 63 64 val = readl_relaxed(addr); 65 val |= HS_PHY_POR_ASSERT; 66 writel(val, addr); 67 /* 68 * wait for minimum 10 microseconds as suggested by manual. 69 * Use a slightly larger value since the exact value didn't 70 * work 100% of the time. 71 */ 72 udelay(12); 73 val &= ~HS_PHY_POR_ASSERT; 74 writel(val, addr); 75 76 return 0; 77 } 78 79 static const struct reset_control_ops ci_hdrc_msm_reset_ops = { 80 .reset = ci_hdrc_msm_por_reset, 81 }; 82 83 static int ci_hdrc_msm_notify_event(struct ci_hdrc *ci, unsigned event) 84 { 85 struct device *dev = ci->dev->parent; 86 struct ci_hdrc_msm *msm_ci = dev_get_drvdata(dev); 87 int ret; 88 89 switch (event) { 90 case CI_HDRC_CONTROLLER_RESET_EVENT: 91 dev_dbg(dev, "CI_HDRC_CONTROLLER_RESET_EVENT received\n"); 92 93 hw_phymode_configure(ci); 94 if (msm_ci->secondary_phy) { 95 u32 val = readl_relaxed(msm_ci->base + HS_PHY_SEC_CTRL); 96 val |= HS_PHY_DIG_CLAMP_N; 97 writel_relaxed(val, msm_ci->base + HS_PHY_SEC_CTRL); 98 } 99 100 ret = phy_init(ci->phy); 101 if (ret) 102 return ret; 103 104 ret = phy_power_on(ci->phy); 105 if (ret) { 106 phy_exit(ci->phy); 107 return ret; 108 } 109 110 /* use AHB transactor, allow posted data writes */ 111 hw_write_id_reg(ci, HS_PHY_AHB_MODE, 0xffffffff, 0x8); 112 113 /* workaround for rx buffer collision issue */ 114 hw_write_id_reg(ci, HS_PHY_GENCONFIG, 115 HS_PHY_TXFIFO_IDLE_FORCE_DIS, 0); 116 117 if (!msm_ci->hsic) 118 hw_write_id_reg(ci, HS_PHY_GENCONFIG_2, 119 HS_PHY_ULPI_TX_PKT_EN_CLR_FIX, 0); 120 121 if (!IS_ERR(ci->platdata->vbus_extcon.edev)) { 122 hw_write_id_reg(ci, HS_PHY_GENCONFIG_2, 123 HS_PHY_SESS_VLD_CTRL_EN, 124 HS_PHY_SESS_VLD_CTRL_EN); 125 hw_write(ci, OP_USBCMD, HSPHY_SESS_VLD_CTRL, 126 HSPHY_SESS_VLD_CTRL); 127 128 } 129 break; 130 case CI_HDRC_CONTROLLER_STOPPED_EVENT: 131 dev_dbg(dev, "CI_HDRC_CONTROLLER_STOPPED_EVENT received\n"); 132 phy_power_off(ci->phy); 133 phy_exit(ci->phy); 134 break; 135 default: 136 dev_dbg(dev, "unknown ci_hdrc event\n"); 137 break; 138 } 139 140 return 0; 141 } 142 143 static int ci_hdrc_msm_mux_phy(struct ci_hdrc_msm *ci, 144 struct platform_device *pdev) 145 { 146 struct regmap *regmap; 147 struct device *dev = &pdev->dev; 148 struct of_phandle_args args; 149 u32 val; 150 int ret; 151 152 ret = of_parse_phandle_with_fixed_args(dev->of_node, "phy-select", 2, 0, 153 &args); 154 if (ret) 155 return 0; 156 157 regmap = syscon_node_to_regmap(args.np); 158 of_node_put(args.np); 159 if (IS_ERR(regmap)) 160 return PTR_ERR(regmap); 161 162 ret = regmap_write(regmap, args.args[0], args.args[1]); 163 if (ret) 164 return ret; 165 166 ci->secondary_phy = !!args.args[1]; 167 if (ci->secondary_phy) { 168 val = readl_relaxed(ci->base + HS_PHY_SEC_CTRL); 169 val |= HS_PHY_DIG_CLAMP_N; 170 writel_relaxed(val, ci->base + HS_PHY_SEC_CTRL); 171 } 172 173 return 0; 174 } 175 176 static int ci_hdrc_msm_probe(struct platform_device *pdev) 177 { 178 struct ci_hdrc_msm *ci; 179 struct platform_device *plat_ci; 180 struct clk *clk; 181 struct reset_control *reset; 182 struct resource *res; 183 int ret; 184 struct device_node *ulpi_node, *phy_node; 185 186 dev_dbg(&pdev->dev, "ci_hdrc_msm_probe\n"); 187 188 ci = devm_kzalloc(&pdev->dev, sizeof(*ci), GFP_KERNEL); 189 if (!ci) 190 return -ENOMEM; 191 platform_set_drvdata(pdev, ci); 192 193 ci->pdata.name = "ci_hdrc_msm"; 194 ci->pdata.capoffset = DEF_CAPOFFSET; 195 ci->pdata.flags = CI_HDRC_REGS_SHARED | CI_HDRC_DISABLE_STREAMING | 196 CI_HDRC_OVERRIDE_AHB_BURST | 197 CI_HDRC_OVERRIDE_PHY_CONTROL; 198 ci->pdata.notify_event = ci_hdrc_msm_notify_event; 199 200 reset = devm_reset_control_get(&pdev->dev, "core"); 201 if (IS_ERR(reset)) 202 return PTR_ERR(reset); 203 204 ci->core_clk = clk = devm_clk_get(&pdev->dev, "core"); 205 if (IS_ERR(clk)) 206 return PTR_ERR(clk); 207 208 ci->iface_clk = clk = devm_clk_get(&pdev->dev, "iface"); 209 if (IS_ERR(clk)) 210 return PTR_ERR(clk); 211 212 ci->fs_clk = clk = devm_clk_get(&pdev->dev, "fs"); 213 if (IS_ERR(clk)) { 214 if (PTR_ERR(clk) == -EPROBE_DEFER) 215 return -EPROBE_DEFER; 216 ci->fs_clk = NULL; 217 } 218 219 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 220 ci->base = devm_ioremap_resource(&pdev->dev, res); 221 if (IS_ERR(ci->base)) 222 return PTR_ERR(ci->base); 223 224 ci->rcdev.owner = THIS_MODULE; 225 ci->rcdev.ops = &ci_hdrc_msm_reset_ops; 226 ci->rcdev.of_node = pdev->dev.of_node; 227 ci->rcdev.nr_resets = 2; 228 ret = reset_controller_register(&ci->rcdev); 229 if (ret) 230 return ret; 231 232 ret = clk_prepare_enable(ci->fs_clk); 233 if (ret) 234 goto err_fs; 235 236 reset_control_assert(reset); 237 usleep_range(10000, 12000); 238 reset_control_deassert(reset); 239 240 clk_disable_unprepare(ci->fs_clk); 241 242 ret = clk_prepare_enable(ci->core_clk); 243 if (ret) 244 goto err_fs; 245 246 ret = clk_prepare_enable(ci->iface_clk); 247 if (ret) 248 goto err_iface; 249 250 ret = ci_hdrc_msm_mux_phy(ci, pdev); 251 if (ret) 252 goto err_mux; 253 254 ulpi_node = of_find_node_by_name(pdev->dev.of_node, "ulpi"); 255 if (ulpi_node) { 256 phy_node = of_get_next_available_child(ulpi_node, NULL); 257 ci->hsic = of_device_is_compatible(phy_node, "qcom,usb-hsic-phy"); 258 of_node_put(phy_node); 259 } 260 of_node_put(ulpi_node); 261 262 plat_ci = ci_hdrc_add_device(&pdev->dev, pdev->resource, 263 pdev->num_resources, &ci->pdata); 264 if (IS_ERR(plat_ci)) { 265 ret = PTR_ERR(plat_ci); 266 if (ret != -EPROBE_DEFER) 267 dev_err(&pdev->dev, "ci_hdrc_add_device failed!\n"); 268 goto err_mux; 269 } 270 271 ci->ci = plat_ci; 272 273 pm_runtime_set_active(&pdev->dev); 274 pm_runtime_no_callbacks(&pdev->dev); 275 pm_runtime_enable(&pdev->dev); 276 277 return 0; 278 279 err_mux: 280 clk_disable_unprepare(ci->iface_clk); 281 err_iface: 282 clk_disable_unprepare(ci->core_clk); 283 err_fs: 284 reset_controller_unregister(&ci->rcdev); 285 return ret; 286 } 287 288 static int ci_hdrc_msm_remove(struct platform_device *pdev) 289 { 290 struct ci_hdrc_msm *ci = platform_get_drvdata(pdev); 291 292 pm_runtime_disable(&pdev->dev); 293 ci_hdrc_remove_device(ci->ci); 294 clk_disable_unprepare(ci->iface_clk); 295 clk_disable_unprepare(ci->core_clk); 296 reset_controller_unregister(&ci->rcdev); 297 298 return 0; 299 } 300 301 static const struct of_device_id msm_ci_dt_match[] = { 302 { .compatible = "qcom,ci-hdrc", }, 303 { } 304 }; 305 MODULE_DEVICE_TABLE(of, msm_ci_dt_match); 306 307 static struct platform_driver ci_hdrc_msm_driver = { 308 .probe = ci_hdrc_msm_probe, 309 .remove = ci_hdrc_msm_remove, 310 .driver = { 311 .name = "msm_hsusb", 312 .of_match_table = msm_ci_dt_match, 313 }, 314 }; 315 316 module_platform_driver(ci_hdrc_msm_driver); 317 318 MODULE_ALIAS("platform:msm_hsusb"); 319 MODULE_ALIAS("platform:ci13xxx_msm"); 320 MODULE_LICENSE("GPL v2"); 321