1 /* 2 * ci.h - common structures, functions, and macros of the ChipIdea driver 3 * 4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved. 5 * 6 * Author: David Lopo 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #ifndef __DRIVERS_USB_CHIPIDEA_CI_H 14 #define __DRIVERS_USB_CHIPIDEA_CI_H 15 16 #include <linux/list.h> 17 #include <linux/irqreturn.h> 18 #include <linux/usb.h> 19 #include <linux/usb/gadget.h> 20 #include <linux/usb/otg-fsm.h> 21 22 /****************************************************************************** 23 * DEFINE 24 *****************************************************************************/ 25 #define TD_PAGE_COUNT 5 26 #define CI_HDRC_PAGE_SIZE 4096ul /* page size for TD's */ 27 #define ENDPT_MAX 32 28 29 /****************************************************************************** 30 * REGISTERS 31 *****************************************************************************/ 32 /* Identification Registers */ 33 #define ID_ID 0x0 34 #define ID_HWGENERAL 0x4 35 #define ID_HWHOST 0x8 36 #define ID_HWDEVICE 0xc 37 #define ID_HWTXBUF 0x10 38 #define ID_HWRXBUF 0x14 39 #define ID_SBUSCFG 0x90 40 41 /* register indices */ 42 enum ci_hw_regs { 43 CAP_CAPLENGTH, 44 CAP_HCCPARAMS, 45 CAP_DCCPARAMS, 46 CAP_TESTMODE, 47 CAP_LAST = CAP_TESTMODE, 48 OP_USBCMD, 49 OP_USBSTS, 50 OP_USBINTR, 51 OP_DEVICEADDR, 52 OP_ENDPTLISTADDR, 53 OP_PORTSC, 54 OP_DEVLC, 55 OP_OTGSC, 56 OP_USBMODE, 57 OP_ENDPTSETUPSTAT, 58 OP_ENDPTPRIME, 59 OP_ENDPTFLUSH, 60 OP_ENDPTSTAT, 61 OP_ENDPTCOMPLETE, 62 OP_ENDPTCTRL, 63 /* endptctrl1..15 follow */ 64 OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2, 65 }; 66 67 /****************************************************************************** 68 * STRUCTURES 69 *****************************************************************************/ 70 /** 71 * struct ci_hw_ep - endpoint representation 72 * @ep: endpoint structure for gadget drivers 73 * @dir: endpoint direction (TX/RX) 74 * @num: endpoint number 75 * @type: endpoint type 76 * @name: string description of the endpoint 77 * @qh: queue head for this endpoint 78 * @wedge: is the endpoint wedged 79 * @ci: pointer to the controller 80 * @lock: pointer to controller's spinlock 81 * @td_pool: pointer to controller's TD pool 82 */ 83 struct ci_hw_ep { 84 struct usb_ep ep; 85 u8 dir; 86 u8 num; 87 u8 type; 88 char name[16]; 89 struct { 90 struct list_head queue; 91 struct ci_hw_qh *ptr; 92 dma_addr_t dma; 93 } qh; 94 int wedge; 95 96 /* global resources */ 97 struct ci_hdrc *ci; 98 spinlock_t *lock; 99 struct dma_pool *td_pool; 100 struct td_node *pending_td; 101 }; 102 103 enum ci_role { 104 CI_ROLE_HOST = 0, 105 CI_ROLE_GADGET, 106 CI_ROLE_END, 107 }; 108 109 enum ci_revision { 110 CI_REVISION_1X = 10, /* Revision 1.x */ 111 CI_REVISION_20 = 20, /* Revision 2.0 */ 112 CI_REVISION_21, /* Revision 2.1 */ 113 CI_REVISION_22, /* Revision 2.2 */ 114 CI_REVISION_23, /* Revision 2.3 */ 115 CI_REVISION_24, /* Revision 2.4 */ 116 CI_REVISION_25, /* Revision 2.5 */ 117 CI_REVISION_25_PLUS, /* Revision above than 2.5 */ 118 CI_REVISION_UNKNOWN = 99, /* Unknown Revision */ 119 }; 120 121 /** 122 * struct ci_role_driver - host/gadget role driver 123 * @start: start this role 124 * @stop: stop this role 125 * @irq: irq handler for this role 126 * @name: role name string (host/gadget) 127 */ 128 struct ci_role_driver { 129 int (*start)(struct ci_hdrc *); 130 void (*stop)(struct ci_hdrc *); 131 irqreturn_t (*irq)(struct ci_hdrc *); 132 const char *name; 133 }; 134 135 /** 136 * struct hw_bank - hardware register mapping representation 137 * @lpm: set if the device is LPM capable 138 * @phys: physical address of the controller's registers 139 * @abs: absolute address of the beginning of register window 140 * @cap: capability registers 141 * @op: operational registers 142 * @size: size of the register window 143 * @regmap: register lookup table 144 */ 145 struct hw_bank { 146 unsigned lpm; 147 resource_size_t phys; 148 void __iomem *abs; 149 void __iomem *cap; 150 void __iomem *op; 151 size_t size; 152 void __iomem *regmap[OP_LAST + 1]; 153 }; 154 155 /** 156 * struct ci_hdrc - chipidea device representation 157 * @dev: pointer to parent device 158 * @lock: access synchronization 159 * @hw_bank: hardware register mapping 160 * @irq: IRQ number 161 * @roles: array of supported roles for this controller 162 * @role: current role 163 * @is_otg: if the device is otg-capable 164 * @fsm: otg finite state machine 165 * @otg_fsm_hrtimer: hrtimer for otg fsm timers 166 * @hr_timeouts: time out list for active otg fsm timers 167 * @enabled_otg_timer_bits: bits of enabled otg timers 168 * @next_otg_timer: next nearest enabled timer to be expired 169 * @work: work for role changing 170 * @wq: workqueue thread 171 * @qh_pool: allocation pool for queue heads 172 * @td_pool: allocation pool for transfer descriptors 173 * @gadget: device side representation for peripheral controller 174 * @driver: gadget driver 175 * @hw_ep_max: total number of endpoints supported by hardware 176 * @ci_hw_ep: array of endpoints 177 * @ep0_dir: ep0 direction 178 * @ep0out: pointer to ep0 OUT endpoint 179 * @ep0in: pointer to ep0 IN endpoint 180 * @status: ep0 status request 181 * @setaddr: if we should set the address on status completion 182 * @address: usb address received from the host 183 * @remote_wakeup: host-enabled remote wakeup 184 * @suspended: suspended by host 185 * @test_mode: the selected test mode 186 * @platdata: platform specific information supplied by parent device 187 * @vbus_active: is VBUS active 188 * @phy: pointer to PHY, if any 189 * @usb_phy: pointer to USB PHY, if any and if using the USB PHY framework 190 * @hcd: pointer to usb_hcd for ehci host driver 191 * @debugfs: root dentry for this controller in debugfs 192 * @id_event: indicates there is an id event, and handled at ci_otg_work 193 * @b_sess_valid_event: indicates there is a vbus event, and handled 194 * at ci_otg_work 195 * @imx28_write_fix: Freescale imx28 needs swp instruction for writing 196 * @supports_runtime_pm: if runtime pm is supported 197 * @in_lpm: if the core in low power mode 198 * @wakeup_int: if wakeup interrupt occur 199 * @rev: The revision number for controller 200 */ 201 struct ci_hdrc { 202 struct device *dev; 203 spinlock_t lock; 204 struct hw_bank hw_bank; 205 int irq; 206 struct ci_role_driver *roles[CI_ROLE_END]; 207 enum ci_role role; 208 bool is_otg; 209 struct usb_otg otg; 210 struct otg_fsm fsm; 211 struct hrtimer otg_fsm_hrtimer; 212 ktime_t hr_timeouts[NUM_OTG_FSM_TIMERS]; 213 unsigned enabled_otg_timer_bits; 214 enum otg_fsm_timer next_otg_timer; 215 struct work_struct work; 216 struct workqueue_struct *wq; 217 218 struct dma_pool *qh_pool; 219 struct dma_pool *td_pool; 220 221 struct usb_gadget gadget; 222 struct usb_gadget_driver *driver; 223 unsigned hw_ep_max; 224 struct ci_hw_ep ci_hw_ep[ENDPT_MAX]; 225 u32 ep0_dir; 226 struct ci_hw_ep *ep0out, *ep0in; 227 228 struct usb_request *status; 229 bool setaddr; 230 u8 address; 231 u8 remote_wakeup; 232 u8 suspended; 233 u8 test_mode; 234 235 struct ci_hdrc_platform_data *platdata; 236 int vbus_active; 237 struct phy *phy; 238 /* old usb_phy interface */ 239 struct usb_phy *usb_phy; 240 struct usb_hcd *hcd; 241 struct dentry *debugfs; 242 bool id_event; 243 bool b_sess_valid_event; 244 bool imx28_write_fix; 245 bool supports_runtime_pm; 246 bool in_lpm; 247 bool wakeup_int; 248 enum ci_revision rev; 249 }; 250 251 static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci) 252 { 253 BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]); 254 return ci->roles[ci->role]; 255 } 256 257 static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role) 258 { 259 int ret; 260 261 if (role >= CI_ROLE_END) 262 return -EINVAL; 263 264 if (!ci->roles[role]) 265 return -ENXIO; 266 267 ret = ci->roles[role]->start(ci); 268 if (!ret) 269 ci->role = role; 270 return ret; 271 } 272 273 static inline void ci_role_stop(struct ci_hdrc *ci) 274 { 275 enum ci_role role = ci->role; 276 277 if (role == CI_ROLE_END) 278 return; 279 280 ci->role = CI_ROLE_END; 281 282 ci->roles[role]->stop(ci); 283 } 284 285 /** 286 * hw_read_id_reg: reads from a identification register 287 * @ci: the controller 288 * @offset: offset from the beginning of identification registers region 289 * @mask: bitfield mask 290 * 291 * This function returns register contents 292 */ 293 static inline u32 hw_read_id_reg(struct ci_hdrc *ci, u32 offset, u32 mask) 294 { 295 return ioread32(ci->hw_bank.abs + offset) & mask; 296 } 297 298 /** 299 * hw_write_id_reg: writes to a identification register 300 * @ci: the controller 301 * @offset: offset from the beginning of identification registers region 302 * @mask: bitfield mask 303 * @data: new value 304 */ 305 static inline void hw_write_id_reg(struct ci_hdrc *ci, u32 offset, 306 u32 mask, u32 data) 307 { 308 if (~mask) 309 data = (ioread32(ci->hw_bank.abs + offset) & ~mask) 310 | (data & mask); 311 312 iowrite32(data, ci->hw_bank.abs + offset); 313 } 314 315 /** 316 * hw_read: reads from a hw register 317 * @ci: the controller 318 * @reg: register index 319 * @mask: bitfield mask 320 * 321 * This function returns register contents 322 */ 323 static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask) 324 { 325 return ioread32(ci->hw_bank.regmap[reg]) & mask; 326 } 327 328 #ifdef CONFIG_SOC_IMX28 329 static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr) 330 { 331 __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr)); 332 } 333 #else 334 static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr) 335 { 336 } 337 #endif 338 339 static inline void __hw_write(struct ci_hdrc *ci, u32 val, 340 void __iomem *addr) 341 { 342 if (ci->imx28_write_fix) 343 imx28_ci_writel(val, addr); 344 else 345 iowrite32(val, addr); 346 } 347 348 /** 349 * hw_write: writes to a hw register 350 * @ci: the controller 351 * @reg: register index 352 * @mask: bitfield mask 353 * @data: new value 354 */ 355 static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg, 356 u32 mask, u32 data) 357 { 358 if (~mask) 359 data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask) 360 | (data & mask); 361 362 __hw_write(ci, data, ci->hw_bank.regmap[reg]); 363 } 364 365 /** 366 * hw_test_and_clear: tests & clears a hw register 367 * @ci: the controller 368 * @reg: register index 369 * @mask: bitfield mask 370 * 371 * This function returns register contents 372 */ 373 static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg, 374 u32 mask) 375 { 376 u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask; 377 378 __hw_write(ci, val, ci->hw_bank.regmap[reg]); 379 return val; 380 } 381 382 /** 383 * hw_test_and_write: tests & writes a hw register 384 * @ci: the controller 385 * @reg: register index 386 * @mask: bitfield mask 387 * @data: new value 388 * 389 * This function returns register contents 390 */ 391 static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg, 392 u32 mask, u32 data) 393 { 394 u32 val = hw_read(ci, reg, ~0); 395 396 hw_write(ci, reg, mask, data); 397 return (val & mask) >> __ffs(mask); 398 } 399 400 /** 401 * ci_otg_is_fsm_mode: runtime check if otg controller 402 * is in otg fsm mode. 403 * 404 * @ci: chipidea device 405 */ 406 static inline bool ci_otg_is_fsm_mode(struct ci_hdrc *ci) 407 { 408 #ifdef CONFIG_USB_OTG_FSM 409 return ci->is_otg && ci->roles[CI_ROLE_HOST] && 410 ci->roles[CI_ROLE_GADGET]; 411 #else 412 return false; 413 #endif 414 } 415 416 u32 hw_read_intr_enable(struct ci_hdrc *ci); 417 418 u32 hw_read_intr_status(struct ci_hdrc *ci); 419 420 int hw_device_reset(struct ci_hdrc *ci); 421 422 int hw_port_test_set(struct ci_hdrc *ci, u8 mode); 423 424 u8 hw_port_test_get(struct ci_hdrc *ci); 425 426 int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask, 427 u32 value, unsigned int timeout_ms); 428 429 #endif /* __DRIVERS_USB_CHIPIDEA_CI_H */ 430