1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ci.h - common structures, functions, and macros of the ChipIdea driver 4 * 5 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved. 6 * 7 * Author: David Lopo 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #ifndef __DRIVERS_USB_CHIPIDEA_CI_H 15 #define __DRIVERS_USB_CHIPIDEA_CI_H 16 17 #include <linux/list.h> 18 #include <linux/irqreturn.h> 19 #include <linux/usb.h> 20 #include <linux/usb/gadget.h> 21 #include <linux/usb/otg-fsm.h> 22 #include <linux/usb/otg.h> 23 #include <linux/ulpi/interface.h> 24 25 /****************************************************************************** 26 * DEFINE 27 *****************************************************************************/ 28 #define TD_PAGE_COUNT 5 29 #define CI_HDRC_PAGE_SIZE 4096ul /* page size for TD's */ 30 #define ENDPT_MAX 32 31 32 /****************************************************************************** 33 * REGISTERS 34 *****************************************************************************/ 35 /* Identification Registers */ 36 #define ID_ID 0x0 37 #define ID_HWGENERAL 0x4 38 #define ID_HWHOST 0x8 39 #define ID_HWDEVICE 0xc 40 #define ID_HWTXBUF 0x10 41 #define ID_HWRXBUF 0x14 42 #define ID_SBUSCFG 0x90 43 44 /* register indices */ 45 enum ci_hw_regs { 46 CAP_CAPLENGTH, 47 CAP_HCCPARAMS, 48 CAP_DCCPARAMS, 49 CAP_TESTMODE, 50 CAP_LAST = CAP_TESTMODE, 51 OP_USBCMD, 52 OP_USBSTS, 53 OP_USBINTR, 54 OP_DEVICEADDR, 55 OP_ENDPTLISTADDR, 56 OP_TTCTRL, 57 OP_BURSTSIZE, 58 OP_ULPI_VIEWPORT, 59 OP_PORTSC, 60 OP_DEVLC, 61 OP_OTGSC, 62 OP_USBMODE, 63 OP_ENDPTSETUPSTAT, 64 OP_ENDPTPRIME, 65 OP_ENDPTFLUSH, 66 OP_ENDPTSTAT, 67 OP_ENDPTCOMPLETE, 68 OP_ENDPTCTRL, 69 /* endptctrl1..15 follow */ 70 OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2, 71 }; 72 73 /****************************************************************************** 74 * STRUCTURES 75 *****************************************************************************/ 76 /** 77 * struct ci_hw_ep - endpoint representation 78 * @ep: endpoint structure for gadget drivers 79 * @dir: endpoint direction (TX/RX) 80 * @num: endpoint number 81 * @type: endpoint type 82 * @name: string description of the endpoint 83 * @qh: queue head for this endpoint 84 * @wedge: is the endpoint wedged 85 * @ci: pointer to the controller 86 * @lock: pointer to controller's spinlock 87 * @td_pool: pointer to controller's TD pool 88 */ 89 struct ci_hw_ep { 90 struct usb_ep ep; 91 u8 dir; 92 u8 num; 93 u8 type; 94 char name[16]; 95 struct { 96 struct list_head queue; 97 struct ci_hw_qh *ptr; 98 dma_addr_t dma; 99 } qh; 100 int wedge; 101 102 /* global resources */ 103 struct ci_hdrc *ci; 104 spinlock_t *lock; 105 struct dma_pool *td_pool; 106 struct td_node *pending_td; 107 }; 108 109 enum ci_role { 110 CI_ROLE_HOST = 0, 111 CI_ROLE_GADGET, 112 CI_ROLE_END, 113 }; 114 115 enum ci_revision { 116 CI_REVISION_1X = 10, /* Revision 1.x */ 117 CI_REVISION_20 = 20, /* Revision 2.0 */ 118 CI_REVISION_21, /* Revision 2.1 */ 119 CI_REVISION_22, /* Revision 2.2 */ 120 CI_REVISION_23, /* Revision 2.3 */ 121 CI_REVISION_24, /* Revision 2.4 */ 122 CI_REVISION_25, /* Revision 2.5 */ 123 CI_REVISION_25_PLUS, /* Revision above than 2.5 */ 124 CI_REVISION_UNKNOWN = 99, /* Unknown Revision */ 125 }; 126 127 /** 128 * struct ci_role_driver - host/gadget role driver 129 * @start: start this role 130 * @stop: stop this role 131 * @irq: irq handler for this role 132 * @name: role name string (host/gadget) 133 */ 134 struct ci_role_driver { 135 int (*start)(struct ci_hdrc *); 136 void (*stop)(struct ci_hdrc *); 137 irqreturn_t (*irq)(struct ci_hdrc *); 138 const char *name; 139 }; 140 141 /** 142 * struct hw_bank - hardware register mapping representation 143 * @lpm: set if the device is LPM capable 144 * @phys: physical address of the controller's registers 145 * @abs: absolute address of the beginning of register window 146 * @cap: capability registers 147 * @op: operational registers 148 * @size: size of the register window 149 * @regmap: register lookup table 150 */ 151 struct hw_bank { 152 unsigned lpm; 153 resource_size_t phys; 154 void __iomem *abs; 155 void __iomem *cap; 156 void __iomem *op; 157 size_t size; 158 void __iomem *regmap[OP_LAST + 1]; 159 }; 160 161 /** 162 * struct ci_hdrc - chipidea device representation 163 * @dev: pointer to parent device 164 * @lock: access synchronization 165 * @hw_bank: hardware register mapping 166 * @irq: IRQ number 167 * @roles: array of supported roles for this controller 168 * @role: current role 169 * @is_otg: if the device is otg-capable 170 * @fsm: otg finite state machine 171 * @otg_fsm_hrtimer: hrtimer for otg fsm timers 172 * @hr_timeouts: time out list for active otg fsm timers 173 * @enabled_otg_timer_bits: bits of enabled otg timers 174 * @next_otg_timer: next nearest enabled timer to be expired 175 * @work: work for role changing 176 * @wq: workqueue thread 177 * @qh_pool: allocation pool for queue heads 178 * @td_pool: allocation pool for transfer descriptors 179 * @gadget: device side representation for peripheral controller 180 * @driver: gadget driver 181 * @resume_state: save the state of gadget suspend from 182 * @hw_ep_max: total number of endpoints supported by hardware 183 * @ci_hw_ep: array of endpoints 184 * @ep0_dir: ep0 direction 185 * @ep0out: pointer to ep0 OUT endpoint 186 * @ep0in: pointer to ep0 IN endpoint 187 * @status: ep0 status request 188 * @setaddr: if we should set the address on status completion 189 * @address: usb address received from the host 190 * @remote_wakeup: host-enabled remote wakeup 191 * @suspended: suspended by host 192 * @test_mode: the selected test mode 193 * @platdata: platform specific information supplied by parent device 194 * @vbus_active: is VBUS active 195 * @ulpi: pointer to ULPI device, if any 196 * @ulpi_ops: ULPI read/write ops for this device 197 * @phy: pointer to PHY, if any 198 * @usb_phy: pointer to USB PHY, if any and if using the USB PHY framework 199 * @hcd: pointer to usb_hcd for ehci host driver 200 * @debugfs: root dentry for this controller in debugfs 201 * @id_event: indicates there is an id event, and handled at ci_otg_work 202 * @b_sess_valid_event: indicates there is a vbus event, and handled 203 * at ci_otg_work 204 * @imx28_write_fix: Freescale imx28 needs swp instruction for writing 205 * @supports_runtime_pm: if runtime pm is supported 206 * @in_lpm: if the core in low power mode 207 * @wakeup_int: if wakeup interrupt occur 208 * @rev: The revision number for controller 209 */ 210 struct ci_hdrc { 211 struct device *dev; 212 spinlock_t lock; 213 struct hw_bank hw_bank; 214 int irq; 215 struct ci_role_driver *roles[CI_ROLE_END]; 216 enum ci_role role; 217 bool is_otg; 218 struct usb_otg otg; 219 struct otg_fsm fsm; 220 struct hrtimer otg_fsm_hrtimer; 221 ktime_t hr_timeouts[NUM_OTG_FSM_TIMERS]; 222 unsigned enabled_otg_timer_bits; 223 enum otg_fsm_timer next_otg_timer; 224 struct work_struct work; 225 struct workqueue_struct *wq; 226 227 struct dma_pool *qh_pool; 228 struct dma_pool *td_pool; 229 230 struct usb_gadget gadget; 231 struct usb_gadget_driver *driver; 232 enum usb_device_state resume_state; 233 unsigned hw_ep_max; 234 struct ci_hw_ep ci_hw_ep[ENDPT_MAX]; 235 u32 ep0_dir; 236 struct ci_hw_ep *ep0out, *ep0in; 237 238 struct usb_request *status; 239 bool setaddr; 240 u8 address; 241 u8 remote_wakeup; 242 u8 suspended; 243 u8 test_mode; 244 245 struct ci_hdrc_platform_data *platdata; 246 int vbus_active; 247 #ifdef CONFIG_USB_CHIPIDEA_ULPI 248 struct ulpi *ulpi; 249 struct ulpi_ops ulpi_ops; 250 #endif 251 struct phy *phy; 252 /* old usb_phy interface */ 253 struct usb_phy *usb_phy; 254 struct usb_hcd *hcd; 255 struct dentry *debugfs; 256 bool id_event; 257 bool b_sess_valid_event; 258 bool imx28_write_fix; 259 bool supports_runtime_pm; 260 bool in_lpm; 261 bool wakeup_int; 262 enum ci_revision rev; 263 }; 264 265 static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci) 266 { 267 BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]); 268 return ci->roles[ci->role]; 269 } 270 271 static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role) 272 { 273 int ret; 274 275 if (role >= CI_ROLE_END) 276 return -EINVAL; 277 278 if (!ci->roles[role]) 279 return -ENXIO; 280 281 ret = ci->roles[role]->start(ci); 282 if (!ret) 283 ci->role = role; 284 return ret; 285 } 286 287 static inline void ci_role_stop(struct ci_hdrc *ci) 288 { 289 enum ci_role role = ci->role; 290 291 if (role == CI_ROLE_END) 292 return; 293 294 ci->role = CI_ROLE_END; 295 296 ci->roles[role]->stop(ci); 297 } 298 299 /** 300 * hw_read_id_reg: reads from a identification register 301 * @ci: the controller 302 * @offset: offset from the beginning of identification registers region 303 * @mask: bitfield mask 304 * 305 * This function returns register contents 306 */ 307 static inline u32 hw_read_id_reg(struct ci_hdrc *ci, u32 offset, u32 mask) 308 { 309 return ioread32(ci->hw_bank.abs + offset) & mask; 310 } 311 312 /** 313 * hw_write_id_reg: writes to a identification register 314 * @ci: the controller 315 * @offset: offset from the beginning of identification registers region 316 * @mask: bitfield mask 317 * @data: new value 318 */ 319 static inline void hw_write_id_reg(struct ci_hdrc *ci, u32 offset, 320 u32 mask, u32 data) 321 { 322 if (~mask) 323 data = (ioread32(ci->hw_bank.abs + offset) & ~mask) 324 | (data & mask); 325 326 iowrite32(data, ci->hw_bank.abs + offset); 327 } 328 329 /** 330 * hw_read: reads from a hw register 331 * @ci: the controller 332 * @reg: register index 333 * @mask: bitfield mask 334 * 335 * This function returns register contents 336 */ 337 static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask) 338 { 339 return ioread32(ci->hw_bank.regmap[reg]) & mask; 340 } 341 342 #ifdef CONFIG_SOC_IMX28 343 static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr) 344 { 345 __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr)); 346 } 347 #else 348 static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr) 349 { 350 } 351 #endif 352 353 static inline void __hw_write(struct ci_hdrc *ci, u32 val, 354 void __iomem *addr) 355 { 356 if (ci->imx28_write_fix) 357 imx28_ci_writel(val, addr); 358 else 359 iowrite32(val, addr); 360 } 361 362 /** 363 * hw_write: writes to a hw register 364 * @ci: the controller 365 * @reg: register index 366 * @mask: bitfield mask 367 * @data: new value 368 */ 369 static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg, 370 u32 mask, u32 data) 371 { 372 if (~mask) 373 data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask) 374 | (data & mask); 375 376 __hw_write(ci, data, ci->hw_bank.regmap[reg]); 377 } 378 379 /** 380 * hw_test_and_clear: tests & clears a hw register 381 * @ci: the controller 382 * @reg: register index 383 * @mask: bitfield mask 384 * 385 * This function returns register contents 386 */ 387 static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg, 388 u32 mask) 389 { 390 u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask; 391 392 __hw_write(ci, val, ci->hw_bank.regmap[reg]); 393 return val; 394 } 395 396 /** 397 * hw_test_and_write: tests & writes a hw register 398 * @ci: the controller 399 * @reg: register index 400 * @mask: bitfield mask 401 * @data: new value 402 * 403 * This function returns register contents 404 */ 405 static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg, 406 u32 mask, u32 data) 407 { 408 u32 val = hw_read(ci, reg, ~0); 409 410 hw_write(ci, reg, mask, data); 411 return (val & mask) >> __ffs(mask); 412 } 413 414 /** 415 * ci_otg_is_fsm_mode: runtime check if otg controller 416 * is in otg fsm mode. 417 * 418 * @ci: chipidea device 419 */ 420 static inline bool ci_otg_is_fsm_mode(struct ci_hdrc *ci) 421 { 422 #ifdef CONFIG_USB_OTG_FSM 423 struct usb_otg_caps *otg_caps = &ci->platdata->ci_otg_caps; 424 425 return ci->is_otg && ci->roles[CI_ROLE_HOST] && 426 ci->roles[CI_ROLE_GADGET] && (otg_caps->srp_support || 427 otg_caps->hnp_support || otg_caps->adp_support); 428 #else 429 return false; 430 #endif 431 } 432 433 #if IS_ENABLED(CONFIG_USB_CHIPIDEA_ULPI) 434 int ci_ulpi_init(struct ci_hdrc *ci); 435 void ci_ulpi_exit(struct ci_hdrc *ci); 436 int ci_ulpi_resume(struct ci_hdrc *ci); 437 #else 438 static inline int ci_ulpi_init(struct ci_hdrc *ci) { return 0; } 439 static inline void ci_ulpi_exit(struct ci_hdrc *ci) { } 440 static inline int ci_ulpi_resume(struct ci_hdrc *ci) { return 0; } 441 #endif 442 443 u32 hw_read_intr_enable(struct ci_hdrc *ci); 444 445 u32 hw_read_intr_status(struct ci_hdrc *ci); 446 447 int hw_device_reset(struct ci_hdrc *ci); 448 449 int hw_port_test_set(struct ci_hdrc *ci, u8 mode); 450 451 u8 hw_port_test_get(struct ci_hdrc *ci); 452 453 void hw_phymode_configure(struct ci_hdrc *ci); 454 455 void ci_platform_configure(struct ci_hdrc *ci); 456 457 int dbg_create_files(struct ci_hdrc *ci); 458 459 void dbg_remove_files(struct ci_hdrc *ci); 460 #endif /* __DRIVERS_USB_CHIPIDEA_CI_H */ 461