xref: /linux/drivers/usb/chipidea/ci.h (revision 04eeb606a8383b306f4bc6991da8231b5f3924b0)
1 /*
2  * ci.h - common structures, functions, and macros of the ChipIdea driver
3  *
4  * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
5  *
6  * Author: David Lopo
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  */
12 
13 #ifndef __DRIVERS_USB_CHIPIDEA_CI_H
14 #define __DRIVERS_USB_CHIPIDEA_CI_H
15 
16 #include <linux/list.h>
17 #include <linux/irqreturn.h>
18 #include <linux/usb.h>
19 #include <linux/usb/gadget.h>
20 #include <linux/usb/otg-fsm.h>
21 
22 /******************************************************************************
23  * DEFINE
24  *****************************************************************************/
25 #define TD_PAGE_COUNT      5
26 #define CI_HDRC_PAGE_SIZE  4096ul /* page size for TD's */
27 #define ENDPT_MAX          32
28 
29 /******************************************************************************
30  * REGISTERS
31  *****************************************************************************/
32 /* register indices */
33 enum ci_hw_regs {
34 	CAP_CAPLENGTH,
35 	CAP_HCCPARAMS,
36 	CAP_DCCPARAMS,
37 	CAP_TESTMODE,
38 	CAP_LAST = CAP_TESTMODE,
39 	OP_USBCMD,
40 	OP_USBSTS,
41 	OP_USBINTR,
42 	OP_DEVICEADDR,
43 	OP_ENDPTLISTADDR,
44 	OP_PORTSC,
45 	OP_DEVLC,
46 	OP_OTGSC,
47 	OP_USBMODE,
48 	OP_ENDPTSETUPSTAT,
49 	OP_ENDPTPRIME,
50 	OP_ENDPTFLUSH,
51 	OP_ENDPTSTAT,
52 	OP_ENDPTCOMPLETE,
53 	OP_ENDPTCTRL,
54 	/* endptctrl1..15 follow */
55 	OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
56 };
57 
58 /******************************************************************************
59  * STRUCTURES
60  *****************************************************************************/
61 /**
62  * struct ci_hw_ep - endpoint representation
63  * @ep: endpoint structure for gadget drivers
64  * @dir: endpoint direction (TX/RX)
65  * @num: endpoint number
66  * @type: endpoint type
67  * @name: string description of the endpoint
68  * @qh: queue head for this endpoint
69  * @wedge: is the endpoint wedged
70  * @ci: pointer to the controller
71  * @lock: pointer to controller's spinlock
72  * @td_pool: pointer to controller's TD pool
73  */
74 struct ci_hw_ep {
75 	struct usb_ep				ep;
76 	u8					dir;
77 	u8					num;
78 	u8					type;
79 	char					name[16];
80 	struct {
81 		struct list_head	queue;
82 		struct ci_hw_qh		*ptr;
83 		dma_addr_t		dma;
84 	}					qh;
85 	int					wedge;
86 
87 	/* global resources */
88 	struct ci_hdrc				*ci;
89 	spinlock_t				*lock;
90 	struct dma_pool				*td_pool;
91 	struct td_node				*pending_td;
92 };
93 
94 enum ci_role {
95 	CI_ROLE_HOST = 0,
96 	CI_ROLE_GADGET,
97 	CI_ROLE_END,
98 };
99 
100 /**
101  * struct ci_role_driver - host/gadget role driver
102  * @start: start this role
103  * @stop: stop this role
104  * @irq: irq handler for this role
105  * @name: role name string (host/gadget)
106  */
107 struct ci_role_driver {
108 	int		(*start)(struct ci_hdrc *);
109 	void		(*stop)(struct ci_hdrc *);
110 	irqreturn_t	(*irq)(struct ci_hdrc *);
111 	const char	*name;
112 };
113 
114 /**
115  * struct hw_bank - hardware register mapping representation
116  * @lpm: set if the device is LPM capable
117  * @phys: physical address of the controller's registers
118  * @abs: absolute address of the beginning of register window
119  * @cap: capability registers
120  * @op: operational registers
121  * @size: size of the register window
122  * @regmap: register lookup table
123  */
124 struct hw_bank {
125 	unsigned	lpm;
126 	resource_size_t	phys;
127 	void __iomem	*abs;
128 	void __iomem	*cap;
129 	void __iomem	*op;
130 	size_t		size;
131 	void __iomem	*regmap[OP_LAST + 1];
132 };
133 
134 /**
135  * struct ci_hdrc - chipidea device representation
136  * @dev: pointer to parent device
137  * @lock: access synchronization
138  * @hw_bank: hardware register mapping
139  * @irq: IRQ number
140  * @roles: array of supported roles for this controller
141  * @role: current role
142  * @is_otg: if the device is otg-capable
143  * @fsm: otg finite state machine
144  * @fsm_timer: pointer to timer list of otg fsm
145  * @work: work for role changing
146  * @wq: workqueue thread
147  * @qh_pool: allocation pool for queue heads
148  * @td_pool: allocation pool for transfer descriptors
149  * @gadget: device side representation for peripheral controller
150  * @driver: gadget driver
151  * @hw_ep_max: total number of endpoints supported by hardware
152  * @ci_hw_ep: array of endpoints
153  * @ep0_dir: ep0 direction
154  * @ep0out: pointer to ep0 OUT endpoint
155  * @ep0in: pointer to ep0 IN endpoint
156  * @status: ep0 status request
157  * @setaddr: if we should set the address on status completion
158  * @address: usb address received from the host
159  * @remote_wakeup: host-enabled remote wakeup
160  * @suspended: suspended by host
161  * @test_mode: the selected test mode
162  * @platdata: platform specific information supplied by parent device
163  * @vbus_active: is VBUS active
164  * @transceiver: pointer to USB PHY, if any
165  * @hcd: pointer to usb_hcd for ehci host driver
166  * @debugfs: root dentry for this controller in debugfs
167  * @id_event: indicates there is an id event, and handled at ci_otg_work
168  * @b_sess_valid_event: indicates there is a vbus event, and handled
169  * at ci_otg_work
170  * @imx28_write_fix: Freescale imx28 needs swp instruction for writing
171  */
172 struct ci_hdrc {
173 	struct device			*dev;
174 	spinlock_t			lock;
175 	struct hw_bank			hw_bank;
176 	int				irq;
177 	struct ci_role_driver		*roles[CI_ROLE_END];
178 	enum ci_role			role;
179 	bool				is_otg;
180 	struct otg_fsm			fsm;
181 	struct ci_otg_fsm_timer_list	*fsm_timer;
182 	struct work_struct		work;
183 	struct workqueue_struct		*wq;
184 
185 	struct dma_pool			*qh_pool;
186 	struct dma_pool			*td_pool;
187 
188 	struct usb_gadget		gadget;
189 	struct usb_gadget_driver	*driver;
190 	unsigned			hw_ep_max;
191 	struct ci_hw_ep			ci_hw_ep[ENDPT_MAX];
192 	u32				ep0_dir;
193 	struct ci_hw_ep			*ep0out, *ep0in;
194 
195 	struct usb_request		*status;
196 	bool				setaddr;
197 	u8				address;
198 	u8				remote_wakeup;
199 	u8				suspended;
200 	u8				test_mode;
201 
202 	struct ci_hdrc_platform_data	*platdata;
203 	int				vbus_active;
204 	struct usb_phy			*transceiver;
205 	struct usb_hcd			*hcd;
206 	struct dentry			*debugfs;
207 	bool				id_event;
208 	bool				b_sess_valid_event;
209 	bool				imx28_write_fix;
210 };
211 
212 static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci)
213 {
214 	BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);
215 	return ci->roles[ci->role];
216 }
217 
218 static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role)
219 {
220 	int ret;
221 
222 	if (role >= CI_ROLE_END)
223 		return -EINVAL;
224 
225 	if (!ci->roles[role])
226 		return -ENXIO;
227 
228 	ret = ci->roles[role]->start(ci);
229 	if (!ret)
230 		ci->role = role;
231 	return ret;
232 }
233 
234 static inline void ci_role_stop(struct ci_hdrc *ci)
235 {
236 	enum ci_role role = ci->role;
237 
238 	if (role == CI_ROLE_END)
239 		return;
240 
241 	ci->role = CI_ROLE_END;
242 
243 	ci->roles[role]->stop(ci);
244 }
245 
246 /**
247  * hw_read: reads from a hw register
248  * @ci: the controller
249  * @reg:  register index
250  * @mask: bitfield mask
251  *
252  * This function returns register contents
253  */
254 static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)
255 {
256 	return ioread32(ci->hw_bank.regmap[reg]) & mask;
257 }
258 
259 #ifdef CONFIG_SOC_IMX28
260 static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
261 {
262 	__asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
263 }
264 #else
265 static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
266 {
267 }
268 #endif
269 
270 static inline void __hw_write(struct ci_hdrc *ci, u32 val,
271 		void __iomem *addr)
272 {
273 	if (ci->imx28_write_fix)
274 		imx28_ci_writel(val, addr);
275 	else
276 		iowrite32(val, addr);
277 }
278 
279 /**
280  * hw_write: writes to a hw register
281  * @ci: the controller
282  * @reg:  register index
283  * @mask: bitfield mask
284  * @data: new value
285  */
286 static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
287 			    u32 mask, u32 data)
288 {
289 	if (~mask)
290 		data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
291 			| (data & mask);
292 
293 	__hw_write(ci, data, ci->hw_bank.regmap[reg]);
294 }
295 
296 /**
297  * hw_test_and_clear: tests & clears a hw register
298  * @ci: the controller
299  * @reg:  register index
300  * @mask: bitfield mask
301  *
302  * This function returns register contents
303  */
304 static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,
305 				    u32 mask)
306 {
307 	u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;
308 
309 	__hw_write(ci, val, ci->hw_bank.regmap[reg]);
310 	return val;
311 }
312 
313 /**
314  * hw_test_and_write: tests & writes a hw register
315  * @ci: the controller
316  * @reg:  register index
317  * @mask: bitfield mask
318  * @data: new value
319  *
320  * This function returns register contents
321  */
322 static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
323 				    u32 mask, u32 data)
324 {
325 	u32 val = hw_read(ci, reg, ~0);
326 
327 	hw_write(ci, reg, mask, data);
328 	return (val & mask) >> __ffs(mask);
329 }
330 
331 /**
332  * ci_otg_is_fsm_mode: runtime check if otg controller
333  * is in otg fsm mode.
334  *
335  * @ci: chipidea device
336  */
337 static inline bool ci_otg_is_fsm_mode(struct ci_hdrc *ci)
338 {
339 #ifdef CONFIG_USB_OTG_FSM
340 	return ci->is_otg && ci->roles[CI_ROLE_HOST] &&
341 					ci->roles[CI_ROLE_GADGET];
342 #else
343 	return false;
344 #endif
345 }
346 
347 u32 hw_read_intr_enable(struct ci_hdrc *ci);
348 
349 u32 hw_read_intr_status(struct ci_hdrc *ci);
350 
351 int hw_device_reset(struct ci_hdrc *ci, u32 mode);
352 
353 int hw_port_test_set(struct ci_hdrc *ci, u8 mode);
354 
355 u8 hw_port_test_get(struct ci_hdrc *ci);
356 
357 int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
358 				u32 value, unsigned int timeout_ms);
359 
360 #endif	/* __DRIVERS_USB_CHIPIDEA_CI_H */
361