xref: /linux/drivers/usb/chipidea/bits.h (revision 5fd54ace4721fc5ce2bb5aef6318fcf17f421460) 
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * bits.h - register bits of the ChipIdea USB IP core
4  *
5  * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
6  *
7  * Author: David Lopo
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2 as
11  * published by the Free Software Foundation.
12  */
13 
14 #ifndef __DRIVERS_USB_CHIPIDEA_BITS_H
15 #define __DRIVERS_USB_CHIPIDEA_BITS_H
16 
17 #include <linux/usb/ehci_def.h>
18 
19 /*
20  * ID
21  * For 1.x revision, bit24 - bit31 are reserved
22  * For 2.x revision, bit25 - bit28 are 0x2
23  */
24 #define TAG		      (0x1F << 16)
25 #define REVISION	      (0xF << 21)
26 #define VERSION		      (0xF << 25)
27 #define CIVERSION	      (0x7 << 29)
28 
29 /* SBUSCFG */
30 #define AHBBRST_MASK		0x7
31 
32 /* HCCPARAMS */
33 #define HCCPARAMS_LEN         BIT(17)
34 
35 /* DCCPARAMS */
36 #define DCCPARAMS_DEN         (0x1F << 0)
37 #define DCCPARAMS_DC          BIT(7)
38 #define DCCPARAMS_HC          BIT(8)
39 
40 /* TESTMODE */
41 #define TESTMODE_FORCE        BIT(0)
42 
43 /* USBCMD */
44 #define USBCMD_RS             BIT(0)
45 #define USBCMD_RST            BIT(1)
46 #define USBCMD_SUTW           BIT(13)
47 #define USBCMD_ATDTW          BIT(14)
48 
49 /* USBSTS & USBINTR */
50 #define USBi_UI               BIT(0)
51 #define USBi_UEI              BIT(1)
52 #define USBi_PCI              BIT(2)
53 #define USBi_URI              BIT(6)
54 #define USBi_SLI              BIT(8)
55 
56 /* DEVICEADDR */
57 #define DEVICEADDR_USBADRA    BIT(24)
58 #define DEVICEADDR_USBADR     (0x7FUL << 25)
59 
60 /* TTCTRL */
61 #define TTCTRL_TTHA_MASK	(0x7fUL << 24)
62 /* Set non-zero value for internal TT Hub address representation */
63 #define TTCTRL_TTHA		(0x7fUL << 24)
64 
65 /* BURSTSIZE */
66 #define RX_BURST_MASK		0xff
67 #define TX_BURST_MASK		0xff00
68 
69 /* PORTSC */
70 #define PORTSC_CCS            BIT(0)
71 #define PORTSC_CSC            BIT(1)
72 #define PORTSC_PEC            BIT(3)
73 #define PORTSC_OCC            BIT(5)
74 #define PORTSC_FPR            BIT(6)
75 #define PORTSC_SUSP           BIT(7)
76 #define PORTSC_HSP            BIT(9)
77 #define PORTSC_PP             BIT(12)
78 #define PORTSC_PTC            (0x0FUL << 16)
79 #define PORTSC_WKCN           BIT(20)
80 #define PORTSC_PHCD(d)	      ((d) ? BIT(22) : BIT(23))
81 /* PTS and PTW for non lpm version only */
82 #define PORTSC_PFSC           BIT(24)
83 #define PORTSC_PTS(d)						\
84 	(u32)((((d) & 0x3) << 30) | (((d) & 0x4) ? BIT(25) : 0))
85 #define PORTSC_PTW            BIT(28)
86 #define PORTSC_STS            BIT(29)
87 
88 #define PORTSC_W1C_BITS						\
89 	(PORTSC_CSC | PORTSC_PEC | PORTSC_OCC)
90 
91 /* DEVLC */
92 #define DEVLC_PFSC            BIT(23)
93 #define DEVLC_PSPD            (0x03UL << 25)
94 #define DEVLC_PSPD_HS         (0x02UL << 25)
95 #define DEVLC_PTW             BIT(27)
96 #define DEVLC_STS             BIT(28)
97 #define DEVLC_PTS(d)          (u32)(((d) & 0x7) << 29)
98 
99 /* Encoding for DEVLC_PTS and PORTSC_PTS */
100 #define PTS_UTMI              0
101 #define PTS_ULPI              2
102 #define PTS_SERIAL            3
103 #define PTS_HSIC              4
104 
105 /* OTGSC */
106 #define OTGSC_IDPU	      BIT(5)
107 #define OTGSC_HADP	      BIT(6)
108 #define OTGSC_HABA	      BIT(7)
109 #define OTGSC_ID	      BIT(8)
110 #define OTGSC_AVV	      BIT(9)
111 #define OTGSC_ASV	      BIT(10)
112 #define OTGSC_BSV	      BIT(11)
113 #define OTGSC_BSE	      BIT(12)
114 #define OTGSC_IDIS	      BIT(16)
115 #define OTGSC_AVVIS	      BIT(17)
116 #define OTGSC_ASVIS	      BIT(18)
117 #define OTGSC_BSVIS	      BIT(19)
118 #define OTGSC_BSEIS	      BIT(20)
119 #define OTGSC_1MSIS	      BIT(21)
120 #define OTGSC_DPIS	      BIT(22)
121 #define OTGSC_IDIE	      BIT(24)
122 #define OTGSC_AVVIE	      BIT(25)
123 #define OTGSC_ASVIE	      BIT(26)
124 #define OTGSC_BSVIE	      BIT(27)
125 #define OTGSC_BSEIE	      BIT(28)
126 #define OTGSC_1MSIE	      BIT(29)
127 #define OTGSC_DPIE	      BIT(30)
128 #define OTGSC_INT_EN_BITS	(OTGSC_IDIE | OTGSC_AVVIE | OTGSC_ASVIE \
129 				| OTGSC_BSVIE | OTGSC_BSEIE | OTGSC_1MSIE \
130 				| OTGSC_DPIE)
131 #define OTGSC_INT_STATUS_BITS	(OTGSC_IDIS | OTGSC_AVVIS | OTGSC_ASVIS	\
132 				| OTGSC_BSVIS | OTGSC_BSEIS | OTGSC_1MSIS \
133 				| OTGSC_DPIS)
134 
135 /* USBMODE */
136 #define USBMODE_CM            (0x03UL <<  0)
137 #define USBMODE_CM_DC         (0x02UL <<  0)
138 #define USBMODE_SLOM          BIT(3)
139 #define USBMODE_CI_SDIS       BIT(4)
140 
141 /* ENDPTCTRL */
142 #define ENDPTCTRL_RXS         BIT(0)
143 #define ENDPTCTRL_RXT         (0x03UL <<  2)
144 #define ENDPTCTRL_RXR         BIT(6)         /* reserved for port 0 */
145 #define ENDPTCTRL_RXE         BIT(7)
146 #define ENDPTCTRL_TXS         BIT(16)
147 #define ENDPTCTRL_TXT         (0x03UL << 18)
148 #define ENDPTCTRL_TXR         BIT(22)        /* reserved for port 0 */
149 #define ENDPTCTRL_TXE         BIT(23)
150 
151 #endif /* __DRIVERS_USB_CHIPIDEA_BITS_H */
152